En Article File 20240322150228 FRH

CM6637
USB 2.0 High Speed Audio Controller
DESCRIPTION FEATURES
The CM6637 is a USB 2.0 high speed audio  Compliant with USB 2.0 high-speed
controller that complaints with USB Audio Device  Compliant with USB Audio Device Class 2.0/1.0
Class 2.0. The CM6637 provides standard I2S and  Compliant with USB Human Interface Device
S/PDIF digital audio interface. The maximum (HID) Class 1.1
outputs are 12 channels separate to I2S, TDM, HDA  Supports USB suspend/resume/reset functions
and S/PDIF. The maximum inputs are 12 channels  Supports control, interrupt, bulk, and
as well and separate to I2S, TDM, HDA and S/PDIF. isochronous data transfers
The first I2S out interface can be used to transfer  Input and output support I2S/TDM/HDA and
PCM and DSD audio data. Moreover, the CM6637 SPDIF digital audio interfaces
supports I2C, SPI and GPIOs to communicate with  The first I2S output supports up to 768KHz/32bits
external device. PCM
The CM6637 is embedded with 8051 MCU and 512KB  The first I2S supports both DoP and Native DSD
flash makes it is very flexible to change the USB  DoP up to 11.2MHz, DSD256
topology or communicate with external device by  Native DSD up to 22.4MHz, DSD512
changing internal flash code.  3 stereo I2S serial audio input interfaces
 The first I2S input supports up to 384KHz/32bits
 S/PDIF input and output up to 192KHz/24bits
 1 I2C master, 1 I2C slave, 6 SPI master, 24 GPIOs
BLOCK DIAGRAM
SPI
Control
8051 I2C Master
I2C Slave
MCU UART
GPIOs
512KB
ROM Flash
SRAM
USB 2.0 Controller
Interrupt
I2S DAC0
I2S DAC4
I2S DAC5
Data SPDIF Out

Bulk In/Out
Iso In/Out FIFO
Routing I2S ADC0
I2S ADC4
I2S ADC5
SPDIF Input
Page 1 / 29 www.cmedia.com.tw
Copyright© C-Media Electronics Inc.
CM6637
Release notes
Revision Date Description
0.93 2018/10/12 - First release of preliminary technical information
0.94 2018/12/17 - Modify pin description
1.00 2020/09/21 - Formal Release
- Modify 7.Electrical Characteristics
1.10 2021/07/21
- Modify pin description
- Remove 8K/16K/32K/64KHz sample rate from I2S interface
1.20 2022/02/08
- Remove 64K sample rate from SPDIF interface
CM6637
TABLE OF CONTENTS
1 DESCRIPTION AND OVERVIEW ........................................................................................................................................... 5
2 ORDERING INFORMATION ................................................................................................................................................. 5
3 FEATURES .......................................................................................................................................................................... 5
3.1 USB COMPLIANCE ................................................................................................................................................................ 5

3.2 DIGITAL AUDIO I/O ............................................................................................................................................................... 5
3.3 INTEGRATED 8051 MICRO PROCESSOR ..................................................................................................................................... 6
3.4 CONTROL INTERFACE ............................................................................................................................................................. 6
3.5 GENERAL............................................................................................................................................................................. 6
3.6 OPTIONAL VALUE-ADDED SOFTWARE FEATURES .......................................................................................................................... 6
4 APPLICATIONS ................................................................................................................................................................... 7
5 PIN ASSIGNMENT .............................................................................................................................................................. 8
5.1 PIN-OUT DIAGRAM ............................................................................................................................................................... 8

5.2 PIN DESCRIPTION .................................................................................................................................................................. 9
6 FUNCTION DESCRIPTION ................................................................................................................................................. 14
6.1 USB TOPOLOGY ................................................................................................................................................................. 14

6.2 USB ENDPOINT .................................................................................................................................................................. 14
6.3 I2S INTERFACE ................................................................................................................................................................... 14
6.3.1 The Basics of I2S Bus ................................................................................................................................................. 14
6.3.2 Left Justified Mode .................................................................................................................................................... 15
6.3.3 I2S Mode ................................................................................................................................................................... 16
6.4 S/PDIF INTERFACE.............................................................................................................................................................. 16
6.5 I2C, TWO-WIRE INTERFACE .................................................................................................................................................. 18
6.5.1 The Concept of I2C, Two Wire Interface .................................................................................................................... 18
6.5.2 Start and Stop Condition ........................................................................................................................................... 19
6.5.3 Bit Transfer ................................................................................................................................................................ 19
6.5.4 Transferring Data with Read/Write Transactions and Acknowledge ........................................................................ 20
6.5.5 Synchronization ......................................................................................................................................................... 22
6.5.6 Standard Mode and Fast Mode ................................................................................................................................. 23
6.6 TDM(TIME-DIVISION MULTIPLEXING) .................................................................................................................................... 24
7 ELECTRICAL CHARACTERISTICS ........................................................................................................................................ 25
7.1 ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................. 25
CM6637
7.2 ESD RATINGS .................................................................................................................................................................... 25

7.3 RECOMMENDED OPERATION CONDITIONS ............................................................................................................................... 25
7.4 STATIC CHARACTERISTICS ...................................................................................................................................................... 25
7.5 POWER CONSUMPTION ........................................................................................................................................................ 25
7.6 DC CHARACTERISTICS .......................................................................................................................................................... 26
8 PACKAGE DIMENSIONS .................................................................................................................................................... 27
CM6637
1 Description and Overview

The CM6637 is a USB 2.0 high speed audio controller that complaints with USB Audio Device Class 2.0. The CM6637
provides standard I2S and S/PDIF digital audio interface. The maximum outputs are 12 channels with 10 channels I2S
and 2 channels S/PDIF and the maximum inputs are 12 channels with 10 channels I2S and 2 channels S/PDIF. The first
I2S interface can be used to transfer PCM and DSD audio data. Moreover, the CM6637 supports I2C, SPI and GPIOs to
communicate with external device.
The CM6637 is embedded with 8051 MCU and 512KB flash makes it is very flexible to change the USB topology or
communicate with external device by changing internal flash code.
2 Ordering Information
Product Package Marking Package Type Transport Media
CM6637 CM6637 QFN-100(12x12mm) Tray
3 Features
3.1 USB Compliance
 Compliant with USB 2.0 high-speed
 Compliant with USB Audio Device Class 2.0/1.0
 Compliant with USB Human Interface Device (HID) Class 1.1
 Supports USB suspend/resume/reset functions
 Supports control, interrupt, bulk, and isochronous data transfers
 USB audio is asynchronous synchronization to reduce clock jitter
3.2 Digital Audio I/O

 2 stereo I2S serial audio and 1 S/PDIF output interfaces, refer below Table 1 for each audio format support
 2 stereo I2S serial audio and 1 S/PDIF input interfaces, , refer below Table 1 for each audio format support
 All the I2S in/out support master and slave
Table 1
Interface Audio Format Bit Depth
PCM 768K/705.6K/384K/352.8K/192K/ 176.4K/96K/88.2K/48K/44.1K Hz 16/24/32 bits
I2S DAC0 DoP: 2.8/5.6/11.2MHz
DSD
Native: 2.8/5.6/11.2/22.4MHz
I2S DAC4 PCM 192K/ 176.4K/96K/88.2K/48K/44.1K Hz 16/24 bits

I2S DAC5 PCM 192K/ 176.4K/96K/88.2K/48K/44.1K Hz 16/24 bits
S/PDIF PCM 192K/ 176.4K/96K/88.2K/48K/44.1K/32K 16/24 bits
Out AC3, DTS Compressed audio data
I2S ADC0 PCM 384K/352.8K/192K/ 176.4K/96K/88.2K/48K/44.1K Hz 16/24/32 bits
I2S ADC4 PCM 192K/ 176.4K/96K/88.2K/48K/44.1K Hz 16/24 bits
CM6637
I2S ADC5 PCM 192K/ 176.4K/96K/88.2K/48K/44.1K Hz 16/24 bits

S/PDIF 16/24 bits
PCM 192K/ 176.4K/96K/88.2K/48K/44.1K/32K
In
3.3 Integrated 8051 Micro Processor

 Embedded 8051 micro-processor handles command/protocol transactions
 The MCU speed is programmable from 3.072 ~65.536 MHz
 HID interrupts can be implemented via firmware codes
 Provides maximum HW configuration flexibility with a firmware code upgrade
 VID/PID/product string can be customized via firmware code programming
3.4 Control Interface

 1 Master I2C control interface to communicate with external devices or EEPROM, the master I2C speed supports
standard mode(100KHz) and fast mode(400KHz)
 1 Slave I2C control interface for external MCU communication, the slave I2C speed supports standard
mode(100KHz) and fast mode(400KHz)
 6 SPI master, supports speed from 32.768M ~ 0.3695Mb/s
 24 GPIOs(programmable multi functions I/O), 8 XDs(can be GPIO or other functions)
 6 PWM LED driver output
3.5 General
 Embedded USB 2.0 transceiver (up to 480MB bandwidth)
 Auto detection for high-speed/full-speed
 Single 12MHz crystal input is required (embedded PLL function), or optional oscillator inputs for 49.152 or
24.576MHz (for x48KHz audio format) and 45.158 or 22.5792MHz (for x44.1KHz audio format)
 3.3V digital I/O pads with 5V tolerance
 QFN-100 package (12 x 12 mm)
3.6 Optional Value-added Software Features

 For Windows, Cmedia drivers provide the following key features:
 Playback feedback endpoints to control data transmission accuracy and maximize audio quality
 Xear™ Pro- ASIO2.2 driver
 Native DSD by ASIO
CM6637
4 Applications
 USB DAC
 USB Headphone Amplifier
 Professional audio-PC musician applications (recording mixer, I/O interface, DJ console, keyboard,
Electric guitar, etc.)
CM6637
5 Pin Assignment
5.1 Pin-out Diagram
X12M_CLK
XGPIO_7
XGPIO_6
XGPIO_4
XGPIO_1
XGPIO_0
XGPIO_5
XGPIO_3
XGPIO_2
DVDD33
DVDD12
DVDD33
DVDD12
XPWDN
XRSTO
XRSTN
DVSS
XD7
XD6
XD5
XD4
XD3
XD2
XD1
XD0
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DVDD33 76 50 DVDD33
XMSCL 77 49 DVDD12
XMSDA 78 48 XADC0_SDIN3
XSSCL 79 47 XADC0_SDIN2
XSSDA 80 46 XADC0_SDIN1
XTEST 81 45 XADC0_SDIN0
DVSS 82 44 XADC0_LRCK
HDA_BCLK 83 43 XADC0_SCLK
CM6637
HDA_SDOUT 84 42 XADC0_MCLK
HDA_SDIN 85 41 DVDD33
DVDD12 86 40 DVDD12
DVDD33 87 39 DVSS
QFN-100
HDA_SYNC 88 38 XSPDIFI
HDA_RST 89 37 XGPIO_15
DVDD12 90 36 XGPIO_14
DVDD33 91 35 XGPIO_13
VCCHSRT 92 34 XGPIO_12
GNDHSRT 93 33 XGPIO_11
USB_DP 94 32 XGPIO_10
USB_DM 95 31 XGPIO_9
XSCI 96 30 XGPIO_8
XSCO 97 29 XSPDIFO
VDD 98 28 XGPIO_21
RREF 99 27 XGPIO_20
DVSS 100 26 XDAC0_SDOUT3

EXP 101
VSS 10
XGPIO_16 11
XGPIO_17 12
XGPIO_18 13
XGPIO_19 14
DVSS 15
DVDD12 16
DVDD33 17
XGPIO_22 18
XGPIO_23 19
XDAC0_MCLK 20
XDAC0_SCLK 21
XDAC0_LRCK 22
XDAC0_SDOUT0 23
XDAC0_SDOUT1 24
XDAC0_SDOUT2 25
DVDD33_OUT 1
DVDD50 2
XRSTB 3
DVDD12 4
LDO1V2_OUT 5
DVDD50 6
CHP_P 7
DV1V2_OUT 8
CHP_N 9
CM6637
5.2 Pin Description

Pin # Symbol I/O Description
Clock
72 X12M_CLK DO 12MHz clock output
96 XSCI AI Crystal oscillator input
97 XSCO AO Crystal oscillator output
USB 2.0 BUS Interface
USB PHY reference resistor. Connect external reference resistor
99 RREF AI
(3301%)
94 USB_DP AIO USB 2.0 data positive
95 USB_DM AIO USB 2.0 data negative
Power/Ground
1 DVDD33_OUT PWR LDO 3.3V Output
2 DVDD50_IN AI Digital supply voltage 5V for digital circuit linear regulator
4 DVDD12 PWR Connect to V1D2_OUT for 1.2V
5 LDO1V2_OUT PWR LDO 1.2V output
6 DVDD50_IN AI Digital supply voltage 5V for DC-DC
7 CHP_P AO Charge-pump positive output, connected to a 2.2uF capacitor
8 D1V2_OUT PWR DC-DC 1.2V output
9 CHP_N AO Charge-pump negative output, connected to a 2.2uF capacitor
10 VSS GND Digital ground supply
15 DVSS GND Digital ground supply
16 DVDD12 PWR Digital supply voltage 1.2V
92 VCCHSRT PWR Analog supply voltage 3.3V
93 GNDHSRT GND Digital ground supply
Digital supply voltage 1.2V, connected to the capacitor filter for
98 VDD PWR
digital core
8 Channel I2S DAC0 Interface
CM6637
1). I2S DAC0 master clock output

20 XDAC0_MCLK DO
2). DSD bit clock output
1). I2S DAC0 bit clock input/output
21 XDAC0_SCLK DIO 2). DSD bit clock output
3). TDM DAC SCLK Output
1). I2S DAC0 left/right clock input/output
22 XDAC0_LRCK DIO 2). DSD channel 1 (or 0, if enable channel switching) data output
3). TDM DAC SYNC Output
1). I2S DAC0 serial data output for channel 0, 1
23 XDAC0_SDOUT0 DO 2). DSD channel 0 (or 1, if enable channel switching) data output
3). TDM DAC DATA Output
24 XDAC0_SDOUT1 DIO, PD 1). I2S DAC0 serial data output for channel 2, 3
8-channel I2S ADC0 Interface
42 XADC0_MCLK DO I2S ADC0 master clock output
1). I2S ADC0 bit clock input/output
43 XADC0_SCLK DIO
2). TDM ADC SCLK Output
1). I2S ADC0 left/right clock input/output
44 XADC0_LRCK DIO
2). TDM ADC SYNC Output
1). I2S ADC0 serial data input for channel 0, 1
45 XADC0_SDIN0 DI
2). TDM ADC DATA Input
46 XADC0_SDIN1 DI I2S ADC0 serial data input for channel 2, 3
S/PDIF I/O
29 XSPDIFO DO S/PDIF transmitter
38 XSPDIFI DI S/PDIF receiver
GPIO
11 XGPIO_16 DIO General purpose input/output 16 (default input)

1). General purpose input/output 22 (default input)
18 XGPIO_22 DIO
2). External 24.576 MHz / 49.152 MHz oscillator input
19 XGPIO_23 DIO
2). External 22.5792 MHz / 45.1584 MHz oscillator input
27 XGPIO_20 DIO
2). I2C Slave interrupt output to external MCU
CM6637

28 XGPIO_21 DIO
2). I2C Slave data ready indication output
1). General purpose input/output 8 (default output)
30 XGPIO_8 DIO 2). SPI Master clock output
3). I2S ADC4 master clock output
1). General purpose input/output 9 (default output)
31 XGPIO_9 DIO 2). SPI Master data output
3). I2S ADC4 bit clock input/output
2). SPI Master Data input
32 XGPIO_10 DIO
4). R8051 serial 1 interface transmit data, TXD1
2). SPI Master chip enable 6 output
33 XGPIO_11 DIO
3). R8051 serial 1 interface receive data, RXD1
34 GPIO_12 DIO 2). I2S ADC5 master clock output
3). LED module 4 Output
35 GPIO_13 DIO 2). I2S ADC5 bit clock input/output
36 GPIO_14 DIO 2). LED module 6 Output
37 GPIO_15 DIO
51 XD0 DO SPI Master clock output
52 XD1 DO SPI Master data output
53 XD2 DI SPI Master data input
54 XD3 DO SPI Master chip enable 0 output
62 XGPIO_0 DIO
2). I2S DAC4 master clock output
CM6637

63 XGPIO_1 DIO
2). I2S DAC4 bit clock input/output
64 XGPIO_2 DIO
2). I2S DAC4 left/right clock input/output
65 XGPIO_3 DIO
66 XGPIO_4 DIO 2). I2S DAC5 master clock output
67 XGPIO_5 DIO 2). I2S DAC5 bit clock input/output
68 XGPIO_6 DIO 2). I2S DAC5 left/right clock input/output
69 XGPIO_7 DIO
Control Interface
77 XMSCL DO I2C Master serial clock
78 XMSDA DIO I2C Master serial data
79 XSSCL DIO I2C Slave serial clock
80 XSSDA DIO I2C Slave serial data
Miscellaneous
3 N.C No connection
External codec reset output
70 XRSTO DO
(default tri-state)
Power down output signal for external device output (default
71 XPWDN DO
tri-state)
73 XRSTN DI Reset input, active low
81 XTEST DI Test mode input (Connect to ground)
83 N.C No connection
AI: Analog Input

AO: Analog Output
AIO: Analog Input/Output
DI: Digital Input
CM6637
DO: Digital Output

DIO: Digital Input/Output
CM6637
6 Function Description
6.1 USB Topology
The CM6637 USB Topology is programmable by changing firmware. If the internal firmware is empty, the CM6637 will
report a HID device to the system. It is used to load the firmware.
6.2 USB Endpoint
All USB devices must support a control pipe at endpoint number zero (default control pipe). The full speed and high
speed devices may support up to a maximum of 16 endpoints. The endpoint table of CM6637 is listed as follows.
EndpointNumber Direction Type Description
IN
0 Control
OUT
IN Bulk, Isochronous Audio, Recording DMA #R5
1
Out Bulk A
2 IN/OUT Bulk B
IN Feedback
3 Audio, Playback DMA #P5
OUT Isochronous
4 IN/OUT Interrupt A
IN Feedback
5 Audio, Playback DMA #P0
OUT Isochronous
IN
6
OUT
IN
7
OUT
8 IN Isochronous Audio, Recording DMA #R0
9 IN
A IN
IN
B
OUT
IN Feedback Audio, Playback DMA #P4
C
OUT Isochronous
D IN
E IN Isochronous Audio, Recording DMA #R4
F IN/OUT Interrupt B
6.3 I2S Interface

The main audio interface of the CM6637 is I2S, which has three clock signals, MCLK, BCLK and LRCK, and at least one
data line depending on the channels supported. One data line contains two channels. The three I2S clock symbols are
explained below.
MCLK = main clock.

BCLK = bit clock.
LRCK = left and right clock.
6.3.1 The Basics of I2S Bus
Both master and slave modes of I2S are supported by the I2S interfaces of the CM6637, namely I2S DAC0, I2S ADC0.
Master mode means BCLK and LRCK are provided by the CM6637 as shown in Fig. 7.3.1(a). On the contrary, slave
mode means BCLK and LRCK are provided by the I2S codecs as depicted in Fig. 7.3.1(b).
CM6637
MCLK MCLK
CM6637 CM6637
BCLK BCLK
I2S Codec I2S Codec
Interface LRCK Interface LRCK
Fig. 7.3.1 (a) Master mode Fig. 7.3.1 (b) Slave mode.
Fig. 7.3.2 indicates the basic waveform of I2S. Note that BCLK is generated at the positive edges of MCLK with the
ratios 1, 1/2, 1/4, or 1/8, and LRCK is generated at the negative edges of BCLK with the ratios 1/64, 1/128, 1/256.
Data bits are transited at the negative edges of BCLK, and are sampled at the positive edges of BCLK. In case of
playback, CM6637 is the data transmitter and the codec is the data receiver. As for recording, the roles of CM6637
and codec are reversed.
Left Channel Right Channel
LRCK
BCLK
DIN/ 1 2 3 4 n-1 n 1 2 3 4 n-1 n

DOUT
MSB LSB MSB LSB
Fig. 7.3.2 The basic timing diagram of the I2S interface.
For the I2S DAC controller, the audio data is transformed from the parallel format to the serial format before
transmitted. Then, the bit data is shifted out one by one with the MSB first via DOUT signal. If the I2S DAC controller
is set to 32 bits, at least 32 BCLK clocks must exist in both LRCK left and right channels. In the same manner, the
audio data is transformed from the coming serial format to the parallel format for a I2S ADC controller.
6.3.2 Left Justified Mode

In the left justified mode of the I2S DAC controller, the MSB data bit is clocked out by the CM6637 at the negative
edge of BCLK which is aligned to the transition of LRCK. In the left justified mode of I2S ADC controllers, the MSB data
bit is clocked out by codecs and sampled by the CM6637 at the first positive edge of BCLK which follows a LRCK
transition. LRCK is high during left channel transmission and low during right channel transmission in the left justified
mode. Fig. 7.3.2 shows all of these.
CM6637
LRCK
the MSB is sampled here
BCLK
where the MSB is clocked out

DIN/ 1 2 3 4 n-1 n 1 2 3 4 n-1 n
DOUT
MSB LSB MSB LSB
Fig. 7.3.2 Left justified mode timing diagram of I2S interface.
6.3.3 I2S Mode

In the I2S mode of the I2S DAC controller, the MSB data bit is clocked out by CM6637 at the first negative edge of BCLK
which follows a LRCK transition. In the I2S mode of I2S ADC controllers, the MSB data bit is clocked out by codecs and
sampled by the CMA6635 at the second positive edge of BCLK which follows a LRCK transition. LRCK is low during left
channel transmission and high during right channel transmission in the I2S mode. Fig. 7.3.3 indicates all of these.
LRCK
the MSB is sampled here
BCLK
1 BCLK where the MSB is clocked out 1 BCLK

DIN/ 1 2 3 n-1 n 1 2 3 n-1 n
DOUT
MSB LSB MSB LSB
Fig. 7.3.3 I2S mode timing diagram of I2S interface.
6.4 S/PDIF Interface

SPDIF is an audio transmission format in digital domain. The data stream format is illustrated in Fig. 7.4.1. The
maximum unit of the S/PDIF stream is a block. A block is composed of 192 frames, and each frame is composed of two
subframes. One frame contains one audio sample, so the frame rate is equal to the sampling rate. The left channel
audio data is carried by bit slot 4-27 (or time slot 4-27) of subframe A, and right channel is carried by bit slot 4-27 of
subframe B. The Sync slot takes preamble signal which is used to label the beginning of a subframe. There are three
types for preamble signal, the first is B type, used only in the first subframe of a block; the W type, used in all
subframe B; the M format, used in all subframe A, besides the first subframe of a block. The block format is shown in
Fig. 7.4.1. The logical level at the start of a bit is always inverted to the level at the end of the previous bit. The level
at the end of a bit is equal (a 0 transmitted) or inverted (a 1 transmitted) to the start of that bit.
The S/PDIF data signal is coded by the “biphase-mark-code,” which is a kind of phase modulation. It is illustrated
in Fig. 7.4.2. The base clock of a S/PDIF signal is twice the bit rate, and the frequency of the base clock is only
CM6637
determined by the sampling rate. The period of the base clock is called the Unit interval (UI). For example, for a
48KHz 2-channel S/PDIF signal, the frame rate is also 48KHz, so a frame period is 20.833us, and a subframe period is
10.416us. A subframe contains 32-bit slot, so a bit slot period is 325.52ns. As we said above, the base clock is twice
the bit rate. Therefore, the period of the base clock is 162.76ns. In other words, the frequency of base clock is 6.144
MHz. Bi-phase coding can prevent PCM data from DC isolated and insensitive to level polarity. A maximum up to 24
data bits can be transmitted by the S/PDIF signal, and the sequence is from LSB to MSB.
block
Frame0 Frame1 Frame2 Frame191
B W M W M W M W B W
SubFrame A SubFrame B
SYNC AUDIO DATA V U C P SYNC AUDIO DATA V U C P
4 24 1 1 1 1
M M
W Or W
B B
When last UI= low When last UI=high
Fig. 7.4.1 S/PDIF Frame format.
CM6637
Base clock
Logic 0 1 1 0 1 0 0
Input
Bi-phase
Output
UI
Fig. 7.4.2 S/PDIF biphase-mark-code (BMC).
6.5 I2C, Two-Wire Interface

The 2-wire master and slave serial buses are designed separately in the CM6637. There are two reasons which let us
make such a decision. The first reason is that the separated 2-wire master and slave buses are easier to design, and
the second reason is that the 2-wire master bus pins have been shared with SPI interface. In the most applications,
the SPI interface is the one that is chosen to control the codecs, so the 2-wire slave bus cannot combine with the
2-wire master bus.
6.5.1 The Concept of I2C, Two Wire Interface

The 2-wire bus, as its name reveals, has 2 lines. One is the serial clock line (SCL), and the other is the serial data line
(SDA). Both of them are operated under open drain. That means if the 2 lines are not driven by a master or a slave,
they are pulled high by the external pull-up resistors as indicated by Fig. 7.5.1. A device connected on the bus can be
recognized as a master or a slave when performing data transfers. A master is the device which initiates a data
transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is
considered a slave. Another concept that we should know is the transmitter-receiver relation. The transmitter is the
device which sends data to the bus, and receiver is the device which receives data from the bus. Note that the
definition of transmitter-receiver is different from that of master-slave. We will use these terms to explain 2-wire
read/write transactions later. The CM6637 use 7 bits to address the slave devices such as codecs, so theoretically, the
2-wire bus is able to connect 128 slave devices. However, in the audio system application, the limitation is on the
codecs, not on the CM6637. Usually, the codecs which support 2-wire bus only have one or two pins to select their
address. Therefore, two or four codecs is allowed in the system indicated by Fig. 7.5.1, unless the codecs are from
different manufactures. In the MCU application, the CM6637 is a slave device, and it can be addressed by the MCU via
four different addresses, 0001000b, 0001001b, 0001010b, 0001011b.
CM6637
VDD
pull-up MSCL: master serial clock
resistors 1.8 KΩ MSDA: master serial data
SSCL: slave serial clock
SSDA: slave serial data
CM6637
2-Wire MSCL Codec
Master MSDA
2-Wire SSCL
MCU
Slave SSDA
Fig. 7.5.1 The connection of 2-wire master and slave buses.
6.5.2 Start and Stop Condition

For a 2-wire bus transaction, the start and stop condition is defined as follows and shown in Fig.7.5.2.
 Start: a high to low transition on the SDA line while SCL is high.
 Stop: a low to high transition on the SDA line while SCL is high.
Start and stop conditions always generated by the master device. The bus is considered to be busy after the start
condition. The bus is considered to be free again after the stop condition.
Fig. 7.5.2 Start and stop conditions of 2-wire bus.
6.5.3 Bit Transfer

The data on the SDA line must be stable during the high period of the clock. The state of the data line can only transit
when the clock signal on SCL line is low. The bit transfer is indicated in Fig. 7.5.3.
CM6637
Fig. 7.5.3 Bit transfer of 2-wire bus.
6.5.4 Transferring Data with Read/Write Transactions and Acknowledge

Every byte put on the SDA line must be 8-bit long. The number of bytes that can be transmitted per transfer is 3 or 4
bytes in the CM6637. The first byte is always the address byte which is composed of the 7-bit address and 1
read/write bit, listed in Fig. 7.5.4.1 For a write transaction, the second byte is called Memory Address Pointer (MAP),
which is usually used to indicate the target register in the slave device that the followed third and fourth bytes will
be applied on. For a read transaction (only 3 bytes), the second and third bytes is the data returned by the slave
device. Each byte has to be ended by an acknowledge bit. Data is transferred with the most significant bit first.
MSB LSB
SDA 7 6 5 4 3 2 1 R/W
R/W: 1, read
Slave Address 0, write
Fig. 7.5.4.1 The first byte after start condition.
The 2-wire master bus of the CM6637 supports read/write transactions. All these transactions are depicted in Fig.
7.5.4.2 to give a whole picture about what the CM6637 can do.
SCL
N(N<9) Byte Write

SDA SlaveTransaction
Address 0 A MAP A Data 1 Data N-1 A Data N A
3 Byte Write Transaction Stop
SDA Slave Address 0 A MAP A Data 1 A
2 Byte Write Transaction (Write-MAP-Only) Stop
SDA Slave Address 0 A MAP A
Stop
3 Byte Read Transaction
SDA Slave Address 1 A Data 1 A Data 2 A
2 Byte Read Transaction Stop
SDA Slave Address 1 A Data 1 A
Start Stop
from master to slave MAP: Memory Address Pointer

A  acknowledge ( SDA Low)
(the target register address
from slave to master A  not acknowledge ( SDA High) in slave device)
Fig. 7.5.4.2 The 5 basic transactions of the 2-wire master bus supported by the CM6637.
CM6637
In a read transaction, usually the slave device returns the data of the register whose address is in the MAP. If the
read transaction is a 3 byte read transaction, the second returned byte is the data in the (address+1) register.
Therefore, the action of obtaining the data in slave device is composed of two transactions, namely a 2 byte write
transaction (Write-MAP-Only) followed by a read transaction. For the convenience of users, we have designed an auto
read transaction, shown in Fig. 7.5.4.3, which is actually the combination of a write and a read transactions.
SCL
Auto Read Transaction (= Write-MAP-Only + 2 or 3 Byte Read Transaction)

SDA Slave Address 0 A MAP A Slave Address 1 A Data Data A
Start Stop Start Stop
Fig. 7.5.4.3 Auto read transaction in the CM6637.
Data transfer with acknowledge is obligatory. The transmitter release SDA line during the acknowledge clock
pulse. Then, the receiver must pull down the SDA line during the acknowledge clock pulse so that it remains low for
the entire acknowledge clock high period. This is shown in Fig. 7.5.4.4. When a salve does not acknowledge the slave
address byte. For example, it is unable to receive or transmit because it is performing some real-time function. The
data line should be left high by the slave. The master can then generate either a stop condition to abort the transfer,
or a repeated start condition to start a new transfer.
Fig. 7.5.4.4 Acknowledge of the 2-wire bus.
For a read transaction, after the slave address byte is transmitted and acknowledged by slave device, the role of
master-transmitter is altered to become master-receiver, and the original slave-receiver is altered to become
slave-transmitter. This conception can be easily observed in Fig. 7.5.4.3 and 7.5.4.4, where we use yellow and white
blocks to denote the data bit transfer direction. Yellow means the data direction is from the master to the slave.
White means the data direction is from the slave to the master. Meanwhile, in a read transaction, the
master-receiver must signal the end of the data to the slave transmitter by generating a not-acknowledge ( A ) on the
last byte that was clocked out of the slave-transmitter. The slave-transmitter should release the SDA line to allow the
CM6637
master to generate a stop or repeated start condition.
6.5.5 Synchronization
The synchronization of the 2-wire bus in the CM6637 can be described in two aspects. The first aspect is the
synchronization used in arbitration. Although we did not implement arbitration, we did implement clock
synchronization. Clock synchronization is used when there are more than two masters connected on the bus. A high to
low transition on the SCL line will cause the concerned masters start counting the clock low period. Before the clock
high state is reached, the masters will hold the SCL line in low state. However, the low to high clock transition of one
of the masters may not change the state of the SCL line if another master’s clock is still in low period (because the
SCL line of the devices are wire-AND connected by open-drain technique). Therefore, the SCL line will be held low by
the device with the longest clock low period. The other devices with shorter low period, including the CM6637, enter
a high wait state during this time. Figure 7.5.5.1 listed below is the timing of clock synchronization.
Fig. 7.5.5.1 Clock synchronization for more than two masters in the bus.
Another aspect of synchronization is the data synchronization between master and slave. If a slave cannot receive
or transmit another complete byte of the data until it has performed some other function, for example servicing an
internal interrupt or waiting for the driver to prepare the data needed, the salve can hold the clock line SCL low to
force the master into a wait state. Data transfer then continues when the slave is ready and releases the clock line
SCL. The data synchronization is shown in Fig. 7.5.5.2.
CM6637
Fig. 7.5.5.2 The data synchronization of the 2-wire master and slave buses in the CM6637.
6.5.6 Standard Mode and Fast Mode

Both the 2-wire master and slave buses in the CM6637 can support standard mode transfer and fast mode transfer.
The data transfer rate of the standard mode is up to 100 Kbits/sec, and the fast mode is up to 400 Kbits/sec. The
clock timing of these modes are listed in Fig. 7.5.6 and Table 7.5.6
SDA
SCL
Start Stop
t low t high
Fig. 7.5.6.1 Standard mode and fast mode timing.
Table 7.5.6 Standard mode and fast mode timing.

Standard mode Fast mode
Parameter Symbol Unit
MIN MAX MIN MAX
SCL clock frequency f SCL 0 100 0 400 KHz
Low period of SCL clock t low 4.8  1.3  S
High period of SCL clock t high 4.8  0.6  S
CM6637
6.6 TDM(Time-Division Multiplexing)

There are two TDM interfaces in CM6637. One is TDM-out and another is TDM-in. TDM has two clock signals and one
data signal used to transmit 8-channel data. Supported audio data format are Mode 1 and Mode 2.
Fig. 7.6.1 TDM Mode 1 (BCLK POLARITY=0)
Fig. 7.6.2 TDM Mode 2 (BCLK POLARITY=0)
CM6637
7 Electrical Characteristics
7.1 Absolute Maximum Ratings
Parameter Min. Max. Unit
Digital Supply Voltage DVDD50_IN 4.5 5.5 V
o
Storge Temperature TS -65 150 C
o
Operating Ambient Temperature(*Note1) TA 0 70 C
Note1: Test conditions: DVDD50_IN = 5V, DVSS =0V
7.2 ESD Ratings

Human-body model (HBM) ±4000 V
Machine mode (MM) ±200 V
7.3 Recommended Operation Conditions

Parameter Min. Typ Max. Units
Digital Supply Voltage DVDD50_IN 4.5 5 5.5 V
o
Operating Ambient Temperature TA 0 - 70 C
Crystal Clock X12M_CLK 12.000 +/- 30 PPM MHz
7.4 Static Characteristics

Digital Core Voltage VDD 1.1 1.25 1.4 V
Digital I/O Voltage DVDD33 3.0 3.3 3.6 V
Input Voltage High VIH 0.7*DVDD33 DVDD33 5.5 V
Input Voltage Low VIL - - 0.3*DVDD33 V
Output Voltage High VOH 0.9*DVDD33 - - V
Output Voltage Low VOL - - 0.1*DVDD33 V
7.5 Power Consumption

Test Conditions: DVDD50_IN, DVSS =0V, TA=+25oC, MCU Clock = 3MHz.
Sample Rate=48kHz, 24Bits, Operation: I2S output and I2S input,
I2S output and I2S input = Gain 0dB

Total power consumption
- 48 - mA
(Playback + Record)
Standby power consumption - 41.6 - mA
Suspend mode power consumption - 2.3 - mA
CM6637
7.6 DC Characteristics
Test Conditions: DVDD50_IN=5V, DVSS =0V, TA=+25oC
Parameter Symbol Min. Typ Max. Units
High-level input voltage Vih 2.4 - 5.3 V
Low-level input voltage Vil - - 0.8 V
High-level output voltage Voh 2.4 - - V
Low-level output voltage Vol - - 0.4 V
SPDIF High-level input voltage - 1.75 - - V
SPDIF Low-level input voltage - - - 1.55 V
CM6637
8 Package Dimensions
CM6637
CM6637
－End of Datasheet－
C-MEDIA ELECTRONICS INC.

6F., 100, Sec. 4, Civil Boulevard, Taipei, Taiwan 106 R.O.C.
TEL：+886-2-8773-1100
FAX：+886-2-8773-2211
E-MAIL：sales@cmedia.com.tw
Disclaimer:
Information provided by C-Media Electronics Inc. is sworn to be accurate and reliable. However, no responsibility is
assumed by C-Media Electronics Inc. for its use, nor for any infringements of patents or other rights of third parties
that may result from its use. Specifications are subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of C-Media. Trademarks, registered or not are the property of their
respective owners.

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CM6637

USB 2.0 High Speed Audio Controller

topology or communicate with external device by  Native DSD up to 22.4MHz, DSD512

Data SPDIF Out

1 DESCRIPTION AND OVERVIEW ........................................................................................................................................... 5

2 ORDERING INFORMATION ................................................................................................................................................. 5

3.1 USB COMPLIANCE ................................................................................................................................................................ 5

5 PIN ASSIGNMENT .............................................................................................................................................................. 8

5.1 PIN-OUT DIAGRAM ............................................................................................................................................................... 8

6 FUNCTION DESCRIPTION ................................................................................................................................................. 14

6.1 USB TOPOLOGY ................................................................................................................................................................. 14

7 ELECTRICAL CHARACTERISTICS ........................................................................................................................................ 25

7.1 ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................. 25

7.2 ESD RATINGS .................................................................................................................................................................... 25

8 PACKAGE DIMENSIONS .................................................................................................................................................... 27

1 Description and Overview

3.2 Digital Audio I/O

I2S DAC4 PCM 192K/ 176.4K/96K/88.2K/48K/44.1K Hz 16/24 bits

I2S ADC5 PCM 192K/ 176.4K/96K/88.2K/48K/44.1K Hz 16/24 bits

3.3 Integrated 8051 Micro Processor

3.4 Control Interface

3.6 Optional Value-added Software Features

DVSS 100 26 XDAC0_SDOUT3

5.2 Pin Description

1). I2S DAC0 master clock output

11 XGPIO_16 DIO General purpose input/output 16 (default input)

1). General purpose input/output 21 (default input)

1). General purpose input/output 1 (default input)

AI: Analog Input

DO: Digital Output

6.3 I2S Interface

MCLK = main clock.

Left Channel Right Channel

DIN/ 1 2 3 4 n-1 n 1 2 3 4 n-1 n

Fig. 7.3.2 The basic timing diagram of the I2S interface.

6.3.2 Left Justified Mode

Left Channel Right Channel

where the MSB is clocked out

Fig. 7.3.2 Left justified mode timing diagram of I2S interface.

6.3.3 I2S Mode

Left Channel Right Channel

1 BCLK where the MSB is clocked out 1 BCLK

Fig. 7.3.3 I2S mode timing diagram of I2S interface.

6.4 S/PDIF Interface

Frame0 Frame1 Frame2 Frame191

Fig. 7.4.1 S/PDIF Frame format.

Fig. 7.4.2 S/PDIF biphase-mark-code (BMC).

6.5 I2C, Two-Wire Interface

6.5.1 The Concept of I2C, Two Wire Interface

Fig. 7.5.1 The connection of 2-wire master and slave buses.

6.5.2 Start and Stop Condition

Fig. 7.5.2 Start and stop conditions of 2-wire bus.

6.5.3 Bit Transfer

Fig. 7.5.3 Bit transfer of 2-wire bus.

6.5.4 Transferring Data with Read/Write Transactions and Acknowledge

N(N<9) Byte Write

3 Byte Write Transaction Stop

SDA Slave Address 0 A MAP A Data 1 A

2 Byte Write Transaction (Write-MAP-Only) Stop