An Eleven-Level Switched-Capacitor Inverter With Boosting Capability
An Eleven-Level Switched-Capacitor Inverter With Boosting Capability
An Eleven-Level Switched-Capacitor Inverter With Boosting Capability
Article
An Eleven-Level Switched-Capacitor Inverter with
Boosting Capability
Md Reyaz Hussan 1 , Adil Sarwar 1, * , Irfan Khan 2, * , Mohd Tariq 1, * , Mohammad Tayyab 1
and Waleed Alhosaini 3,4
1 Department of Electrical Engineering, ZHCET, Aligarh Muslim University, Aligarh 202002, India;
md.reyazhussan@zhcet.ac.in (M.R.H.); mtayyab1@myamu.ac.in (M.T.)
2 Clean and Resilient Energy Systems (CARES) Lab., Texas A&M University at Galveston,
Galveston, TX 77553, USA
3 Department of Electrical Engineering, College of Engineering, Jouf University,
Sakaka 72388, Saudi Arabia; wsalhosaini@ju.edu.sa
4 Engineering and Applied Sciences Research Unit, Jouf University, Sakaka 72388, Saudi Arabia
* Correspondence: adil.sarwar@zhcet.ac.in (A.S.); irfankhan@tamu.edu (I.K.); tariq.ee@zhcet.ac.in (M.T.)
Abstract: An 11-level switched-capacitor multilevel inverter (SCMLI) with 2.5 times boosting feature
is presented in this paper. It can produce an 11-level output voltage waveform by utilizing 14 switches,
3 capacitors, 2 diodes, and 1 DC source. Only nine driver circuits are needed as the topology has
three pairs of complementary switches and two bidirectional switches. It has inherent capacitor
self-balancing property as the capacitors are connected across the DC voltage source during several
states within a fundamental cycle to charge the capacitors to the input voltage. A detailed comparison
shows the effectiveness of the proposed topology in terms of the number of switches, number of
capacitors, number of sources, total standing voltage (TSV), efficiency, and boosting ability with the
state-of-art recently proposed circuits. Subsequently, the performance of the proposed SCMLI is
Citation: Hussan, M.R.; Sarwar, A.;
validated experimentally utilizing the nearest level control (NLC), a fundamental frequency-based
Khan, I.; Tariq, M.; Tayyab, M.;
switching technique.
Alhosaini, W. An Eleven-Level
Switched-Capacitor Inverter with
Boosting Capability. Electronics 2021,
Keywords: multilevel inverter; nearest level control; switched-capacitor circuits; voltage boosting
10, 2262. https://doi.org/10.3390/
electronics10182262
Topologies having a single DC source are more attractive because of their lower cost.
A nine-level inverter is proposed in [1], which utilizes 10 switches and 3 capacitors for
producing output voltage with no voltage boosting. A nine-level output voltage with a
voltage boosting of two has been developed in [3], using two capacitors, one bidirectional
switch, and nine unidirectional switches. The authors of [4,15] reduced the number of
switches to eight to obtain a nine-level output voltage with a boosting of 2 times. Even
though the device components are reduced, the total standing voltage (TSV) is high for
the circuit. An 11-level inverter was proposed in [16] using twelve switches and a total
of five capacitors using an auxiliary circuit for the complex control logic. For the same
number of levels, the authors of [17] reduced the number of switches to 10, but it requires
a large number of capacitors and diodes (nine capacitors and nine diodes). Eleven-level
inverters having three DC sources are proposed in [18,19], which have eight and three
switches, respectively. Switches have been reduced, but the TSV is high, and there is no
voltage boosting. In this paper, an 11-level SCMLI topology is proposed to have 2.5 times
voltage boosting with reduced component count and reduced TSV. The maximum voltage
stress on the switches is restricted to twice the input voltage. In the proposed circuit,
10 unidirectional switches and 2 bidirectional switches are used. Three pairs of switches
are complementary in nature, as a result of which a simplified control logic is used. A
simple NLC-based algorithm is used to obtain the switching pulses for IGBTs employed in
the proposed circuit. All three capacitors have self-voltage-balancing property. Negative
voltage levels are obtained without using H-bridge.
The circuit of the proposed topology, its operating principle with NLC, and the
fundamental frequency-based switching scheme are given in detail. Hardware results
are provided to verify the performance of the proposed SCMLI. A detailed comparison
is carried out to justify the merits of the proposed topology against the other recently
published topologies.
Figure 1. Proposed topology: (a) circuit diagram; (b) 11-level output voltage.
through reverse body diode. The capacitors are connected in the circuit in such a way that
they are self-balanced and are charged to the extent that desired output voltage levels are
obtained. The capacitors C1 and C2 are charged to Vdc /2, and the capacitor C3 is charged
to Vdc to obtain the 11 output voltage levels as 0, ±Vdc /2, ±Vdc , ±3 Vdc /2, ±2 Vdc , and
±5 Vdc /2.
Table 1. Switching table and capacitor states for the proposed 11-level inverter.
Figure 2. All the conduction states of the proposed topology: (a) zero output voltage; (b–f) positive half-cycle; (g–k) negative
half-cycle.
Electronics 2021, 10, 2262 5 of 13
The largest discharging period for C3 is [t5 , T/2 − t5 ]. Hence, the maximum discharg-
ing amount during this interval can be expressed as
T −t
1
Z 5
2
∆QC3 = i L (t) dt (2)
2π f t5
From Equations (1) and (2), the values of C1 , C2 , and C3 can be calculated as
∆QC1,2 1
Z T −t
2 3
C1 = C2 = = i L (t) dt (3)
∆VC1,2 2π f × ∆VC1,2 t3
∆QC3
T −t
1
Z 5
2
C3 = = i L (t) dt (4)
∆VC3 2π f × ∆VC3 t5
Electronics 2021, 10, 2262 6 of 13
Thus, by taking maximum allowable ripple voltage (∆V c ) equal to 10% of the corre-
sponding capacitor voltage, the solution of Equations (3) and (4) give the optimum value
of all the capacitors.
3
Cn
PR = ∑ 2
(∆VCn )2 ×f (5)
n =1
where n is the number of capacitors present in the circuit, f is the fundamental frequency,
and ∆VCn is the capacitor voltage ripple of the nth capacitor. ∆VCn can also be obtained
from the following equation:
Z t
1
∆VCn = iCn (t)dt (6)
Cn 0
where duration [0, t] is the largest discharging period and iC is the capacitor charging current.
where IO is the load current; Rs is the on-state switch resistance; Rd is the diode resistance;
Rc is the internal resistance of the capacitor; and n, m, and p are the numbers of switches,
diodes, and capacitors present in the conduction path of the corresponding level.
where I is the current flowing through the switch during the turn-on time, I 0 is the current
flowing through the switch during the turn-off time, ‘f ’ is the switching frequency, and
VS is the withstanding voltage of the switch. Total switching loss of the topology can be
Electronics 2021, 10, 2262 7 of 13
calculated by multiplying the number of the on (Non ) switching states and number of the
off switching states (No f f ) in one complete cycle with (8) and (9), resulting in (10):
14 Non No f f
PS = ∑ ∑ PS,on,km + ∑ PS,o f f ,km (10)
k =1 m =1 m =1
Figure 4. Nearest level control: (a) level generation method; (b) working of NLC.
Electronics 2021, 10, 2262 8 of 13
3. Comparative Analysis
Comparison of the proposed 11-level inverter with recently published 11-level topolo-
gies was carried out in order to show its advantages over these topologies. The detailed
comparison is shown in Table 2 on the basis of the number of switches (Nsw ), number of
diodes (Nd ), number of DC sources (Ndc ), number of capacitors (Nc ), the voltage gain of
the converter, TSVpu , and efficiency (η). Total standing voltage (TSV) is the sum of all the
maximum voltage stresses across all the switches. It is the deciding factor for the voltage
rating of the switches to be used in the topology. TSVpu is the ratio of TSV to the peak
value of AC output voltage. The proposed topology and the one presented in [16] have the
minimum TSVpu . The proposed topology needs 14 IGBTs, but as it has two bidirectional
switches and six unidirectional switches, the number of drivers required is reduced to nine.
Among single DC source topologies, that presented in [16] has fewer switches than the
proposed one, but it uses five capacitors as compared to three in the proposed topology.
Further, it has no voltage-boosting ability. Only the proposed topology has the boosting
feature with a gain of 2.5. Topologies presented in [18,21] use three DC sources, while
the topology presented in [22] uses two DC sources. In terms of efficiency, the proposed
topology stands better than these topologies except that of [16]. The efficiency of the
proposed topology is quite high at 96.75%.
Figure 5. Output voltage and current waveforms of the proposed 11-level inverter for (a) resistive
load of 50 Ω, (b) RL load (R = 50 Ω, L = 120 mH), (c) dynamic load change from R = 50 Ω to R = 100 Ω
and L = 120 mH, and (d) change in modulation from M = 1.0 to M = 0.8 to M = 0.6.
Electronics 2021, 10, 2262 10 of 13
Figure 7. Output voltage and current waveform of the proposed 11-level inverter for (a) resistive load of 50 Ω, (b) dynamic
load change from no load to 60 Ω to 30 Ω, (c) dynamic load change from 60 Ω–50 mH to 50 Ω–50 mH, (d) change in modu-
lation from M = 1.0 to M = 0.8 to M = 0.6, (e) THD of the output voltage, and (f) efficiency in different loading conditions.
Electronics 2021, 10, 2262 12 of 13
5. Conclusions
A switched-capacitor MLI topology with the detailed operating principle and circuit
analysis is proposed. It has 2.5 times voltage boosting, and the maximum voltage stress
across the switches is restricted to twice the input voltage, which results in reduced TSV
of the proposed inverter. All the capacitors are self-balanced, which simplifies the control
complexity. A simple fundamental modulation technique, i.e., NLC, is implemented to
generate the gating pulses for IGBTs. Hardware results validate the performance of the
proposed topology under different dynamic loading conditions. A thorough comparison
reflects the efficacy of the proposed topology over the recently published 11-level topologies.
The output voltage THD of the proposed inverter is 8.6%. The maximum efficiency achieved
for the converter is 96.75%.
Author Contributions: Conceptualization, M.R.H., A.S., M.T. (Mohd Tariq), and M.T. (Mohammad
Tayyab); formal analysis, M.R.H., A.S., I.K., M.T. (Mohd Tariq), and M.T. (Mohammad Tayyab);
funding acquisition, M.T. (Mohd Tariq) and W.A.; investigation, M.R.H., A.S., I.K., M.T. (Mohd Tariq),
M.T. (Mohammad Tayyab), and W.A.; methodology, M.R.H., A.S., I.K., M.T. (Mohd Tariq), M.T.
(Mohammad Tayyab) and W.A.; project administration, M.T. (Mohd Tariq) and W.A.; supervision:
A.S. and M.T. (Mohd Tariq); writing—original draft, M.R.H. and A.S.; writing—review and editing,
I.K., M.T. (Mohd Tariq), M.T. (Mohammad Tayyab), and W.A. All authors have read and agreed to
the published version of the manuscript.
Funding: The authors extend their appreciation to the Deputyship for Research Innovation, Ministry
of Education in Saudi Arabia, for funding this work through the project number “375213500”.
The authors acknowledge the financial support provided from the Collaborative Research Grant
Scheme (CRGS) Project CRGS/MOHD TARIQ/01 and CRGS/MOHD TARIQ/02 sponsored by the
Capability Systems Centre, UNSW, Canberra, to the Hardware-In-the-Loop (HIL) Lab, Department
of Electrical Engineering, Aligarh Muslim University, India, and the technical support provided by
the Non-Conventional Energy (NCE) Lab, Department of Electrical Engineering, Aligarh Muslim
University, India.
Data Availability Statement: Not applicable.
Conflicts of Interest: The authors declare no conflict of interest.
Electronics 2021, 10, 2262 13 of 13
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