3932 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO.

8, AUGUST 2014

A New General Topology for Cascaded Multilevel

Inverters With Reduced Number of Components
Based on Developed H-Bridge
Ebrahim Babaei, Member, IEEE, Somayeh Alilu, and Sara Laali, Student Member, IEEE

Abstract—In this paper, a new general cascaded multilevel is one of the most important features in determining the cost
inverter using developed H-bridges is proposed. The proposed of the inverter. On the other hand, because some of them use a
topology requires a lesser number of dc voltage sources and power high number of bidirectional power switches, a high number of
switches and consists of lower blocking voltage on switches, which
results in decreased complexity and total cost of the inverter. insulated gate bipolar transistors (IGBTs) are required, which
These abilities obtained within comparing the proposed topology is the main disadvantage of these topologies. An asymmetric
with the conventional topologies from aforementioned points of topology has been presented in [16]. The main disadvantage
view. Moreover, a new algorithm to determine the magnitude of of this structure is related to its bidirectional power switches,
dc voltage sources is proposed. The performance and functional which cause an increase in the number of IGBTs and the
accuracy of the proposed topology using the new algorithm in
generating all voltage levels for a 31-level inverter are confirmed total cost of the inverter. In [15], a new topology with three
by simulation and experimental results. algorithms have been presented, which reduce the number of
required power switches but increase the variety of dc voltage
Index Terms—Cascaded multilevel inverter, developed
H-bridge, multilevel inverter, voltage source inverter. sources. In [1], [4] and [17], and [18], several algorithms
for determining the magnitudes of dc voltage sources for the
I. I NTRODUCTION conventional cascaded multilevel inverter have been presented.
The major advantage of this topology and its algorithms is
N OWADAYS, multilevel inverters have received more at-
tention for their ability on high-power and medium-
voltage operation and because of other advantages such as high
related to its ability to generate a considerable number of output
voltage levels by using a low number of dc voltage sources
and power switches but the high variety in the magnitude of
power quality, lower order harmonics, lower switching losses,
dc voltage sources is their most remarkable disadvantage.
and better electromagnetic interference [1], [2]. These inverters
In this paper, in order to increase the number of output
generate a stepped voltage waveform by using a number of dc
voltage levels and reduce the number of power switches, driver
voltage sources as the input and an appropriate arrangement of
circuits, and the total cost of the inverter, a new topology of
the power-semiconductor-based devices [3].
cascaded multilevel inverters is proposed. It is important to
Three main structures of the multilevel inverters have been
note that in the proposed topology, the unidirectional power
presented: “diode clamped multilevel inverter,” “flying capaci-
switches are used. Then, to determine the magnitude of the
tor multilevel inverter,” and “cascaded multilevel inverter” [4].
dc voltage sources, a new algorithm is proposed. Moreover,
The cascaded multilevel inverter is composed of a number of
the proposed topology is compared with other topologies from
single-phase H-bridge inverters and is classified into symmetric
different points of view such as the number of IGBTs, number
and asymmetric groups based on the magnitude of dc voltage
of dc voltage sources, the variety of the values of the dc
sources. In the symmetric types, the magnitudes of the dc volt-
voltage sources, and the value of the blocking voltages per
age sources of all H-bridges are equal while in the asymmetric
switch. Finally, the performance of the proposed topology in
types, the values of the dc voltage sources of all H-bridges are
generating all voltage levels through a 31-level inverter is
different.
confirmed by simulation using power system computer aided
In recent years, several topologies with various control tech-
design (PSCAD) software and experimental results.
niques have been presented for cascaded multilevel inverters
[5]–[8]. In [4] and [9]–[15], different symmetric cascaded mul-
tilevel inverters have been presented. The main advantage of all II. P ROPOSED T OPOLOGY
these structures is the low variety of dc voltage sources, which In Fig. 1, two new topologies are proposed for a seven-level
inverter [19]. As shown in Fig. 1, the proposed topologies are
Manuscript received February 18, 2013; revised June 8, 2013; accepted obtained by adding two unidirectional power switches and one
August 4, 2013. Date of publication October 21, 2013; date of current version dc voltage source to the H-bridge inverter structure. In other
February 7, 2014.
The authors are with the Faculty of Electrical and Computer Engineer- words, the proposed inverters are comprised of six unidirec-
ing, University of Tabriz, Tabriz 51664, Iran (e-mail: e-babaei@tabrizu.ac.ir; tional power switches (Sa , Sb , SL,1 , SL,2 , SR,1 , and SR,2 ) and
somaieh_alilu_s@yahoo.com; s.laali@tabrizu.ac.ir). two dc voltage sources (VL,1 and VR,1 ). In this paper, these
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. topologies are called developed H-bridge. As shown in Fig. 1,
Digital Object Identifier 10.1109/TIE.2013.2286561 the simultaneous turn-on of SL,1 and SL,2 (or SR,1 and SR,2 )

0278-0046 © 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
BABAEI et al.: TOPOLOGY FOR CASCADED MULTILEVEL INVERTERS WITH REDUCED NUMBER OF COMPONENTS 3933

Fig. 1. Proposed seven-level inverters. (a) First proposed topology. (b) Second
proposed topology. Fig. 2. Proposed 31-level inverter.
TABLE I
O UTPUT VOLTAGES OF THE P ROPOSED S EVEN -L EVEL I NVERTERS

Fig. 3. Proposed 127-level inverter.

causes the voltage sources to short-circuit. Therefore, the si-

multaneous turn-on of the mentioned switches must be avoided.
In addition, Sa and Sb should not turn on, simultaneously. The
difference in the topologies illustrated in Fig. 1 is in the connec-
tion of the dc voltage sources polarity. Table I shows the output
voltages of the proposed inverters for different states of the
switches. In this table, 1 and 0 indicate the ON- and OFF-states
of the switches, respectively. As it is obvious from Table I, if
the values of the dc voltage sources are equal, the number of
voltage levels decreases to three. Therefore, the values of dc
voltage sources should be different to generate more voltage
levels without increasing the number of switches and dc voltage
sources. Considering Table I, to generate all voltage levels (odd
and even) in the proposed topology shown in Fig. 1(a), the
magnitudes of VL,1 and VR,1 should be considered 3pu and
1pu, respectively. Similarly, for the topology shown in Fig. 1(a),
the magnitudes of VL,1 and VR,1 should be considered 2pu and Fig. 4. Proposed general topology.
1pu, respectively. Considering the aforementioned explana-
consists of 14 unidirectional power switches and 6 dc voltage
tions, the total cost of the proposed topology in Fig. 1(b) is low
sources. Similarly, by developing the proposed basic topology,
because dc voltage sources with low magnitudes are needed.
a general topology, as shown in Fig. 4, can be proposed. The
By developing the seven-level inverter shown in Fig. 1(b),
general topology consists of 2n dc voltage sources (n is the
the 31-level inverter shown in Fig. 2 can be proposed. This
number of the dc voltage sources on each leg) and 4n + 2
topology consists of ten unidirectional power switches and four
unidirectional power switches.
dc voltage sources. According to Fig. 2, if the power switches of
In the proposed general topology, the number of output
(SL,1 , SL,2 ), (SL,3 , SL,4 ), (SR,1 , SR,2 ), and (SR,3 , SR,4 ) turn
voltage levels (Nstep ), number of switches (Nswitch ), number
on simultaneously, the dc voltage sources of VL,1 , VL,2 , VR,1 ,
of dc voltage sources (Nsource ), and the maximum magnitude
and VR,2 will be short-circuited, respectively. Therefore, the
of the generated voltage (Vo,max ) are calculated as follows,
simultaneous turn-on of these switches should be avoided. In
respectively:
addition, Sa and Sb should not turn on simultaneously. It is
important to note that the 31-level topology can be provided Nstep = 22n+1 − 1 (1)
through the structure presented in Fig. 1(a), where the only dif-
Nswitch = 4n + 2 (2)
ference will be in the polarity of the applied dc voltage sources.
By developing the proposed 31-level inverter, a 127-level Nsource = 2n (3)
inverter can be proposed as shown in Fig. 3. This topology Vo,max = VL,n + VR,n . (4)
3934 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 8, AUGUST 2014

The other important parameters of the total cost of a mul- III. P ROPOSED A LGORITHM TO D ETERMINE THE
tilevel inverter for evaluation are the variety of the values of M AGNITUDES OF DC VOLTAGE S OURCES
dc voltage sources and the value of the blocking voltage of the
In this paper, the following algorithm is applied to determine
switches. As the variety of dc voltage sources and the value of
the magnitude of dc voltage sources. It is important to note that
the blocking voltage of the switches are low, the inverter’s total
all voltage levels (even and odd) can be generated.
cost decreases [20]. The number of variety of the values of dc
voltage sources (Nvariety ) is given by
A. Proposed Seven-Level Inverter
Nvariety = 2n. (5)
The magnitudes of the dc voltage sources of the seven-level
The following pattern is utilized to calculate the maximum inverter shown in Fig. 1(b) are determined as follows:
magnitude of the blocking voltage of the power switches. As
shown in Fig. 1(b), the blocking voltage of SR,1 and SR,2 are VL,1 = Vdc (17)
calculated as follows: VR,1 = 2Vdc . (18)
VSR,1 = VSR,2 = VR,1 (6) Considering (17), (18), and Table I, the proposed seven-level
inverter can generate 0, ±Vdc , ±2Vdc , and ±3Vdc at output.
where VSR,1 and VSR,2 indicate the maximum blocking volt-
ages of SR,1 and SR,2 , respectively.
The blocking voltage of SL,1 and SL,2 are as follows: B. Proposed 31-Level Inverter

VSL,1 = VSL,2 = VL,1 (7) The magnitudes of the dc voltage sources of the proposed
31-level inverter are recommended as follows:
where VSL,1 and VSL,2 indicate the maximum blocking voltages
of SL,1 and SL,2 , respectively. VL,1 = Vdc (19)
Therefore, the maximum blocking voltage of all switches VR,1 = 2Vdc (20)
in the proposed seven-level inverter (Vblock,1 ) is calculated as VL,2 = 5Vdc (21)
follows:
VR,2 = 10Vdc . (22)
Vblock,1 = VSR,1 + VSR,2 + VSL,1 + VSL,2 + VSa + VSa
The proposed inverter can generate all negative and positive
= 4(VR,1 + VL,1 ). (8) voltage levels from 0 to 15Vdc with steps of Vdc .

Considering Fig. 2, the maximum blocking voltage of the

switches is as follows: C. Proposed 127-Level Inverter
The magnitudes of the dc voltage sources of the proposed
VSR,1 = VSR,2 = VR,1 (9)
127-level inverter are calculated as follows:
VSR,3 = VSR,4 = VR,2 − VR,1 (10)
VL,1 = Vdc (23)
VSL,1 = VSL,2 = VL,1 (11) VR,1 = 2Vdc (24)
VSL,3 = VSL,4 = VL,2 − VL,1 (12) VL,2 = 5Vdc (25)
VSa = VSb = VR,2 + VL,2 . (13) VR,2 = 10Vdc (26)

Therefore, the maximum blocking voltage of all switches of the VL,3 = 25Vdc (27)
proposed 31-level inverter (Vblock,2 ) is as follows: VR,3 = 50Vdc . (28)
Vblock,2 = VSR,1 + VSR,2 + VSR,3 + VSR,4 + VSL,1 + VSL,2 By using this algorithm, the inverter can generate all negative
+ VSL,3 + VSL,4 + VSa + VSb and positive voltage levels from 0 to 63Vdc with steps of Vdc .

= 4(VR,2 + VL,2 ). (14)

D. Proposed General Multilevel Inverter
Similarly, the maximum blocking voltage of all switches of the The magnitudes of the dc voltage sources of the proposed
127-level inverter is calculated as follows: general multilevel inverter can be obtained as follows:
Vblock,3 = 4(VR,3 + VL,3 ). (15) VL,j = 5j−1 Vdc for j = 1, 2, 3, . . . , n (29)
Finally, the maximum blocking voltage of all the switches of VR,j = 2 × 5j−1 Vdc for j = 1, 2, 3, . . . , n. (30)
the general topology (Vblock,n ) is calculated as follows:
Considering (4) and (16), the values of Vo,max and Vblock,n
Vblock,n = 4(VR,n + VL,n ). (16) of the proposed general multilevel inverter are as follows,
BABAEI et al.: TOPOLOGY FOR CASCADED MULTILEVEL INVERTERS WITH REDUCED NUMBER OF COMPONENTS 3935

respectively: where f is the fundamental frequency and Non,k and Noff,k

are the numbers of turn-on and turn-off of the switch k during
Vo,max = VL,n + VR,n = 3 × 5n−1 Vdc (31) a fundamental cycle. Also, Eon,ki is the energy loss of the
Vblock,n = 4(VL,n + VR,n ) = 12(5n−1 )Vdc . (32) switch k during the ith turn-on and Eoff,ki is the energy loss
of the switch k during the ith turn-off.
The total loss (Ploss ) of the multilevel converter is the sum
of the conduction and switching losses as follows:
IV. C ALCULATION OF L OSSES
Ploss = Pc + Psw . (39)
Mainly, two kinds of losses (i.e., conduction and switching
losses) are associated with the switches. Since the switches Finally, the efficiency (η) of the inverter is calculated as
include IGBTs and diodes, the conduction losses of an IGBT follows:
(pc,IGBT (t)) and a diode (pc,D (t)) are calculated as follows,
respectively [7], [22]: Pout Pout
η= = (40)
  Pin Pout + Ploss
pc,IGBT (t) = VIGBT + RIGBT iβ (t) i(t) (33)
where Pout and Pin denote the output and input powers of the
pc,D (t) = [VD + RD i(t)] i(t) (34) inverter.

where VIGBT and VD are the forward voltage drops of the IGBT
and diode, respectively. RIGBT and RD are the equivalent V. C OMPARING THE P ROPOSED G ENERAL T OPOLOGY
resistances of the IGBT and diode, respectively, and β is a W ITH THE C ONVENTIONAL T OPOLOGIES
constant related to the specification of the IGBT. In order to clarify the advantages and disadvantage of the
Considering that at instant t, there are NIGBT transistors proposed topology, it should be compared with the different
and ND diodes in the current path, the average value of the kinds of topologies presented in literature. In [4], the con-
conduction power loss (Pc ) of the multilevel inverter can be ventional cascaded multilevel inverter with two different algo-
written as follows: rithms has been presented. These algorithms are known as the
2π symmetric cascaded multilevel inverters and the asymmetric
1 ones with the binary method for determining the magnitude
Pc = [NIGBT (t)pc,T (t) + ND (t)pc,D (t)] dt. (35)
2π of dc voltage sources. In the comparison, the conventional
0
symmetric cascaded multilevel inverter is indicated by R1
The switching losses are calculated based on the energy and the conventional binary asymmetric cascaded multilevel
loss calculation. The switching losses occur during the turn-off inverter is shown by R2 . Three other algorithms have been
and turn-on periods. For simplicity, the linear variations of the presented for this topology in [1], [17], and [18], which are
voltage and current of the switches in the switching period are indicated by R3 –R5 , respectively. Moreover, another topology
considered. Based on this assumption, the following relations with three different algorithms for determining the value of
can be written [7], [22]: dc voltage sources have been introduced in [15], which are
shown by R13 –R15 in this comparison. In [9]–[12], four dif-
toff ferent structures for the cascaded multilevel inverter have been
1
Eoff,k = v(t)i(t)dt = Vsw,k I toff (36) presented, and in this paper, they are indicated by R6 –R7 and
6
0 R11 –R12 . It is important to note that the power switches in the
ton aforementioned topologies are unidirectional. In addition, other
1 topologies based on bidirectional switches have been presented
Eon,k = v(t)i(t)dt = Vsw,k I  ton (37)
6 in [13] and [14]. In [14], three different algorithms have been
0 recommended, which are denoted as R8 –R10 , and the presented
where Eoff,k and Eon,k are the turn-off and turn-on losses of topology in [13] is indicated by R16 in this comparison. Fig. 5
the switch k, respectively. toff and ton are the turn-off and turn- shows all of the aforementioned structures.
on times of the switch, respectively, I is the current through the Fig. 6 compares the number of IGBTs of the proposed
switch before turning off, I  is the current through the switch general topology with the aforementioned cascaded multilevel
after turning on, and Vsw,k is the OFF-state voltage on the inverters. It is obvious that the proposed inverter requires a
switch. lesser number of IGBTs in comparison with the other men-
The switching power loss (Psw ) is equal to the sum of tioned topologies to generate particular levels.
all turn-on and turn-off energy losses in a fundamental cy- Fig. 7 compares the number of dc voltage sources of the
cle of the output voltage. This can be written as follows proposed inverter with the aforementioned cascaded multilevel
[7], [22]: inverter. As shown in Fig. 7, the proposed inverter has better
⎛ ⎞ performance in comparison with the other presented topologies
N
switch 
Non,k

Noff,k except the topology presented in R3 . However, the magnitude
Psw = f ⎝ Eon,ki + Eoff,ki ⎠ (38) of the dc voltage sources in R3 is a little more than that of the
k=1 i=1 i=1 proposed topology.
3936 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 8, AUGUST 2014

Fig. 5. Cascaded multilevel inverters presented in literature: (a) Conventional cascaded multilevel inverters R1 for V1 = V2 = · · · = Vn = Vdc , R2 for
V1 = 2j−1 Vdc (j = 1, 2, . . . , n), R3 for V1 = 3j−1 Vdc (j = 1, 2, . . . , n), R4 for V1 = 0.5V2 = 0.5V3 = · · · = 0.5Vn = Vdc , and R5 for V1 = V2 /3 =
V3 /3 = · · · = Vn /3 = Vdc . (b) Presented topology in [12], namely, R12 for V1 = V2 = · · · = Vn = Vdc . (c) Presented topology in [10], i.e., R7 for
V1 = V2 = · · · = Vn = Vdc . (d) Presented topology in [9], i.e., R6 for V1 = V2 = · · · = Vn = Vdc . (e) Presented topologies in [14], i.e., R8 for V1 = V2 =
· · · = Vn = Vdc , R9 for V1 = 0.5V2 = 0.5V3 = · · · = 0.5Vn = Vdc , and R10 for V1 = 2j−1 Vdc (j = 1, 2, . . . , n). (f) Presented topologies in [15], i.e.,
R13 for V1 = V2 = · · · = Vn = Vdc , R14 for V1 = 2j−1 Vdc (j = 1, 2, . . . , n), and R15 for V1 = 0.5V2 = 0.5V3 = · · · = 0.5Vn = Vdc . (g) Presented
topology in [13], i.e., R16 for V1 = V2 = · · · = Vn = Vdc . (h) Presented topology in [11], i.e., R11 for V1 = V2 = · · · = Vn = Vdc .

Fig. 6. Variation of NIGBT versus Nstep .

Fig. 8. Variation of Nvariety versus Nstep .

inverter uses a wider variety of magnitudes of the dc voltage

sources in comparison with those of all the aforementioned
topologies. This feature is the most important disadvantage
of the proposed topology because the variety of the values
of dc voltage sources is as one of the remarkable factors in
determining the cost of the inverter. However, this feature in the
proposed topology is similar to the presented topologies of R2
and R14 .
Fig. 9 compares the magnitude of the blocking voltage of
Fig. 7. Variation of Nsource versus Nstep . the switches of the proposed inverter with that of the afore-
mentioned cascaded multilevel inverter. This figure shows the
Fig. 8 compares the variety of magnitudes of the dc voltage reduction of the magnitude of the blocking voltage of the
sources of the proposed inverter with that of the aforemen- proposed inverter in comparison with those of all the aforemen-
tioned cascaded multilevel inverter. Obviously, the proposed tioned multilevel inverters.
BABAEI et al.: TOPOLOGY FOR CASCADED MULTILEVEL INVERTERS WITH REDUCED NUMBER OF COMPONENTS 3937

Fig. 9. Variation of Vblock versus Nstep .

Fig. 10. Photograph of the experimental setup.
TABLE II
O UTPUT VOLTAGES OF THE P ROPOSED 31-L EVEL I NVERTER

Fig. 11. Proposed 31-level inverter. (a) Output voltage waveform. (b) Output
current waveform.

inverter. The simulation is done by using PSCAD software, and

the practical prototype is made in the experimental environ-
ment. Fig. 10 shows the experimental setup. It is important to
note that the IGBTs used in the prototype are HGTP10N40CID
(with an internal antiparallel diode) with the voltage and current
ranges of 400 V and 10 A, respectively. The 89C52 micro-
controller by ATMEL Company has been used to generate
all switching patterns. In all processes of the simulation and
experiment, the load is assumed as R–L with R = 45Ω and
L = 55 mH. Moreover, the magnitude of VL,1 is considered
15 V, so based on (29) and (30), the magnitudes of the other
dc voltage sources will be 30, 75, and 150 V, which are
related to VR,1 , VL,2 , and VR,2 , respectively. According to (31),
the maximum output voltage of this inverter will be 225 V.
In this paper, the fundamental frequency switching control
method has been used [21]. In this method, the sinusoidal
reference voltage is compared with the available dc voltage
levels and the level that is nearest to the reference voltage
is chosen [22]. The main advantage of this control method
is related to its low switching frequency, which is leads to
reduction of switching losses.
The simulated output voltage and current waveforms are
shown in Fig. 11. As Fig. 11(a) shows, the proposed topology
is able to generate 31 levels (15 positive levels, 15 negative
levels, and 1 zero level) with the maximum voltage of 225 V.
Comparing the output voltage and current waveforms indicates
that the output current waveform is more similar to the ideal
sinusoidal waveform than the output voltage because the R–L
load acts as a low-pass filter. In addition, there is a phase
difference between the output voltage and current waveforms,
which is caused by the inductive feature of the load. The
VI. S IMULATION AND E XPERIMENTAL R ESULTS
total harmonic distortions of the output voltage and current
In order to verify the correct performance of the proposed are equal to 0.94% and 0.19%, respectively. Fig. 12(a) and (b)
multilevel inverter in generating all output voltage levels (even shows the harmonic spectrum of the output voltage and current,
and odd), a 31-level inverter based on the topology shown respectively. The figure shows that the magnitudes of harmonics
in Fig. 2 has been used for the simulation and experimental of both voltage and current waveforms are low. However, the
prototypes. Table II shows the switching states of the 31-level harmonics of the current waveform are lower than the voltage
3938 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 8, AUGUST 2014

Fig. 12. Harmonic spectrum of (a) output voltage and (b) current.

waveform. It is important to note that in Fig. 12, in order

to show the magnitudes of the fundamental and high-order Fig. 13. Voltages of switches (a) SL,1 , (b) SL,2 , (c) SL,3 , (d) SL,4 , and
harmonics, the scale of the vertical axis is considered nonlinear. (e) Sa .
In the test condition, the measured input and output powers are
about 1203 and 1112 W, respectively. Therefore, the efficiency
is about 92.4%. Based on the loss calculations given before, the
power loss is about 86 W. Therefore, the calculated loss has a
good accordance with the measured efficiency.
As mentioned before, the power switches in the proposed
topology are unidirectional from the voltage viewpoint. In order
to prove this issue, the voltages on the switches of a single leg
of the inverter (i.e., SL,1 , SL,2 , SL,3 , SL,4 , and Sa ) are shown
in Fig. 13. As can be seen, the maximum blocking voltage by
switches SL,1 , SL,2 , SL,3 , SL,4 , and Sa are equal to 15, 15, 60,
60, and 225 V, respectively. Obviously, the voltage values are
zero or equal to the positive ones, which is well in accordance
to the unidirectional feature of the switches from the voltage
viewpoint. Considering the magnitude of the blocking voltage
of the switches, the relations associated to the maximum volt-
age drop of the switches are well confirmed. Fig. 14 shows the
experimental results of the implemented inverter. It is important
to note that there is a good agreement between the experimental
and simulation results.

VII. C ONCLUSION
In this paper, two basic topologies have been proposed for
multilevel inverters to generate seven voltage levels at the
output. The basic topologies can be developed to any number of
levels at the output where the 31-level, 127-level, and general
topologies are consequently presented. In addition, a new algo- Fig. 14. Experimental results: (a) Output voltage and output current voltage;
rithm to determine the magnitude of the dc voltage sources has (b) SL,1 ; (c) SL,2 ; (d) SL,3 ; (e) SL,4 ; and (f) Sa .
been proposed. The proposed general topology was compared
with the different kinds of presented topologies in literature than that of conventional topologies. However, the proposed
from different points of view. According to the comparison re- topology has a higher number of variety of dc voltage sources
sults, the proposed topology requires a lesser number of IGBTs, in comparison with the others. The performance accuracy of the
power diodes, driver circuits, and dc voltage sources. Moreover, proposed topology was verified through the PSCAD simulation
the magnitude of the blocking voltage of the switches is lower and the experimental results of a 31-level inverter.
BABAEI et al.: TOPOLOGY FOR CASCADED MULTILEVEL INVERTERS WITH REDUCED NUMBER OF COMPONENTS 3939

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[6] N. Abd Rahim, M. F. Mohamad Elias, and W. P. Hew, “Transistor-clamped in 1970. He received the B.S. and M.S. degrees in
H-bridge based cascaded multilevel inverter with new method of capacitor electrical engineering from the Department of Engi-
voltage balancing,” IEEE Trans. Ind. Electron., vol. 60, no. 8, pp. 2943– neering, University of Tabriz, Tabriz, Iran, in 1992
2956, Aug. 2013. and 2001, respectively, graduating with first class
[7] M. Farhadi Kangarlu and E. Babaei, “A generalized cascaded multilevel honors, and the Ph.D. degree in electrical engineer-
inverter using series connection of submultilevel inverters,” IEEE Trans. ing from the Department of Electrical and Computer
Power Electron., vol. 28, no. 2, pp. 625–636, Feb. 2013. Engineering, University of Tabriz, in 2007.
[8] S. R. Pulikanti, G. Konstantinou, and V. G. Agelidis, “Hybrid seven-level In 2004, he joined the Faculty of Electrical and
cascaded active neutral-point-clamped-based multilevel converter under Computer Engineering, University of Tabriz. He was
SHE-PWM,” IEEE Trans. Ind. Electron., vol. 60, no. 11, pp. 4794–4804, an Assistant Professor from 2007 to 2011 and has
Nov. 2013. been an Associate Professor since 2011. He is the author of more than
[9] Y. Hinago and H. Koizumi, “A single-phase multilevel inverter using 230 journal and conference papers. His current research interests include the
switched series/parallel dc voltage sources,” IEEE Trans. Ind. Electron., analysis and control of power electronic converters, power system transients,
vol. 57, no. 8, pp. 2643–2650, Aug. 2010. and power system dynamics.
[10] G. Waltrich and I. Barbi, “Three-phase cascaded multilevel inverter using
power cells with two inverter legs in series,” IEEE Trans. Ind. Appl.,
vol. 57, no. 8, pp. 2605–2612, Aug. 2010.
[11] W. K. Choi and F. S. Kang, “H-bridge based multilevel inverter using Somayeh Alilu was born in Khoy, Iran, in 1983. She
PWM switching function,” in Proc. INTELEC, 2009, pp. 1–5. received the B.S degree in electronics engineering
[12] E. Babaei, M. Farhadi Kangarlu, and F. Najaty Mazgar, “Symmetric from Islamic Azad University, Tabriz, Iran, in 2007
and asymmetric multilevel inverter topologies with reduced switching and the M.S degree in electrical engineering from the
devices,” Elect. Power Syst. Res., vol. 86, pp. 122–130, May 2012. Science and Research Branch, Islamic Azad Univer-
[13] J. Ebrahimi, E. Babaei, and G. B. Gharehpetian, “A new multilevel con- sity, Tehran, Iran, in 2013.
verter topology with reduced number of power electronic components,” She is currently with the Faculty of Electrical and
IEEE Trans. Ind. Electron., vol. 59, no. 2, pp. 655–667, Feb. 2012. Computer Engineering, University of Tabriz, Tabriz.
[14] E. Babaei, S. H. Hosseini, G. B. Gharehpetian, M. Tarafdar Haque, and
M. Sabahi, “Reduction of DC voltage sources and switches in asymmetri-
cal multilevel converters using a novel topology,” Elect. Power Syst. Res.,
vol. 77, no. 8, pp. 1073–1085, Jun. 2007.
[15] E. Babaei and S. H. Hosseini, “New cascaded multilevel inverter topology
with minimum number of switches,” Energy Convers. Manage., vol. 50, Sara Laali (S’12) was born in Tehran, Iran, in 1970.
no. 11, pp. 2761–2767, Nov. 2009. She received the B.S. degree in electronics engineer-
[16] S. Mekhilef and M. N. Kadir, “Voltage control of three-stage hybrid multi- ing from Islamic Azad University, Tabriz, Iran, in
level inverter using vector transformation,” IEEE Trans. Power Electron., 2008 and the M.S. degree in electrical engineering
vol. 25, no. 10, pp. 2599–2606, Oct. 2010. from Islamic Azad University, Tehran, Iran, in 2010.
[17] A. Rufer, M. Veenstra, and K. Gopakumar, “Asymmetric multilevel con- She is currently working toward the Ph.D. degree in
verter for high resolution voltage phasor generation,” presented at the electrical engineering in the Faculty of Electrical and
Proc. EPE, Lausanne, Switzerland, 1999. Computer Engineering, University of Tabriz, Tabriz.
[18] S. Laali, K. Abbaszades, and H. Lesani, “A new algorithm to determine In 2010, she joined the Department of Electri-
the magnitudes of dc voltage sources in asymmetrical cascaded multilevel cal Engineering, Adiban Higher Education Institute,
converters capable of using charge balance control methods,” in Proc. Semnan, Iran. Her major fields of interest include the
ICEMS, Incheon, Korea, 2010, pp. 56–61. analysis and control of power electronic converters.