Ci5 LM13700
Ci5 LM13700
Ci5 LM13700
LM13700
SNOSBW2F – NOVEMBER 1999 – REVISED NOVEMBER 2015
Connection Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM13700
SNOSBW2F – NOVEMBER 1999 – REVISED NOVEMBER 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 10
2 Applications ........................................................... 1 8 Application and Implementation ........................ 11
3 Description ............................................................. 1 8.1 Application Information............................................ 11
4 Revision History..................................................... 2 8.2 Typical Application ................................................. 11
8.3 System Examples ................................................... 12
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Power Supply Recommendations...................... 29
6.1 Absolute Maximum Ratings ..................................... 4 10 Layout................................................................... 29
6.2 Recommended Operating Conditions....................... 4 10.1 Layout Guidelines ................................................. 29
6.3 Thermal Information .................................................. 4 10.2 Layout Example .................................................... 29
6.4 Electrical Characteristics .......................................... 5 11 Device and Documentation Support ................. 30
6.5 Typical Characteristics .............................................. 6 11.1 Community Resources.......................................... 30
7 Detailed Description .............................................. 9 11.2 Trademarks ........................................................... 30
7.1 Overview ................................................................... 9 11.3 Electrostatic Discharge Caution ............................ 30
7.2 Functional Block Diagram ......................................... 9 11.4 Glossary ................................................................ 30
7.3 Feature Description................................................... 9 12 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
• Removed soldering information in Absolute Maximum Ratings table .................................................................................... 4
D or NFG Package
16-Pin SOIC or PDIP
Top View
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
Amp bias input 1, 16 A Current bias input
Buffer input 7, 10 A Buffer amplifier input
Buffer output 8, 9 A Buffer amplifier output
Diode bias 2, 15 A Linearizing diode bias input
Input+ 3, 14 A Positive input
Input– 4, 13 A Negative input
Output 5, 12 A Unbuffered output
V+ 11 P Positive power supply
V– 6 P Negative power supply
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage 36 VDC or ±18 V
DC input voltage +VS −VS V
Differential input voltage ±5 V
Diode bias current (ID) 2 mA
Amplifier bias current (IABC) 2 mA
Buffer output current (2) 20 mA
Power dissipation (3) TA = 25°C – LM13700N 570 mW
Output short circuit duration Continuous
Storage temperature, Tstg −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Buffer output current should be limited so as to not exceed package dissipation.
(3) For operation at ambient temperatures above 25°C, the device must be derated based on a 150°C maximum junction temperature and a
thermal resistance, junction to ambient, as follows: LM13700N, 90°C/W; LM13700M, 110°C/W.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(1) These specifications apply for VS = ±15 V, IABC = 500 μA, ROUT = 5-kΩ connected from the buffer output to −VS and the input of the
buffer is connected to the transconductance amplifier output.
Figure 5. Peak Output Voltage and Common Mode Range Figure 6. Leakage Current
Figure 9. Input Resistance Figure 10. Amplifier Bias Voltage vs. Amplifier Bias Current
Figure 11. Input and Output Capacitance Figure 12. Output Resistance
Figure 13. Distortion vs. Differential Input Voltage Figure 14. Voltage vs. Amplifier Bias Current
7 Detailed Description
7.1 Overview
The LM13700 is a two channel current controlled differential input transconductance amplifier with additional
output buffers. The inputs include linearizing diodes to reduce distortion, and the output current is controlled by a
dedicated pin. The outputs can sustain a continuous short to ground.
(1)
where VIN is the differential input voltage, kT/q is approximately 26 mV at 25°C and I5 and I4 are the collector
currents of transistors Q5 and Q4 respectively. With the exception of Q12 and Q13, all transistors and diodes are
identical in size. Transistors Q1 and Q2 with Diode D1 form a current mirror which forces the sum of currents I4
and I5 to equal IABC:
I4 + I5 = IABC (2)
where IABC is the amplifier bias current applied to the gain pin.
For small differential input voltages the ratio of I4 and I5 approaches unity and the Taylor series of the In function
is approximated as:
(3)
(4)
(5)
The term in brackets is then the transconductance of the amplifier and is proportional to IABC.
(6)
Since the diodes and the input transistors have identical geometries and are subject to similar voltages and
temperatures, the following is true:
(7)
Notice that in deriving Equation 7 no approximations have been made and there are no temperature-dependent
terms. The limitations are that the signal current not exceed ID / 2 and that the diodes be biased with currents. In
practice, replacing the current sources with resistors will generate insignificant errors.
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
-5
-15
-20
-25
-30
-35
-15 -10 -5 0 5 10 15
Control Voltage (V) D001
For optimum signal-to-noise performance, IABC should be as large as possible as shown by the Output Voltage vs
Amplifier Bias Current graph. Larger amplitudes of input signal also improve the S/N ratio. The linearizing diodes
help here by allowing larger input signals for the same output distortion as shown by the Distortion vs. Differential
Input Voltage graph. S/N may be optimized by adjusting the magnitude of the input signal via RIN (Figure 20) until
the output distortion is below the desired level. The output voltage swing can then be set at any level by selecting
RL.
Although the noise contribution of the linearizing diodes is negligible relative to the contribution of the amplifier's
internal transistors, ID should be as large as possible. This minimizes the dynamic junction resistance of the
diodes (re) and maximizes their linearizing action when balanced against RIN. A value of 1 mA is recommended
for ID unless the specific application demands otherwise.
(8)
If VC is derived from a second signal source then the circuit becomes an amplitude modulator or two-quadrant
multiplier as shown in Figure 23, where:
(9)
The constant term in the above equation may be cancelled by feeding IS × IDRC/2(V− + 1.4 V) into IO. The circuit
of Figure 24 adds RM to provide this current, resulting in a four-quadrant multiplier where RC is trimmed such that
VO = 0 V for VIN2 = 0 V. RM also serves as the load resistor for IO.
(10)
where gm ≈ 19.2IABC at 25°C. Note that the attenuation of VO by R and RA is necessary to maintain VIN within the
linear range of the LM13700 input.
Figure 27 shows a similar VCR where the linearizing diodes are added, essentially improving the noise
performance of the resistor. A floating VCR is shown in Figure 28, where each “end” of the “resistor” may be at
any voltage within the output voltage range of the LM13700.
Figure 36 shows how to build a VCO using one amplifier when the other amplifier is needed for another function.
The operation of the multiplexer of Figure 38 is very straightforward. When A1 is turned on it holds VO equal to
VIN1 and when A2 is supplied with bias current then it controls VO. CC and RC serve to stabilize the unity-gain
configuration of amplifiers A1 and A2. The maximum clock rate is limited to about 200 kHz by the LM13700 slew
rate into 150 pF when the (VIN1–VIN2) differential is at its maximum allowable value of 5 V.
The Phase-Locked Loop of Figure 39 uses the four-quadrant multiplier of Figure 24 and the VCO of Figure 36 to
produce a PLL with a ±5% hold-in range and an input sensitivity of about 300 mV.
The Schmitt Trigger of Figure 40 uses the amplifier output current into R to set the hysteresis of the comparator;
thus VH = 2 × R × IB. Varying IB will produce a Schmitt Trigger with variable hysteresis.
The Ramp-and-Hold of Figure 44 sources IB into capacitor C whenever the input to A1 is brought high, giving a
ramp-rate of about 1 V/ms for the component values shown.
The true-RMS converter of Figure 45 is essentially an automatic gain control amplifier which adjusts its gain such
that the AC power at the output of amplifier A1 is constant. The output power of amplifier A1 is monitored by
squaring amplifier A2 and the average compared to a reference voltage with amplifier A3. The output of A3
provides bias current to the diodes of A1 to attenuate the input signal. Because the output power of A1 is held
constant, the RMS value is constant and the attenuation is directly proportional to the RMS value of the input
voltage. The attenuation is also proportional to the diode bias current. Amplifier A4 adjusts the ratio of currents
through the diodes to be equal and therefore the voltage at the output of A4 is proportional to the RMS value of
the input voltage. The calibration potentiometer is set such that VO reads directly in RMS volts.
The circuit of Figure 46 is a voltage reference of variable Temperature Coefficient. The 100-kΩ potentiometer
adjusts the output voltage which has a positive TC above 1.2 V, zero TC at about 1.2 V, and negative TC below
1.2 V. This is accomplished by balancing the TC of the A2 transfer function against the complementary TC of D1.
The wide dynamic range of the LM13700 allows easy control of the output pulse width in the Pulse Width
Modulator of Figure 47.
For generating IABC over a range of 4 to 6 decades of current, the system of Figure 48 provides a logarithmic
current out for a linear voltage in.
Since the closed-loop configuration ensures that the input to A2 is held equal to 0 V, the output current of A1 is
equal to I3 = −VC/RC.
The differential voltage between Q1 and Q2 is attenuated by the R1,R2 network so that A1 may be assumed to
be operating within its linear range. From Equation 5, the input voltage to A1 is:
(11)
The voltage on the base of Q1 is then
(12)
The ratio of the Q1 and Q2 collector currents is defined by:
(13)
Combining and solving for IABC yields:
(14)
This logarithmic current is used to bias the circuit of Figure 22 to provide temperature independent stereo
attenuation characteristic.
10 Layout
1 2 2 1
V+ IBIAS1 ILIN2 V+
2 1 1 2
V+ IBIAS1 IBIAS2 V+
ILIN1
ILIN2
1 IBIAS1 16 IBIAS2
1 2 2 1
VIN1 VIN1+ VIN2+ VIN2
2 ILIN1 15 ILIN2
2 1 1 2
GND 3 VIN1+ 14 VIN2+ VIN2 VIN2+ GND GND
VIN1+
v+
1 2
2 1
4VIN1– 13 VIN2– VIN2– GND
GND VIN1–
GND
1 2 2 1 1
DARL1 5 DARL1 12 DARL2 DARL2DARL2 1
1 2 GND GND VIN2– GND
GND
GND VIN1–
DARL1
DARL2
1 2 v– 6 V– 11 V+ v+ 2 1
1 2
2 1 GND V– V+ GND VOUT2
VOUT1 VOUT2 VOUT2
VOUT1 VOUT1
GND 7 DARL1 10 DARL2
V– v+ v+ V+ GND
V–
VOUT1 8 VOUT1 9 VOUT2
v+
v+
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 14-Dec-2015
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 14-Dec-2015
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Oct-2015
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Oct-2015
Pack Materials-Page 2
MECHANICAL DATA
N0016E
NFG0016E
N16E (Rev G)
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