74 HCT 245
74 HCT 245
74 HCT 245
VCC
DIR
A bus to the B bus or from the B bus to the A bus,
OE
A2
A1
depending upon the logic level at the
direction-control (DIR) input. The output-enable 3 2 1 20 19
(OE) input can be used to disable the device so A3 4 18 B1
that the buses are effectively isolated. A4 5 17 B2
A5 6 16 B3
The SN54HCT245 is characterized for operation A6 7 15 B4
over the full military temperature range of –55°C A7 8 14 B5
to 125°C. The SN74HCT245 is characterized for 9 10 11 12 13
operation from –40°C to 85°C.
A8
B8
B7
B6
GND
FUNCTION TABLE
INPUTS
OPERATION
OE DIR
L L B data to A bus
L H A data to B bus
H X Isolation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright 1997, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
logic symbol†
19
OE G3
1
DIR 3 EN1 [BA]
3 EN2 [AB]
2 18
A1 1 B1
2
3 17
A2 B2
4 16
A3 B3
5 15
A4 B4
6 14
A5 B5
7 13
A6 B6
8 12
A7 B7
9 11
A8 B8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
1
DIR
19
OE
2
A1
18
B1
50 pF
tpd or tt –– or Open Open
150 pF
LOAD CIRCUIT
3V
Input 1.3 V 2.7 V 2.7 V
1.3 V
0.3 V 0.3 V 0 V
tr tf
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
3V Output 3V
Input 1.3 V 1.3 V Control
1.3 V 1.3 V
0V (Low-Level
Enabling) 0V
tPLH tPHL
tPZL tPLZ
In-Phase VOH ≈ VCC
90% 90% Output
Output 1.3 V 1.3 V Waveform 1 1.3 V
10% 10% V
OL (See Note B) 10% VOL
tr tf
tPHL tPLH tPZH
Out-of- VOH
90% 90% Output VOH
Phase 1.3 V 1.3 V 90%
Output 10% 10% Waveform 2 1.3 V
VOL (See Note B) ≈0V
tf tr tPHZ
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