B.SC Electronics - Digital Principles and Applications (.PDF) - Course Syllabus & Material - All Units (Bharathiar University)

SRI VASAVI COLLEGE, ERODE
(SELF FINANCE WING)
DEPARTMENT OF ELECTRONICS
Prepared By
Dr. S. KUMAR M.Sc., M.Phil., PGDCA., Ph.D.,
Assistant Professor of Electronics,
Sri Vasavi College (SF Wing),
Erode - 638 316.
SYLLABUS
DIGITAL PRINCIPLES AND APPLICATIONS
DIGITAL PRINCIPLES AND
Course code L T P C
APPLICATIONS
Core/Elective/Supportive Core Paper IV 4 0 0 4
Syllabus
Pre-requisite Basic Physics 2021-22
Version
Course Objectives:
The main objectives of this course are to:
 To acquire the basic knowledge of Number system, Digital logic circuits and its application
 To outline the formal procedures for the analysis and design of combinational and
sequential circuits
 To learn the concepts of A/D, D/A conversions and their types
Expected Course Outcomes:

On the successful completion of the course, student will be able to:
1 Understand the basics of Number system and gates K2
2 Realize the operation of various logic gates and analysing the outputs K1
3 Analyse and design the combinational logic circuits K4
4 Analyse and design the Sequential logic circuits K4
5 Design various synchronous and asynchronous sequential circuits K6
K1 - Remember; K2 - Understand; K3 - Apply; K4 - Analyze; K5 - Evaluate; K6 - Create
Unit:1 NUMBER SYSTEM AND CODES 12 hours

Decimal, Binary, Octal and Hexa Decimal Numbers – Conversion – Floating Point
Representation – Binary Addition, Subtraction and Multiplication – 1‟s and 2‟s Compliments -
Binary Coded Decimal (BCD) – Weighted Codes and Non-weighted Codes – Excess Three –
Grey Code – Error Detection Codes – Hamming Codes – ASCII Codes – EBCDIC Codes –
Hollerith Code – Parity Advantages.
Unit:2 BOOLEAN ALGEBRA AND LOGIC GATES 12 hours
Boolean logic operations – Boolean functions – Truth Tables – Basic Laws – DeMorgans
Theorem – Sum of Products and Products of Sums – Karnaugh map – Logic Gates – OR, AND,
NOT, NAND, NOR, EX-OR and EX-NOR Gates – Code Conversion – VHDL Coding for Logic
Gates
Unit:3 COMBINATIONAL LOGIC CIRCUITS 12 hours

Half Adder – Full Adder – Half Sub tractor – Full Sub tractor – Parallel Binary Adder – 4 bit
Binary Adder / Subtractor – BCD adder – Multiplexer – Demultiplexer – Decoders – Encoders –
Parity Generators / Checkers – Magnitude Comparators – VHDL Coding for Combinational
Circuits
Unit:4 SEQUENTIAL LOGIC CIRCUITS 12 hours
Flip Flops – RS, Clocked RS, JK, JK Master Slave, D and T Flip Flops – Shift Registers and its
Types – Ring Counters – Ripple Counters – Synchronous Counter – Up Down counter – Mod-3,
Mod-5 Counters – Decade Counter – Applications
Unit:5 D/A AND A/D CONVERTERS 12 hours

Digital to Analog Converters: Resistive Divider Type - Ladder Type – Accuracy and Resolution
- Analog to Digital Converters: Counter – Ramp Type – simultaneous Conversion – Dual Slope
Type – Successive Approximation Type – Accuracy and Resolution.
Total Lecture Hours 60 hours

Text Book(s)
1 Malvino & Leech, DIGITAL PRINCIPLES AND APPLICATIONS”, Tata McGrawHill
Edition V, 2002.
2 M.Morris Mano, DIGITAL LOGIC AND COMPUTER DESIGN”, PHI 2005.
Reference Books
1 Floyd and Jain, Digital Fundamentals, Prentice Hall 2010
2 M. Morris Mano Charles Kime, Digital Logic and Computer Design Fundamentals, Pearson
Education Limited, 2014
Related Online Contents [MOOC, SWAYAM, NPTEL, Websites etc.]

1 https://soaneemrana.org/onewebmedia/DIGITAL%20PRINCIPLES%20AND%20APPL
ICATION%20BY%20LEACH%20&%20MALVINO.pdf E book, Malvino & Leech,
―DIGITALPRINCIPLESANDAPPLICATIONS, Tata McGraw Hill Edition XI,2011
2 https://nptel.ac.in/courses/117/106/117106086/Introduction to digital circuits
Course Designed By: R.Archana, Assistant professor, Nehru Arts and Science College,
Coimbatore & Dr.N Om Muruga, Assistant Professor, Government Arts College, Ooty.
Mapping with Programme Outcomes

COs PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10
CO1 S S S M M M S L L S
CO2 S S S M M M S L L L
CO3 S S S M M L L S S M
CO4 M M M S S S L L M M
CO5 M M S S S L M M S S
*S-Strong; M-Medium; L-Low
DIGITAL PRINCIPLES AND APPLICATIONS Dr. S. KUMAR
UNIT - I
NUMBER SYSTEM AND CODES
NUMBER SYSTEM:
The number system or the numeral system is the system of naming or representing numbers.
We know that a number is a mathematical value that helps to count or measure objects and it
helps in performing various mathematical calculations. There are different types of number
systems in Maths like Decimal number system, Binary number system, Octal number system,
and Hexadecimal number system.
TYPES OF NUMBER SYSTEMS
There are various types of number systems in mathematics. The four most common number
system types are:
 Binary number system (Base - 2)
 Octal number system (Base - 8)
 Decimal number system (Base - 10)
 Hexadecimal number system (Base - 16)
The table below summaries the characteristics of the above mentioned number representation
systems.
System Number of Symbols Symbols Example

Binary 2 0, 1 100100112
Octal 8 0, 1, 2, 3, 4, 5, 6, 7 418
Decimal 10 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 14710
Hexadecimal 16 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A,B, C, D, E, F A2F716
Binary:
A binary number is defined as a number that is expressed in the binary system or base 2
numeral system. It describes numeric values by two separate symbols; 1 (one) and 0 (zero).
The base-2 system is the positional notation with 2 as a radix.
A single binary digit is called a “Bit”. A binary number consists of several bits. Examples are:
 101 is a three-bit binary number
 10101 is a five-bit binary number
 100001 is a six-bit binary number
[Dr.S.KUMAR, Assistant Professor of Electronics, Sri Vasavi College (SF Wing), Erode] Page 1
Octal to Binary Conversion
Octal to Binary Conversion

(Fractional Part)
Decimal to Binary Conversion
 Step 1: Divide the obtained decimal number by 2 and write down the remainder.
 Step 2: Now, divide the quotient that is obtained in the above steps by 2, and note the
remainder again.
 Step 3: Repeat the above two steps until you get 0 as the quotient.
 Step 4: Now, list down the remainder in such a way that the last remainder is written
first, followed by the rest in the reverse order.
This process can also be understood in another way which states that the Least Significant Bit
(LSB) of the binary number will be placed at the top and the Most Significant Bit (MSB) will
be placed at the bottom. This number obtained will be the binary value of the given decimal
number.
Example:
 118 (divide by 2) = 59 plus remainder 0 (LSB)
 59 (divide by 2) = 29 plus remainder 1 (↑)
 1 (divide by 2) = 0 plus remainder 1 (MSB)
Then the binary equivalent of 11810 is therefore: 11101102 ← (LSB)
Decimal to Binary Conversion (Fractional Part)
Example 1:
Find the binary fraction equivalent of the decimal fraction: 0.812510
 0.8125 (multiply by 2) = 1.625 = 0.625 carry 1 (MSB)
 0.625 (multiply by 2) = 1.25 = 0.25 carry 1 (↓)
 0.5 (multiply by 2) = 1.00 = 0.0 carry 1 (LSB)
Thus the binary equivalent of 0.812510 is therefore: 0.11012 ← (LSB)
Example 2:
Find the binary fraction equivalent of the following decimal number: 54.6875
First we convert the integer 54 to a binary number in the normal way using successive division
from above.
 54 (divide by 2) = 27 remainder 0 (LSB)
 27 (divide by 2) = 13 remainder 1 (↑)
 1 (divide by 2) = 0 remainder 1 (MSB)
Thus the binary equivalent of 5410 is therefore: 1101102
Next we convert the decimal fraction 0.6875 to a binary fraction using successive
multiplication.
 0.6875 (multiply by 2) = 1.375 = 0.375 carry 1 (MSB)
 0.5 (multiply by 2) = 1.00 = 0.0 carry 1 (LSB)
Thus the binary equivalent of 0.687510 is therefore: 0.10112 ← (LSB)
Hence the binary equivalent of the decimal number: 54.687510 is 110110.10112
Hexadecimal to Binary Conversion
When converting from Hexadecimal to binary number pick a single hexadecimal digit and
convert it to equivalent binary number. One thing you have to keep in mind that binary number
should be represent in 4 bit format. For example
Hexadecimal to Binary Conversion (Fractional Part)
Example 1:
03: 3333.E38)16 = ? )2
Hexadecimal number 3 3 3 3 . E 3 8
Binary number 0011 0011 0011 0011 . 1110 0011 1000
Answer 3333.E38)16= 11001100110011.111000111)2
Octal:
Octal Number System has a base of eight and uses the numbers from 0 to 7. The octal
numbers, in the number system, are usually represented by binary numbers when they are
grouped in pairs of three. For example, an octal number 128 is expressed as 0010102 in the
binary system, where 1 is equivalent to 001 and 2 is equivalent to 010.
Binary to Octal Conversion (Fractional Part)
Decimal to Octal Conversion
Follow the steps given below to learn the decimal to octal conversion:
 Write the given decimal number
 If the given decimal number is less than 8 the octal number is the same.
 If the decimal number is greater than 7 then divide the number by 8.
 Note the remainder, we get after division
 Repeat step 3 and 4 with the quotient till it is less than 8
 Now, write the remainders in reverse order (bottom to top)
 The resultant is the equivalent octal number to the given decimal number.
Therefore, (350)10 = (536)8 Therefore, (540)10 = (1034)8
Decimal to Octal Conversion (Fractional Part)
Hexadecimal to Octal Conversion
Therefore, (1A)16 = (32)8 Therefore, (2A5)16 = (1245)8
Hexadecimal to Octal Conversion (Fractional Part)
Decimal:
Decimal is a term that describes the base-10 number system, probably the most commonly
used number system. The decimal number system consists of ten single-digit numbers: 0, 1, 2,
3, 4, 5, 6, 7, 8 and 9. The number after 9 is 10. The number after 19 is 20 and so forth.
Additional powers of 10 require the addition of another positional digit.
Binary to Decimal Conversion
Binary to Decimal Conversion (Fractional Part)
Octal to Decimal Conversion
Octal to Decimal Conversion (Fractional Part)
Hexadecimal to Decimal Conversion
Hexadecimal to Decimal Conversion (Fractional Part)
Hexa Decimal:
Hexadecimal Number System is one the type of Number Representation techniques, in which
there value of base is 16. That means there are only 16 symbols or possible digit values, there
are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F. Where A, B, C, D, E and F are single bit
representations of decimal value 10, 11, 12, 13, 14 and 15 respectively. It requires only 4 bits
to represent value of any digit.
Binary to Hexadecimal Conversion
Binary to Hexadecimal Conversion (Fractional Part)
Hex to Binary
Octal to Hexadecimal Conversion
Octal to Hexadecimal Conversion (Fractional Part)
Decimal to Hexadecimal Conversion
Decimal to Hexadecimal Conversion (Fractional Part)
Conversion:
Numeral systems conversion table

Decimal Binary Octal Hexadecimal Decimal Binary Octal Hexadecimal
Base-10 Base-2 Base-8 Base-16 Base-10 Base-2 Base-8 Base-16
0 0 0 0 16 10000 20 10
1 1 1 1 17 10001 21 11
2 10 2 2 18 10010 22 12
3 11 3 3 19 10011 23 13
4 100 4 4 20 10100 24 14
5 101 5 5 21 10101 25 15
6 110 6 6 22 10110 26 16
7 111 7 7 23 10111 27 17
8 1000 10 8 24 11000 30 18
9 1001 11 9 25 11001 31 19
10 1010 12 A 26 11010 32 1A
11 1011 13 B 27 11011 33 1B
12 1100 14 C 28 11100 34 1C
13 1101 15 D 29 11101 35 1D
14 1110 16 E 30 11110 36 1E
15 1111 17 F 31 11111 37 1F
32 100000 40 20
Floating Point Representation:

The floating point representation (FP) is the representation that uses a formulaic
representation of real numbers as an approximation to enable a trade-off between range and
accuracy. As a result, the floating point representation is frequently utilized in systems with
very small and extremely large real numbers that demand quick processing speeds.
Binary numbers can also be expressed in exponential form. The representation of binary
integers in exponential form is known as floating point representation. The floating point
representation divides the number into two parts: the left side is a signed, fixed-point integer
known as a mantissa, and the right side is the exponent.
Sign bit -The fixed-point numbers in binary uses a sign bit. A positive number has a sign bit 0,
while a negative number has a sign bit 1.
Integral Part – The integral part is of different lengths at different places. It depends on the
register's size, like in an 8-bit register, integral part is 4 bits.
Fractional part – Fractional part is also of different lengths at different places. It depends on
the register's size, like in an 8-bit register, integral part is of 3 bits.
 8 bits = 1Sign bit + 4 bits(integral) + 3bits (fractional part)
 16 bits = 1Sign bit + 9 bits(integral) +6 bits (fractional part)
 32 bits = 1Sign bit + 15 bits(integral) + 9 bits (fractional part)
Example:
Step 1:- Convert the number into binary form.
4.5 = 100.1
Step 2:- Represent binary number in Fixed point notation
Binary Addition:
Binary addition is the sum of two or more binary numbers. Binary addition is much similar to
decimal addition, even a bit easier. In the decimal addition, if the sum of two numbers results
in two digits, we carry the digit in the ten‟s place to the next column to the left. Similarly in
binary addition, if the sum of two numbers is greater than 1, we carry the 2‟s digit over to the
next column to the left For example, 1+ 1 = 10₂. In this case, we write 1‟s digit (0) and carry
the 2‟s digit i.e. 1 of the result to the next column to the left. For this reason, the bit that is
carried to the next column is known as the carry bit.
Example (Addition):
Binary Subtraction:
Binary subtraction is the process of subtracting binary numbers. Binary numbers include only
0 and 1. The process of binary subtraction is the same as the arithmetic operation of
subtraction that we do with numbers. Since only 0 and 1 are involved here, we may sometimes
need to subtract 0 from 1. In such cases, we use the concept of borrowing as we do in an
arithmetic subtraction.
Binary Number Subtraction Value
0–0 0
1–0 1
0–1 1 (Borrow 1 from the next high order digit)
–1 0
Example (Subtraction):
Binary Multiplication:
Binary multiplication is similar to decimal multiplication. It is simpler than decimal
multiplication because only 0s and 1s are involved. There are four rules of binary
multiplication.
Example (Multiplication):
Binary Division:
Binary division is similar to decimal division. It is called as the long division procedure.
Example (Devision):
1’s and 2’s Compliments:

1’s Complement of a Binary Number
There is a simple algorithm to convert a binary number into 1‟s complement. To get 1‟s
complement of a binary number, simply invert the given number.
Examples:
2’s Complement of a Binary Number

There is a simple algorithm to convert a binary number into 2‟s complement. To get 2‟s
complement of a binary number, simply invert the given number and add 1 to the least
significant bit (LSB) of given result.
Examples:
Binary Coded Decimal (BCD):

BCD or Binary Coded Decimal is that number system or code which has the binary
numbers or digits to represent a decimal number.
A decimal number contains 10 digits (0-9). Now the equivalent binary numbers can be found
out of these 10 decimal numbers. In case of BCD the binary number formed by four binary
digits, will be the equivalent code for the given decimal digits. In BCD we can use the binary
number from 0000-1001 only, which are the decimal equivalent from 0-9 respectively.
Suppose if a number have single decimal digit then it‟s equivalent Binary Coded Decimal will
be the respective four binary digits of that decimal number and if the number contains two
decimal digits then it‟s equivalent BCD will be the respective eight binary of the given decimal
number. Four for the first decimal digit and next four for the second decimal digit.
Truth Table for Binary Coded Decimal
Decimal Binary Number Binary Coded Decimal

Number (BCD)
0 0000 0000 0000
1 0001 0000 0001
2 0010 0000 0010
3 0011 0000 0011
4 0100 0000 0100
5 0101 0000 0101
6 0110 0000 0110
7 0111 0000 0111
8 1000 0000 1000
9 1001 0000 1001
10 (1+0) 1010 0001 0000
11 (1+1) 1011 0001 0001
12 (1+2) 1100 0001 0010
… … …
20 (2+0) 10100 0010 0000
21 (2+1) 10101 0010 0001
22 (2+2) 10110 0010 0010
… … …
Binary Coded Decimal Decoder IC:
Weighted Codes and Non-weighted Codes:

Classification of binary codes
 Weighted Codes
 Non-Weighted Codes
 Alphanumeric Codes
 Error Detecting Codes
 Error Correcting Codes In an isolated
Weighted Codes:
Weighted binary codes are those binary codes which obey the positional weight principle.
Each position of the number represents a specific weight. Several systems of the codes are
used to express the decimal digits 0 through 9. In these codes each decimal digit is represented
by a group of four bits.
Non-Weighted Codes:
In this type of binary codes, the positional weights are not assigned. The examples of non-
weighted codes are Excess-3 code and Gray code.
Excess Three (Excess-3):

The Excess-3 code is also called as XS-3 code. It is non-weighted code used to express
decimal numbers. The Excess-3 code words are derived from the 8421 BCD code words
adding (0011)2 or (3)10 to each code word in 8421. The excess-3 codes are obtained as
follows,
Grey Code:
It is the non-weighted code and it is not arithmetic codes. That means there are no specific
weights assigned to the bit position. It has a very special feature that, only one bit will change
each time the decimal number is incremented as shown in fig. As only one bit changes at a
time, the gray code is called as a unit distance code. The gray code is a cyclic code. Gray code
cannot be used for arithmetic operation.
Binary to Gray Code Conversion:

 The MSB (Most Significant Bit) of the gray code will be exactly equal to the first bit of
the given binary number.
 The second bit of the code will be exclusive-or (XOR) of the first and second bit of the
given binary number, i.e if both the bits are same the result will be 0 and if they are
different the result will be 1.
 The third bit of gray code will be equal to the exclusive-or (XOR) of the second and
third bit of the given binary number. Thus the binary to gray code conversion goes on.
An example is given below to illustrate these steps.
Gray Code to Binary Conversion
Gray code to binary conversion is again a very simple and easy process. Following steps can
make your idea clear on this type of conversions.
 The MSB of the binary number will be equal to the MSB of the given gray code.
 Now if the second gray bit is 0, then the second binary bit will be the same as the
previous or the first bit. If the gray bit is 1 the second binary bit will alter. If it was 1 it
will be 0 and if it was 0 it will be 1.
 This step is continued for all the bits to do Gray code to binary conversion.
Application of Gray code

 Gray code is popularly used in the shaft position encoders.
 A shaft position encoder produces a code word which represents the angular position of
the shaft.
Error Detection Codes:

Error
A condition when the receiver‟s information does not match with the sender‟s information.
During transmission, digital signals suffer from noise that can introduce errors in the binary
bits travelling from sender to receiver. That means a 0 bit may change to 1 or a 1 bit may
change to 0.
Error Detecting Codes

Whenever a message is transmitted, it may get scrambled by noise or data may get corrupted.
To avoid this, we use error-detecting codes which are additional data added to a given digital
message to help us detect if any error has occurred during transmission of the message.
Some popular techniques for error detection are:

 Simple Parity check
 Two-dimensional Parity check
 Checksum
 Cyclic redundancy check
The codes which are used for both error detecting and error correction are called as “Error
Correction Codes”. The error correction techniques are of two types. They are,
 Single bit error correction
 Burst error correction
The process or method of correcting single bit errors is called “single bit error correction”. The
method of detecting and correcting burst errors in the data sequence is called “Burst error
correction”.
Hamming Codes:
This error detecting and correcting code technique is developed by R.W.Hamming . This code
not only identifies the error bit, in the whole data sequence and it also corrects it. This code
uses a number of parity bits located at certain positions in the codeword. The number of parity
bits depends upon the number of information bits. The hamming code uses the relation
between redundancy bits and the data bits and this code can be applied to any number of data
bits.
Alpha Numeric Codes

Alphanumeric codes are basically binary codes which are used to represent the alphanumeric
data. As these codes represent data by characters, alphanumeric codes are also called
“Character codes”.
These codes can represent all types of data including alphabets, numbers, punctuation marks
and mathematical symbols in the acceptable form by computers. These codes are implemented
in I/O devices like key boards, monitors, printers etc. In earlier days, punch cards are used to
represent the alphanumeric codes. They are
 MORSE code
 BAUDOT code
 HOLLERITH code
 ASCII code
 EBCDI code
 UNICODE
ASCII Codes:
ASCII means American Standard Code for Information Interchange. It is the world‟s most
popular and widely used alphanumeric code. This code was developed and first published in
1967. ASCII code is a 7 bit code that means this code uses 27 = 128 characters. This includes
26 lower case letters (a – z), 26 upper case letters (A – Z), 33 special characters and symbols
(like ! @ # $ etc), 33 control characters (* – + / and % etc) and 10 digits (0 – 9). In this 7 bit
code we have two parts, the leftmost 3 bits and right side 4 bits. The left most 3 bits are known
“ZONE bits” and the right side 4 bits are known as “NUMERIC bits”.
EBCDIC Codes:
EBCDI stands for Extended Binary Coded Decimal Interchange code. This code is developed
by IBM Inc Company. It is an 8 bit code, so we can represent 28 = 256 characters by using
EBCDI code. This include all the letters and symbols like 26 lower case letters (a – z), 26
upper case letters (A – Z), 33 special characters and symbols (like ! @ # $ etc), 33 control
characters (* – + / and % etc) and 10 digits (0 – 9). In the EBCDI code, the 8 bit code the
numbers are represented by 8421 BCD code preceded by 1111.
Hollerith Code:
This code is developed by a company founded by Herman Hollerith in 1896. The 12 bit code
used to punch cards according to the transmitting information is called “Hollerith code”.
Parity Advantages:
Simple Parity check
Blocks of data from the source are subjected to a check bit or parity bit generator form, where
a parity of :
 1 is added to the block if it contains odd number of 1‟s, and

 0 is added if it contains even number of 1‟s
This scheme makes the total number of 1‟s even, that is why it is called even parity checking.
The two types of parity checking are
 Even Parity − Here the total number of bits in the message is made even.
 Odd Parity − Here the total number of bits in the message is made odd.
UNIT - II
BOOLEAN ALGEBRA AND LOGIC GATES
Boolean logic operations:

Boolean Logic is a form of algebra which is centered around three simple words known as
Boolean Operators: “Or,” “And,” and “Not”. At the heart of Boolean Logic is the idea that
all values are either true or false. Boolean algebra was invented by George Boole in 1854.
Boolean algebra is the category of algebra in which the variable‟s values are the truth values,
true and false, ordinarily denoted 1 and 0 respectively. It is used to analyze and simplify
digital circuits or digital gates. It is also called Binary Algebra or logical Algebra. It has been
fundamental in the development of digital electronics and is provided for in all modern
programming languages. It is also used in set theory and statistics.
The important operations performed in Boolean algebra are conjunction (∧), disjunction (∨)
and negation (¬). Hence, this algebra is far way different from elementary algebra where the
values of variables are numerical and arithmetic operations like addition, subtraction is been
performed on them. The basic operations of Boolean algebra are as follows:
 Conjunction or AND operation

 Disjunction or OR operation
 Negation or NOT operation
Boolean functions:
A Boolean Function is described by an algebraic expression called Boolean expression which
consists of binary variables, the constants 0 and 1, and the logic operation symbols. The
rudimentary symmetric Boolean functions (logical connectives or logic gates) are:
 NOT, negation or complement - which receives one input and returns true when that
input is false ("not")
 AND or conjunction - true when all inputs are true ("both")
 OR or disjunction - true when any input is true ("either")
 XOR or exclusive disjunction - true when one of its inputs is true and the other is false
("not equal")
 NAND or Sheffer stroke - true when it is not the case that all inputs are true ("not both")
 NOR or logical nor - true when none of the inputs are true ("neither")
 XNOR or logical equality - true when both inputs are the same ("equal")
Truth Tables:
A truth table is a breakdown of a logic function by listing all possible values the function can
attain. Such a table typically contains several rows and columns, with the top row representing
the logical variables and combinations, in increasing complexity leading up to the final
function.
Basic Laws:
Commutative Law
Any binary operation which satisfies the following expression is referred to as commutative
operation. Commutative law states that changing the sequence of the variables does not have
any effect on the output of a logic circuit.
Associative Law
This law states that the order in which the logic operations are performed is irrelevant as their
effect is the same.
Distributive Law
Distributive law states the following condition.
AND Law
These laws use the AND operation. Therefore they are called as AND laws.
OR Law
These laws use the OR operation. Therefore they are called as OR laws.
INVERSION Law
This law uses the NOT operation. The inversion law states that double inversion of a variable
results in the original variable itself.
DeMorgans Theorem:
In an isolated
DEMORGAN’S FIRST THEOREM
According to DeMorgan‟s First Theorem, the resultant of two (or more) variables AND‟ed and
inverted (NOT) as a whole is equivalent to the OR of the complements of individual variables.
Thus, AND + NOT (NAND) operation on variables is equivalent to the sum (OR) of the
individual complement of each variable. In Boolean expression, it is stated as follow:
DEMORGAN’S SECOND THEOREM

According to DeMorgan‟s Second Theorem, the resultant of two (or more) variables OR‟ed
and inverted (NOT) as a whole is equivalent to the AND of the complements of individual
variables. Thus, OR + NOT (NOR) operation on variables is equivalent to AND of the
individual complement of each variable. In Boolean expression, it is stated as follow:
Sum of Products and Products of Sums:

Sum Of Product (SOP)
Sum of Product is the abbreviated form of SOP. Sum of product form is a form of expression
in Boolean algebra in which different product terms of inputs are being summed together. This
product is not arithmetical multiply but it is Boolean logical AND and the Sum is Boolean
logical OR.
Min Term
Minterm means the term that is true for a minimum number of combination of inputs. That is
true for only one combination of inputs. Since AND gate also gives True only when all of its
inputs are true so we can say min terms are AND of input combinations like in the table given
below. 3 inputs have 8 different combinations. Each combination has a min terms denoted by
small m and its decimal combination number written in subscript. Each of these minterms will
be only true for the specific input combination.
Types of Sum Of Product (SOP) Forms
 Canonical SOP Form

 Non-Canonical SOP Form
 Minimal SOP Form
Canonical SOP Form

This is the standard form of Sum of Product. It is formed by O Ring the minterms of the
function for which the output is true. This is also known as Sum of Min terms or Canonical
disjunctive normal form (CDNF). It is just a fancy name. “canonical” means “standardized”
and “disjunctive” means “Logical OR union”. Canonical SOP expression is represented by
summation sign ∑ and minterms in the braces for which the output is true. For example, a
functions truth table is given below,
For this function the canonical SOP expression is

F = ∑( m1, m2, m3, m5 )
Which means that the function is true for the min terms {1, 2, 3, 5}.
By expanding the summation we get.

F = m1 + m2 + m3 + m5
Now putting min terms in the expression

F = ABC ABC ABC ABC
Canonical form contains all inputs either complemented or non-complemented in its product
terms.
Non-Canonical SOP Form

As the name suggests, this form is the non-standardized form of SOP expressions. The product
terms are not the min terms but they are simplified. Let‟s take the above function in canonical
form as an example.
F = ABC ABC ABC ABC
F = ABC AB(C C) ABC
F = ABC AB(1) ABC
F = ABC AB ABC
This expression is still in Sum of Product form but it is non-canonical or non-standardized

form.
Minimal SOP Form

This form is the most simplified SOP expression of a function. It is also a form of non-
canonical form. Minimal SOP form can be made using Boolean algebraic theorems but it is
very easily made using Karnaugh map (K-map). Minimal SOP form is preferred because it
uses the minimum number of gates and input lines. it is commercially beneficial because of its
compact size, fast speed, and low fabrication cost.
Schematic Design of Sum of Product

The expression of the sum of product executes two-level AND-OR design, and this design
requires a collection of AND gates and one OR gate. Each expression of the sum of the
product has similar designing.
Difference between SOP and POS in Digital Logic
Product of Sum (POS)

Product of Sum abbreviated for POS. The product of Sum form is a form in which products of
different sum terms of inputs are taken. These are not arithmetic product and sum but they are
logical Boolean AND and OR respectively.
Max Term
Maxterm means the term or expression that is true for a maximum number of input
combinations or that is false for only one combination of inputs. Since OR gate also gives false
for only one input combination. So Maxterm is OR of either complemented or non-
complemented inputs. Max terms for 3 input variables are given below.
Types of Product Of Sum Forms
 Canonical POS Form

 Non – Canonical Form
 Minimal POS Form
Canonical POS Form
It is also known as Product of Max term or Canonical conjunctive normal form (CCNF).
Canonical means standard and conjunctive means intersection. In this form, Maxterms are
AND together for which output is false. Canonical POS expression is represented by ∏ and
Maxterms for which output is false in brackets as shown in the example given below.
F = ∏ (M0, M4, M6, M7)
Expanding the product

F = M0.M4.M6.M7
Putting Max terms

F = (A B C)(A B C)(A B C)(A B C)
The canonical form contains all inputs either complemented or non-complemented in its each
Sum term.
Non – Canonical Form
The product of sum expression that is not in standard form is called non-canonical form. Let‟s
take the above-given function as an example.
F = (A B C)(A B C)(A B C)(A B C)
F = (B C) (A B C)(A B C)
Same but inverted terms eliminates from two Max terms and form a single term to prove it
here is an example.
= (A B C) (A B C)
= AA AB AC AB BB BC AC BC CC
= 0 AB AC AB AC B BC C
= A(B C) A(B C) B(1 C) C
= (B C)(A A) B(1) C
= (B+C)(0)+B+C
= B+C
The expression achieved is still in Product of Sum form but it is non-canonical form.
Minimal POS Form
This is the most simplified and optimized form of a POS expression which is non-canonical.
Minimal Product of Sum form can be achieved using Boolean algebraic theorems like in the
non-canonical example given above. Another method of achieving minimal POS form is by
using Karnaugh map which is comparatively easier than using Boolean algebraic theorems.
Minimal POS form uses less number of inputs and logic gates during its implementation, that‟s
why they are being preferred over canonical form for their compact,fast and low-cost
implementation.
Schematic Design of Product of Sum
The expression of the product of the sum executes two levels OR- AND design and this design
requires a collection of OR gates and one AND gate. Each expression of the product of the
sum has similar designing.
Karnaugh map:
Karnaugh Maps or K-maps is one among such simplification technique, introduced by Maurice
Karnaugh in 1953, which is graphical in nature. This method of minimizing the logical
expressions is most suitable when the number of variables involved is less than or equal to
four. This is because, a K-map employs the use of two-dimensional tables to simplify the
expressions, whose size increases at a very high rate with the increase in the number of
variables. This fact is further established by Figure which shows the K-maps for two, three and
four variables in order.
Advantages of Karnaugh Map

 K-map simplification does not demand for the knowledge of Boolean algebraic
theorems.
 Usually it requires less number of steps when compared to algebraic minimization
technique.
Disadvantages of K-map
 Complexity of K-map simplification process increases with the increase in the number
of variables
 The minimum expression obtained might not be uniqueIn an isolated
Sum Of Product (SOP)

In an isolated
According to the K-map, the output expression will be
F = BC AB
Product of Sum (POS)
Minimal expression using K-map

F = (B C) (A B)
Logic Gates – AND, OR, NOT, NAND, NOR, EX-OR and EX-NOR
Gates:
A logic gate is a device that acts as a building block for digital circuits. They perform basic
logical functions that are fundamental to digital circuits. In a circuit, logic gates will make
decisions based on a combination of digital signals coming from its inputs. Most logic gates
have two inputs and one output. Logic gates are based on Boolean algebra. At any given
moment, every terminal is in one of the two binary conditions, false or true. False represents 0,
and true represents 1.
There are mainly seven types of logic gates. They are,

AND gate, OR gate, NOT gate, NOR gate, NAND gate, EX-OR gate and EX-NOR gate
AND Gate: (IC7408)
 An AND gate has a single output and two or more inputs.

 When all of the inputs are 1, the output of this gate is 1.
 The AND gate‟s Boolean logic is Y=A.B if there are two inputs A and B.
OR Gate: (IC7432)
 Two or more inputs and one output can be used in an OR gate.

 The logic of this gate is that if at least one of the inputs is 1, the output will be 1.
 The OR gate‟s output will be given by the following mathematical procedure if there
are two inputs A and B: Y=A+B
NOT Gate: (IC7404)
 The NOT gate is a basic one-input, one-output gate.

 When the input is 1, the output is 0, and vice versa. A NOT gate is sometimes called an
inverter because of its feature.
 If there is only one input A, the output may be calculated using the Boolean equation
Y=A’.
NAND Gate: (IC 7400)
 A NAND gate, sometimes known as a „NOT-AND‟ gate, is essentially a Not gate

followed by an AND gate.
 This gate‟s output is 1 only if none of the inputs is 1. Alternatively, when all of the
inputs are not high and at least one is low, the output is high.
 If there are two inputs A and B, the Boolean expression for the NAND gate is Y=(A.B)’
 By comparing their truth tables, we can observe that their outputs are the polar opposite
of an AND gate.
 The NAND gate is known as a universal gate because it may be used to implement the
AND, OR, and NOT gates.
NOR Gate: (IC 7402)
 A NOR gate, sometimes known as a “NOT-OR” gate, consists of an OR gate followed

by a NOT gate.
 This gate‟s output is 1 only when all of its inputs are 0. Alternatively, when all of the
inputs are low, the output is high.
 The Boolean statement for the NOR gate is Y=(A B)’ if there are two inputs A and B.
 By comparing the truth tables, we can observe that the outputs of the NOR gate are the
polar opposite of those of an OR gate.
 The NOR gate is sometimes known as a universal gate since it may be used to
implement the OR, AND, and NOT gates.
EX-OR Gate: (IC 7486)
 The Exclusive-OR or „Ex-OR‟ gate is a digital logic gate that accepts more than two
inputs but only outputs one value.
 If any of the inputs is „High,‟ the output of the XOR Gate is „High.‟ If both inputs are
„High,‟ the output is „Low.‟ If both inputs are „Low,‟ the output is „Low.‟
 The Boolean equation for the XOR gate is Y=A’.B A.B’ if there are two inputs A and
B.
EX-NOR Gate: (IC 74266)
 The Exclusive-NOR or „EX-NOR‟ gate is a digital logic gate that accepts more than
two inputs but only outputs one.
 If both inputs are „High,‟ the output of the XNOR Gate is „High.‟ If both inputs are
„Low,‟ the output is „High.‟ If one of the inputs is „Low,‟ the output is „Low.‟
 If there are two inputs A and B, then the XNOR gate‟s Boolean equation is:
Y=A.B A’B’.
Code Conversion:
The Code converter is used to convert one type of binary code to another. There are different
types of binary codes like BCD code, gray code, excess-3 code, etc. Different codes are used
for different types of digital applications.
 Binary to BCD code converter

 BCD to Excess-3 code converter
 BCD to Gray code converter
 Gray code to Excess-3 code converter
VHDL Coding for Logic Gates

What is VHDL?
VHDL stands for VHSIC Hardware Description Language / Very High-Speed Integrated
Circuit Hardware Description Language. It is a programming language used to model a
digital system by dataflow, behavioral and structural style of modeling. This language was first
introduced in 1981 for the department of Defense (DoD) under the VHSIC program.
Different Types of VHDL Modelling Styles

The architecture of VHDL code is written in three different coding styles :
 Dataflow Modelling
 Behavioral Modelling
 Structural Modelling
Describing a Design
In VHDL an entity is used to describe a hardware module. An entity can be described using,
 Entity declaration
 Architecture
 Configuration
 Package declaration
 Package body
Simulator Softwares
 Xilinx Simulator
 Active-HDL
 Quartus II Simulator (Qsim)
 ModelSim
 MPSim
 Verilog-XL Etc…,
VHDL Coding for Logic Gates (TYPE - 1)

AND LOGIC:
LIBRARY DECLARATION
Library IEEE;
Use IEEE.std_logic_1164.all;
ENTITY DECLARATION
Entity andgate is
Port (A, B: in std_logic;
C: out std_logic);
End andgate;
ARCHITECTURE DECLARATION
Architecture dataflow of andgate is
Begin
C<=A AND B;
End dataflow;
OR LOGIC:
LIBRARY DECLARATION
Library IEEE;
ENTITY DECLARATION
Entity orgate is
C: out std_logic);
End orgate;
Architecture dataflow of orgate is
Begin
C<= A OR B;
End dataflow;
NOT LOGIC:
LIBRARY DECLARATION
Library IEEE;
ENTITY DECLARATION
Entity notgate is
Port (A: in std_logic;
C: out std_logic);
End notgate;
Architecture dataflow of notgate is
Begin
C<=NOT A;
End dataflow;
NAND LOGIC
LIBRARY DECLARATION
Library IEEE;
ENTITY DECLARATION
Entity nandgate is
C: out std_logic);
End nandgate;
Architecture dataflow of nandgate is
Begin
C<=A NAND B;
End dataflow;
NOR LOGIC
LIBRARY DECLARATION
Library IEEE;
ENTITY DECLARATION
Entity norgate is
C: out std_logic);
End norgate;
Architecture dataflow of norgate is
Begin
C<=A NOR B;
End dataflow;
EX-OR LOGIC
LIBRARY DECLARATION
Library IEEE;
ENTITY DECLARATION
Entity xorgate is
C: out std_logic);
End xorgate;
Architecture dataflow of xorgate is
Begin
C<=A XOR B;
End dataflow;
EX-NOR LOGIC
LIBRARY DECLARATION
Library IEEE;
ENTITY DECLARATION
Entity xnorgate is
C: out std_logic);
End xnorgate;
Architecture dataflow of xnorgate is
Begin
C<=A XNOR B;
End dataflow;
VHDL Coding for Logic Gates (TYPE - 2)

LIBRARY DECLARATION
Library IEEE;
ENTITY DECLARATION
Entity logicgate is
Y0, Y1, Y2, Y3, Y4, Y5, Y6: out std_logic);
End logicgate;
Architecture dataflow of logicgate is
Begin
Y0<= A AND B;
Y1 <=A OR B;
Y2 <=NOT A;
Y3 <=A NAND B;
Y4 <=A NOR B;
Y5 <=A XOR B;
Y6) <=A XNOR B;
End dataflow;
UNIT - III
COMBINATIONAL LOGIC CIRCUITS
Half Adder:
A half adder is a type of adder, an digital circuit that performs the addition of numbers. The
half adder is able to add two single binary digits and provide the output plus a carry value. It
has two inputs, called A and B, and two outputs S (sum) and C (carry). The common
representation uses a XOR logic gate and an AND logic gate.
Block diagram
Half-Adder Logical Circuit and Truth Table
Full Adder:
A full adder is a digital circuit that performs addition. Full adders are implemented with logic
gates in hardware. A full adder adds three one-bit binary numbers, two operands and a carry
bit. The adder outputs two numbers, a sum and a carry bit. The term is contrasted with a half
adder, which adds two binary digits.
Block diagram
Construction of Full Adder Using Half Adder Circuit:
The above block diagram describes the construction of the Full adder circuit. In the above
circuit, there are two half adder circuits that are combined using the OR gate. The first half
adder has two single-bit binary inputs A and B. As we know that, the half adder produces two
outputs, i.e., Sum and Carry. The 'Sum' output of the first adder will be the first input of the
second half adder, and the 'Carry' output of the first adder will be the second input of the
second half adder. The second half adder will again provide 'Sum' and 'Carry'. The final
outcome of the Full adder circuit is the 'Sum' bit. In order to find the final output of the 'Carry',
we provide the 'Carry' output of the first and the second adder into the OR gate. The outcome
of the OR gate will be the final carry out of the full adder circuit. The MSB is represented by
the final 'Carry' bit.
Truth Table
3 Input Full Adder Logical Circuit
Half Subtractor:
The half subtractor is also a building block for subtracting two binary numbers. It has two
inputs and two outputs. This circuit is used to subtract two single bit binary numbers A and B.
The 'difference' and 'borrow' are two output states of the half subtractor.
Block diagram
Half Subtractor Logical Circuit and Truth Table
Full Subtractor:
A full subtractor is an arithmetic circuit that performs a subtraction between two bits,
considering that a lower significant stage may have borrowed a '1'. Thus a full subtractor has
three inputs and two outputs.
Block diagram
Construction of Full Subtractor Using Half Subtractor Circuit:
The above block diagram describes the construction of the Full subtractor circuit. In the above
circuit, there are two half adder circuits that are combined using the OR gate. The first half
subtractor has two single-bit binary inputs A and B.
As we know that, the half subtractor produces two outputs, i.e., 'Diff' and 'Borrow'. The 'Diff'
output of the first subtractor will be the first input of the second half subtractor, and the
'Borrow' output of the first subtractor will be the second input of the second half subtractor.
The second half subtractor will again provide 'Diff' and 'Borrow'. The final outcome of the Full
subtractor circuit is the 'Diff' bit. In order to find the final output of the 'Borrow', we provide
the 'Borrow' of the first and the second subtractor into the OR gate. The outcome of the OR
gate will be the final carry 'Borrow' of full subtractor circuit. The MSB is represented by the
final 'Borrow' bit.
Truth Table
3 Input Full Subtractor Logical Circuit
Parallel Binary Adder:

What is the need for parallel adder?
Half adder is used to add only two single bit binary digits(A and B). Using full adder, addition
of two single bit binary digits(A and B) along with the carry from the previous digit addition is
possible. But, if we have to add two multi bit binary digits(eg. 1011 and 1001), What to do?
The simple solution to add multi bit binary number is the design of parallel adder.
What is Parallel Adder?

Parallel adder is a combinational logic circuit used to add multi bit binary digits. To perform
this addition, full adders are cascaded with one another. The number of full adders to be
cascaded depends on the number of bits in a binary digit.
For example, if you want to add two 4-bit binary numbers, you have to connect 4 number of
full adders in parallel. The below block diagram shows „n‟ number of full adders cascaded
with one another to design a n-bit parallel adder.
 The 'A' and 'B' are the augend, and addend bits are defined by the subscript numbers.
The subscripts start from right to left, and the lower-order bit is defined by subscript '0'.
 The C0, C1, C2, and C3 are the carry inputs which are connected together as a chain
using Full Adder. The C4 is the carry output produced by the last Full-Adder.
 The Cout of the first Adder is connected as the Cin of the next Full-Adder.
 The S0, S1, S2, and S3 are the sum outputs that produce the sum of augend and addend
bits.
 The inputs for the input variable 'A' and 'B' are fetched from different source registers.
For example, the bit for the input variable 'A' comes from register 'R1', and a bit for the
input variable 'B' comes from register 'R2'.
 The outcome produced by adding both input variables is stored into either third register
or to one of the source registers.
Advantages
 Computation is fast.
 Bits are added simultaneously.
 They are economical.
Disadvantages
 The major drawback of this Adder is the Propagation Delay.
 The delay is directly proportional to the length of binary numbers that are to be added.
4 bit Binary Adder / Subtractor:
4 bit Binary Adder:
Parallel 4-bit Binary Adder, which has three full adders and one half adder. The two binary
numbers to be added are „A3 A2 A1 A0„ and „B3 B2 B1 B0„ , which are applied to the
corresponding inputs of the Full Adders. This parallel adder produces their result as „C4 S3 S2
S1 S0„ , where C4 is the final carry.
4 bit Binary Subtractor
In this subtractor, 4 bit minuend „A3 A2 A1 A0„ is subtracted by 4 bit subtrahend „B3 B2 B1
B0„ and the result is the difference output „D3 D2 D1 D0„ . The borrow output of each
subtractor is connected as the borrow input to the next subtractor.
BCD adder:
The digital systems handles the decimal number in the form of binary coded decimal numbers
(BCD). A BCD Adder Circuit that adds two BCD digits and produces a sum digit also in BCD.
BCD numbers use 10 digits, 0 to 9 which are represented in the binary form 0 0 0 0 to 1 0 0 1,
i.e. each BCD digit is represented as a 4-bit binary number. When we write BCD number say
526, it can be represented as
Here, we should note that BCD cannot be greater than 9. The addition of two BCD numbers
can be best understood by considering the three cases that occur when two BCD digits are
added.
Sum Equals 9 or less with carry 0
Let us consider additions of 3 and 6 in BCD. The addition is carried out as in normal binary
addition and the sum is 1 0 0 1, which is BCD code for 9.
Sum greater than 9 with carry 0

Let us consider addition of 6 and 8 in BCD.
The sum 1 1 1 0 is an invalid BCD number. This has occurred because the sum of the two
digits exceeds 9. Whenever this occurs the sum has to be corrected by the addition of six
(0110) in the invalid BCD number, as shown below
After addition of 6 carry is produced into the second decimal position.
Sum equals 9 or less with carry 1

Let us consider addition of 8 and 9 in BCD.
In this, case, result (0001 0001) is valid BCD number, but it is incorrect. To get the correct
BCD result correction factor of 6 has to be added to the least significant digit sum, as shown
below
Going through these three cases of BCD addition we can summarise the BCD addition
procedure as follows :
 Add two BCD numbers using ordinay binary addition.
 If four-bit sum is equal to or less than 9, no correction is needed. The sum is in proper
BCD form.
 If the four-bit sum is greater than 9 or if a carry is generated from the four-bit sum, the
sum is invalid.
 To correct the invalid sum, add 01102 to the four-bit sum. If a carry results from this
addition, add it to the next higher-order BCD digit.
Multiplexer:
What are Multiplexer and Demultiplexer?
In-network transmission, both the multiplexer and demultiplexer are combinational circuits. A
multiplexer selects an input from several inputs then it is transmitted in the form of a single
line. An alternative name of the multiplexer is MUX or data selector. A demultiplexer uses one
input signal and generates many. So it is known as Demux or data distributor.
What is a Multiplexer?
The multiplexer is a device that has multiple inputs and single line output. The select lines
determine which input is connected to the output, and also increase the amount of data that can
be sent over a network within a certain time. It is also called a data selector. Multiplexer is
also called as Mux.
ONE into MANY
Multiplexer Types
 2-1 multiplexer ( 1select line)
 4-1 multiplexer (2 select lines)
 8-1 multiplexer(3 select lines)
 16-1 multiplexer (4 select lines) Etc…,
2x1 Multiplexer
In 2×1 multiplexer, there are only two inputs, i.e., A0 and A1, 1 selection line, i.e., S0 and
single outputs, i.e., Y. On the basis of the combination of inputs which are present at the
selection line S0, one of these 2 inputs will be connected to the output. The block diagram and
the truth table of the 2×1 multiplexer are given below.
Truth Table & Logic Diagram
4x1 Multiplexer
4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one output
Y. The block diagram of 4x1 Multiplexer is shown in the following figure.
One of these 4 inputs will be connected to the output based on the combination of inputs
present at these two selection lines.
8 to 1 Multiplexer
In the 8 to 1 multiplexer, there are total eight inputs, i.e., A0, A1, A2, A3, A4, A5, A6, and A7,
3 selection lines, i.e., S0, S1and S2 and single output, i.e., Y. On the basis of the combination
of inputs that are present at the selection lines S0, S1, and S2, one of these 8 inputs are
connected to the output. The block diagram and the truth table of the 8×1 multiplexer are given
below.
16 to 1 Multiplexer
Advantages
 In multiplexer, the usage of a number of wires can be decreased
 It reduces the cost as well as the complexity of the circuit
 The implementation of a number of combination circuits can be possible by using a
multiplexer
 The multiplexer can make the transmission circuit less complex & economical
 The multiplexer ability can be extended to switch audio signals, video signals, etc.
 The digital system reliability can be improved using a MUX as it decreases the number
of exterior wired connections.
 MUX is used to implement several combinational circuits
 The logic design can be simplified through MUX
Disadvantages
 Additional delays required within switching ports & I/O signals which propagate
throughout the multiplexer.
 The ports which can be utilized at the same time have limitations
 Switching ports can be handled by adding the complexity of firmware
 The controlling of multiplexer can be done by using additional I/O ports.
Demultiplexer:
What is Demultiplexer?
Demultiplexer or Demux is a combinational circuit that distributes the single input data to a
specific output line. The control inputs or selection lines are used to select a specific output
line from the possible output lines. Demultiplexer works opposite to that of the multiplexer.
Demux has one output, 2n possible outputs and n control or selection lines. It is also called a
data distributor.
MANY into ONE
Types of Demultiplexer
 1-2 demultiplexer (1 select line)
 1-4 demultiplexer (2 select lines)
 1-8 demultiplexer (3 select lines)
 1-16 demultiplexer (4 select lines) Etc…,
1×2 De-multiplexer:
In the 1 to 2 De-multiplexer, there are only two outputs, i.e., Y0, and Y1, 1 selection lines, i.e.,
S0, and single input, i.e., A. On the basis of the selection value, the input will be connected to
one of the outputs. The block diagram and the truth table of the 1×2 multiplexer are given
below.
Block Diagram and Truth Table
Logic Circuit
1×4 De-multiplexer:
In 1 to 4 De-multiplexer, there are total of four outputs, i.e., Y0, Y1, Y2, and Y3, 2 selection
lines, i.e., S0 and S1 and single input, i.e., A. On the basis of the combination of inputs which
are present at the selection lines S0 and S1, the input be connected to one of the outputs. The
block diagram and the truth table of the 1×4 multiplexer are given below.
Logic Circuit
1×8 De-multiplexer
In 1 to 8 De-multiplexer, there are total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and
Y7, 3 selection lines, i.e., S0, S1and S2 and single input, i.e., A. On the basis of the
combination of inputs which are present at the selection lines S0, S1 and S2, the input will be
connected to one of these outputs. The block diagram and the truth table of the 1×8 de-
multiplexer are given below.
Block Diagram
Truth Table
Logic Circuit
1 x 16 De-multiplexer
In 1×16 de-multiplexer, there are total of 16 outputs, i.e., Y0, Y1, …, Y16, 4 selection lines,
i.e., S0, S1, S2, and S3 and single input, i.e., A. On the basis of the combination of inputs
which are present at the selection lines S0, S1, and S2, the input will be connected to one of
these outputs. The block diagram and the truth table of the 1×16 de-multiplexer are given
below.
Logic Circuit
Advantages
 A demultiplexer or Demux is used to divide the mutual signals back into separate
streams.
 The function of Demux is quite opposite to MUX.
 The Audio or Video signals transmission needs a combination of Mux and Demux.
 Demux is used as a decoder within the security systems of banking sectors.
 The communication system efficiency can be enhanced through the combination of
Mux & Demux.
Disadvantages
 Bandwidth wastage might happen
 Because of the synchronization of the signals, delays might take place
Difference between multiplexer and demultiplexer
Multiplexer Demultiplexer
It is a data selector. It is a data distributor.
It has multiple inputs and a single output. It has a single input and multiple outputs.
It performs parallel to serial conversion. It performs serial to parallel conversion.
In time-division multiplexing, mux is used In time-division multiplexing, demux is used

at the transmitting end to transmit a single at the receiving end to receive the single
input data input data.
Encoders:
The combinational circuits that change the binary information into N output lines are known as
Encoders. The binary information is passed in the form of 2N input lines. The output lines
define the N-bit code for the binary information. In simple words, the Encoder performs the
reverse operation of the Decoder. At a time, only one input line is activated for simplicity. The
produced N-bit output code is equivalent to the binary information.
Types of Encoder
 2-1 Encoder (1 select line)
 4-1 Encoder (2 select lines)
 8-1 Encoder (3 select lines)
 16-1 Encoder (4 select lines) Etc…,
4-1 Encoder
In 4 to 2 line encoder, there are total of four inputs, i.e., Y0, Y1, Y2, and Y3, and two outputs,
i.e., A0 and A1. In 4-input lines, one input-line is set to true at a time to get the respective
binary code in the output side. Below are the block diagram and the truth table of the 4 to 2
line encoder.
Block Diagram
Logic Circuit and Truth Table
8 to 3 Line Encoder: (Octal to Binary)

The 8 to 3 line Encoder is also known as Octal to Binary Encoder. In 8 to 3 line encoder, there
is a total of eight inputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs, i.e., A0,
A1, and A2. In 8-input lines, one input-line is set to true at a time to get the respective binary
code in the output side. Below are the block diagram and the truth table of the 8 to 3 line
encoder.
Truth Table
Logic Circuit
16 to 4 Line Encoder: (Hexadecimal to Binary)
Decoders:
Basically, Decoder is a combinational logic circuit that converts coded input to coded outputs
provided both of these are different from one another. The name decoder means translating of
coded information from one format into another.
A decoder is a multiple input, multiple output logic circuit that changes codes i/ps into coded
o/ps, where both the inputs and outputs are dissimilar for instance n-to-2n, and binary coded
decimal decoders.
Types of Decoders
 1-2 decoder (1 select line)
 1-4 decoder (2 select lines)
 1-8 decoder (3 select lines)
 1-16 decoder (4 select lines) Etc…,
2 to 4 Line Decoder:
In the 2 to 4 line decoder, there is a total of three inputs, i.e., A0, and A1 and E and four
outputs, i.e., Y0, Y1, Y2, and Y3. For each combination of inputs, when the enable 'E' is set to
1, one of these four outputs will be 1. The block diagram and the truth table of the 2 to 4 line
decoder are given below.
Block Diagram:
Truth Table:
Logic Circuit
The 3 to 8 line decoder is also known as Binary to Octal Decoder. In a 3 to 8 line decoder,
there is a total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs,
i.e., A0, A1, and A2. This circuit has an enable input 'E'. Just like 2 to 4 line decoder, when
enable 'E' is set to 1, one of these four outputs will be 1. The block diagram and the truth table
of the 3 to 8 line encoder are given below.
Block Diagram:
Truth Table:
Logic Circuit
In the 4 to 16 line decoder, there is a total of 16 outputs, i.e., Y0, Y1, Y2,……, Y16 and four
inputs, i.e., A0, A1, A2, and A3. The 3 to 16 line decoder can be constructed using either 2 to
4 decoder or 3 to 8 decoder. There is the following formula used to find the required number of
lower-order decoders. Required number of lower order decoders=m2/m1
Block Diagram:
Truth Table:
Logic Circuit
Parity Generators / Checkers:

What is Parity Bit?
Definition: The parity bit or check bit are the bits added to the binary code to check whether
the particular code is in parity or not, for example, whether the code is in even parity or odd
parity is checked by this check bit or parity bit. The parity is nothing but number of 1‟s and
there are two types of parity bits they are even bit and odd bit.
In odd parity bit, the code must be in an odd number of 1‟s, for example, we are taking 6-bit
code 100011, this code is said to be odd parity because there is three number of 1‟s in the code
which we have taken. In even parity bit the code must be in even number of 1‟s, for example,
we are taking 6-bit code 101101, this code is said to be even parity because there are four
number of 1‟s in the code which we have taken.
What is the Parity Generator?
Definition: The parity generator is a combination circuit at the transmitter, it takes an original
message as input and generates the parity bit for that message and the transmitter in this
generator transmits messages along with its parity bit. Types of Parity generator,
Even Parity Generator

Let us assume that a 3-bit message is to be transmitted with an even parity bit. Let the three
inputs A, B and C are applied to the circuit and output bit is the parity bit P. The total number
of 1s must be even, to generate the even parity bit P. The figure below shows the truth table of
even parity generator in which 1 is placed as parity bit in order to make all 1s as even when the
number of 1s in the truth table is odd.
Logic Circuit
Odd Parity Generator

Let us consider that the 3-bit data is to be transmitted with an odd parity bit. The three inputs
are A, B and C and P is the output parity bit. The total number of bits must be odd in order to
generate the odd parity bit. In the given truth table below, 1 is placed in the parity bit in order
to make the total number of bits odd when the total number of 1s in the truth table is even.
Logic Circuit
What is the Parity Check?
Definition: The combinational circuit at the receiver is the parity checker. This checker takes
the received message including the parity bit as input. It gives output „1‟ if there is some error
found and gives output „0‟ if no error is found in the message including the parity bit. Types of
Parity Checker,
Even Parity Checker

Consider that three input message along with even parity bit is generated at the transmitting
end. These 4 bits are applied as input to the parity checker circuit, which checks the possibility
of error on the data. Since the data is transmitted with even parity, four bits received at circuit
must have an even number of 1s. If any error occurs, the received message consists of odd
number of 1s. The output of the parity checker is denoted by PEC (Parity Error Check). The
below table shows the truth table for the Even Parity Checker in which PEC = 1 if the error
occurs, i.e., the four bits received have odd number of 1s and PEC = 0 if no error occurs, i.e., if
the 4-bit message has even number of 1s.
Logic Circuit
Odd Parity Checker

Consider that a three bit message along with odd parity bit is transmitted at the transmitting
end. Odd parity checker circuit receives these 4 bits and checks whether any error are present
in the data. If the total number of 1s in the data is odd, then it indicates no error, whereas if the
total number of 1s is even then it indicates the error since the data is transmitted with odd
parity at transmitting end. The below figure shows the truth table for odd parity generator
where PEC =1 if the 4-bit message received consists of even number of 1s (hence the error
occurred) and PEC= 0 if the message contains odd number of 1s (that means no error).
Logic Circuit
Magnitude Comparators:
A magnitude digital Comparator is a combinational circuit that compares two digital or binary
numbers in order to find out whether one binary number is equal, less than, or greater than the
other binary number. We logically design a circuit for which we will have two inputs one for A
and the other for B and have three output terminals, one for A > B condition, one for A = B
condition, and one for A < B condition.
Types of Magnitude Comparators,
 1-bit Magnitude Comparator

 2-bit Magnitude Comparator
 n-bit Magnitude Comparator
1-bit Magnitude Comparator Circuit

A comparator used to compare two bits is called a single-bit comparator. It consists of two
inputs each for two single-bit numbers and three outputs to generate less than, equal to, and
greater than between two binary numbers. The truth table for a 1-bit comparator is given
below:
Logic Circuit
2-bit Magnitude Comparator Circuit

A comparator used to compare two binary numbers each of two bits is called a 2-bit Magnitude
comparator. It consists of four inputs and three outputs to generate less than, equal to, and
greater than between two binary numbers. The truth table for a 2-bit comparator is given
below:
Block Diagram
Truth Table
Logic Circuit
VHDL Coding for Combinational Circuits

HALF ADDER:
LIBRARY DECLARATION
Library IEEE;
ENTITY DECLARATION
Entity halfadder is
Sum, Carry: out std_logic);
End halfadder;
Architecture behavioral of halfadder is
Begin
Process (A, B)
Begin
Sum <= A XOR B;
Carry <= A AND B;
End process;
End behavioral;
FULL ADDER HA+HA (TYPE)

LIBRARY DECLARATION
Library IEEE;
ENTITY DECLARATION
Entity fulladder is
Port (A, B, C: in std_logic;
Sum, Carry: out std_logic);
End fulladder;
Architecture behavioral of fulladder is
Begin
Process (A, B, C)
Begin
Sum <= A XOR B XOR C;
Carry <= (A AND B) OR ((A XOR B) AND C);
End process;
End behavioral;
HALF SUBTRACTOR:
LIBRARY DECLARATION
Library IEEE;
ENTITY DECLARATION
Entity halfsubtractor is
Difference, Borrow: out std_logic);
End halfsubtractor;
Architecture behavioral of halfsubtractor is
Begin
Process (A, B)
Begin
Difference <= A XOR B;
Borrow <= (NOT A) AND B;
End process;
End behavioral;
FULL SUBTRACTOR (HS+HS TYPE)
LIBRARY DECLARATION
Library IEEE;
ENTITY DECLARATION
Entity fullsubtractor is
Port (A, B, C: in std_logic;
Difference, Borrow: out std_logic);
End fullsubtractor;
Architecture behavioral of fullsubtractor is
Begin
Process (A, B, C)
Begin
Difference <= A XOR B XOR C;
Borrow <= (NOT (A XOR B) AND C) OR (NOT A AND B);
End process;
End behavioral;
THREE BIT MULTIPLEXER:

LIBRARY DECLARATION
Library IEEE;
ENTITY DECLARATION
Entity mux is
Port (S0,S1,S2,D0,D1,D2,D3,D4,D5,D6,D7:in std_logic;
Y: out std_logic);
End mux;
Architecture behavioral of mux is
Signal M: std_logic_vector (0 to 7);
Begin
M (0) <= (NOT s0) AND (NOT s1) AND (NOT s2) AND d0;
M (1) <= s0 AND (NOT s1) AND (NOT s2) AND d1;
M (2) <= (NOT s0) AND s1 AND (NOT s2) AND d2;
M (3) <= s0 AND s1 AND (NOT s2) AND d3;
M (4) <= (NOT s0) AND (NOT s1) AND s2 AND d4;
M (5) <= s0 AND (NOT s1) AND s2 AND d5;
M (6) <= (NOT s0) AND s1 AND s2 AND d6;
M (7) <= s0 AND s1 AND s2 AND d7;
Y <= M(0) OR M(1) OR M(2) OR M(3) OR M(4) OR M(5) OR M(6) OR M(7);
End behavioral;
THREE BIT DEMULTIPLEXER:

LIBRARY DECLARATION
Library IEEE;
ENTITY DECLARATION
Entity eighttoone is
Port (S0, S1, S2, I: in std_logic;
D: out std_logic_vector(0 to 7));
End eighttoone;
Architecture three bit of eighttoone is
Begin
Process (S0, S1, S2, I)
Begin
D (0) <= (NOT S0) AND (NOT S1) AND (NOT S2) AND I;
D (1) <= S0 AND (NOT S1) AND (NOT S2) AND I;
D (2) <= (NOT S0) AND S1 AND (NOT S2) AND I;
D (3) <= S0 AND S1 AND (NOT S2) AND I;
D (4) <= NOT S0 AND (NOT S1) AND S2 AND I;
D (5) <= S0 AND (NOT S1) AND S2 AND I;
D (6) <= NOT S0 AND S1 AND S2 AND I;
D (7) <= S0 AND S1 AND S2 AND I;
End process;
End three bit;
THREE BIT ENCODER:

LIBRARY DECLARATION
Library IEEE;
ENTITY DECLARATION
Entity threebit is
Port (S0, S1, S2, S3, S4, S5, S6, S7: in std_logic;
A, B, C: out std_logic);
End threebit;
Architecture encoder of threebit is
Begin
Process (S0, S1, S2, S3, S4, S5, S6, S7)
Begin
C <= S1 OR S3 OR S5 OR S7;
B <= S2 OR S3 OR S6 OR S7;
A <= S4 OR S5 OR S6 OR S7;
End process;
End encoder;
THREE BIT DECODER:

LIBRARY DECLARATION
Library IEEE;
ENTITY DECLARATION
Entity decoder is
Port (s0, s1, s2: in std_logic;
D: out std_logic_vector (0 to 7));
End decoder;
Architecture behavioral of decoder is
Begin
Process (s0, s1, s2)
Begin
D (0) <= (NOT s0) AND (NOT s1) AND (NOT s2);
D (1) <= s0 AND (NOT s1) AND (NOT s2);
D (2) <= (NOT s0) AND s1 AND (NOT s2);
D (3) <= s0 AND s1 AND (NOT s2);
D (4) <= (NOT s0) AND (NOT s1) AND s2;
D (5) <= s0 AND (NOT s1) AND s2;
D (6) <= (NOT s0) AND s1 AND s2;
D (7) <= s0 AND s1 AND s2;
End process;
End behavioral;
UNIT - IV
SEQUENTIAL LOGIC CIRCUITS
Flip Flops – RS, Clocked RS, JK, JK Master Slave, D and T Flip Flops:
What is Flip-Flop?
A flip flop is a binary storage device. It can store binary bit either 0 or 1. It has two stable
states HIGH and LOW i.e. 1 and 0. It has the property to remain in one state indefinitely until
it is directed by an input signal to switch over to the other state. We can construct a basic flip-
flop using four-NOR and four-NAND gates.
Types of Flip-Flops
 S-R Flip Flop (SR "set-reset")

 J-K Flip Flop
 T Flip Flop (T "toggle")
 D Flip Flop (D "data" or "delay")
RS / SR Flip Flop
The S-R flip flop is the most common flip flop used in the digital system. In SR flip flop, when
the set input "S" is true, the output Y will be high, and Y' will be low. It is required that the
wiring of the circuit is maintained when the outputs are established. We maintain the wiring
until set or reset input goes high, or power is shutdown.
Clocked RS Flip Flop

A gated SR latch (or clocked SR Latch) can only change its output state when there is an
enabling signal along with required inputs. For this reason it is also known as a synchronous
SR latch. So, gated S-R latch is also called clocked S-R Flip flop or synchronous S-R
latch.Since this latch responds to the applied inputs only when the level of the clock pulse is
high, this type of flip-flop is also called level triggered flip flop. The logical circuit of a Gated
SR Latch or Clocked SR Flip-Flop is shown below.
JK Flip Flop
The JK flip flop is used to remove the drawback of the S-R flip flop, i.e., undefined states. The
JK flip flop is formed by doing modification in the SR flip flop. The S-R flip flop is improved
in order to construct the J-K flip flop. When S and R input is set to true, the SR flip flop gives
an inaccurate result. But in the case of JK flip flop, it gives the correct output.
In J-K flip flop, if both of its inputs are different, the value of J at the next clock edge is taken
by the output Y. If both of its input is low, then no change occurs, and if high at the clock
edge, then from one state to the other, the output will be toggled. The JK Flip Flop is a Set or
Reset Flip flop in the digital system.
JK Master Slave Flip Flop

The master-slave flip-flop is designed by two JK flip-flops connected in series. The output of
the first flip-flop is connected to the input of the second flip-flop. The CLK terminals of the
flip-flops are connected through a NOT gate. When the clock pulse is high the first or master
flip-flop is active and when the clock pulse is low the second or slave flip-flop is active.
D Flip Flop
D flip flop is a widely used flip flop in digital systems. The D flip flop is mostly used in shift-
registers, counters, and input synchronization.
T Flip Flop:
Just like JK flip-flop, T flip flop is used. Unlike JK flip flop, in T flip flop, there is only single
input with the clock input. The T flip flop is constructed by connecting both of the inputs of JK
flip flop together as a single input.
Applications of Flip-Flops:
These are the various types of flip-flops being used in digital electronic circuits and the
applications of Flip-flops are as specified below.
 Counters
 Frequency Dividers
 Shift Registers
 Storage Registers
 Bounce elimination switch
 Data storage
 Data transfer
 Latch
 Registers
 Memory
Shift Registers and its Types:

What is a Shift Register?
A register can be defined as when a set of FFs can be connected within the series, the
definition of the shift register is when the stored data can be moved in the registers. It is a
sequential circuit, mainly used to store the data, & moves it to the output on each CLK (clock)
cycle. Types of Shift Registers
 Serial in Serial out (SISO) Shift Register
 Serial in parallel out (SIPO) Shift Register
 Parallel in Serial out (PISO) Shift Register
 Parallel in Parallel out (PIPO) Shift Register
Serial-In Serial-Out(SISO) Shift Register

It is one of the simplest of all the shift registers. The Serial In Serial Out shift register is
constructed with four flip-flops. It has one input, one output and a clock pulse input. The block
diagram is shown below.
Here, the data is inserted at the input bit by bit. For each clock pulse, the data bit is shifted
from one flip-flop to the next flip-flop. At the output side, the inserted data will be received bit
by bit for each clock pulse. Since the inserted data and the received data are done in a bit-by-
bit fashion, this register is known as the Serial in Serial out shift register.
Serial-In Parallel-Out(SIPO) shift register

In the Serial-in Parallel-out shift register, the data is inserted bit by bit serially. The data input
at all the flip-flops is shifted by one position for every clock pulse. The output at each flip-flop
can be taken out in a parallel fashion. The circuit of the Serial-in Parallel-out shift register is
shown in the figure below.
During the clock pulse, the D input of each flip-flop is shifted to the Q output. The Q outputs
of all the flip-flops are tapped separately. Thus the parallel output data(QAQBQCQD) will
have the bit from each individual register. The Serial-in Parallel-out shift register is mainly
used for communication purposes where the serial input data in converted into parallel output
data.
Parallel-In Serial-Out(PISO) shift register

It is just opposite to the one we discussed above. In the parallel In Serial Out Shift register, the
data is inserted or loaded into each register in parallel and the inserted data is received serially
at the output. Here the data is to be loaded at the input of each flip-flop. At the same time,
while applying the clock pulse, the data at the output of each flip-flop will be moved to the
input of the next flip-flop. So to avoid conflicts between the loaded data and the shifted data at
the inputs, the control input is added in this shift register. The Parallel In Serial Out Shift
register is shown in the below diagram.
Parallel-In Parallel-Out(PIPO) shift register

In Parallel-in Parallel-out shift register(PIPO), the input data is loaded parallelly into each
individual register and the output is received from each flip-flop output. It is used for the
temporary storage of data or as time delay devices. The block diagram of the Parallel-in
Parallel-out shift register is shown below.
D flip-flop is used for the construction of the Parallel-in Parallel-out shift register. The four-bit
data is loaded at the input of four flip-flops. When a clock pulse is applied, the loaded data is
shifted to the output of the flip-flop, which is tapped out for measurements. A single clock
pulse will load the data and unload the data.
Ring Counters:
A ring counter is a special type of application of the Serial IN Serial OUT Shift register. The
only difference between the shift register and the ring counter is that the last flip flop outcome
is taken as the output in the shift register. But in the ring counter, this outcome is passed to the
first flip flop as an input. All of the remaining things in the ring counter are the same as the
shift register.
In this diagram, we can see that the clock pulse (CLK) is applied to all the flip-flops
simultaneously. Therefore, it is a Synchronous Counter. Also, here we use Overriding input
(ORI) for each flip-flop. Preset (PR) and Clear (CLR) are used as ORI. When PR is 0, then the
output is 1. And when CLR is 0, then the output is 0. Both PR and CLR are active low signal
that always works in value 0.
Asynchronous / Ripple Counters:

Ripple counter is a special type of Asynchronous counter in which the clock pulse ripples
through the circuit. The n-MOD ripple counter forms by combining n number of flip-flops.
The n-MOD ripple counter can count 2n states, and then the counter resets to its initial value.
Features of the Ripple Counter:

 Different types of flip flops with different clock pulse are used.
 It is an example of an asynchronous counter.
 The flip flops are used in toggle mode.
 The external clock pulse is applied to only one flip flop. The output of this flip flop is
treated as a clock pulse for the next flip flop.
 In counting sequence, the flip flop in which external clock pulse is passed, act as LSB.
A counter may be an up counter that counts upwards or can be a down counter that counts
downwards or can do both i.e.count up as well as count downwards depending on the input
control. The sequence of counting usually gets repeated after a limit. When counting up, for
the n-bit counter the count sequence goes from 000, 001, 010, … 110, 111, 000, 001, … etc.
When counting down the count sequence goes in the opposite manner: 111, 110, … 010, 001,
000, 111, 110, … etc.
In the circuit shown in the above figure, Q0(LSB) will toggle for every clock pulse because JK
flip-flop works in toggle mode when both J and K are applied 1, 1, or high input. The
following counter will toggle when the previous one changes from 1 to 0.
Timing diagram: Let us assume that the clock is negative edge triggered so the above the
counter will act as an up counter because the clock is negative edge triggered and output is
taken from Q.
Synchronous Counter:
Definition: The synchronous counter is a type of counter in which the clock signal is
simultaneously provided to each flip-flop present in the counter circuit. More specifically, we
can say that each flip-flop is triggered in synchronism with the clock input.
Circuit and Operation of Synchronous Counter
The circuit is composed of 3 J-K flip-flops and 2 AND gates. And the clock signal to trigger
the flip-flop is provided at the same time. It is noteworthy here that only the input terminal of
flip-flop A is provided with active high signal and therefore it toggles at the falling edge of
each clock input. Furthermore, the input to flip-flop B will be provided through an AND gate
whose output will depend on the input and output of previous flip-flop i.e., B in this case. And
the gate turns on and causes flip-flop B to toggle only when the output of flip-flop A will be
high. In a similar way, the input to flip-flop C will be the output of 2nd AND gate. Therefore,
flip-flop C toggles only when gate A2 will be on. And A2 will be on only in case when the
output of A1, as well as flip-flop B, will be high.
It is noteworthy in case of synchronous counters that the resetting of all the flip-flops in the
circuit occurs at the same time. Thus the settling time of the counter is equivalent to the
propagation delay time of each flip-flop in the circuit. Thus the synchronous counter can be
operated with a clock signal of high frequency.
Timing Diagram of 3-bit Synchronous Counter
Up Down counter:
What is an Up/Down Counter?
The up/Down counter is also known as the bidirectional counter which is used to count in any
direction based on the condition of the input control pin. These are used in different
applications to count up from zero to provide a change within the output condition on attaining
a fixed value & others count down from a fixed value to zero to give an output condition
change. There are some types of counters like TTL 74LS190 & 75LS191 which can function
in both up & down count mode based on the condition of an input pin of up/down count mode.
Up/Down Counter Circuit

The circuit diagram of the 3-bit up/down counter is shown below. This circuit is designed with
flip-flops. In the up counter, every flip-flop is activated through the normal o/p of the previous
FF (from „Q‟ o/p of primary flip-flop to the next FF‟s CLK); while in a down-counter, every
flip-flop is activated through the complement o/p of the previous FF (from the output of first
FF to CLK of next FF).
Up/Down Counter Working

The up/down counter operation can be controlled through the control input of up-down. This
up/down counter works in two modes like count up mode and countdown mode. The timing
forms of count up and countdown are shown below.
Mod-3, Mod-5 Counters:

Modulo 3 Counter
A modulo 3 (MOD-3) counter can be made using three D-type flip-flops. We simply look for
the count of 3 which is 011 in binary. In this type of counter application, this is the only time
when those bits will be 1‟s at the same time, therefore we simply feed them into an AND gate
to generate the RESET control signal. When the counter reaches this number, the output from
the AND gate will initiate a reset on all the D-type flip-flops, and the count will begin again.
Modulo 5 Counter
A MOD-5 counter would produce a 3-bit binary count sequence from 0 to 4, as 000 is a valid
count state, giving us a binary count sequency of: 000, 001, 010, 011, 100. Therefore we need
the counter circuit to reset itself on the next counting state as the count of six (the next count)
would produce an output condition of: QA = 1, QB = 0, and QC = 1 in binary as shown in the
following state diagram.
MOD-5 Count Sequence
While it appears that the counter counts up to the 101 state, when the asynchronous count
sequence reaches the next binary state of 101 (5), the combinational logic decoding circuit will
detect this 101 condition, so the AND gate will produce a logic level “1” (HIGH) output
resetting the counter back to its initial zero state. Thus the counter only remains in this 101
temporary state for only a few nanoseconds before it resets back to 000.
Therefore we can use the input decoding of the AND gate to reset the counter back to zero
after its output of 5 (decimal) count giving us the required MOD-5 counter. When the output
from the decoding circuit is LOW, it has no effect on the counting sequence.
Decade Counter (BCD Counter):

A binary coded decimal (BCD) is a serial digital counter that counts ten digits .And it resets for
every new clock input. As it can go through 10 unique combinations of output, it is also called
as “Decade counter”. A BCD counter can count 0000, 0001, 0010, 1000, 1001, 1010, 1011,
1110, 1111, 0000, and 0001 and so on.
A 4 bit binary counter will act as decade counter by skipping any six outputs out of the 16 (24)
outputs. There are some available ICs for decade counters which we can readily use in our
circuit, like 74LS90. It is an asynchronous decade counter.
The above figure shows a decade counter constructed with JK flip flop. The J output and K
outputs are connected to logic 1. The clock input of every flip flop is connected to the output
of next flip flop, except the last one.
The output of the NAND gate is connected in parallel to the clear input „CLR‟ to all the flip
flops. This ripple counter can count up to 16 i.e. 24.
Decade Counter Operation

When the Decade counter is at REST, the count is equal to 0000. This is first stage of the
counter cycle. When we connect a clock signal input to the counter circuit, then the circuit will
count the binary sequence. The first clock pulse can make the circuit to count up to 9 (1001).
The next clock pulse advances to count 10 (1010). Then the ports X1 and X3 will be high. As
we know that for high inputs, the NAND gate output will be low. The NAND gate output is
connected to clear input, so it resets all the flip flop stages in decade counter. This means the
pulse after count 9 will again start the count from count 0.
Truth Table of Decade Counter
The above table describes the counting operation of Decade counter. It represents the count of
circuit for decimal count of input pulses. The NAND gate output is zero when the count
reaches 10 (1010). The count is decoded by the inputs of NAND gate X1 and X3. After count
10, the logic gate NAND will trigger its output from 1 to 0, and it resets all flip flops.
Applications:
They are widely used in lots of other designs as well such as processors, calculators, real time
clock etc. Some common uses and application of synchronous counters are follow:
 Alarm Clock, Set AC Timer, Set time in camera to take the picture, flashing light
indicator in automobiles, car parking control etc.
 Counting the time allotted for special process or event by the scheduler.
 The UP/DOWN counter can be used as a self-reversing counter.
 It is also used as clock divider circuit.
 The parallel load feature can be used to preset the counter for some initial count.
 Commons used in home appliances like washing machine, microwave own, Time
schedule led indicator, key board controller etc.
 They are also used in machine moving control.
 Mostly used in digital clocks and multiplexing circuits.
 They are used to generate saw-tooth waveform (Stair case voltage)
 It is also used in digital to analog converters.
Difference between Synchronous and Asynchronous Counter
S.No. Synchronous Counter Asynchronous Counter
1. In the synchronous counter there are In Asynchronous counters there are

continuous clock input signals with flip- different clock signals used to
flops used to produce the output. produce the output.
2. In the synchronous counter, the operation In Asynchronous counter the

is faster. operation is slower.
3. Synchronous counter is also known as Asynchronous counter is also known

Parallel counter. as Serial counter.
4. Synchronous counter produces less error Asynchronous counter produces

than asynchronous counter. more errors than a synchronous
counter.
5. Design of the Synchronous counter is Design of the Asynchronous counter

complex. is simple.
6. Synchronous counters can work with a Asynchronous counters can work

flexible number of count sequences. with a fixed number of count
sequences.
UNIT - V
D/A AND A/D CONVERTERS
Digital to Analog Converters:

A Digital to Analog Converter (DAC) converts a digital input signal into an analog output
signal. The digital signal is represented with a binary code, which is a combination of bits 0
and 1. This chapter deals with Digital to Analog Converters in detail. A Digital to Analog
Converter (DAC) consists of a number of binary inputs and a single output.
Types of DACs
There are two types of DACs
 Weighted Resistor DAC
 R-2R Ladder DAC
Resistive Divider Type: (Weighted Resistor DAC)

A weighted resistor DAC produces an analog output, which is almost equal to the digital
(binary) input by using binary weighted resistors in the inverting adder circuit. In short, a
binary weighted resistor DAC is called as weighted resistor DAC.
Recall that the bits of a binary number can have only one of the two values. i.e., either 0 or 1.
Let the 3-bit binary input is b2b1b0. Here, the bits b2 and b0 denote the Most Significant Bit
(MSB) and Least Significant Bit (LSB) respectively.
The digital switches shown in the above figure will be connected to ground, when the
corresponding input bits are equal to „0‟. Similarly, the digital switches shown in the above
figure will be connected to the negative reference voltage, −VR when the corresponding input
bits are equal to „1‟.
In the above circuit, the non-inverting input terminal of an op-amp is connected to ground.
That means zero volts is applied at the non-inverting input terminal of op-amp. According to
the virtual short concept, the voltage at the inverting input terminal of opamp is same as that of
the voltage present at its non-inverting input terminal. So, the voltage at the inverting input
terminal‟s node will be zero volts. The nodal equation at the inverting input terminal‟s node is:
The above equation represents the output voltage equation of a 3-bit binary weighted resistor
DAC. Since the number of bits are three in the binary (digital) input, we will get seven
possible values of output voltage by varying the binary input from 000 to 111 for a fixed
reference voltage, VR. We can write the generalized output voltage equation of an N-bit binary
weighted resistor DAC as shown below based on the output voltage equation of a 3-bit binary
weighted resistor DAC.
Disadvantages of a Binary Weighted Resistor DAC
 The difference between the resistance values corresponding to LSB & MSB will
increase as the number of bits present in the digital input increases.
 It is difficult to design more accurate resistors as the number of bits present in the
digital input increases.
Ladder Type: (R-2R Ladder DAC)

The R-2R Ladder DAC overcomes the disadvantages of a binary weighted resistor DAC. As
the name suggests, R-2R Ladder DAC produces an analog output, which is almost equal to the
digital (binary) input by using a R-2R ladder network in the inverting adder circuit.
Recall that the bits of a binary number can have only one of the two values. i.e., either 0 or 1.
Let the 3-bit binary input is b2b1b0. Here, the bits b2 and b0 denote the Most Significant Bit
(MSB) and Least Significant Bit (LSB) respectively.
The digital switches shown in the above figure will be connected to ground, when the
corresponding input bits are equal to „0‟. Similarly, the digital switches shown in above figure
will be connected to the negative reference voltage, −VR when the corresponding input bits are
equal to „1‟. It is difficult to get the generalized output voltage equation of a R-2R Ladder
DAC. But, we can find the analog output voltage values of R-2R Ladder DAC for individual
binary input combinations easily.
Advantages of a R-2R Ladder DAC
 R-2R Ladder DAC contains only two values of resistor: R and 2R. So, it is easy to
select and design more accurate resistors.
 If more number of bits are present in the digital input, then we have to include required
number of R-2R sections additionally.
Accuracy and Resolution:

What is accuracy DAC?
Absolute accuracy is the maximum deviation between the actual converter output and the
ideal converter output. Relative accuracy is the maximum deviation after gain and offset
errors have been removed.
Why is resolution important for DAC?
For a DAC, resolution describes the number of bits available in the digital domain to
represent the analog output signal. With the resolution, we can calculate the number of
codes, or total number of possible outputs, that we can write to the converter.
Two very important aspects of the D/A converter are the resolution and the accuracy of the
conversion. There is a definite distinction between the two, and you should clearly understand
the differences. The accuracy of the D/A converter is primarily a function of the accuracy of
the precision resistors used in the ladder and the precision of the reference voltage supply used.
Accuracy is a measure of how close the actual output voltage is to the theoretical output value.
For example, suppose that the theoretical output voltage for a particular input should be+ 10
V.An accuracy of l0 percent means that the actual output voltage must be somewhere between
+9 and + 11 V. Similarly, if the actual output voltage were somewhere between +9.9 and+ 10.1
V, this would imply an accuracy of 1 percent.
Resolution, on the other hand, defines the smallest increment in voltage that can be discerned.
Resolution is primarily a function of the number ofbits in the digital input signal; that is, the
smallest increment in output voltage is determined by the LSB.
Analog to Digital Converters:

What is Analog to Digital Converter?
A converter that is used to change the analog signal to digital is known as an analog to
digital converter or ADC converter. This converter is one kind of integrated circuit or IC that
converts the signal directly from continuous form to discrete form. This converter can be
expressed in A/D, ADC, A to D. The inverse function of DAC is nothing but ADC.
Counter:
The counter type ADC is constructed using a binary counter, DAC and a comparator. The
output voltage of a DAC is VD which is equivalent to corresponding digital input to DAC.
The following figure shows the n-bit counter type ADC.
Operation:
The n-bit binary counter is initially set to 0 by using reset command. Therefore the
digital output is zero and the equivalent voltage VD is also 0V. When the reset command is
removed, the clock pulses are allowed to go through AND gate and are counted by the binary
counter. The D to A converter (DAC) converts the digital output to an analog voltage and
applied as the inverting input to the comparator.
The output of the comparator enables the AND gate to pass the clock. The number of
clock pulses increases with time and the analog input voltage VD is a rising staircase
waveform as shown in figure below. The counting will continue until the DAC output VD,
equals and just rises more than unknown analog input voltage VA. Then the comparator output
becomes low and this disables the AND gate from passing the clock. The counting stops at the
instance VA< VD, and at that instant the counter stops its progress and the conversion is said
to be complete.
The numbers stored in the n-bit counter is the equivalent n-bit digital data for the given
analog input voltage.
Advantages:
 Simple construction.
 Easy to design and less expensive.
 Speed can be adjusted by adjusting the clock frequency.
 Faster than dual slope type ADC.
Ramp Type:
A ramp-type analog-to-digital converter (also known as ramp-compare or time-base ADC)
comprises five basic circuits: a ramp generator, a counter, a comparator circuit, a clock pulse
generator, and a gate circuit, which are simultaneously operated to provide analog-to-digital
conversion. The block diagram of a typical ramp-type ADC is shown in the figure below.
Two inputs are applied to the comparator in the figure above. These are: (1) the analog input,
and (2) a linear ramp (sawtooth) voltage from the ramp generator. The generator output is
initiated each time a start signal is applied. The start signal also resets the counter to zero and
enables the gate circuit. As long as the analog and ramp generator inputs to the comparator
differ in magnitude, the clock pulse generator will be permitted to transmit pulses at a constant
repetition rate through the gate into the counter. When the two inputs to the comparator
become equal (as a result of the linearly rising sawtooth) the comparator will generate a stop
signal which disables the gate circuit and ends the comparison time interval. The disabled gate
circuit blocks the flow of pulses from the clock pulse generator to the counter. The number of
pulses accumulated in the counter during the comparison time interval is proportional to the
amplitude of the analog input voltage. The counter indication is the desired digital
representation of the input signal.
Simultaneous Conversion
This ADC converter IC is also called parallel ADC, which is the most widely used efficient
ADC in terms of its speed. This flash analog to digital converter circuit consists of a series of
comparators where each one compares the input signal with a unique reference voltage. At
each comparator, the output will be a high state when the analog input voltage exceeds the
reference voltage. This output is further given to the priority encoder for generating binary
code based on higher-order input activity by ignoring other active inputs. This flash type is a
high-cost and high-speed device.
Advantages:
 1)It is the fastest type of ADC because the conversion is performed simultaneously
through a set of comparators, hence referred as flash type ADC. Typical conversion
time is 100ns or less.
 2)The construction is simple and easier to design.
Disadvantages:
 1)It is not suitable for higher number of bits.
 2)To convert the analog input voltage into a digital signal of n-bit output, (2n – 1)
comparators are required. The number of comparators required doubles for each added
bit.
Dual Slope Type:

In this type of ADC converter, comparison voltage is generated by using an integrator circuit
which is formed by a resistor, capacitor, and operational amplifier combination. By the set
value of Vref, this integrator generates a sawtooth waveform on its output from zero to the
value Vref. When the integrator waveform is started correspondingly counter starts counting
from 0 to 2^n-1 where n is the number of bits of ADC.
Dual Slope Analog to Digital Converter
When the input voltage Vin equal to the voltage of the waveform, then the control
circuit captures the counter value which is the digital value of the corresponding analog input
value. This Dual slope ADC is a relatively medium cost and slow speed device.
Successive Approximation Type:

The SAR ADC a most modern ADC IC and much faster than dual slope and flash ADCs since
it uses a digital logic that converges the analog input voltage to the closest value. This circuit
consists of a comparator, output latches, successive approximation register (SAR), and D/A
converter.
Successive Approximation A/D Converter
At the start, SAR is reset and as the LOW to HIGH transition is introduced, the MSB of
the SAR is set. Then this output is given to the D/A converter that produces an analog
equivalent of the MSB, further it is compared with the analog input Vin. If comparator output
is LOW, then MSB will be cleared by the SAR, otherwise, the MSB will be set to the next
position. This process continues till all the bits are tried and after Q0, the SAR makes the
parallel output lines to contain valid data.
Advantages:
 1 Conversion time is very small.
 2 Conversion time is constant and independent of the amplitude of the analog
input signal VA.
Disadvantages:
 1 Circuit is complex.
 2 The conversion time is more compared to flash type ADC.
Accuracy and Resolution:

Accuracy
For converters, resolution is the number of bits per conversion cycle that the converter is
capable of processing. For example, a converter with 12 bits of resolution is often referred to
as “12 bits wide,” since 12 bits get processed in each conversion cycle. Higher resolution
correlates to a slower conversion rate.
Resolution
The accuracy of a converter refers to how many bits, from conversion to conversion, are
repeatable. That is, accuracy reflects how true the ADC‟s output reflects the actual input.
Accuracy is determined by the DC specifications for gain, offset, and linearity (integral
nonlinearity and differential nonlinearity). The accuracy as stated in the datasheet will always
be equal to or less than the resolution of the converter, with most experiences in the “less than”
category. A common experience is to see a solid conversion of several bits wide with an
unpredictable, nonsensical behavior from the last, or least significant bits (LSB). The ADC
still has a resolution as advertised, but accuracy suffers with the LSBs.
Resolution determines the precision of conversion at each interval. The precision of conversion
is, in turn, determined by the accuracy or fineness of quantization in the A/D conversion
process. If a signal value is quantized by 7 bits (binary digits) the precision of conversion
would be 1/27=1/128; and if a signal value is quantized by 10 bits, the precision of conversion
would be 1/210=1/1024. Thus, resolution is a function of the number of bits in the binary code
which is used in the conversion device. For instance, a resolution of one part in 1000 would
require 10 bits in the binary code.
Kilo (K)
2^10 = 1,024
Mega (M)
2^20 = 1,048,576
Giga (G)
2^30 = 1,073,741,824
Tera (T)
2^40 = 1,099,511,627,776
Peta (P)
2^50 = 1,125,899,906,842,624
Exa (E)
2^60 = 1,152,921,504,606,846,976
Zetta (Z)
2^70 = 1,180,591,620,717,411,303,424
Yotta (Y)
2^80 = 1,208,925,819,614,629,174,706,176

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SRI VASAVI COLLEGE, ERODE

(SELF FINANCE WING)

Expected Course Outcomes:

K1 - Remember; K2 - Understand; K3 - Apply; K4 - Analyze; K5 - Evaluate; K6 - Create

Unit:1 NUMBER SYSTEM AND CODES 12 hours

Unit:2 BOOLEAN ALGEBRA AND LOGIC GATES 12 hours

Unit:3 COMBINATIONAL LOGIC CIRCUITS 12 hours

Unit:5 D/A AND A/D CONVERTERS 12 hours

Total Lecture Hours 60 hours

Related Online Contents [MOOC, SWAYAM, NPTEL, Websites etc.]

Mapping with Programme Outcomes

TYPES OF NUMBER SYSTEMS

System Number of Symbols Symbols Example

Hexadecimal 16 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A,B, C, D, E, F A2F716

Octal to Binary Conversion

Octal to Binary Conversion

Decimal to Binary Conversion

Decimal to Binary Conversion (Fractional Part)

Hexadecimal to Binary Conversion

Hexadecimal to Binary Conversion (Fractional Part)

Binary number 0011 0011 0011 0011 . 1110 0011 1000

Answer 3333.E38)16= 11001100110011.111000111)2

Binary to Octal Conversion (Fractional Part)

Decimal to Octal Conversion

Therefore, (350)10 = (536)8 Therefore, (540)10 = (1034)8

Decimal to Octal Conversion (Fractional Part)

Hexadecimal to Octal Conversion

Therefore, (1A)16 = (32)8 Therefore, (2A5)16 = (1245)8

Hexadecimal to Octal Conversion (Fractional Part)

Binary to Decimal Conversion

Binary to Decimal Conversion (Fractional Part)

Octal to Decimal Conversion

Octal to Decimal Conversion (Fractional Part)

Hexadecimal to Decimal Conversion

Hexadecimal to Decimal Conversion (Fractional Part)

Binary to Hexadecimal Conversion

Binary to Hexadecimal Conversion (Fractional Part)

Octal to Hexadecimal Conversion

Octal to Hexadecimal Conversion (Fractional Part)

Decimal to Hexadecimal Conversion

Decimal to Hexadecimal Conversion (Fractional Part)

Numeral systems conversion table

Floating Point Representation:

Binary Number Subtraction Value

0–1 1 (Borrow 1 from the next high order digit)

1’s and 2’s Compliments:

2’s Complement of a Binary Number

Binary Coded Decimal (BCD):

Decimal Binary Number Binary Coded Decimal

1 0001 0000 0001

2 0010 0000 0010

3 0011 0000 0011

4 0100 0000 0100

5 0101 0000 0101

6 0110 0000 0110

7 0111 0000 0111

8 1000 0000 1000

9 1001 0000 1001

10 (1+0) 1010 0001 0000