DEMP

SRI VENKATESWARA ENGINEERING COLLEGE
KARAKAMBADI ROAD, TIRUPATI-517507
DEPARTMENT OF ELECTRONICS AND COMMUNICATIONENGINEERING
LECTURE NOTES
20A04304T- DIGITAL ELECTRONICS &

MICROPROCESSORS
Regulation : R20
Academic Year : 2021- 2022
Year / Semester : II / I
Prepared by
Mrs C Rajani, Mr. Revanthkumar T R, Mr. Manjunath K M ,Mrs C. Radhika
Head of the Department
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JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR
Course Code DIGITAL ELECTRONICS L T P C

20A04304T & 3 0 0 3
MICROPROCESSORS
Pre-requisite Basic Electronics Semester III
Course Objectives:
 To understand all the concepts of Logic Gates and Boolean Functions.
 To learn about Combinational Logic and Sequential Logic Circuits.
 To design logic circuits using Programmable Logic Devices.
 To understand basics of 8086 Microprocessor and 8051 Microcontroller.
 To understand architecture of 8086 Microprocessor and 8051 Microcontroller.
 To learn Assembly Language Programming of 8086 and 8051.
Course Outcomes (CO):
After Completion of this course, the student will be able to:
 Design any Logic circuit using basic concepts of Boolean Algebra.
 Design any Logic circuit using basic concepts of PLDs.
 Design and develop any application using 8086 Microprocessor.
 Design and develop any application using 8051 Microcontroller.
UNIT - I Number Systems & Code Conversion
Number Systems & Code conversion, Boolean Algebra & Logic Gates, Truth Tables, Universal
Gates,Simplification of Boolean functions, SOP and POS methods – Simplification of
Boolean functions
using K-maps,Signed and Unsigned Binary Numbers.
UNIT - II Combinational Circuits
Combinational Logic Circuits: Adders &Subtractors, Multiplexers, Demultiplexers, Encoders,
Decoders, Programmable Logic Devices.
UNIT - III Sequential Circuits
Sequential Logic Circuits: RS, Clocked RS, D, JK, Master Slave JK, T Flip-Flops, Shift
Registers, Types of Shift Registers, Counters, Ripple Counter, Synchronous Counters,
Asynchronous Counters, Up-Down Counter.
UNIT - IV Microprocessors - I
8085 microprocessor Review (brief details only), 8086 microprocessor, Functional Diagram,
register organization 8086, Flag register of 8086 and its functions, Addressing modes of 8086,
Pin diagram of8086, Minimum mode & Maximum mode operation of 8086, Interrupts in 8086.
UNIT – V Microprocessors - II
Instruction set of 8086, Assembler directives, Procedures and Macros, Simple programs
involving arithmetic, logical, branch instructions, Ascending, Descending and Block move
programs, String Manipulation Instructions. Overview of 8051 microcontroller, Architecture,
I/O ports and Memory organization, addressing modes and instruction set of 8051(Brief details
only), Simple Programs.
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Text Books:
1.M. Morris Mano, Michael D. Ciletti, Digital Design, Pearson Education, 5th Edition, 2013
2. Anil K. Maini, Digital Electronics: Principles, Devices and Applications, John Wiley &
Sons, Ltd.,2007.
3. N. Senthil Kumar, M. Saravanan, S. Jeevanathan, Microprocessor
andMicrocontrollers,Oxford Publishers, 2010.
4. Advanced microprocessors and peripherals-A.K Ray and K.M.Bhurchandani, TMH, 2nd
edition,2006.
Reference Books:
1. Thomas L. Floyd, Digital Fundamentals – A Systems Approach, Pearson, 2013.
2. Charles H. Roth, Fundamentals of Logic Design, Cengage Learning, 5th, Edition, 2004.
3. D.V.Hall, Microprocessors and Interfacing. TMGH, 2nd edition, 2006.
Kenneth.J.Ayala, The 8051 microcontroller, 3rd edition, Cengage Learning,2010.
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CONTENTS
1 Unit-I : Number Systems and Code Conversion Page NO

1.1 Introduction 5
1.2 Unit-I notes 6
1.3 Part A Questions 68
1.4 Part B Questions 70
2 Unit-II : Combinational Circuits
2.1 Introduction 72
2.2 Unit-II notes 73
3 Unit-III : Sequential Circuits
3.1 Introduction 151
3.2 Unit-III notes 152
4 Unit-IV : Microprocessors - I
5 Unit-V : Microprocessors - II
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UNIT-I
1.1 INTRODUCTION
Data are a collection of facts and figures which act as a raw material for information. The
processed data which help to make decisions or further manipulations are called information.
The total number of symbols used in a particular number system is called base or radix and each
symbol is called a digit. The decimal number system has base 10and the digits are 0, 1, 2, 3, 4, 5, 5, 6, 7,
8, 9.
To binary number system have base 2 and the binary digits 0 and 1. BIT is acontraction of the
world’s Binary digit.
Electronic and electrical components of a computer are bistable in nature. Thebinary digit 0 and 1
are most suitable and are conveniently used to express the two possible status. Internal circuit designs
of a computer become simplified as the circuits have to handle only two bits instead of ten digits
of the decimal system. Also all the operations that can be done in decimal system can also isdone
in binary system.
Conversion of number from one system to another is necessary to understand thelogic and process of
operations. Binary numbers can be easily converted to decimal numbers and vice versa.
Conversion of binary numbers to decimal numbers can be conveniently accomplished by either
actual expansion methodor by value box method. Similarly decimal numbers may be converted to
binary numbers either by value box method or by multiplication and division method.
Octal and hexadecimal number systems are also used in digital computers. Octalnumber system has
a base 8 and the symbols used are 0, 1, 2, 3, 4, 5, 6, 7.
Hexadecimal number system has a base 16 and the symbols used are 0, 1, 2, 3,
4, 5, 6, 7, 8, 9, A, B, C, D, E, F. Conversion of binary numbers to octal or hexadecimal numbers
and vice versa can also be easily accomplished.
Addition, subtraction, multiplication and division of binary number system can bemade by following
the usual rules of arithmetic.
What is the difference between data and information?
In data and information; data is the plural of the word datum, mean facts andmay be looked upon as
the raw materials for information. The term information cannot be precisely defined as it has some
abstract meaning. Information can
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be exchanged between different sources which are capable of understanding those. Information
enriches the knowledge of human being and helps to achieve the specific purpose. In the perspective
of computer science, we shall say thatinformation is data arranged in a relevant order to fulfil the
necessity of the problems concerned. Information may be represented by combinations of
symbols which may be alphabetic or numeric or both, i.e. alphanumeric.
Since in a digital computer data must be represented by numbers for processing work, different
number systems along with the specific one which a computer is able to manipulate.
1.2 Number Systems
In number system modern method of representing numbers symbolically is based on positional
notations.
In this method, each number is represented by a string of symbols where eachsymbol is associated
with a specific weight depending upon its positions. The totalnumber of different symbols which are
used in a particular number system iscalled the base or radix of the system and the weight of
each position of a particular number is expressed as a power of the base. When a number is formed
with the combination of the symbols, each symbol is then called a digit and the position of each
symbol is referred to as the digit position.
Thus if a number system has symbols starting from 0, and the digits of the systemare 0, 1, 2, ….. (r - 1)
then the base or radix is r. If a number D of this system then the magnitude of this number is given by
|D| = dn-1 rn-1 + dn-2 rn-2 + …… di ri + …… d1 r1 + d0 r0
Where each d₀ ranges from 0 to r - 1, such that
0 ≤ d₀ ≤ r - 1, i = 0, 1, 2 (n - 1).
The digit at the extreme left has the highest positional value and is generally called the Most
Significant Digit, or in short MSD; similarly, the digit occupying theextreme right position has the least
positional value and is referred to as the LeastSignificant Digit or LSD
1.2.1 Decimal Number System
Thebase or radix of Decimal numbersystem is 10. So, the numbersranging
from 0 to 9 are used in this number system. The part of the number thatlies to the left of the
decimal point is known as integer part. Similarly, the
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part of the number that lies to the right of the decimal point is known as fractional part.
In this number system, the successive positions to the left of the decimal point having
weights of 100, 101, 102, 103 and so on. Similarly, the successive positions to the right of
the decimal point having weights of 10-1, 10-2, 10-3 and so on. That means, each position
has specific weight,which is power of base 10
Example
Consider the decimal number 1358.246. Integer part of this number is 1358and fractional part
of this number is 0.246. The digits 8, 5, 3 and 1 have
weights of 100, 101, 102 and 103 respectively. Similarly, the digits 2, 4 and 6
have weights of 10-1, 10-2 and 10-3 respectively.

Mathematically, we can write it as
1358.246 = (1 × 103) + (3 × 102) + (5 × 101) + (8 × 100) + (2 × 10-1) +
(4 × 10-2) + (6 × 10-3)
After simplifying the right hand side terms, we will get the decimal number,which is on left
hand side.
1.2.2 Binary Number System
All digital circuits and systems use this binary number system. The base orradix of this number
system is 2. So, the numbers 0 and 1 are used in thisnumber system.
The part of the number, which lies to the left of the binary point is known as integer part.
Similarly, the part of the number, which lies to the right of the binary point is known as
fractional part.
In this number system, the successive positions to the left of the binary point having weights
of 20, 21, 22, 23 and so on. Similarly, the successive positions to the right of the binary point
having weights of 2-1, 2-2, 2-3 andso on. That means, each position has specific weight,
which is power ofbase 2.
Example
Consider the binary number 1101.011. Integer part of this number is 1101and fractional part of
this number is 0.011. The digits 1, 0, 1 and 1 of integer
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part have weights of 20, 21, 22, 23 respectively. Similarly, the digits 0, 1 and
1 of fractional part have weights of 2-1, 2-2, 2-3 respectively.Mathematically, we can write it
as
1101.011 = (1 × 23) + (1 × 22) + (0 × 21) + (1 × 20) + (0 × 2-1) +
(1 × 2-2) + (1 × 2-3)
After simplifying the right hand side terms, we will get a decimal number,which is an
equivalent of binary number on left hand side.
1.2.3 Octal Number System
The base or radix of octal number system is 8. So, the numbers ranging from 0 to 7 are used
in this number system. The part of the number thatlies to the left of the octal point is known as
integer part. Similarly, the partof the number that lies to the right of the octal point is known as
fractionalpart.
In this number system, the successive positions to the left of the octal pointhaving weights of 80,
81, 82, 83 and so on. Similarly, the successive positions to the right of the octal point having
weights of 8-1, 8-2, 8-3 and so on. Thatmeans, each position has specific weight, which is
power of base 8.
Example
Consider the octal number 1457.236. Integer part of this number is 1457 and fractional part
of this number is 0.236. The digits 7, 5, 4 and 1 have
weights of 80, 81, 82, 83 respectively. Similarly, the digits 2, 3 and 6 have
weights of 8-1, 8-2, 8-3 respectively. Mathematically, we can

write it as
1457.236 = (1 × 83) + (4 × 82) + (5 × 81) + (7 × 80) + (2 × 8-1) +
(3 × 8-2) + (6 × 8-3)
After simplifying the right hand side terms, we will get a decimal number, which is an
equivalent of octal number on left hand side.
1.2.4 Hexadecimal Number System
The base or radix of Hexa-decimal number system is 16. So, the numbersranging from 0 to 9
and the letters from A to F are used in this numbersystem. The decimal equivalent of Hexa-
decimal digits from A to F are 10to 15.
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The part of the number, which lies to the left of the hexadecimal point is known as integer
part. Similarly, the part of the number, which lies to the right of the Hexa-decimal point is
known as fractional part.
In this number system, the successive positions to the left of the Hexa-decimal point having
weights of 160, 161, 162, 163 and so on. Similarly, thesuccessive positions to the right of the
Hexa-decimal point having weights of 16-1, 16-2, 16-3 and so on. That means, each position
has specific weight,which is power of base 16.
Example
Consider the Hexa-decimal number 1A05.2C4. Integer part of this number is 1A05 and
fractional part of this number is 0.2C4. The digits 5, 0, A and 1have weights of 160, 161, 162,
163 respectively. Similarly, the digits 2, C and
4 have weights of 16-1, 16-2 and 16-3 respectively.

Mathematically, we can write it as
1A05.2C4 = (1 × 163) + (10 × 162) + (0 × 161) + (5 × 160) + (2 × 16-1) +
(12 × 16-2) + (4 × 16-3)

After simplifying the right hand side terms, we will get a decimal number,which is an
equivalent of Hexa-decimal number on left hand side.
1.3 Number Conversions
1.3.1 Binary to Octal
An easy way to convert from binary to octal is to group binary digits intosets of three, starting
with the least significant (rightmost) digits.
Binary: 11100101 = 11 100 101
011 100 101 Pad the most significant digits with zeros if necessary tocomplete a group of
three.
Then, look up each group in a table:
Binary: 000 001 010 011 100 101 110 111
Octal: 0 1 2 3 4 5 6 7
Binary = 011 100 101
Octal = 3 4 5 = 345 oct
1.3.2 Binary to Hexadecimal An equally easy way to convert from binaryto
hexadecimal is to group binary digits into sets of four, starting with the least significant (rightmost)
digits. 9
Binary: 11100101 = 1110 0101
Then, look up each group in a table:
Binary: 0000 0001 0010 0011 0100 0101 0110 0111
Hexadecimal: 0 1 2 3 4 5 6 7
Binary: 1000 1001 1010 1011 1100 1101 1110 1111
Hexadecimal: 8 9 A B C D E F
Binary = 1110 0101
Hexadecimal = E 5 = E5 hex
1.3.3 Binary to Decimal
Start the decimal result at 0.
Remove the most significant binary digit (leftmost) and add it to the result.If all binary digits
have been removed, you’re done. Stop.
Otherwise, multiply the result by 2.Go to
step 2.
B inary Digits Operation Decimal Result Operation Decimal Result
1 1100000000 +1 1 ×2 2
1100000000 +1 3 ×2 6
100000000 +1 7 ×2 14
00000000 +0 14 ×2 28
0000000 +0 28 ×2 56
000000 +0 56 ×2 112
00000 +0 112 ×2 224
0000 +0 224 ×2 448
000 +0 448 ×2 896
00 +0 896 ×2 1792
1
0 +0 1792 done.
1.3.4 Decimal to Binary

Example 1: (152.25)10
Operation Quotient Remainder
152/2 76 0 (LSB)
76/2 38 0
38/2 19 0
19/2 9 1
9/2 4 1
4/2 2 0
2/2 1 0
½0 1 (MSB)
Now, perform the multiplication of 0.27 and successive fraction withbase 2.
Operation Result Carry
0.25×2 0.50 0
0.50×2 0 1
1.3.5 Decimal to Octal Conversion

For converting decimal to octal, there are two steps required to perform,which are as
follows:
1. In the first step, we perform the division operation on the integer andthe successive
quotient with the base of octal(8).
2. Next, we perform the multiplication on the integer and the successivequotient with the
base of octal(8).
Example 1: (152.25)10
Step 1:
Divide the number 152 and its successive quotients with base 8.Operation
Quotient Remainder
152/8 19 0
19/8 2 3
1
2/8 0 2
(152)10=(230)8
Step 2:
Now perform the multiplication of 0.25 and successive fraction with base8.
Operation Result carry
0.25×8 0 2
(0.25)10 = (2)8
So, the octal number of the decimal number 152.25 is 230.2
1.3.6 Decimal to hexadecimal conversion
For converting decimal to hexadecimal, there are two steps required toperform, which are as
follows:
1. In the first step, we perform the division operation on the integer andthe successive
quotient with the base of hexadecimal (16).
2. Next, we perform the multiplication on the integer and the successivequotient with the
base of hexadecimal (16).
Example 1: (152.25)10
Step 1:
Divide the number 152 and its successive quotients with base 8.Operation
Quotient Remainder
152/16 9 8
9/16 0 9
(152)10=(98)16
Step 2:
Now perform the multiplication of 0.25 and successive fraction with base16.
Operation Result carry
0.25×16 0 4
(0.25)10=(4)16
So, the hexadecimal number of the decimal number 152.25 is 230.4.
1.3.7 Octal to Decimal Conversion
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The process of converting octal to decimal is the same as binary to decimal. The process
starts from multiplying the digits of octal numbers with its corresponding positional
weights. And lastly, we add all thoseproducts.
Let's take an example to understand how the conversion is done fromoctal to decimal.
Example 1: (152.25)8
Step 1:
We multiply each digit of 152.25 with its respective positional weight, andlast we add the
products of all the bits with its weight. (152.25)8=(1×82)+(5×81)+(2×80)+(2×8-

1)+(5×8-2) (152.25)8=64+40+2+(2×1⁄8)+(5×1⁄64)
(152.25)8=64+40+2+0.25+0.078125
(152.25)8=106.328125
So, the decimal number of the octal number 152.25 is 106.328125
1.3.8 Octal to Binary Conversion
The process of converting octal to binary is the reverse process of binaryto octal. We write
the three bits binary code of each octal number digit.
Example 1: (152.25)8
We write the three-bit binary digit for 1, 5, 2, and 5.
(152.25)8 =(001101010.010101)2
So, the binary number of the octal number 152.25 is (001101010.010101)2
1.3.9. Octal to hexadecimal conversion
For converting octal to hexadecimal, there are two steps required toperform, which are as
follows:
1. In the first step, we will find the binary equivalent of number 25.
2. Next, we have to make the pairs of four bits on both sides of the binarypoint. If there will
be one, two, or three bits left in a pair of four bits pair,
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we add the required number of zeros on extreme sides and write the hexadecimal digits
corresponding to each pair.
Example 1: (152.25)8
Step 1:
We write the three-bit binary digit for 1, 5, 2, and 5.
(152.25)8=(001101010.010101)2
So, the binary number of the octal number 152.25 is (001101010.010101)2Step 2:
1. Now, we make pairs of four bits on both sides of the binary point.
0 0110 1010.0101 01
On the left side of the binary point, the first pair has only one digit, and onthe right side, the
last pair has only two-digit. To make them completepairs of four bits, add zeros on extreme
sides.
0000 0110 1010.0101 0100
2. Now, we write the hexadecimal digits, which correspond to each pair.(0000 0110
1010.0101 0100)2=(6A.54)16
1.3.10. Hexa-decimal to Decimal Number System
The process of converting hexadecimal to decimal is the same as binaryto decimal. The
process starts from multiplying the digits of hexadecimal numbers with its corresponding
positional weights. And lastly, we add all those products.
Let's take an example to understand how the conversion is done fromhexadecimal to decimal.
Example 1: (152A.25)16
Step 1:
1
We multiply each digit of 152A.25 with its respective positional weight, andlast we add the
products of all the bits with its weight.
(152A.25)16=(1×163)+(5×162)+(2×161)+(A×160)+(2×16-1)+(5×16-2)
(152A.25)16=(1×4096)+(5×256)+(2×16)+(10×1)+(2×16-1)+(5×16-2)
(152A.25)16=4096+1280+32+10+(2×1⁄16)+(5×1⁄256)
(152A.25)16=5418+0.125+0.125
(152A.25)16=5418.14453125
So, the decimal number of the hexadecimal number 152A.25 is5418.14453125
1.3.11 Hexadecimal to Binary Conversion
The process of converting hexadecimal to binary is the reverse process of binary to

hexadecimal. We write the four bits binary code of each hexadecimal number digit.
Example 1: (152A.25)16
We write the four-bit binary digit for 1, 5, A, 2, and 5.
(152A.25)16=(0001 0101 0010 1010.0010 0101)2
So, the binary number of the hexadecimal number 152.25 is(1010100101010.00100101)2
1.3.12 Hexadecimal to Octal Conversion
For converting hexadecimal to octal, there are two steps required toperform, which are as
follows:
1. In the first step, we will find the binary equivalent of the hexadecimalnumber.
2. Next, we have to make the pairs of three bits on both sides of the binary point. If there
will be one or two bits left in a pair of three bits pair,we add the required number of zeros on
extreme sides and write the octal digits corresponding to each pair.
Example 1: (152A.25)16
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Step 1:
We write the four-bit binary digit for 1, 5, 2, A, and 5.
(152A.25)16=(0001 0101 0010 1010.0010 0101)2
So, the binary number of hexadecimal number 152A.25 is(0011010101010.010101)2
Step 2:
3. Then, we make pairs of three bits on both sides of the binary point.001 010
100 101 010.001 001 010
4. Then, we write the octal digit, which corresponds to each pair.
(001010100101010.001001010)2=(12452.112)8
So, the octal number of the hexadecimal number 152A.25 is 12452.112
1.4 Signed Numbers
Fig 1.1 Classification of Binary Number Representation
The signed numbers have a sign bit so that it can differentiate positive and negative integer
numbers. The signed binary number technique has both the signbit and the magnitude of the number.
For representing the negative decimal number, the corresponding symbol in front of the binary
number will be added.
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The signed numbers are represented in three ways. The signed bit makes two possible
representations of zero (positive (0) and negative (1)), which is an ambiguous representation.
The third representation is 2's complement representation in which no double representation of zero
is possible, which makesit unambiguous representation. There are the following types of representation
ofsigned binary numbers:
1. Sign-Magnitude form
In this form, a binary number has a bit for a sign symbol. If this bit is set to 1, the number will be
negative else the number will be positive if it is set to 0. Apart fromthis sign-bit, the n-1 bits represent the
magnitude of the number.
2. 1's Complement
By inverting each bit of a number, we can obtain the 1's complement of a number. The negative
numbers can be represented in the form of 1's complement. In this form, the binary number also
has an extra bit for sign representation as a sign-magnitude form.
3. 2's Complement
By inverting each bit of a number and adding plus 1 to its least significant bit, wecan obtain the 2's
complement of a number. The negative numbers can also be represented in the form of 2's
complement. In this form, the binary number also has an extra bit for sign representation as a sign-
magnitude form.
Positive Signed Binary Numbers
Negative Signed Binary Numbers
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1’s Complementation in Signed Binary number Representation:
1’s complement binary numbers are very useful in Signed number representation.Positive numbers are
simply represented as Binary number number. There isnothing to do for positive binary number.
But in case of negative binary numberrepresentation, we represent in 1’s complement. If the number is
negative then it is represented using 1’s complement. First represent the number with positive signand
then take 1’s complement of that number.
Example: Let we are using 5 bits register. The representation of -5 and +5 will beas follows:
+5 is represented as it is represented in sign magnitude method. -5 is representedusing the following

steps:
(i) +5 = 0 0101
(ii) Take 1’s complement of 0 0101 and that is 1 1010. MSB is 1 which indicates thatnumber is negative.
MSB is always 1 in case of negative numbers.
Range of Numbers: For k bits register, positive largest number that can be stored is ( 2 (k-1) -1) and
negative lowest number that can be stored is -( 2 (k-1) -1).
Note that drawback of this system is that 0 has two different representation oneis -0 (e.g., 1 1111 in
five bit register) and second is +0 (e.g., 0 0000 in five bitregister).
Lets see arithmetic operations: Subtractions and Additions in 1’s complementbinary numbers.
1.4.1 Addition and Subtraction using 1's complement
Consider the two signed binary numbers A & B, which are represented in 2’scomplement form.
We can perform the addition of these two numbers, which is similar to the addition of two
unsigned binary numbers. But, if the resultant sum contains carry out from sign bit, then discard
ignore it in order
to get the correct value.
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If resultant sum is positive, you can find the magnitude of it directly. But, if the resultant sum is
negative, then take 2’s complement of it in order to get themagnitude.
Example 1
Let us perform the addition of two decimal numbers +7 and +4 using 2’scomplement method.
The 2’s complement representations of +7 and +4 with 5 bits each are shownbelow.
+710 = 001112
+410 = 001002
The addition of these two numbers is
+710 ++410 = 001112+001002
⇒ +710 ++410 = 010112.
The resultant sum contains 5 bits. So, there is no carry out from sign bit. Thesign bit ‘0’ indicates
that the resultant sum is positive. So, the magnitude ofsum is 11 in decimal number system.
Therefore, addition of two positivenumbers will give another positive number.
Example 2
Let us perform the addition of two decimal numbers -7 and -4 using 2’scomplement method.
The 2’s complement representation of -7 and -4 with 5 bits each are shownbelow.
−710 = 110012
−410 = 111002
The addition of these two numbers is
−710 + −410 = 110012 + 111002
1
⇒ −710 + −410 =
1101012.
The resultant sum contains 6 bits. In this case, carry is obtained from sign bit. So, we can remove it
Resultant sum after removing carry is −710 + −410 = 101012.
The sign bit ‘1’ indicates that the resultant sum is negative. So, by taking 2’scomplement of it we
will get the magnitude of resultant sum as 11 in decimalnumber system. Therefore, addition of
two negative numbers will give another negative number.
Subtraction of two Signed Binary Numbers
Consider the two signed binary numbers A & B, which are represented in 2’scomplement form.
We know that 2’s complement of positive number givesa negative number. So, whenever
we have to subtract a number B fromnumber A, then take 2’s complement of B and add it
to A. So, mathematically we can write it as
A - B = A + 2′scomplement of B
Similarly, if we have to subtract the number A from number B, then take 2’scomplement of A
and add it to B. So, mathematically we can write it as
B - A = B + 2′scomplementofA
So, the subtraction of two signed binary numbers is similar to the addition oftwo signed binary
numbers. But, we have to take 2’s complement of the number, which is supposed to be
subtracted. This is the advantage of 2’scomplement technique. Follow, the same rules of
addition of two signedbinary numbers.
Example 3
Let us perform the subtraction of two decimal numbers +7 and +4 using 2’s complement
method.
The subtraction of these two numbers is
2
+710 − +410 = +710 + −410.
The 2’s complement representation of +7 and -4 with 5 bits each are shownbelow.
+710 = 001112
+410 = 111002
⇒ +710 + +410 = 001112 + 111002
Here, the carry obtained from sign bit. So, we can remove it. The resultant sum after removing
carry is
+710 + +410 = 000112
The sign bit ‘0’ indicates that the resultant sum is positive. So, the magnitudeof it is 3 in decimal
number system. Therefore, subtraction of two decimalnumbers +7 and +4 is +3.
Example 4
Let us perform the subtraction of two decimal numbers +4 and +7 using 2’s complement
method.
The subtraction of these two numbers is
+410 − +710 = +410 + −7
The 2’s complement representation of +4 and -7 with 5 bits each are shownbelow.
+410 = 001002
−710 = 110012
⇒ +410 + −710 = 001002 + 110012 = 111012
Here, carry is not obtained from sign bit. The sign bit ‘1’ indicates that theresultant sum is
negative. So, by taking 2’s complement of it we will get themagnitude of resultant sum as 3 in
decimal number system. Therefore,
subtraction of two decimal numbers +4 and +7 is -3.
2
1.5. Binary Arithmetic
1.5.1 Binary Addition
The table of adding two binary numbers 0 and 1 is given below:
x Y x+y
0 0 0
0 1 1
1 0 1
1 1 0 (where 1 is carried over)
Example 1: 10001 + 11101
Solution:
10001
(+) 1 1 1 0 1
———————–
101110
1.5.2 Binary Subtraction
Binary subtraction is also similar to that of decimal subtraction with the difference that
when 1 is subtracted from 0, it is necessary to borrow 1 fromthe next higher order bit and that
bit is reduced by 1 (or 1 is added to the next bit of subtrahend) and the remainder is 1.
Thus the rules of binary subtraction are as follows:
0-0=0
1-0=1
2
1-1=0
0 - 1 = 1 with a borrow of 1
Example 1: 0011010 – 001100
Solution:
1 1 Borrow
0011010
(-) 0 0 1 1 0 0
——————
0001110
Subtraction by 1’s Complement
The steps to be followed in subtraction by 1’s complement are:

i) To write down 1’s complement of the subtrahend.
ii) To add this with the minuend.
iii) If the result of addition has a carry over then it is dropped andan 1 is added in
the last bit.
iv) If there is no carry over, then 1’s complement of the result ofaddition is
obtained to get the final result and it is negative. Evaluate:
(i) 110101 – 100101
Solution:
1’s complement of 10011 is 011010. Hence
Minued - 110101
1’s complement of subtrahend - 011010
Carry over - 1 001111
2
010000
The required difference is 10000
(ii) 101011 – 111001

Solution:
1’s complement of 111001 is 000110. Hence
Minued - 101011
1’s complement - 000110
110001
Hence the difference is – 1 1 1 0
Subtraction by 2’s Complement
With the help of subtraction by 2’s complement method we caneasily subtract two
binary numbers.
The operation is carried out by means of the following steps:
(i) At first, 2’s complement of the subtrahend is found.
(ii) Then it is added to the minuend.
(iii) If the final carry over of the sum is 1, it is dropped and the resultis positive.
(iv) If there is no carry over, the two’s complement of the sum willbe the result and
it is negative.
The following examples on subtraction by 2’s complement willmake the
procedure clear:
Evaluate:
(i) 110110 - 10110
Solution:
2
The numbers of bits in the subtrahend is 5 while that of minuend is
6. We make the number of bits in the subtrahend equal to that ofminuend by taking
a `0’ in the sixth place of the subtrahend. Now, 2’s complement of 010110 is (101101
+ 1) i.e.101010. Addingthis with the minuend.
1 10110 Minuend
1 01010 2’s complement of subtrahend
Carry over 1 1 00000 Result of addition
After dropping the carry over we get the result of subtraction tobe 100000.
(ii) 10110 – 11010
Solution:
2’s complement of 11010 is (00101 + 1) i.e. 00110. Hence
Minued - 10110
2’s complement of subtrahend - 00110
Result of addition - 11100
As there is no carry over, the result of subtraction is negative and is obtained by

writing the 2’s complement of 11100 i.e.(00011 + 1)or 00100.
Hence the difference is – 100.
1.5.3 Binary Multiplication

Binary multiplication is one of the four binary arithmetic. The other three fundamental
operations are addition, subtraction and division. In the case of a binary operation, we
deal with only two digits, i.e. 0 and 1. Theoperation performed while finding the binary
product is similar to the
2
conventional multiplication method. The four major steps in binary digitmultiplication are:
• 0×0=0
• 0×1=0
• 1×0=0
• 1×1=1
Example 1: Solve 1010 × 101
Solution:
1010 × 101
1010
(×) 101
—————–1010
0000
——————
01010 ……. First Intermediate Sum 1010
——————–
110010
1.5.4 Binary Division

The binary division is much easier than the decimal division when you remember the following
division rules. The main rules of the binary divisioninclude:
• 1÷1 = 1
• 1÷0 = Meaningless
• 0÷1 = 0
• 0÷0 = Meaningless
2
1.6 Binary Codes
In the coding, when numbers or letters are represented by a specific group ofsymbols, it is said to
be that number or letter is being encoded. The group ofsymbols is called as code. The digital data is
represented, stored and transmittedas group of bits. This group of bits is also called as binary code.
Binary codes can be classified into two types.
(i) Weighted codes
(ii) Unweighted codes
If the code has positional weights, then it is said to be weighted code. Otherwise,it is an un-weighted
code. Weighted codes can be further classified as positively weighted codes and negatively
weighted codes.
Binary Codes for Decimal digits
The following table shows the various binary codes for decimal digits 0 to 9.
D.No 8421 Code 2421 Code 84-2-1 Code Excess3 Code
0 0000 0000 0000 0011
1 0001 0001 0111 0100
2 0010 0010 0110 0101
3 0011 0011 0101 0110
4 0100 0100 0100 0111
5 0101 1011 1011 1000
6 0110 1100 1010 1001
7 0111 1101 1001 1010
8 1000 1110 1000 1011

2
9 1001 1111 1111 1100
1.6.1 BCD Addition method

1. For 984 and 599, Find BCD Addition methodSolution:
984+599 BCD addition Steps
for BCD additionFor A+B
1. Add each digit of A and B using binary addition
2. If sum of two digits is more than 9 then result is Invalid BCD and add 6 to the result, Otherwise
result is valid BCD.
3. If carry then add it to the next bits Add 984
and 599 using BCD addition
BCD code for 984 : 1001 1000 0100
BCD code for 599 : 0101 1001 1001
Addition : 1110 10001 1101
If Invalid BCD then add 6 : 0110 0110 0110
Addition : 10100 10111 10011
Remaining bits except carry : 10100 0111 0011
Carry : 1 1
Addition : 10101 1000 0011
BCD value : 15 8 3
So final answer of BCD addition is 1583
2
1.6.2 BCD Subtraction
Steps for BCD subtraction using 9′s complementFor A-B
1. Take 9′s complement for B
2. Add it to A using BCD addition
3. If addition is invalid BCD then add 6
4. If carry then add it to the next bits
5. In final result, if carry is occurred then add it the remaining result and if there is no any carry
over, then take 9′s complement of the result and it isnegative.
1. Take 9′s complement for 599
Note : 9's complement of a number is obtained by subtracting all bits from999.
9's complement of 599 is
9 9 9
-5 9 9
4 0 0
2. Add 984 and 400 using BCD addition
BCD code for 984 : 1001 1000 0100
BCD code for 400 : 0100 0000 0000
Addition : 1101 1000 0100

If Invalid BCD then add 6 : 0110
Addition : 1 0011 1000 0100

BCD value : 138 4
The left most bit of the result is 1, called carry and This will be added to 384.384+1=385
So final answer of BCD Subtraction is 385
2. For 983 and 187, Find BCD Subtraction using 9's complement method
2
Solution:
983-187 BCD subtraction using 9′s complement Steps for BCD
subtraction using 9′s complement
Note : 9's complement of a number is obtained by subtracting all bits from999.
9 9 9
-1 8 7
8 1 2
BCD code for 983 : 1001 1000 0011

BCD code for 812 : 1000 0001 0010
Addition : 10001 1001 0101If

Invalid BCD then add 6 : 0110
Addition : 10111 1001 0101

BCD value : 179 5
The left most bit of the result is 1, called carry and This will be added to 795.795+1=796
so final answer of BCD Subtraction is 796
BCD Subtraction using 10's complement method example
1. Example-1
1. For 984 and 599, Find BCD Subtraction using 10's complement methodSolution:
984-599 BCD subtraction using 10′s complement
3
Steps for BCD subtraction using 10′s complementFor A-B
1. Take 10′s complement for B
2. Add it to A using BCD addition
3. If addition is invalid BCD then add 6
4. If carry then add it to the next bits
5. In final result, if carry is occured then it is ignored and if
there is no any carry over, then take 10′s complement of the result and it isnegative.
Note : 10's complement of a number is 1 added to it's 9's complementnumber.
9 9 9
-5 9 9
4 0 0
Now add 1 : 400 + 1 = 401

BCD code for 984 : 1001 1000 0100

BCD code for 401 : 0100 0000 0001
Addition : 1101 1000 0101

Addition : 10011 1000 0101

BCD value : 138 5
The left most bit of the result is 1, called carry and it is ignored.So final answer
of BCD Subtraction is 385
2. Example-2
3
2. For 983 and 187, Find BCD Subtraction using 10's complement methodSolution:
983-187 BCD subtraction using 10′s complement Steps for BCD
subtraction using 10′s complement
Note : 10's complement of a number is 1 added to it's 9's complementnumber.
9 9 9
-1 8 7
8 1 2
Now add 1 : 812 + 1 = 813

2. Add 983 and 813 using BCD additionBCD
code for 983 : 1001 1000 0011 BCD code for 813 :
1000 0001 0011
Addition : 10001 1001 0110

Addition : 10111 1001 0110

BCD value : 179 6
The left most bit of the result is 1, called carry and it is ignored.So final answer
of BCD Subtraction is 796
1.6.3 Gray code
The Gray Code is a sequence of binary number systems, which is also knownas reflected binary
code. The reason for calling this code as reflected binarycode is the first N/2 values compared
with those of the last N/2 values in
3
reverse order. In this code, two consecutive values are differed by one bit of binary digits. Gray
codes are used in the general sequence of hardware- generated binary numbers. These
numbers cause ambiguities or errors when the transition from one number to its successive
is done. This codesimply solves this problem by changing only one bit when the transition is
between numbers is done.
Binary To Gray Code
1. The Most Significant Bit (MSB) of the gray code is always equal to the MSBof the given
binary code.
2. Other bits of the output gray code can be obtained by XORing binarycode bit at that
index and previous index.
1. (10011)2 = ( ? )Gray Code
Solution:
Binary code : 10011
Method-1: (Binary to Gray code)
g4=b4=1
g3=b4⊕ b3=1⊕ 0=1
g2=b3⊕ b2=0⊕ 0=0
g1=b2⊕ b1=0⊕ 1=1
g0=b1⊕ b0=1⊕ 1=0
∴ Gray code : 11010
Gray to Binary
3
1. The Most Significant Bit (MSB) of the binary code is always equal to the MSB of the given
binary number.
2. Other bits of the output binary code can be obtained by checking graycode bit at that
index. If current gray code bit is 0, then copy previous binarycode bit, else copy invert of previous
binary code bit.
Example: (11100)Gray Code = ( ? )2
Solution:
Gray code : 11100
Method-1: (Gray code to Binary)b4=g4=1
b3=b4⊕g3=1⊕1=0
b2=b3⊕g2=0⊕1=1
b1=b2⊕g1=1⊕0=1
b0=b1⊕g0=1⊕0=1
∴ Binary : 10111
1.6.4 Error Detection codes : Parity bit positionError
Detection Codes :
The binary information is transferred from one location to another location through some
communication medium. The external noise can change bits from 1 to 0 or 0 to 1.This changes
in values are called errors. For efficientdata transfer, there should be an error detection and
correction codes. An error detection code is a binary code that detects digital errors during
transmission. A famous error detection code is a Parity Bit method.
3
SVEC TIRUPATI
Parity Bit Method :

A parity bit is an extra bit included in binary message to make total numberof 1’s either odd or
even. Parity word denotes number of 1’s in a binarystring. There are two parity system-even
and odd. In even parity system 1 is appended to binary string it there is an odd number of 1’s in
string otherwise0 is appended to make total even number of 1’s.
Fig 1.2 Even Parity Generator

In odd parity system, 1 is appended to binary string if there is even a numberof 1’s to make an
odd number of 1’s. The receiver knows that whether sender is an odd parity generator or
even parity generator. Suppose if sender is an odd parity generator then there must be an odd
number of 1’s in received binary string. If an error occurs to a single bit that is either bit is
changed to 1 to 0 or O to 1, received binary bit will have an even numberof 1’s which will
indicate an error.
Fig 1.3 ODD Parity Generator
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The limitation of this method is that only error in a single bit would beidentified.
MESSAGE(XYZ)
P(ODD) P(EVEN)
000 1 0
001 0 1
010 0 1
011 1 0
100 0 1
101 1 0
110 1 0
111 0 1
Fig 1.4 – Error Detection with Odd Parity Bit
Hamming Code
Hamming code is a block code that is capable of detecting up to twosimultaneous bit errors
and correcting single-bit errors. It was developed by
R.W. Hamming for error correction.
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In this coding method, the source encodes the message by inserting redundant bits within the
message. These redundant bits are extra bits that aregenerated and inserted at specific positions in
the message itself to enable error detection and correction. When the destination receives this
message, itperforms recalculations to detect errors and find the bit position that has error.Encoding
a message by Hamming Code
The procedure used by the sender to encode the message encompasses thefollowing steps −
• Step 1 − Calculation of the number of redundant bits.
• Step 2 − Positioning the redundant bits.
• Step 3 − Calculating the values of each redundant bit.
Once the redundant bits are embedded within the message, this is sent to theuser.
Step 1 − Calculation of the number of redundant bits.
If the message contains m𝑚number of data bits, r𝑚number of redundant bits are added to it so
that m𝑚 is able to indicate at least (m + r+ 1) different states.Here, (m + r) indicates location of an
error in each of (𝑚 + 𝑚) bit positions andone additional state indicates no error. Since, r𝑚 bits
can indicate 2r𝑚 states, 2r𝑚 must be at least equal to (m + r + 1). Thus the following equation
should hold2r ≥ m+r+1

Step 2 − Positioning the redundant bits.
The r redundant bits placed at bit positions of powers of 2, i.e. 1, 2, 4, 8, 16 etc.They are referred in the
rest of this text as r1 (at position 1), r2 (at position 2), r3(at position 4), r4 (at position 8) and so on.
Step 3 − Calculating the values of each redundant bit.
The redundant bits are parity bits. A parity bit is an extra bit that makes thenumber of 1s either
even or odd. The two types of parity are −
• Even Parity − Here the total number of bits in the message is made even.
• Odd Parity − Here the total number of bits in the message is made odd. Each redundant bit, ri,
is calculated as the parity, generally even parity, basedupon its bit position. It covers all bit
positions whose binary representationincludes a 1 in the ith position except the position of ri. Thus −
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• r1 is the parity bit for all data bits in positions whose binary representationincludes a 1 in the
least significant position excluding 1 (3, 5, 7, 9, 11 and so on)
position 2 from right except 2 (3, 6, 7, 10, 11 and so on)
position 3 from right except 4 (5-7, 12-15, 20-23 and so on) Decoding a message in Hamming Code
Once the receiver gets an incoming message, it performs recalculations todetect errors and
correct them. The steps for recalculation are −
• Step 1 − Calculation of the number of redundant bits.
• Step 2 − Positioning the redundant bits.
• Step 3 − Parity checking.
• Step 4 − Error detection and correction
Step 1 − Calculation of the number of redundant bits
Using the same formula as in encoding, the number of redundant bits areascertained.
2r ≥ m + r + 1 where m is the number of data bits and r is the number ofredundant bits.
Step 2 − Positioning the redundant bits
The r redundant bits placed at bit positions of powers of 2, i.e. 1, 2, 4, 8, 16 etc.Step 3 − Parity
checking
Parity bits are calculated based upon the data bits and the redundant bitsusing the same rule as
during generation of c1,c2 ,c3 ,c4 etc. Thus
c1 = parity(1, 3, 5, 7, 9, 11 and so on)
c2 = parity(2, 3, 6, 7, 10, 11 and so on) c3 =
parity(4-7, 12-15, 20-23 and so on)Step 4 − Error
detection and correction
The decimal equivalent of the parity bits binary values is calculated. If it is 0, there is no error.
Otherwise, the decimal value gives the bit position which haserror. For example, if c1c2c3c4 = 1001,
it implies that the data bit at position 9, decimal equivalent of 1001, has error. The bit is flipped to
get the correct message.
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1.6.5 ASCII Codes

The ASCII stands for American Standard Code for Information Interchange. The ASCII code is an
alphanumeric code used for data communication in digitalcomputers. The ASCII is a 7-bit code
capable of representing 27 or 128 numberof different characters. The ASCII code is made up of a
three-bit group, whichis followed by a four-bit code.
The ASCII Code is a 7 or 8-bit alphanumeric code. This code
can represent 127 unique characters.
The ASCII code starts from 00h to 7Fh. In this, the code from 00h to 1Fh is used for control
characters, and the code from 20h to 7Fh is used for graphic symbols.
Binary Hexadecimal Decim ASCII Description Group
al Symb
ol
000000 0 0 NUL The null character Control

0 encourage the device Character
to do nothing
000000 1 1 SOH The symbol Control

1 SOH(Starts of Character
heading) Initiates the
header.
000001 2 2 STX The symbol Control

0 STX(Start of Text) Character
ends the header
and marks the
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beginning of a
message.
000001 3 3 ETX The symbol Control

1 ETX(End of Text) Character
indicates the end of
the message.
000010 4 4 EOT The EOT(end oftext) Control

0 symbolmarks the end Character
of a completes
transmission
000010 5 5 ENQ The ENQ(Enquiry) Control

1 symbol is a Character
request that
requires a
response
000011 6 6 ACK The Control

0 ACK(Acknowled ge) Character
symbol is apositive
answer tothe request.
000011 7 7 BEL The BEL(Bell) Control

1 symbol triggers a Character
beep.
000100 8 8 BS Lets the cursor move Control

0 back one step Character
(Backspace)
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000100 9 9 TAB A horizontal tabthat Control
1 (HT) moves the Character
cursor within a
row to the next
predefined position
(Horizontal Tab)
000101 A 10 LF Causes the cursor to Control

0 jump to the next line Character
(Line Feed)
000101 B 11 VT The vertical tab lets Control

1 the cursor jump to a Character
predefined line
(Vertical Tab)
000110 C 12 FF Requests a page break Control

0 (Form Feed) Characte
r
…………………………………………etc
1.7 Boolean Algebra

As well as the logic symbols “0” and “1” being used to represent a digital input oroutput, we can also
use them as constants for a permanently “Open” or “Closed”circuit or contact respectively.
A set of rules or Laws of Boolean Algebra expressions have been invented to helpreduce the number
of logic gates needed to perform a particular logic operationresulting in a list of functions or theorems
known commonly as the Laws of BooleanAlgebra.
Boolean Algebra is the mathematics we use to analyse digital gates and circuits. We can use these
“Laws of Boolean” to both reduce and simplify a complex
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Boolean expression in an attempt to reduce the number of logic gates required. Boolean Algebra
is therefore a system of mathematics based on logic that has its own set of rules or laws which are
used to define and reduce Booleanexpressions.
The variables used in Boolean Algebra only have one of two possible values, alogic “0” and a
logic “1” but an expression can have an infinite number of variables all labelled individually to
represent inputs to the expression, For example, variables A, B, C etc, giving us a logical
expression of A + B = C, buteach variable can ONLY be a 0 or a 1.
Examples of these individual laws of Boolean, rules and theorems for BooleanAlgebra are given
in the following table.
Equivalent Boolean
Boolean Description
Switching Algebra Law
Expression
Circuit or Rule
A in parallel with
A+1=1 Annulment
closed = “CLOSED”
A in parallel with
A+0=A Identity
open = “A”
A in series with
A.1=A Identity
closed = “A”
A in series withopen =
A.0=0 Annulment
“OPEN”
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A in parallel with
A+1=1 Annulment
A in parallel with
A+0=A Identity
open = “A”
A in series with
A.1=A Identity
closed = “A”
A.0=0 Annulment
“OPEN”
A in parallel with
A+1=1 Annulment
A in parallel with
A+0=A Identity
open = “A”
A in series with
A.1=A Identity
closed = “A”
A.0=0 Annulment
“OPEN”
A in parallel with
A+1=1 Annulment
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Other algebraic Laws of Boolean not detailed above include:
Boolean Postulates – While not Boolean Laws in their own right, these are a set ofMathematical Laws
which can be used in the simplification of BooleanExpressions.
0.0=0 A 0 AND’ed with itself is always equal to 0
1.1=1 A 1 AND’ed with itself is always equal to 1
1.0=0 A 1 AND’ed with a 0 is equal to 0
0+0=0 A 0 OR’ed with itself is always equal to 0
1+1=1 A 1 OR’ed with itself is always equal to 1
1+0=1 A 1 OR’ed with a 0 is equal to 1
1=0 The Inverse (Complement) of a 1 is always equal

to 00 = 1 The Inverse (Complement) of a 0 is always equal to 1
Distributive Law – This law permits the multiplying or factoring out of an expression.
A(B + C) = A.B + A.C (OR Distributive Law)

A + (B.C) = (A + B).(A + C) (AND Distributive Law)
Absorptive Law – This law enables a reduction in a complicated expression to asimpler one by absorbing like
terms.
A + (A.B) = (A.1) + (A.B) = A(1 + B) = A (OR Absorption Law)

A(A + B) = (A + 0).(A + B) = A + (0.B) = A (AND Absorption Law)
Associative Law – This law allows the removal of brackets from an expression andregrouping of the variables.
A + (B + C) = (A + B) + C = A + B + C (OR Associate Law)

A(B.C) = (A.B)C = A . B . C (AND As sociate Law)
Absorption Law Proof
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SVEC TIRUPATI
A B AB A+A.B
0 0 0 0
0 1 0 0
1 0 0 1
1 1 1 1
Examples on Simplifying Boolean expression
1. Simplify: AB(A + B)(B + B)
Expression Rule(s) Used
AB(A + B)(B + B) Original Expression
AB(A + B) Complement law, Identity law.
(A + B)(A + B) DeMorgan's Law
Distributive law. This step uses the fact that or distributes overand. It can look a
bit strange since addition does not
A + BB distribute over multiplication.
Complement, Identity.
A
2. Simplify: (A + C)(AD + AD) + AC + C:
(A + C)(AD + AD) + AC + C Original Expression
(A + C)A(D + D) + AC + C Distributive.
(A + C)A + AC + C Complement, Identity.
A((A + C) + C) + C Commutative, Distributive.
A(A + C) + C Associative, Idempotent.
AA + AC + C Distributive.
A + (A + T)C Idempotent, Identity, Distributive.
Identity, twice.
A+C
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3. Simplify: A(A + B) + (B + AA)(A + B):
A(A + B) + (B + AA)(A + B) Original Expression
Idempotent (AA to A), then Distributive, used

AA + AB + (B + A)A + (B + A)B
twice.
Complement, then Identity. (Strictly speaking, we also

used the Commutative
AB + (B + A)A + (B + A)B Law for each of these applications.)
AB + BA + AA + BB + AB Distributive, two places.
Idempotent (for the A's), then

AB + BA + A + AB Complement and Identity to remove BB.
Commutative, Identity; setting up for the

AB + AB + AT + AB next step.
AB + A(B + T + B) Distributive.
Identity, twice (depending how you count

AB + A it).
A + AB Commutative.
(A + A)(A + B) Distributive.
A+B Complement, Identity.
1.7.1 Logic Gates
Device implementing a Boolean function, a logical operation performed onone or more binary
inputs that produces a single binary output.
Logic gates are the basic building blocks of any digital system. It is an electronic circuit
having one or more than one input and only one output. The relationship between the input and
the output is based on a certain logic. Based on this, logic gates are named as AND gate, OR
gate, NOT gate etc.
AND gate
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OR gate
NOT gate
NAND gate
NOR gate
EXOR gate
EXNOR gate
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Logic gate symbols
Fig 1.5 Logic Symbols

Here are some logic gate circuit problems:
 Draw a logic circuit for (A + B)C.
 Draw a logic circuit for A + BC + D.
 Draw a logic circuit for AB + AC.
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 Draw a logic circuit for (A + B)(C + D)C.
Logic Gates using only

NAND
Logic Gates using only

NOR Gates
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1.7.2 Sum of Products and Product of Sums
What is a Sum of Product (SOP)?
The short form of the sum of the product is SOP, and it is one kind of Boolean
algebra expression. In this, the different product inputs are beingadded together. The product of
inputs is Boolean logical AND whereas the sum or addition is Boolean logical OR. Before going
to understand the concept ofthe sum of products, we have to know the concept of minterm.
The min term can be defined as, when the minimum combinations of inputs arehigh then the output
will be high. The best example of this is AND gate, so we can say that min terms are combinations
of AND gate inputs. The truth table ofthe min term is shown below.
X Y Z Min Term (m)
0 0 0 X’Y’Z’ = m0
0 0 1 X’Y’Z = m1
0 1 0 X’Y Z’ = m2
X’YZ = m3
0 1 1
XY’Z’= m4
1 0 0
1
0 1 XY’Z = m5
XYZ’ = m6
1 1 0
XYZ = m7
p1 1 1
In the above table, there are three inputs namely X, Y, Z and the combinationsof these inputs are 8.
Every combination has a minterm that is specified with m.
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Canonical SOP form
Conversion of SOP form to standard SOP form or Canonical SOP form
We can include all the variables in each product term of the SOP form equation,which doesn’t have
all the variables by converting into standard SOP form. The normal SOP form function can be
converted to standard SOP form by using theBoolean algebraic law, (A + A’ = 1) and by following
the below steps.
Step 1:
By multiplying each non-standard product term with the sum of its missing variable and its
complement, which results in 2 product terms
Step 2:
By repeating the step 1, until all resulting product terms contain all variables
By these two steps we can convert the SOP function into standard SOP function.In this process, for
each missing variable in the function, the number of productterms will double.
Convert the non standard SOP function F = x y + x z + y z Sol:
F=xy+xz+yz
= x y (z + z’) + x (y + y’) z + (x + x’) y z
= x y z + x y z’ + x y z + x y’ z + x y z + x’ y z
= x y z + x y z’ + x y’ z + x’ y z
The standard SOP form is F = x y z + x y z’ + x y’ z + x’ y z
What is a Product of Sum (POS)?
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The short form of the product of the sum is POS, and it is one kind of Booleanalgebra expression.
In this, it is a form in which products of the dissimilar sum ofinputs are taken, which are not arithmetic
result & sum although they are logical Boolean AND & OR correspondingly. Before going to
understand the conceptof the product of the sum, we have to know the concept of the max term.
The maxterm can be defined as a term that is true for the highest number ofinput combinations
otherwise that is false for single input combinations. BecauseOR gate also provides false for just one
input combination. Thus Max term is ORof any complemented otherwise non-complemented inputs.
X Y Z Max Term (M)

0 X+Y+Z = M0
0 0
X+Y+Z’ = M1
0 0 1
0
1 0 X+Y’+ Z = M2
X+Y’+Z’ = M3
0 1 1
1
0 0 X’+Y+Z= M4
X’+Y+Z’ = M5
1 0 1
1
1 0 X’+Y’+Z = M6
In the above table, there are three inputs namely X, Y, Z and the combinationsof these inputs are 8.
Every combination has a max term that is specified with M.
Conversion of POS form to standard POS form or Canonical POS form
We can include all the variables in each product term of the POS form equation,which doesn’t have
all the variables by converting into standard POS form. The
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normal POS form function can be converted to standard POS form by using theBoolean algebraic law, (A *
A’ = 0) and by following the below steps.
Step 1:
By adding each non-standard sum term to the product of its missing variableand its complement,
which results in 2 sum terms
Step 2:
Applying Boolean algebraic law, A + BC = (A + B) * (A + C)Step 3:
By repeating the step 1, until all resulting sum terms contain all variables
By these three steps we can convert the POS function into standard POSfunction.
Example:
F = (A’ + B + C) * (B’ + C + D’) * (A + B’ + C’ + D)
In the first term, the variable D or D’ is missing, so we add D*D’ = 1 to it. Then(A’ + B + C + D*D’) =
(A’ + B + C + D) * (A’ + B + C + D’)
Similarly, in the second term, the variable A or A’ is missing, so we add A*A’ = 1to it. Then
(B’ + C + D’ + A*A’) = (A + B’ + C + D’) * (A’ + B’ + C + D’)
The third term is already in the standard form, as it has all the variables. Now thestandard POS form equation
of the function is
F = (A’ + B + C + D) * (A’ + B + C + D’) * (A + B’ + C + D’) * (A’ + B’ + C + D’) * (A

+ B’ + C’ + D)
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1.7.3 NAND and NOR implementation
Consider the following SOP expressionF =
W.X.Y + X.Y.Z + Y.Z.W
The above expression can be implemented with three AND gates in first stageand one OR gate in
second stage as shown in figure.
If bubbles are introduced at AND gates output and OR gates inputs (the samefor NOR gates), the
above circuit becomes as shown in figure.
Now replace OR gate with input bubble with the NAND gate. Now we havecircuit which is
fully implemented with just NAND gates.
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NOR implementation
Consider the following POS expressionF = (X+Y)
. (Y+Z)
The above expression can be implemented with three OR gates in first stageand one AND gate
in second stage as shown in figure.
If bubble are introduced at the output of the OR gates and the inputs of ANDgate, the above
circuit becomes as shown in figure.
Now replace AND gate with input bubble with the NOR gate. Now we havecircuit which is
fully implemented with just NOR gates.
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1.8. K-MAP
The K-map is a systematic way of simplifying Boolean expressions. With the help of theK-map method, we
can find the simplest POS and SOP expression, which is known as the minimum expression. The K-map
provides a cookbook for simplification.
Just like the truth table, a K-map contains all the possible values of input variables and their
corresponding output values. However, in K-map, the values are stored incells of the array. In each cell, a
binary value of each input variable is stored.
The K-map method is used for expressions containing 2, 3, 4, and 5 variables. For ahigher number of
variables, there is another method used for simplification called the Quine-McClusky method. In K-
map, the number of cells is similar to the totalnumber of variable input combinations. For example, if
the number of variables is three, the number of cells is 23=8, and if the number of variables is four, the
numberof cells is 24. The K-map takes the SOP and POS forms. The K-map grid is filled using0's and 1's.
The K-map is solved by making groups. There are the following steps usedto solve the expressions using K-
map:
First, we find the K-map as per the number of variables.Find the maxterm
and minterm in the given expression.
Fill cells of K-map for SOP with 1 respective to the minterms. Fill cells of the
block for POS with 0 respective to the maxterm.
Next, we create rectangular groups that contain total terms in the power oftwo like 2, 4, 8, …
and try to cover as many elements as we can in one group.
With the help of these groups, we find the product terms and sum them up forthe SOP form.
2 Variable K-map There is a total of 4 variables in a 2-variable K-map. There aretwo variables in the
2-variable K-map.
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In the above figure, there is only one possibility of grouping four adjacent minterms.
The possible combinations of grouping 2 adjacent minterms are {(m0, m1), (m2,m3), (m0, m2) and (m1,
m3)}.
3-variable K-map
The 3-variable K-map is represented as an array of eight cells. In this case, weused A, B, and C for
the variable. We can use any letter for the names of thevariables. The binary values of variables A
and B are along the left side, and thevalues of C are across the top. The value of the given cell is the
binary values ofA and B at left side in the same row combined with the value of C at the top in the
same column. For example, the cell in the upper left corner has a binaryvalue of 000, and the cell
in the lower right corner has a binary value of 101.
The 4-Variable Karnaugh Map
The 4-variable K-map is represented as an array of 16 cells. Binary values of A and B are along the
left side, and the values of C and D are across the top. Thevalue of the given cell is the binary values
of A and B at left side in the same rowcombined with the binary values of C and D at the top in the
same column. For
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example, the cell in the upper right corner has a binary value of 0010, and the cell in the lower right
corner has a binary value of 1010
5-variable K-map
With the help of the 32- cell K-map, the boolean expression with 5 variables canbe simplified. For
constructing a 5-variable K-map, we use two 4-variable K- maps. The cell adjacencies within
each of the 4- variable maps for the 5- variable map are similar to the 4- variable map.
Karnaugh Map Simplification Rules-
To minimize the given boolean function,
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We draw a K Map according to the number of variables it contains.We fill the K Map
with 0’s and 1’s according to its function.
Then, we minimize the function in accordance with the following rules.
Rule-01:
We can either group 0’s with 0’s or 1’s with 1’s but we can not group 0’s and 1’stogether.
X representing don’t care can be grouped with 0’s as well as 1’s.
Rule-02:
Groups may overlap each other.
Rule-03:
We can only create a group whose number of cells can be represented in thepower of 2.
In other words, a group can only contain 2n i.e. 1, 2, 4, 8, 16 and so on numberof cells.
Example-
Rule-04:
Groups can be only either horizontal or vertical.
We can not create groups of diagonal or any other shape.
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Rule-05:
Each group should be as large as possible.
Example-
Rule-06:
Opposite grouping and corner grouping are allowed.
The example of opposite grouping is shown illustrated in Rule-05.The example of
corner grouping is shown below.
Example-
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Rule-07:
There should be as few groups as possible.
Simplification of boolean expressions using Karnaugh MapZ = f(A,B,C) =
+ B + AB + AC
By using the rules of simplification and ringing of adjacent cells in order tomake as many
variables redundant, the minimised result obtained is B +
AC+
Z = f(A,B,C) = B + B + BC + A
By using the rules of simplification and ringing of adjacent cells in order to make as many
variables redundant, the minimised result obtained is B + A
Example
Simplify the given 4-variable Boolean equation by using k-map. F (W, X, Y, Z) =(1, 5, 12, 13)
Sol: F (W, X, Y, Z) = (1, 5, 12, 13)
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By preparing k-map, we can minimize the given Boolean equation asF = W Y’ Z + W
‘Y’ Z
Simplify the given 5-variable Boolean equation by using k-map.f (A, B, C, D, E) =
∑ m (0, 5, 6, 8, 9, 10, 11, 16, 20, 42, 25, 26, 27)
Problem-01:
Minimize the following boolean function- F(A, B, C, D)
= Σm(0, 1, 2, 5, 7, 8, 9, 10, 13, 15)
Since the given boolean expression has 4 variables, so we draw a 4 x 4 K Map.We fill the cells of K
Map in accordance with the given boolean function.
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Then, we form the groups in accordance with the above rules.Then, we have-
Now,
F(A, B, C, D)
= (A’B + AB)(C’D + CD) + (A’B’ + A’B + AB + AB’)C’D + (A’B’ + AB’)(C’D’ + CD’)
= BD + C’D + B’D’
Thus, minimized boolean expression is-F(A, B, C,
D) = BD + C’D + B’D’
Problem-02:
Minimize the following boolean function- F(A, B, C, D)
= Σm(0, 1, 3, 5, 7, 8, 9, 11, 13, 15)
Solution-
Since the given boolean expression has 4 variables, so we draw a 4 x 4 K Map.We fill the cells of K
Map in accordance with the given boolean function.
Then, we form the groups in accordance with the above rules.
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Now,
F(A, B, C, D)
= (A’B’ + A’B + AB + AB’)(C’D + CD) + (A’B’ + AB’)(C’D’ + C’D)
= D + B’C’
Thus, minimized boolean expression is-F(A, B, C,
D) = B’C’ + D
Problem 3: Y=A'B'C'+A' BC'+AB' C'+AB' C+ABC'+ABC
Simplified expression: Y=A+C'
Problem 4: Y=A'B'C' D'+A' B' CD'+A' BCD'+A' BCD+AB' C' D'+ABCD'+ABCD
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Simplified expression: Y=BD+B'D'
Problem 5: Y=(A + B + C') + (A + B' + C') + (A' + B' + C) + (A' + B' + C')
Simplified expression: Y=(A + C') .(A' + B')
Problem 6: F(A,B,C,D)=π(3,5,7,8,10,11,12,13)
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1.8.1 Don’t Care (X) Conditions in K-Maps
The “Don’t Care” conditions allow us to replace the empty cell of a K-Map toform a grouping
of the variables which is larger than that of forming groupswithout don’t cares. While forming
groups of cells, we can consider a “Don’t Care” cell as 1 or 0 or we can also ignore that cell.
Therefore, “Don’t Care” condition can help us to form a larger group of cells.
A Don’t Care cell can be represented by a cross(X) in K-Maps representing a invalid

combination. For example, in Excess-3 code system, the states 0000, 0001, 0010, 1101, 1110 and
1111 are invalid or unspecified. These states are called don’t cares.
Example-1:
Minimise the following function in SOP minimal form using K-Maps:f = m(1, 5, 6, 11,
12, 13, 14) + d(4)
Example-2:
Minimise the following function in POS minimal form using K-Maps:F(A, B, C, D) =
m(0, 1, 2, 3, 4, 5) + d(10, 11, 12, 13, 14, 15)
Writing the given expression in POS form:
F(A, B, C, D) = M(6, 7, 8, 9) + d(12, 13, 14, 15)
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The POS K-map for the given expression is:
F = (A'+ C)(B' + C')
Example-3:
Minimise the following function in SOP minimal form using K-Maps:
F(A, B, C, D) = m(1, 2, 6, 7, 8, 13, 14, 15) + d(0, 3, 5, 12)
Explanation:
The SOP K-map for the given expression is:
f = AC'D' + A'D + A'C + AB
1.8.2 Tabular Method of Minimization
The tabular method which is also known as the Quine-McCluskey method isparticularly
useful when minimising functions having a large number of
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variables, e.g. The six-variable functions. Computer programs have been developed
employing this algorithm. The method reduces a function in standard sum of products
form to a set of prime implicants from which as many variables are eliminated as possible.
These prime implicants are thenexamined to see if some are redundant.
The tabular method makes repeated use of the law A + = 1. Note thatBinary notation is
used for the function, although decimal notation is also used for the functions. As usual a
variable in true form is denoted by 1, ininverted form by 0, and the abscence of a variable by a
dash ( - ).
Example 1:
Consider the function f(A, B, C, D) = (0,1,2,3,5,7,8,10,12,13,15), note that this is in decimal

form.
(0000,0001,0010,0011,0101,0111,1000,1010,1100,1101,1111) in binary
form.
(0,1,1,2,2,3,1,2,2,3,4) in the index form.
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The prime implicants are: + + D + BD + A + AB
The chart is used to remove redundant prime implicants. A grid is prepared

having all the prime implicants listed at the left and all the minterms of the
function along the top. Each minterm covered by a given prime implicant is
marked in the appropriate position.
From the above chart, BD is an essential prime implicant. It is the only prime
implicant that covers the minterm decimal 15 and it also includes 5, 7 and 13.
is also an essential prime implicant. It is the only prime implicant that covers the
minterm denoted by decimal 10 and it also includes the terms 0, 2 and 8. The
other minterms of the function are 1, 3 and 12. Minterm 1 is present in and
D. Similarly for minterm 3. We can therefore use either of these prime implicantsfor
these minterms. Minterm 12 is present in A and AB , so again either canbe
used.
Thus, one minimal solution is: Z = + BD + + A
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1.3 Part A Questions
S.N Question BL C
o & O
Answers
1 What are basic properties of Boolean algebra?
Ans. The basic properties of Boolean algebra are commutative BL CO
property, associative property and distributive property. 1 1
2 State the associative property of boolean algebra.
Ans. The associative property of Boolean algebra states that the
OR ing of several variables results in the same regardless of the BL CO
grouping of the variables. The associative property is statedas 1 1
follows:
A+ (B+C) = (A+B) +C
3 State De Morgan's theorem.
Ans. De Morgan suggested two theorems that form importantpart
of Boolean algebra. They are,
1) The complement of a product is equal to the sum of the BL CO
complements. 1 1
(AB)' = A' + B'
2) The complement of a sum term is equal to the product of
the complements. (A + B)' = A'B'
4 Reduce A'B'C' + A'BC' + A'BC
Ans. A'B'C' + A'BC' + A'BC = A'C'(B' + B) + A'B'C
= A'C' + A'BC [A + A' = 1] BL CO
= A'(C' + BC) 3 1
= A'(C' + B) [A + A'B = A + B]
5 Reduce AB + (AC)' + AB'C(AB + C)
Ans. AB + (AC)' + AB'C(AB + C) = AB + (AC)' + AAB'BC + AB'CC
= AB + (AC)' + AB'CC [A.A' = 0]
= AB + (AC)' + AB'C [A.A = 1]
= AB + A' + C' =AB'C [(AB)' = A' + B']
= A' + B + C' + AB'C [A + AB' = A + B] BL CO
= A' + B'C + B + C' [A + A'B = A + B] 3 1
= A' + B + C' + B'C
=A' + B + C' + B'
=A' + C' + 1
= 1 [A + 1 =1]
6 Define duality property.
Ans. Duality property states that every algebraic expression
deducible from the postulates of Boolean algebra remains
valid if the operators and identity elements are BL CO
interchanged. If the dual of an algebraic expression is 1 1
desired, we simply interchange OR and AND
operators
and replace 1's by 0's and 0's by 1's.
7 Find the complement of the functions F1 = x'yz' + x'y'z and F2
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=x(y'z' + yz). By applying De-Morgan's theorem.
Ans. F1' = (x'yz' + x'y'z)' = (x'yz')'(x'y'z)' = (x + y' + z)(x + y +z') F2' =[x(y'z' BL CO
+ yz)]' = x' + (y'z' + yz)' 3 1
= x' + (y'z')'(yz)'
= x' + (y + z)(y' + z')
8 Find the minterms of the logical expression Y = A'B'C' + A'B'C +
A'BC + ABC'
Ans. Y = A'B'C' + A'B'C + A'BC + ABC' BL CO
=m0 + m1 +m3 +m6 3 1
=m(0, 1, 3, 6)
9 What are called don’t care conditions?
Ans. In some logic circuits certain input conditions never occur,
therefore the corresponding output never appears. In suchcases the
output level is not defined, it can be either high or low. These BL CO
output levels are indicated by ‘X’ or‘d’ in the truth tables and are 1 2
called don’t care conditions or incompletely specified functions.
10 What is an essential implicant?

Ans. If a min term is covered by only one prime implicant, theprime BL CO
implicant is said to be essential 1 2
11 What is a Logic gate?
Ans. Logic gates are the basic elements that make up a digitalsystem.
The electronic gate is a circuit that is able to operate on a BL CO
number of binary inputs in order to perform a particular logical 1 4
function.
12 Given the two binary numbers X = 1010100 and Y = 1000011,perform
the subtraction
Ans. (a) X -Y and (b) Y - X using 2's complements. a) X =1010100
2's complement of Y = 0111101
Sum = 10010001 BL CO
Discard end carry Answer: X - Y = 0010001 b) Y = 10000112's 3 3
complement of X = + 0101100
Sum = 1101111
There is no end carry, The MSB BIT IS 1.
Answer is Y-X = - (2's complement of 1101111) = - 0010001
13 Convert (1101)2 into a decimal

number.Ans. 1 × 23 + 1 × 22 + 0 × 21 + 1 × BL CO
20
=8+4+0+1 3 3
= 13
14 Convert (89)16 into a binary number.
Ans. 8 = 1000 and 9 = 1001 BL CO
Therefore, (89)16 = (10001001)2 3 3
1.4 Part B Questions
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S.No Question BL
C
O
1 a) Explain ny two binary codes with example. NOV 2019 he BL1,BL3
b) Each of tfollowing arithmetic operations is correct in at least one
number system. Determine the possible bases of thenumbers in each operation: 2 = CO4
i) 1234 + 543 6666.
(ii) 41/3 = 13.
(iii) 33/3 = 11.
2 (a) Simplify the following algebraic expression:(x’ + xyz’)
+ (x’ + xyz’)(x+x’y’z)
(b) Prove that if w’x+yz’ = 0 , then wx+
y’(w’+z’) = wx + xz + x’z’+w’y’z
(c) Determine the canonical sum-of- products representationof th
function:
f(x,y,z) = z + (x’+y)(x+y’) p
3 (a) Find the minterms of the following Boolean expressions byfirst
function in a map:
(i) xy +yz+ xy’z.
(ii) wxy +x’z’ + w’xz.
(b) Draw a NAND logic diagram that implements thecomplement
following function:
F(A,B,C,D) = Σ ( 0,1,2,3,4,8,9,12)
4 Using QM method, simplify the following function: F(x1, ..................
Σ( 0,1,2,8,9,15,17,21,24,25,27,31) and find the Prime implicantsand es
implicants.
5 (a) Perform the subtraction with the following decimal numbers u
complement and 9’s complement: (i) 5250
– 321. (ii) 20 – 1000.
(b) Prove the Boolean identity x + yz = (x + y) (x + z).
6 (a) Represent decimal number 6027 in: (i) BCD. (ii) excess-3code. (i
2421 code.
(b) Expand A (𝑚̅ +B) to maxterms and minterms.
7 (a) Simplify the following Boolean functions using Karnaughmap:
F(A, B, C, D) = Π (1, 3, 4, 5, 10, 11, 12, 13, 14, 15)
(b) Realize Y = A+BC using NOR gates.
8 Using the tabular method, obtain the minimal expression forf(w, x, y

Σ𝑚(1,3,4,5,9,10,11) + d(6,8).
9 (a) Convert the following:
(i) (163.789)10 = ( )8.
(ii) (101101110001.00101)2 = ( )8.
(iii) (292)16 = ( )2. n
(b) Prove that AND - OR network is equivalent to NAND-NAND
w
10 Using 5-variable k-map, find minimal SOP expressions for thefollo
function:
F = Σ(0, 2, 4, 5, 6, 7, 8, 10, 17, 18, 21, 29, 31)+d(11, 20, 22)
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11 Implement the Boolean function F(A,B,C,D)=A′B′+C′D′+B′C′ using the following BL4 CO4
two level gates: (i) NAND – AND. (ii) NOR –
OR.
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UNIT-II
1.1.1 INTRODUCTION TO COMBINATIONAL CIRCUITS

The digital system consists of two types of circuits, namely
i) Combinational circuits
ii) Sequential circuits
Combinational circuit consists of logic gates whose output at any time is determined from the
present combination of inputs. The logic gate is the mostbasic building block of combinational
logic. The logical function performed by a combinational circuit is fully defined by a set of
Boolean expressions. A combinational circuit consists of input variables, logic gates, and output
variables. The logic gates accept signals from inputs and output signals are generated according
to the logic circuits employed in it. Binary information from the given data transforms to desired
output data in this process. Both inputand output are obviously the binary signals, i.e., both the
input and output signals are of two possible states, logic 1 and logic 0.
n inputs Combinational . . m outputs

circuits .
.
.
.
Block diagram of a combinational logic circuit
For n number of input variables to a combinational circuit, 2n possible combinations of binary
input states are possible. For each possible combination, there is one and only one possible output
combination. A combinational logiccircuit can be described by m Boolean functions and each
output can be expressed in terms of n input variables.
1.1.2 INTRODUCTION TO SEQUENTIAL CIRCUITS

Sequential logic circuit comprises both logic gates and the state of storage elements such as flip-
flops. As a consequence, the output of a sequential circuit depends not only on present value of inputs
but also on the past state of inputs
Block diagram of a sequential logic circuit
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Sequential logic circuits, it consists of combinational circuits to which storage elements are
connected to form a feedback path. The storage elements are devices capable of storing binary
information either 1 or 0. The information stored in the memory elements at any given time
defines the present state of the sequential circuit. The present state and the external circuit
determine theoutput and the next state of sequential circuits.
Classification of Logic Circuits
The sequential circuits can be classified depending on the timing of their signals:
i) Synchronous sequential circuits.
ii) Asynchronous sequential circuits.
In synchronous sequential circuits, signals can affect the memory elements onlyat discrete instants of
time.
In asynchronous sequential circuits change in input signals can affect memoryelement at any instant
of time
The memory elements used in both circuits are Flip-Flops, which are capable ofstoring 1- bit
information
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1.1.3 DIFFERENCE BETWEEN COMBINATIONAL AND SEQUENTIAL CIRCUITS
S.No Combinational logic Sequential logic

The output variable, at all timesdepends The output variable depends not only on
1
on the combination of input variables. the present input but alsodepend upon the
past history of
inputs.
2 Memory unit is not required Memory unit is required to store thepast

history of input variables.
3 Faster in speed Slower than combinational circuits.

4 Easy to design Comparatively harder to design.
5 Eg. Parallel adder Eg. Serial adder
1.1.4 ANALYSIS OF COMBINATIONAL CIRCUITS

Given a combinational circuit, the analysis procedure is used to determine the Boolean function
implemented by the combinational circuit. The circuitfunction is determined y Boolean function or
Truth table.
Example: Analyze the given combinational circuit and determine the Booleanfunction
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SOLUTION
Identify the function at the output of each gate
F1=AB'C'+A'BC'+A'B'C+ABC
F2=AB+AC+BC
Truth Table Approach
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F1=AB'C'+A'BC'+A'B'C+ABCF2=AB+AC+BC
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1.1.5 DESIGN OF COMBINATIONAL CIRCUITS (PROCEDURE)

 Any combinational circuit can be designed by the following steps of designprocedure.
 The problem is stated.
 Identify the input and output variables.
 The input and output variables are assigned letter symbols
 Construction of a truth table to meet input -output requirements.
 Writing Boolean expressions for various output variables in terms of inputvariables.
 The simplified Boolean expression is obtained by any method of minimizationalgebraic method,
Karnaugh map method, or tabulation method.
 A logic diagram is realized from the simplified Boolean expression using logicgates.
 There should be a minimum number of interconnections.
 Limitation on the driving capability of the gates should not be ignored
 The implementation should have the minimum number of gates, with thegates used having
the minimum number of inputs.
1.1.6 CIRCUITS FOR ARITHMETIC OPERATIONS – BINARY ADDER- HALF ADDER

Half Adder is a combinational circuit that can be used to add two binary bits. Ithas two inputs that
represent the two bits to be added and two outputs, with one producing the SUM output and the
other producing the CARRY.
Block Diagram of Half Adder
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The truth table of a half-adder, showing all possible input combinations and thecorresponding outputs
are shown below.
Inputs Outputs
A B Carry (C) Sum (S)
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
K-map simplification for carry and sum
The Boolean expressions for the SUM and CARRY outputs are given by theequations
Sum, S= A’B+ AB’,
Carry, C = A . B
The first one representing the SUM output is that of an EX-OR gate, the secondone representing the
CARRY output is that of an AND gate.
The logic diagram of the half adder is,
1.1.7 CIRCUITS FOR ARITHMETIC OPERATIONS – BINARY ADDER- FULL ADDER
A full adder is a combinational circuit that forms the arithmetic sum of three input bits. Itconsists of 3
inputs and 2 outputs. Two of the input variables, represent the significant bits to be added. The third
input represents the carry from previous lower significant
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Position. The block diagram of full adder is given by
Block Diagram of Full Adder

The full adder circuit overcomes the limitation of the half-adder, which can be used to add two bits
only. As there are three input variables, eight different input combinations are possible. The truth
table is shown below,
Inputs Outputs
A B Cin Sum (S) Carry (Cout)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
K-map simplification for carry and sum
The Boolean expressions for the SUM and CARRY outputs are given by theequations,
Sum, S = A’B’Cin+ A’BC’in + AB’C’in + ABCin
Carry, Cout = AB+ ACin + BCin
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The logic diagram for the above functions is shown
1.1.8 CIRCUITS FOR ARITHMETIC OPERATIONS – BINARY ADDER- FULL ADDER USING
TWOHALF ADDERS.
The logic diagram of the full adder can also be implemented with two half- adders and one OR
gate. The S output from the second half adder is the exclusive-OR of Cin and the output of the first
half-adder, giving
Sum = Cin (A B)
= Cin (A‗B+AB‗)
= C‗in (A‗B+AB‗) + Cin (A‗B+AB‗)‗
= C‗in (A‗B+AB‗) + Cin (AB+A‗B‗)
= A‗BC‗in + AB‗C‗in + ABCin + A‗B‗Cin
And the carry output is,
Carry, Cout = AB+ Cin (A’B+AB’)
= AB+ A‗BCin+ AB‗Cin
= AB (Cin+1) + A‗BCin+ AB‗Cin [Cin+1= 1]
= ABCin+ AB+ A‗BCin+ AB‗Cin
= AB+ ACin (B+B‗) + A‗BCin= AB+ ACin+ A‗BCin
= AB (Cin+1) + ACin+ A‗BCin [Cin+1= 1]
= ABCin+ AB+ ACin+ A‗BCin
= AB+ ACin+ BCin (A +A‗)= AB+ ACin+ BCin
The logic diagram of the full adder can also be implemented with two half-adders and one OR gate is
as follows,
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1.1.9 CIRCUITS FOR ARITHMETIC OPERATIONS – BINARY PARALLEL ADDER.

The 4-bit binary adder using full adder circuits is capable of adding two 4-bitnumbers resulting in
a 4-bit sum and a carry output as shown in figure below,
Since all the bits of augend and addend are fed into the adder circuits simultaneously and the
additions in each position are taking place at the sametime, this circuit is known as parallel adder.
Let the 4-bit words to be added be represented by, A3A2A1A0= 1111 and B3B2B1B0= 0011
 The bits are added with full adders, starting from the least significant position,to form the sum it
and carry bit. The input carry C0 in the least significant position must be 0.
 The carry output of the lower order stage is connected to the carry input of the next higher
order stage. Hence this type of adder is called ripple-carry adder.
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 In the least significant stage, A0, B0 and C0 (which is 0) are added resulting insum S0 and carry
C1. This carry C1 becomes the carry input to the second stage. Similarly in the second stage, A1,
B1 and C1 are added resulting in sumS1 and carry C2, in the third stage, A2, B2 and C2 are added
resulting in sum S2and carry C3, in the third stage, A3, B3 and C3 are added resulting in sum S3
and C4, which is the output carry. Thus the circuit results in a sum (S3S2S1S0) and a carry output (Cout).
 Though the parallel binary adder is said to generate its output immediatelyafter the inputs are
applied, its speed of operation is limited by the carry propagation delay through all stages.
However, there are several methods toreduce this delay.
 One of the methods of speeding up this process is look-ahead carry additionwhich eliminates the
ripple-carry delay.
1.1.10 CARRY LOOK-A-HEAD ADDER

 In Parallel adder, all the bits of the augend and the addend are available forcomputation at the
same time.
 The carry output of each full-adder stage is connected to the carry input ofthe next high-order
stage. Since each bit of the sum output depends on the value of the input carry, time delay
occurs in the addition process. This timedelay is called as carry propagation delay.
 For example, addition of two numbers (0011+ 0101) gives the result as 1000.Addition of the LSB
position produces a carry into the second position. This carrywhen added to the bits of the second
position, produces a carry into the thirdposition.
 This carry when added to bits of the third position, produces a carry into thelast position. The
sum bit generated in the last position (MSB) depends on the carry that was generated by the
addition in the previous position. i.e., the adder will not produce correct result until LSB carry has
propagated through theintermediate full-adders.
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 This represents a time delay that depends on the propagation delay produced in an each full-
adder. For example, if each full adder is considered to have a propagation delay of 30nsec, then S3
will not react its correct value until 90nsec after LSB is generated. Therefore total time required to
perform additionis 90+ 30 = 120nsec.
 The method of speeding up this process by eliminating inter stage carry delayis called look ahead-
carry addition. This method utilizes logic gates to look atthe lower order bits of the augend and
addend to see if a higher-order carry isto be generated. It uses two functions: carry generate and carry
propagate.
Consider the circuit of the full-adder shown above. Here we define twofunctions:
Carry generate (Gi) and carry propagate (Pi) as,Carry generate,
Gi = Ai Bi
Carry propagate, Pi = Ai Bi
the output sum and carry can be expressed as,

Si = Pi Ci Ci+1 = Gi+PiCi
Gi (carry generate), it produces a carry 1 when both Ai and Bi are 1, regardlessof the input carryCi.
Pi (carry propagate) because it is the term associated with the propagation ofthe carry from Ci to
Ci+1.
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The Boolean functions for the carry outputs of each stage and substitute for each Ci its value from
the previous equation:
C0= input
carryC1= G0
+ P0C0
C2= G1 + P1C1 = G1 + P1 (G0 + P0C0)= G1 + P1G0 + P1P0C0
C3= G2 + P2C2 = G2 + P2 (G1 + P1G0 + P1P0C0)= G2 + P2G1 + P2P1G0 + P2P1P0C0
Since the Boolean function for each output carry is expressed in sum of products, each function
can be implemented with one level of AND gates followed by an OR gate. The three Boolean
functions for C1, C2 and C3 are implemented in the carry look-ahead generator as shown below.
Note that C3 does not have to wait for C2 and C1 to propagate; in fact C3 is propagated at the
same time as C1 and C2
 Using a Look-ahead Generator we can easily construct a 4-bit parallel adderwith a Look-ahead
carry scheme. Each sum output requires two exclusive-ORgates.
 The output of the first exclusive-OR gate generates the Pi variable, and theAND gate generates
the Gi variable. The carries are propagated through thecarry look- ahead generator and applied as
inputs to the second exclusive-ORgate.
 All output carries are generated after a delay through two levels of gates. Thus, outputs S1
through S3 have equal propagation delay times.
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1.1.11 CIRCUITS FOR ARITHMETIC OPERATIONS – BINARY SUBTRACTOR- HALF

SUBTRACTOR
 Half Subtractor is a combinational circuit that performs the subtraction of twobits.
 It has two inputs and two outputs as shown in the block diagram.
 Two inputs A and B form the minuend and the subtrahend.
 Two outputs B and B form the Difference and borrow output.
Block Diagram
• The truth table for the half subtractor is listed in the table. The Borrow output is 1 when A
is 0 and B is 1. The difference output is 1 when boththe inputs are different.
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Truth Table:
Inputs Outputs
A B B D
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
The simplified Boolean function for the two outputs can be obtained directlyfrom the truth table.
The logic diagram of the half subtractor implemented in sum of products isshown in the figure.
Limitations:
Multi-digit subtraction along with borrow of the previous digit subtraction is notpossible with half
subtractor
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1.1.12 CIRCUITS FOR ARITHMETIC OPERATIONS – BINARY SUBTRACTOR- FULL

SUBTRACTOR
 A full subtractor is a combinational circuit that performs a subtraction between two bits, taking
into account borrow of the lower significant stage.
 The circuit has three inputs X, Y and Z, and two outputs Difference and Borrowas shown in the
block diagram.
 Three Inputs (X,Y, Z is borrow)

 Two outputs (D-Difference, B-Borrow)
 The truth table for the full subtractor is listed in the table.























 The simplified Boolean function for the two outputs can be obtaineddirectly from the
truth table.
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 K Map for Difference K Map for Borrow
 The logic diagram of the full subtractor implemented in sum of products isshown in the
figure.
1.1.13 CIRCUITS FOR ARITHMETIC OPERATIONS – FULL SUBTRACTOR- USING TWO HALF
SUBTRACTOR
 A full subtractor is formed by two half subtractors,
 It involves three inputs such as minuend, subtrahend and borrow.
 Borrow bit among the inputs is obtained from subtraction of two binarydigits and is
subtracted from next higher order pair of bits, outputs as difference and borrow.
Difference =X’Y’Z+ X’YZ’+ XY’Z’ + XYZ = X Y Z
Borrow = X’Y+ X’Z+ YZ = X’Y + Z(X’+Y)

= X’Y+ X’YZ + X’Y’Z + XYZ + X’YZ
= X’Y+ X’YZ + X’YZ + X’Y’Z + XYZ
= X’Y (1+ Z + Z) + (X’Y’ + XY) Z
= X’Y + (X’ Y)’ Z
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 Logic Diagram:
1.1.14 CIRCUITS FOR ARITHMETIC OPERATIONS – PARALLEL SUBTRACTOR- FOUR BIT

SUBTRACTOR.
 A 4-bit subtractor is a digital circuit that produces the arithmetic subtraction of two binary numbers.
 It can be constructed with full adders connected in cascade with the output carry from each full
adder connected to the input carry of the next full adder in the chain.
 Subtraction of binary numbers are done by means of 2‘s complementA-B = A+2‘s
complement (B)= A+B‘+1
 The circuit for subtracting A-B consists of an adder with inverters placed
 Between each data input B and the corresponding input of the adder.
 The input carry Co must be equal to 1 when subtraction is performed.
 4-bit Subtractor / Parallel Subtractor
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 Here, A4, A3, A2, A1 is minuend and B4, B3, B2, B1 is subtrahend. S4, S3, S2, S1 isresult of subtraction
where C4 is final carry which is ignored.
 The input carry to the adder is C0 and it ripples through the full adders to theoutput carry C4.
 The sums bits are generated starting from the right most position and areavailable as soon as
the corresponding previous carry bit is generated.
 All the carry bits must be generated for the correct sum bits to appear at theoutputs.
1.1.15 CIRCUITS FOR ARITHMETIC OPERATIONS – BINARY ADDER-SUBTRACTOR.
 The addition and subtraction operations can be combined into one circuit withone common binary
adder.
 This is done by including an exclusive-OR gate with each full adder.
 The mode input (M) controls the operation of the circuit.
 Binary Adder-Subtractor
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 When M = 0, we have B 0 = B. The full adders receive the value of B, theinput carry is 0, and
the circuit performs A plus B .
 When M = 0, we have B 0 = B’ and C0 = 1.
 The B inputs are all complemented and a 1 is added through the input carry.The circuit performs
the operation A plus the 2‘s complement of B. (The exclusive-OR with output V is for detecting an
overflow.)
1.1.16 OVERFLOW DETECTION
Overflow occurs when:

 Two negative numbers are added and an answer comes positive or
 Two positive numbers are added and an answer comes as negative.
 So overflow can be detected by checking Most Significant Bit(MSB) of two operands and
answer.
 Overflow can also be detected using 2 Bit Comparator just by checking Carry- in(C- in) and
Carry-Out(C-out) from MSB‘s. Consider N-Bit Addition of 2‘s Compliment number.
 Overflow Occurs when C-in ≠ C-out.
1.1.17 BCD ADDER

BCD Adder consists of
 4-bit binary adder for initial condition.
 Logic circuit to detect sum >9.
 Adder to add (0110)2, if the sum >9 or carry is 1.
 The logic circuit to detect sum > 9 can be given by simplifying the boolean expression of the
given truth table.
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Truth Table
 When Y = 1, it indicates that the sum is greater than 9 or if there is a carry.
 When K = 1, it indicates that there is carry.
 When Y = 1, a binary 0110 is added to the binary sum through the secondadder.
 A decimal parallel adder that adds n‘ decimal digit needs n‘ BCD adderstages.
 A BCD adder that adds two BCD digits and produces a sum digit in BCD isshown in Figure.
 The two decimal digits, together with the input carry, are first added in the topfour-bit adder to
produce the binary sum.
 When the output carry is equal to 0, nothing is added to the binary sum.
 When it is equal to 1, binary 0110 is added to the binary sum through the bottom four-bit adder.
The output carry generated from the bottom adder can be ignored, since it supplies information
already available at the output carryterminal.
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 BCD Adder Block Diagram
1.1.18 BINARY MULTIPLIER
 Multiplication of binary numbers is performed in the same way as multiplication of decimal

numbers.
 The multiplicand is multiplied by each bit of the multiplier, starting from the leastsignificant bit.
 Each such multiplication forms a partial product. Successive partial products are shifted one
position to the left. The final product is obtained from the sum ofthe partial products.
1.1.19 BINARY MULTIPLIER-2 BY 2 BIT BINARY MULTIPLIER.
 Binary multiplier can be implemented with a combinational circuit.
 2 bit by 2 bit multiplier is shown in figure.
 The multiplicand bits are B1 and B0, the multiplier bits are A1 and A0, and theproduct is
C3C2C1C0.
 The multiplication of two bits such as A0 & B0 produces ‗1‘ if both bits are 1,otherwise, it
produces a ‗0‘. This is identical to the AND operation.
 Therefore , the partial products can be implemented with AND gates.
 The second partial product is formed similarly by shifting one position to the left.
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 The two partial products are added with two half adders.
 The least significant bit of the product does not have to go through an adder,since it is formed by
the output of the first AND gate.
 The binary output in each level of AND gates is added with the partial productof the previous level
to form a new partial product.
1.1.20 BINARY MULTIPLIER-4 BY 3 BIT BINARY MULTIPLIER
 For J multiplier bits and K multiplicand bits, we need (J * K) AND gates and(J – 1) K- bit
adders to produce a product of (J + K) bits.
 For 4 bit by 3 bit binary multiplier, we need 12 AND gates and 2- 4 bit adder toproduce a product
of 7 bits.
 The logic diagram of the multiplier is shown in the figure.
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1.1.21 MAGNITUDE COMPARATOR
 A magnitude comparator is a combinational circuit that compares twonumbers A and B and

determines their relative magnitudes.
 The comparison of two numbers is an operation that determines whether onenumber is greater
than, less than, or equal to the other number.
 The outcome of the comparison is specified by three binary variables thatindicate whether A <
B, A = B, or A > B.
1.1.22 4-BIT MAGNITUDE COMPARATOR
 The circuit for comparing two n -bit numbers has 22n entries in the truth tableand becomes
complicated, even with n = 3.
 The algorithm here, is a direct application of the procedure we use to compare
 the relative magnitudes of two numbers.
 Consider two numbers, A and B , with four digits eachA = A3 A2

A1 A0
B = B3 B2 B1 B0
A=B
 The two 4-bit numbers A and B are said to be equal if A3=B3 & A2=B2 & A1=B1 &A0=B0
 This can be written as

E3 = A3 ⊙ B3 (The ⊙ XNOR operation returns 1 if two bits are equal)E2 = A2 ⊙
B2
E1 = A1 ⊙
B2 E0 = A0 ⊙
B0
 The comparison A=B can be logically expressed by the following Booleanfunction F(A =
B) =E3.E2.E1.E0
 The binary variable A = B is equal to 1 only if all pairs of digits of the two numbersare equal.
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A>B
 To determine whether A is greater than B , the relative magnitudes of pairs ofsignificant digits
must be inspected starting from the most significant position(MSB).
 If the two digits of a pair are equal, we compare the next lower significant pair of digits. The
comparison continues until a pair of unequal digits is reached. Ifthe corresponding digit of A is 1
and that of B is 0, we conclude that A > B.
The number A is greater than B in one of the four cases:
o A3 > B3 (i.e. A3=1, B3=0). It is represented as A3 B3‘
o A3=B3 & A2>B2 (i.e. A2=1, B2=0). It is represented as E3A2B2‘
o A3=B3 & A2=B2 & A1>B1 (i.e. A1=1, B1=0). It is represented asE3E2A1B1‘
o A3=B3 & A2=B2 & A1=B1 & A0>B0 (i.e.A0=1, B0=0). It is representedas
E3E2E1A0B0‘
 The comparison A>B can be logically expressed by the following Boolean function F(A > B) =
A3 B3’ + E3A2B2’ + E3E2A1B1’ + E3E2E1A0B0’.
A<B
 To determine whether A is less than B , the relative magnitudes of pairs of significant digits
must be inspected starting from the most significant position(MSB).
 If the two digits of a pair are equal, we compare the next lower significant pair of digits. The
comparison continues until a pair of unequal digits is reached. Ifthe corresponding digit of A is 0
and that of B is 1, we conclude that A < B.
The number A is less than B in one of the four cases:
o A3 < B3 (i.e. A3=0, B3=1). It is represented as A3‘B3
o A3=B3 & A2<B2 (i.e. A2=0, B2=1). It is represented as E3A2'B2
o A3=B3 & A2=B2 & A1<B1 (i.e. A1=0, B1=1). It is represented asE3E2A1‘B1
o A3=B3 & A2=B2 & A1=B1 & A0<B0 (i.e.A0=0, B0=1). It is representedas
E3E2E1A0‘B0
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 The comparison A<B can be logically expressed by the following Booleanfunction F(A <
B)= A3’B3+ E3A2'B2 + E3E2A1’B1 + E3E2E1A0’B0
 Logic Diagram for 4-bit Magnitude Comparator
1.1.23 2-BIT MAGNITUDE COMPARATOR

The circuit for comparing two n -bit numbers has 22n entries in the truth tableSo, for comparing two
2-bit numbers, the truth table has 22x2=16 entries.
Consider two numbers, A and B , with two digits eachA = A1 A0
B = B1 B0
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Truth table for comparison of two 2-bit numbers
The outputs A=B, A>B and A<B is expressed as follows:
F(A<B) = ∑m (1,2,3,6,7,11)
F(A>B) = ∑m (4,8,9,12,13,14)
F(A=B) = ∑m (0,5,10,15)
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K-map for F(A<B)
F(A<B) = A1’B1 + A1’A0’B0 + A0’B1B0

K-map for F(A>B)
F(A>B) = A1B1’ + A1A0B0’ + A0B1’B0’
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K-map for F (A=B)
Logic diagram for 2-bit Magnitude Comparator
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1.1.24 DESIGN OF CODE CONVERTERS

 The availability of a large variety of codes for the same discrete elements ofinformation results
in the use of different codes by different digital systems.
 It is sometimes necessary to use the output of one system as the input toanother.
 A conversion circuit must be inserted between the two systems if each usesdifferent codes for
the same information.
 Thus, a code converter is a circuit that makes the two systems compatible eventhough each uses a
different binary code.
 To convert from binary code A to binary code B, the input lines must supply the bit combination of
elements as specified by code A and the output lines must generate the corresponding bit
combination of code B. A combinational circuitperforms this transformation by means of logic gates.
1.1.25 DESIGN OF BCD TO EXCESS-3 CODE CONVERTER
 BCD is the binary code to represent the decimal numbers 0 – 9.
 In Excess 3 code in each coded combination is obtained from the corresponding binary value plus
3.
 TRUTH TABLE
 Let A,B,C,D be the bits of the BCD code
 Let E3,E2,E1,E0 be the bits of the Excess-3 code
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1.1.26 DESIGN OF CODE CONVERTERS

The output E3, E2, E1 and E0 are expressed as follows
E3 = ∑m (5,6,7,8,9) + ∑d
(10,11,12,13,14,15)
E2 = ∑m (1,2,3,4,9) + ∑d
(10,11,12,13,14,15)
E1 = ∑m (0,3,4,7,8) + ∑d
(10,11,12,13,14,15)
K-map
E0 = for
∑mE3(0,2,4,6,8) + ∑d
(10,11,12,13,14,15)
E3 = A + BC + BD
K-map for E2
E2 = B’C + B’D + BC’D’
K-map for E1
E1 = C’D’ + CD
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K-map for E0
E0 = D’
Logic Diagram for BCD to Excess-3 Code Converter
1.1.27 DESIGN OF BINARY TO GRAY CODE CONVERTER
 The Most Significant Bit (MSB) of the gray code is always equal to the MSB of thegiven binary code.
 Other bits of the output gray code can be obtained by XOR-ing binary code bitat that index and
previous index.
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 Example
Convert 1101 to Gray code
 The gray code equivalent for 1101 is 1011
 TRUTH TABLE:
Let A,B,C,D be the input bits of the binary number. Let G3,G2,G1,G0 be the bitsof the gray code
output
The outputs G3,G2,G1 and G0 are expressed as follows:
G3 = ∑m G2 = ∑m (4,5,6,7,8,9,10,11)
(8,9,10,11,12,13,14,15)
G0 = ∑m (1,2,5,6,9,10,13,14)
G1 = ∑m (2,3,4,5,10,11,12,13)
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K- map for G3
G3 = A
K- map for G2
G2 = A’B +
AB’
K- map for G1`
G1 = BC’ +
B’C
K- map for G0
G0 = C’D +C D’
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Logic Diagram for Binary to Gray Code Converter
1.1.28 DESIGN OF GRAY TO BINARY CONVERTER

The Most Significant Bit (MSB) of the binary code is always equal to the MSB ofthe given binary
number.
Other bits of the output binary code can be obtained by XOR-ing the graycode bit at that
index with the previous binary code bit.
Example: Convert the gray code 1000 to Binary
The gray code equivalent for 1000 is 1111TRUTH

TABLE
Let A,B,C,D be the input bits of the Gray code
Let B3,B2,B1,B0 be the bits of the Binary output
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B3 = ∑ B2 = ∑ (4,5,6,7,8,9,10,11)
(8,9,10,11,12,13,14,15)
B0 = ∑ (1,2,4,7,8,11,13,14)
B1 = ∑ (2,3,4,5,8,9,14,15)
The outputs B3,B2,B1 and B0 are expressed as follows:
K- map for B3 K- map for B2
K- map for B1 K- map for B0
B2 = A’B + AB’
B3 = A
SVEC TIRUPATI
B1=A xor B xor C B0=A xor B xor C xor D
Logic Diagram for Gray to Binary Code Converter
1.1.29 DECODERS
 A decoder is a combinational circuit that converts binary information from n input lines to a
maximum of 2n unique output lines. One of these outputs will be active High based on the
combination of inputs present, when the decoder isenabled. The general structure of decoder circuit
is –
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 Generally a decoder’s output code normally has more bits than its input code and practical
―binary decoder‖ circuits include 2-to-4, 3-to-8 and 4-to-16 line configurations.
1.1.30 BINARY DECODER (2 TO 4 DECODER)
 Let 2 to 4 Decoder has two inputs A1 & A0 and four outputs Y3, Y2, Y1 & Y0. Theblock diagram of
2 to 4 decoder
 One of these four outputs will be 1‘ for each combination of inputs when enable, E is 1‘. The
Truth table of 2 to 4 decoder
Enable Inputs Outputs
E A B Q0 Q1 Q2 Q3
0 X X 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
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 The binary inputs A and B determine which output line from Q0 to Q3 is ―HIGH at logic level ―1
while the remaining outputs are held ―LOW at logic ―0 so onlyone output can be active (HIGH) at
any one time. Therefore, whichever output line is ―HIGH identifies the binary code present at the
input, in other words it decodes the binary input.
 Circuit diagram of 2 to 4 decoder
 Therefore, the outputs of 2 to 4 decoder are nothing but the min terms of twoinput variables A1 &
A0, when enable, E is equal to one. If enable, E is zero, thenall the outputs of decoder will be equal to
zero.
 if enable input is 1 (EN= 1) only one of the outputs (Q0 – Q3), is active for agiven input.
 The output Y0 is active, ie., Y0=1 when inputs, A= 0 and B= 0,
 The output Y3 is active, ie., Y3=1 when inputs, A= 1 and B= 1.
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1.1.31 HIGH ORDER DECODERS

Now, let us implement the following two higher-order decoders using lower-order decoders.
o 3 to 8 decoder
o 4 to 16 decoder
 A decoder with 3 binary inputs ( n = 3 ), would produce a 3-to-8 line decoder(TTL 74138) and 4
inputs ( n = 4 ) would produce a 4-to-16 line decoder (TTL74154) and so on. But a decoder can
also have less than 2n outputs such asthe BCD to seven-segment decoder (TTL 7447) which has
4 inputs and only 7 active outputs to drive a display rather than the full 16 (24) outputs as you
would expect
1.1.32 3- TO-8 LINE DECODER
 A 3-to-8 line decoder has three inputs (A, B, C) and eight outputs (Y0- Y7). Based on the 3 inputs
one of the eight outputs is selected.
 The three inputs are decoded into eight outputs, each output representing oneof the min-terms of the
3-input variables. This decoder is used for binary-to-octalconversion.
 The input variables may represent a binary number and the outputs will represent the eight digits
in the octal number system. The output variables are mutually exclusive because only one output can
be equal to 1 at any one time.
 The output line whose value is equal to 1 represents the minterm equivalent of the binary number
presently available in the input lines.
 Required No of Decoder =m1/m2
 m1 is the number of outputs of lower order decoder. m2 is the number of outputs of higher order
decoder.
 Here, m1 = 4 and m2 = 8.
 Required number of 2 to 4 decoders=8/4
 Therefore, we require two 2 to 4 decoders for implementing one 3 to 8 decoder.
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BLOCK DIAGRAM FOR 3- TO 8 DECODER
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TRUTH TABLE OF 3 TO 8 DECODER
Outputs
Inputs
A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Circuit implementation of 3- to 8 decoder
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The parallel inputs B and C are applied to each 2 to 4 decoder. The complement of input A is
connected to Enable, E of lower 3 to 8 decoder in order to get the outputs, Y3 to Y0. These are the
lower four min terms. The input,A3 is directly connected to Enable, E of upper 2 to 4 decoder in order
to get the outputs, Y4 to Y7. These are the higher four min terms.
1.1.33 4 TO 16 DECODERS USING 3- TO-8 DECODER
 To implement 4 to 16 decoder using 3 to 8 decoders. We know that 3 to 8 Decoder has three

inputs A2, A1 & A0 and eight outputs, Y7 to Y0. Whereas, 4 to
16 Decoder has four inputs A3, A2, A1 & A0 and sixteen outputs, Y15 to Y0
 The formula for finding the number of lower order decoders required.
 Required number of lower order decoders= m2/m1=16/8=2
 Therefore, we require two 3 to 8 decoders for implementing one 4 to 16 decoder. The block
diagram of 4 to 16 decoder using 3 to 8 decoders
 The parallel inputs A2, A1 & A0 are applied to each 3 to 8 decoder. The complement of input,
A3 is connected to Enable, E of lower 3 to 8 decoder inorder to get the outputs, Y7 to Y0. These
are the lower eight min terms. Theinput, A3 is directly connected to Enable, E of upper 3 to 8
decoder in order toget the outputs, Y15 to Y8. These are the higher eight min terms.
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 Truth table for 4 - to -16 decoder
Inputs Outputs
A3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y
7
0 0 0 0 1 0 0 0 0 0 0 0
0 0 0 1 0 1 0 0 0 0 0 0
0 0 1 0 0 0 1 0 0 0 0 0
0 0 1 1 0 0 0 1 0 0 0 0
0 1 0 0 0 0 0 0 1 0 0 0
0 1 0 1 0 0 0 0 0 1 0 0
0 0 1 1 0 0 0 0 0 0 1 0
0 1 1 1 0 0 0 0 0 0 0 1
1 0 0 0 1 0 0 0 0 0 0 0
1 0 0 1 0 1 0 0 0 0 0 0
1 0 1 0 0 0 1 0 0 0 0 0
1 0 1 1 0 0 0 1 0 0 0 0
1 1 0 0 0 0 0 0 1 0 0 0
1 1 0 1 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 0 0 1 0
1 1 1 1 0 0 0 0 0 0 0 1
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1.1.34 4- TO 16 DECODER USING 2 TO 4 DECODERS
Required number of lower order decoders= m2/m1=16/4=4. Therefore, we requiretwo 2 to 4 decoders for
implementing one 4 to 16 decoder.
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1.1.35 ENCODERS
 An encoder is a digital circuit that performs the inverse operation of adecoder. An
encoder has 2n input lines and n output lines.
 Block Diagram
The various implementations of an encoder is
• Octal-to-binary encoder
• Priority encoder
1.1.36 DESIGN AN OCTAL – TO –BINARY ENCODER
 It has eight inputs (one for each of the octal digits) and three outputs thatgenerate the
corresponding binary number.
 It is called as 8 – to – 3 line encoder.
 It is assumed that only one input has a value of 1 at any given time. Otherwise
 The circuit has no meaning.
 Boolean output functions
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 The encoder can be implemented with OR gates whose inputs are determineddirectly from the
truth table.
 Truth Table
 Output z is equal to 1 when the input octal digit is 1, 3, 5, or 7.

 Output y is 1 for octal digits 2, 3, 6, or 7,
 Output x is 1 for digits 4, 5, 6, or 7
 The encoder can be implemented with three OR gates
 Logic Diagram
 Limitations:
The encoder has the limitation that only one input can be active at any given time. If two inputs are
active simultaneously, the output produces an undefinedcombination.
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1.1.37 PRIORITY ENCODER

 A priority encoder is an encoder circuit that includes the priority function.
Operation of Priority Encoder:
 If two or more inputs are equal to 1 at the same time, the input having the highest priority will
take precedence
 In addition to the two outputs x and y , the priority encoder circuit has a thirdoutput designated by
V
 The V bit is a valid bit indicator that is set to 1 when one or more inputs areequal to 1. Also, if all
inputs are 0, there is no valid input and V is equal to 0.
 When V is 0, the other two outputs (x and y) are not inspected and are specified as don‘t-care
conditions and is marked as X.
 The X‘s in output columns represent don‘t-care conditions, the X‘s in the input columns are
representing either 0 or 1. That is, Instead of listing all 16 min-terms of four variables, the truth table uses
an X to represent either 1 or 0.
 For example, X100 represents the two min-terms 0100 and 1100.
 Truth Table
 In priority encoder, the higher the subscript number of inputs (D0, D1, D2, and D3) gets the higher
the priority of the input. That is, Input D3 has the highestpriority, so, regardless of the values of the
other inputs, when this input is 1, theoutput for xy is 11 (binary 3).
 D2 has the next priority level. The output is 10 if D2 = 1, provided that D3 = 0, regardless of the
values of the other two lower priority inputs.
 The output for D1 is generated only if higher priority inputs are 0.
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1.1.38 K-MAP FOR PRIORITY ENCODER

The K map simplification for the outputs x and y are shown below
 The min-terms for K-map are obtained by considering each X in a row is replaced first by 0 and
then by 1. Hence, all 16 possible input combinations are obtained.
 For example, the fourth row in the truth table, with inputs XX10, represents the four min-terms 0010,
0110, 1010, and 1110.
 The condition for output V is an OR function of all the input variables.
 The simplified Boolean expressions for the outputs x and y are obtained from theK-maps are shown
below.
 Logic Diagram
The logic diagram for the priority encoder is shown below.
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1.1.39 MULTIPLEXER
 A multiplexer or MUX is a combinational circuit that has maximum of 2n datainputs, n‘ selection

lines and single output line.
 One of these data inputs will be connected to the output based on the valuesof selection lines.
Therefore, the selection of a particular input line is controlled by a set of selection lines.
 The multiplexer is also called as a data selector , since it selects one of manyinputs.
 Block Diagram
 Examples
 Two – to – 1 line Multiplexer
 Four – to – 1 line Multiplexer
 Eight – to – 1 line Multiplexer
1.1.40 DESIGN OF 2 – TO - 1 MULTIPLEXER
 The 2 - to -1 line MUX has two data input lines, one output line, and one selection line, S.
 There are 2 input lines, 21 = 2, therefore, the circuit requires 1 selection line.
Block Diagram
 The block diagram of 2 – to - 1 line MUX is shown below.
 The I0 and I1 are the two inputs and S is the selection line. This MUX directs only one output,
designated as Y.
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 Truth Table
S Y
0 I0
1 I1
 The truth table of 2 – to - 1 line MUX is shown below.

 The output expression can be written as, Y = S'I0 + SI1
 Logic Diagram
The logic diagram of 2 - to -1 line MUX is shown below
 Each of the two inputs, I0 and I1, is applied to one input of an AND gate. Theother input of the
AND gates the selection line, S.
 The outputs of the AND gates are connected to a single OR gate that providesthe one-line output.
 When S = 0, the upper AND gate is enabled and I0 has a path to the output.When S = 1, the lower
AND gate is enabled and I1 has a path to the output.
1.1.41 DESIGN OF 4 – to - 1 MULTIPLEXER
 The 4 - to -1 line MUX has four data input lines, one output line, and twoselection lines, S0
and S1.
 There are 4 input lines, 22= 4, therefore, the circuit requires 2 selection lines.
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 Block Diagram
The block diagram of 4 – to - 1 line MUX is shown below.
 The I0, I1, I2 and I3 are the four inputs and, S0 and S1 are the selection lines. This
 MUX directs one output, labeled as Y.
 Truth Table: The truth table of 4 – to - 1 line MUX is shown below
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
The output expression can be written as,
Y = S1'S0'I0 + S1'S0I1 + S1S0'I2 + S1S0I3
 Logic Diagram
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 Each of the four inputs, I0 through I3, is applied to one input of an AND gate.The other inputs of
the AND gates are the selection lines.
 Selection lines S1 and S0 are decoded to select a particular AND gate.
 When S1S0 = 10, the AND gate associated with input I2 has two of its inputsequal to 1 and the
third input connected to I2. At the same time, the other three AND gates have at least one input
equal to 0, which makes their outputsequal to 0.
1.1.42 DESIGN OF 8 – TO - 1 MULTIPLEXER

 The 8 - to -1 line MUX has eight data input lines, one output line, and three selection lines, S0, S1
and S2.
 There are 8 input lines, 23 = 8, therefore, the circuit requires 3 selection lines.
 The block diagram of 8 – to - 1 line MUX is shown below.
 The I0 through I7 are the eight inputs and, S0, S1 and S2 are the selection lines. This MUX
directs one output, labeled as Y
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 Block Diagram
 Truth Table
The truth table of 8 – to - 1 line MUX is shown below
S2 S1 S0 Y
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7
 The output expression can be written as,

Y = S2'S1'S0'I0 + S2'S1'S0I1 +S2'S1S0'I2 +S2’S1S0I3 + S2S1'S0'I4 + S2S1'S0I5 +S2
S1S0'I6 +S2 S1S0I7
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 Logic Diagram
 Each of the eight inputs, I0 through I7, is applied to one input of an AND gate.The other inputs of
the AND gates are the selection lines.
 Selection lines S2 , S1 and S0 are decoded to select a particular AND gate.
1.1.43 DESIGN OF 8 X 1 MULTIPLEXER USING TWO 4X1 MUX AND ONE 2X 1 MUX
 The 8 X 1 multiplexer can be designed using two 4X1 MUX and one 2X1multiplexer.
 Block diagram
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 The 8 X 1 multiplexer accepts 8 inputs from I0 through I7.

 Logic Diagram
 The inputs from I0 through I3 are applied to one 4 X 1 multiplexer and inputs I4through I7 are
applied to another 4 X 1 multiplexer.
 The output of both the multiplexers are applied to one 2X1 multiplexer which inturn produces one
output and was designated to Y.
 The selection lines from S0 and S1 are applied to both 4 X1 multiplexers and S2selection line is
applied to 2X1 multiplexer.
1.1.44 DESIGN A 16 X 1 MULTIPLEXER USING TWO 8X1 MUX AND ONE 2X1 MULTIPLEXER
 The 16 X 1 multiplexer can be designed using two 8X1 MUX and one 2X1multiplexer.
 Block diagram
 The 16 X 1 multiplexer accepts 16 inputs from I0 through I15 .
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 Logic Diagram
 The inputs from I0 through I7 are applied to one 8 X 1 multiplexer and inputs I8through I15 are
applied to another 8 X 1 multiplexer.
 The output of both the multiplexers are applied to one 2X1 multiplexer which inturn produces one
output and was designated to Y.
 The selection lines from S0 to S2 are applied to both 8X1 multiplexers and S3selection
 line is applied to 2X1 multiplexer.
1.1.45 DEMULTIPLEXER
 De-multiplex means one into many.
 Demultiplexing is the process of taking information from oneinput and transmitting the same over one
of several outputs.
 A demultiplexer is combinational circuit that receives information on a singleinput and transmits
the same information over one of several (2n) output lines where n is the number of select lines.
The demultiplexer is also called a distributor or a serial to parallel converter.
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 As an example, consider a 1 to 8 demultiplexer which has a single input (D) andeight outputs (Y0 to
Y7) and three select inputs (S0,Si &S2).
 It distributes one input line to eight output lines based on the select inputs. Thetruth table is shown
below.
Select In Outputs
S2 S1 S0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 D 0 0 0 0 0 0 0
0 0 1 0 D 0 0 0 0 0 0
0 1 0 0 0 D 0 0 0 0 0
0 1 1 0 0 0 D 0 0 0 0
1 0 0 0 0 0 0 D 0 0 0
1 0 1 0 0 0 0 0 D 0 0
1 1 0 0 0 0 0 0 0 D 0
1 1 1 0 0 0 0 0 0 0 D
 The logic diagram of a 1 to 8 demultiplexer is shown in, figure
 The expressions for eight outputs can be written as
Y0= S2‘S1‘S0‘Din Y4= S2 S1‘S0‘Din

Y1= S2‘S1‘S0Din Y5= S2S1‘S0Din
Y2= S2‘S1S0‘Din Y6= S2S1S0‘Din
Y3= S2‘S1S0Din Y7= S2S1S0Din
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 Here, the single data input line Din is connected to all the eight AND gates butonly one of the eight
AND gates will be enabled by the select input lines.
 The key difference between a decoder and a Demultiplexer is that the former isa logic circuit that
decrypts an encoded bit stream from one format into another, while the latter is a combination
circuit that routes a single input line tomultiple digital output lines
1.1.46 1: 4 DEMULTIPLER
 1x4 De-Multiplexer has one input I, two selection lines, si & so and four outputs Y3, Y2, Y1&Y0.
The block diagram of 1x4 De-Multiplexer is shown in the followingfigure.
 The single input 'I' will be connected to one of the four outputs, Y3 to Y0 based on the values of
selection lines S1 & S0. The Truth table of 1x4 De-Multiplexer isshown below.
Selection Outputs
Inputs
S1 S0 Y3 Y2 Y1 Y0
0 0 0 0 0 I
0 1 0 0 I 0
1 0 0 I 0 0
1 1 I 0 0 0
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SVEC TIRUPATI
 From the Truth table, we can directly write the Boolean functions foreach output as
Y0=s1's0'I Y1=s1's0I
Y2=s1s0'I Y3=s1s0I
 We can implement these Boolean functions using Inverters & 3-input AND gates. The circuit diagram
of 1x4 De-Multiplexer is shown in the following figure
1.1.47 DESIGNING LARGER DEMULTIPLERS USING SMALLER DEMULTIPLEXERS

 We can implement 1x8 De-Multiplexer using lower order Multiplexers easily byconsidering the
above Truth table. The block diagram of 1x8 De-Multiplexer using 1x4 DeMUX is shown in the
following figure.
 The common selection lines, s1 & s0 are applied to both 1x4 De-Multiplexers.
 The outputs of upper 1x4 De-Multiplexer are Y7 to Y4 and the outputs of lower1x4 De-Multiplexer
are Y3to Y0.
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 the other selection line, s2 is applied to 1x2 De-Multiplexer. If s2 is zero, then oneof the four outputs
of lower 1x4 De-Multiplexer will be equal to input, I based onthe values of selection lines s1 & s0.
 Similarly, if s2 is one, then one of the four outputs of upper 1x4 DeMultiplexer willbe equal to input, I
based on the values of selection lines s1 & s0.
1.1.48 IMPLEMENT 1X16 DE-MULTIPLEXER USING 1X8 DE-MULTIPLEXERS AND 1X2

DEMULTIPLEXER.
 We know that 1x8 De-Multiplexer has single input, three selection lines and eightoutputs. Whereas,
1x16 De-Multiplexer has single input, four selection lines andsixteen outputs.
 So, we require two 1x8 De-Multiplexers in second stage in order to get the final sixteen outputs.
Since, the number of inputs in second stage is two, we require 1x2 DeMultiplexer in first stage so that
the outputs of first stage will be the inputsof second stage. Input of this 1x2 De-Multiplexer will be the
overall input of 1x16DeMultiplexer.
 Let the 1x16 De-Multiplexer has one input I, four selection lines s3, s2, s1 & s0 and outputs Y15 to Y0.
The block diagram of 1x16 De-Multiplexer using lower order Multiplexers is shown in the above
figure.
 The common selection lines s2, s1 & s0 are applied to both 1x8 De- Multiplexers. The outputs of
upper 1x8 De-Multiplexer are Y15 to Y8 and the outputs of lower 1x8 DeMultiplexer are Y7 to Y0.
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SVEC TIRUPATI
 The other selection line, s3 is applied to 1x2 De-Multiplexer. If s3 is zero, then one
of the eight outputs of lower 1x8 De-Multiplexer will be equal to input, I based
on the values of selection lines s2, s1 & s0. Similarly, if s3 is one, then one of the 8
outputs of upper 1x8 De-Multiplexer will be equal to input, I based on the values
of selection lines s2, s1 & s0.
Programmable Logic Devices (PLDs)
Lesson Objectives:
In this lesson you will be introduced to some types of Programmable Logic Devices
(PLDs):
 PROM, PAL, PLA, CPLDs, FPGAs, etc.

 How to implement digital circuits using PLAs and PALs.
Introduction:
An IC that contains large numbers of gates, flip-flops, etc. that can be configured by
the user to perform different functions is called a Programmable Logic Device
(PLD).
The internal logic gates and/or connections of PLDs can be changed/configured by a

programming process.
One of the simplest programming technologies is to use fuses. In the original state of
the device, all the fuses are intact.
Programming the device involves blowing those fuses along the paths that must be
removed in order to obtain the particular configuration of the desired logic function.
PLDs are typically built with an array of AND gates (AND-array) and an array of
OR gates (OR-array).
Advantages of PLDs:
Problems of using standard ICs:
Problems of using standard ICs in logic design are that they require hundreds or
thousands of these ICs, considerable amount of circuit board space, a great deal of
time and cost in inserting, soldering, and testing. Also require keeping a significant
inventory of ICs.
Advantages of using PLDs:

Advantages of using PLDs are less board space, faster, lower power requirements
(i.e., smaller power supplies), less costly assembly processes, higher reliability (fewer
ICs and circuit connections means easier troubleshooting), and availability of design
64|
BTECH_ECE-SEM 21
SVEC TIRUPATI
There are three fundamental types of standard PLDs: PROM, PAL, and PLA.
A fourth type of PLD, which is discussed later, is the Complex Programmable Logic
Device (CPLD), e.g., Field Programmable Gate Array (FPGA).
A typical PLD may have hundreds to millions of gates.
II
SVEC TIRUPATI
In order to show the internal logic diagram for such technologies in a concise form, it
is necessary to have special symbols for array logic.
Figure shows the conventional and array logic symbols for a multiple input AND and
a multiple input OR gate.
Three Fundamental Types of PLDs:

The three fundamental types of PLDs differ in the placement of programmable
connections in the AND-OR arrays. Figure shows the locations of the programmable
connections for the three types.
II
SVEC TIRUPATI
 The PROM (Programmable Read Only Memory) has a fixed AND array
(constructed as a decoder) and programmable connections for the output OR gates
array. The PROM implements Boolean functions in sum-of-minterms form.
 The PAL (Programmable Array Logic) device has a programmable AND array
and fixed connections for the OR array.
 The PLA (Programmable Logic Array) has programmable connections for both
AND and OR arrays. So it is the most flexible type of PLD.
The ROM (Read Only Memory) or PROM (Programmable Read Only

Memory):
The input lines to the AND array are hard-wired and the output lines to the OR array
are programmable.
Each AND gate generates one of the possible AND products (i.e., minterms).
In the previous lesson, you have learnt how to implement a digital circuit using ROM.
The PLA (Programmable Logic Array):

In PLAs, instead of using a decoder as in PROMs, a number (k) of AND gates is used
where k < 2n, (n is the number of inputs).
Each of the AND gates can be programmed to generate a product term of the input
variables and does not generate all the minterms as in the ROM.
The AND and OR gates inside the PLA are initially fabricated with the links (fuses)
among them.
The specific Boolean functions are implemented in sum of products form by opening
appropriate links and leaving the desired connections.
A block diagram of the PLA is shown in the figure. It consists of n inputs, m outputs,
and k product terms.
The product terms constitute a group of k AND gates each of 2n inputs.
Links are inserted between all n inputs and their complement values to each of the
AND gates.
Links are also provided between the outputs of the AND gates and the inputs of the
OR gates.
II
SVEC TIRUPATI
Since PLA has m-outputs, the number of OR gates is m.
The output of each OR gate goes to an XOR gate, where the other input has two sets
of links, one connected to logic 0 and other to logic 1. It allows the output function to
be generated either in the true form or in the complement form.
The output is inverted when the XOR input is connected to 1 (since X 1 = X/). The
output does not change when the XOR input is connected to 0 (since X 0 = X).
Thus, the total number of programmable links is 2n x k + k x m + 2m.
The size of the PLA is specified by the number of inputs (n), the number of product
terms (k), and the number of outputs (m), (the number of sum terms is equal to the
number of outputs).
Example:
Implement the combinational circuit having the shown truth table, using PLA.
Each product term in the expression requires an AND gate. To minimize the cost, it is
necessary to simplify the function to a minimum number of product terms.
Designing using a PLA, a careful investigation must be taken in order to reduce the
distinct product terms. Both the true and complement forms of each function should
be simplified to see which one can be expressed with fewer product terms and which
one provides product terms that are common to other functions.
The combination that gives a minimum number of product terms is:

F ’ = AB + AC + BC or F = (AB + AC + BC)’
1 1
F2 = AB + AC + A’B’C’
A’B’C’.
II
SVEC TIRUPATI
So the PLA table will be as follows:
For each product term, the inputs are marked with 1, 0, or – (dash). If a variable in the
product term appears in its normal form (unprimed), the corresponding input variable
is marked with a 1.
A 1 in the Inputs column specifies a path from the corresponding input to the input of
the AND gate that forms the product term.
A 0 in the Inputs column specifies a path from the corresponding complemented

input to the input of the AND gate. A dash specifies no connection.
The appropriate fuses are blown and the ones left intact form the desired paths. It is
assumed that the open terminals in the AND gate behave like a 1 input.
In the Outputs column, a T (true) specifies that the other input of the corresponding
XOR gate can be connected to 0, and a C (complement) specifies a connection to 1.
Note that output F1 is the normal (or true) output even though a C (for complement) is
marked over it. This is because F1’ is generated with AND-OR circuit prior to the
output XOR. The output XOR complements the function F1’ to produce the true F1
output as its second input is connected to logic 1.
II
SVEC TIRUPATI
The PAL (Programmable Array Logic):

The PAL device is a PLD with a fixed OR array and a programmable AND array.
As only AND gates are programmable, the PAL device is easier to program but it is
not as flexible as the PLA.
The device shown in the figure has 4 inputs and 4 outputs. Each input has a buffer-
inverter gate, and each output is generated by a fixed OR gate.
The device has 4 sections, each composed of a 3-wide AND-OR array, meaning that
there are 3 programmable AND gates in each section.
Each AND gate has 10 programmable input connections indicating by 10 vertical

lines intersecting each horizontal line. The horizontal line symbolizes the multiple
input configuration of an AND gate.
One of the outputs F1 is connected to a buffer-inverter gate and is fed back into the
inputs of the AND gates through programmed connections.
(see animation in authorware version)
Designing using a PAL device, the Boolean functions must be simplified to fit into
each section.
The number of product terms in each section is fixed and if the number of terms in the
function is too large, it may be necessary to use two or more sections to implement
one Boolean function.
II
SVEC TIRUPATI
Example:
Implement the following Boolean functions using the PAL device as shown above:
W(A, B, C, D) = ∑m(2, 12, 13)

X(A, B, C, D) = ∑m(7, 8, 9, 10, 11, 12, 13, 14, 15)
Y(A, B, C, D) = ∑m(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
Z(A, B, C, D) = ∑m(1, 2, 8, 12, 13)
Simplifying the 4 functions to a minimum number of terms results in the following

Boolean functions:
W = ABC’ + A’B’CD’
X = A + BCD
Y = A’B + CD + B’D’
Z = ABC’ + A’B’CD + AC’D’ + A’B’C’D
=W +AC’D’ + A’B’C’D
Note that the function for Z has four product terms. The logical sum of two of these
terms is equal to W. Thus, by using W, it is possible to reduce the number of terms for
Z from four to three, so that the function can fit into the given PAL device.
The PAL programming table is similar to the table used for the PLA, except that only
the inputs of the AND gates need to be programmed.
The figure shows the connection map for the PAL device, as specified in the
programming table.
(see animation in authorware version)
II
SVEC TIRUPATI
Since both W and X have two product terms, third AND gate is not used. If all the
inputs to this AND gate left intact, then its output will always be 0, because it receives
both the true and complement of each input variable i.e., AA’ =0
Complex Programmable Logic Devices (CPLDs):

A CPLD contains a bunch of PLD blocks whose inputs and outputs are connected
together by a global interconnection matrix.
Thus a CPLD has two levels of programmability: each PLD block can be
programmed, and then the interconnections between the PLDs can be programmed.
II
SVEC TIRUPATI
Field Programmable Gate Arrays (FPGAs):

The FPGA consists of 3 main structures:
1. Programmable logic structure,
2. Programmable routing structure, and
3. Programmable Input/Output (I/O).
1. Programmable logic structure

The programmable logic structure FPGA consists of a 2-dimensional array of
configurable logic blocks (CLBs).
Each CLB can be configured (programmed) to implement any Boolean function of its
input variables. Typically CLBs have between 4-6 input variables. Functions of larger
number of variables are implemented using more than one CLB.
In addition, each CLB typically contains 1 or 2 FFs to allow implementation of

sequential logic.
Large designs are partitioned and mapped to a number of CLBs with each CLB
configured (programmed) to perform a particular function.
These CLBs are then connected together to fully implement the target design.
Connecting the CLBs is done using the FPGA programmable routing structure.
2. Programmable routing structure

To allow for flexible interconnection of CLBs, FPGAs have 3 programmable routing
resources:
1. Vertical and horizontal routing channels which consist of different length wires
that can be connected together if needed. These channel run vertically and
horizontally between columns and rows of CLBs as shown in the Figure.
II
SVEC TIRUPATI
2. Connection boxes, which are a set of programmable links that can connect input and
output pins of the CLBs to wires of the vertical or the horizontal routing channels.
3. Switch boxes, located at the intersection of the vertical and horizontal channels. These are
a set of programmable links that can connect wire segments in the horizontal and vertical
channels. (see animation in authorware version)
3. Programmable I/O
These are mainly buffers that can be configured either as input buffers, output buffersor
input/output buffers.
They allow the pins of the FPGA chip to function either as input pins, output pins orinput/output
pins.
ProgrammableI/Os
SVEC TIRUPATI
2.3 Part A- Question & Answers
S.No Question& Answers BL CO

1 What are combinational circuits?
A combinational circuit consists of logic gates whose outputs at any time are
determined from the present combination of inputs. A combinational circuit BL2 CO3
performs an operation that can be specified logically by a set of Boolean
functions. It consists of
input variables, logic gates, and output variables.
2 Define half adder.
A combinational circuit that performs the addition of two bits is called a half
adder. A half adder needs two binary inputs and two binary outputs. The input BL2 CO3
variables designate the augend and addend bits; the output variables
produce the sum and
carry
3 Define full adder?
A combinational circuit that performs the addition of three bits isa full adder. It BL2 CO3
consists of three inputs and two outputs.
4 Define binary adder.
A binary adder is a digital circuit that produces arithmetic sum of two binary
numbers. It can be constructed with full adders constructed in cascade, with BL2 CO3
output carry from each full adder
connected to the input carry of the next full adder in the chain.
5 Define magnitude comparator?
A magnitude comparator is a combinational circuit that
compares two numbers, A and B, and determines their relative BL2 CO3
magnitudes. The outcome of the comparison is specified bythree binary
variables that indicate whether a>b, A = b, or A < B.
6 What are decoders?
A decoder is a combinational circuit that converts binary information from n
input lines to a maximum of 2n unique outputlines. If the n bit coded information BL2 CO3
has unused combinations, he
decoder may have fewer than 2n outputs.
SVEC TIRUPATI
7 What are encoders?

An encoder is a digital circuit that performs the inverse operationof a decoder. An BL2 CO3
encoder has 2n and n output lines. The output lines generate the binary code
corresponding to the input value.
8 Define sequential circuit?
In sequential circuits the output variables dependent not only on BL2 CO3
the present input variables but they also depend up on the pasthistory of these
input variables.
9 Give the comparison between combinational circuits andsequential circuits.
Memory unit is not required Memory unity is required Paralleladder is a
combinational circuit Serial adder is a sequential BL2 CO3
circuit
10 Define synchronous sequential circuit and Asynchronous

sequential circuit?
In synchronous sequential circuits, signals can affect the memoryelements only at BL2 CO3
discrete instant of time.
In asynchronous sequential circuits change in input signals canaffect memory
element at any instant of time
2.4 Part B- Questions
S.No Question BL CO
1. Implement the function with NOR-NOR logic Y= A C + B C + A B+ D.
1 2. (a)
Convert the following to Decimal and then to BL3 CO2
Hexadecimal.(1) 12348 (2) 110011112
(b)Find the complement of the following Boolean function and reduce
intominimum numberof literals. Y= (C’+A’D)(DB’+CD’)
1.Minimize the following function using K-map
(i) F (A,B,C,D) = Σ𝑚 (1,2,3,4,7,8,9,10,11,12,14)
2 (ii) F (A,B,C,D)= 𝑚M (0,1,3,5,6,7,9,10,11,12,13,15) BL3 CO2
(b) Minimize the following Boolean functions. (i) F (A,B,C,D)
=Σ𝑚(1,3,5,8,9,11,15) +d (2,13)
(ii) F (A,B,C,D) =𝑚M (1,2,3,8,9,10,11,14) +d (7,15)
1.(a) What is function of magnitude comparator? Explain with

anExample.
(b) Design a combinational circuit with four input lines that represent a
3 decimal digit in BCD and four output lines that generate the 9’s BL3 CO2
complementof the input digit.
2. (a) Design a 4 bit binary-to-BCD code converter.
(b) Design 32:1 Mux using two 16:1 Mux and one 2:1 Mux.
SVEC TIRUPATI
1. Draw the block diagram of sequential circuit. Explain.
4 (b) What is state assignment? Explain with a suitable example. BL3 CO3
2. a)Design JK flip-flop using SR flip-flop and logic gates.
(b)Classify sequential logic circuits.
2.A 12 bit hamming code word containing 8 bits of data and 4 parity
bits is readfrom memory. What was the original 8 bit data word that
was written in to memory if 12 bit words read out asfollows?
5 (a). 001111101010 (b) 101110010110 (c) 1011110110100(d) BL3 CO2
11001101011
2.Tabulate the PAL programmable table for the followings listed below
A(x,y,z)=∑m(1,2,4,6) B(x,y,z)=∑m(0,1,6,7)
C(x,y,z)=∑m(2,6) D(x,y,z)= )=∑m(1,2,3,5,7)
SVEC TIRUPATI
UNIT-III
3.1 LATCHES
There are two types of memory elements based on the type of triggering that is suitable to operate it.
Latches
Flip-flops
Latches operate with enable signal, which is level sensitive. Whereas, flip-flops are edge sensitive. We will discuss about flip-flops in
next chapter. Now, let us discuss about SR Latch & D Latch one by one.
SR Latch
SR Latch is also called as Set Reset Latch. This latch affects the outputs as long as the enable, E is maintained at ‘1’. The circuit
diagram of SR Latch is shown in the following figure.
SVEC TIRUPATI
This circuit has two inputs S & R and two outputs Qtt & Qtt’. The upper NOR gate has two inputs R & complement of present state,
Qtt’ and produces next state, Qt+1t+1 when enable, E is ‘1’.
Similarly, the lower NOR gate has two inputs S & present state, Qtt and produces complement of next state, Qt+1t+1’ when enable, E
is ‘1’.
We know that a 2-input NOR gate produces an output, which is the complement of another input when one of the input is ‘0’.
Similarly, it produces ‘0’ output, when one of the input is ‘1’.
If S = 1, then next state Qt+1t+1 will be equal to ‘1’ irrespective of present state, Qtt values.
If R = 1, then next state Qt+1t+1 will be equal to ‘0’ irrespective of present state, Qtt values.
At any time, only of those two inputs should be ‘1’. If both inputs are ‘1’, then the next state Qt+1t+1 value is undefined.
The following table shows the state table of SR latch.
S R Qt+1t+1
0 0 Qtt
0 1 0
1 0 1
1 1 -
Therefore, SR Latch performs three types of functions such as Hold, Set & Reset based on the input conditions.
D Latch
There is one drawback of SR Latch. That is the next state value can’t be predicted when both the inputs S & R are one. So, we can
overcome this difficulty by D Latch. It is also called as Data Latch. The circuit diagram of D Latch is shown in the following figure.
SVEC TIRUPATI
This circuit has single input D and two outputs Qtt & Qtt’. D Latch is obtained from SR Latch by placing an inverter between S
amp;& R inputs and connect D input to S. That means we eliminated the combinations of S & R are of same value.
If D = 0 → S = 0 & R = 1, then next state Qt+1t+1 will be equal to ‘0’ irrespective of present state, Qtt values. This is corresponding
to the second row of SR Latch state table.
If D = 1 → S = 1 & R = 0, then next state Qt+1t+1 will be equal to ‘1’ irrespective of present state, Qtt values. This is corresponding
to the third row of SR Latch state table.
The following table shows the state table of D latch.
D Qt+1t+1
0 0
1 1
Therefore, D Latch Hold the information that is available on data input, D. That means the output of D Latch is sensitive to the
changes in the input, D as long as the enable is High.
In this chapter, we implemented various Latches by providing the cross coupling between NOR gates. Similarly, you can implement
these Latches using NAND gates.
3.6 FLIP-FLOPS
SVEC TIRUPATI
SR Flip-Flop
SR flip-flop operates with only positive clock transitions or negative clock transitions. Whereas, SR latch operates with enable signal.
The circuit diagram of SR flip-flop is shown in the following figure.
This circuit has two inputs S & R and two outputs Qtt & Qtt’. The operation of SR flipflop is similar to SR Latch. But, this flip-flop
affects the outputs only when positive transition of the clock signal is applied instead of active enable.
The following table shows the state table of SR flip-flop.
S RQt+1t+1
0 0 Qtt
0 10
1 01
1 1-
Here, Qtt & Qt+1t+1 are present state & next state respectively. So, SR flip-flop can be used for one of these three functions such as
Hold, Reset & Set based on the input conditions, when positive transition of clock signal is applied. The following table shows the
characteristic table of SR flip-flop.
Present Inputs Present State Next State
S RQtt Qt+1t+1
0 00 0
0 01 1
0 10 0
0 11 0
1 00 1
1 01 1
1 10 x
1 11 x
By using three variable K-Map, we can get the simplified expression for next state, Qt+1t+1. The three variable K-Map for next state,
Qt+1t+1 is shown in the following figure.
The maximum possible groupings of adjacent ones are already shown in the figure. Therefore, the simplified expression for next state
Qt+1t+1 is
Q(t+1)=S+R′Q(t)Q(t+1)=S+R′Q(t)
D Flip-Flop
D flip-flop operates with only positive clock transitions or negative clock transitions. Whereas, D latch operates with enable signal.
That means, the output of D flip-flop is insensitive to the changes in the input, D except for active transition of the clock signal. The
circuit diagram of D flip-flop is shown in the following figure.
SVEC TIRUPATI
This circuit has single input D and two outputs Qtt & Qtt’. The operation of D flip-flop is similar to D Latch. But, this flip-flop affects
the outputs only when positive transition of the clock signal is applied instead of active enable.
The following table shows the state table of D flip-flop.
D Qt + 1t + 1
0 0
1 1
Therefore, D flip-flop always Hold the information, which is available on data input, D of earlier positive transition of clock signal.
From the above state table, we can directly write the next state equation as
Qt+1t+1 = D
Next state of D flip-flop is always equal to data input, D for every positive transition of the clock signal. Hence, D flip-flops can be
used in registers, shift registers and some of the counters.
JK Flip-Flop
JK flip-flop is the modified version of SR flip-flop. It operates with only positive clock transitions or negative clock transitions. The
circuit diagram of JK flip-flop is shown in the following figure.
This circuit has two inputs J & K and two outputs Qtt & Qtt’. The operation of JK flip-flop is similar to SR flip-flop. Here, we
considered the inputs of SR flip-flop as S = J Qtt’ and R = KQtt in order to utilize the modified SR flip-flop for 4 combinations of
inputs.
The following table shows the state table of JK flip-flop.
J KQt+1t+1
0 0 Qtt
0 10
1 01
1 1 Qtt'
Here, Qtt & Qt+1t+1 are present state & next state respectively. So, JK flip-flop can be used for one of these four functions such as
Hold, Reset, Set & Complement of present state based on the input conditions, when positive transition of clock signal is applied. The
following table shows the characteristic table of JK flip-flop.
Present Inputs Present State Next State
J KQtt Qt+1t+1
0 00 0
0 01 1
0 10 0
0 11 0
1 00 1
SVEC TIRUPATI
1 01 1
1 10 1
1 11 0
By using three variable K-Map, we can get the simplified expression for next state, Qt+1t+1. Three variable K-Map for next state,
Qt+1t+1 is shown in the following figure.
The maximum possible groupings of adjacent ones are already shown in the figure. Therefore, the simplified expression for next state
Qt+1t+1 is
Q(t+1)=JQ(t)′+K′Q(t)Q(t+1)=JQ(t)′+K′Q(t)
T Flip-Flop
T flip-flop is the simplified version of JK flip-flop. It is obtained by connecting the same input ‘T’ to both inputs of JK flip-flop. It
operates with only positive clock transitions or negative clock transitions. The circuit diagram of T flip-flop is shown in the following
figure.
This circuit has single input T and two outputs Qtt & Qtt’. The operation of T flip-flop is same as that of JK flip-flop. Here, we
considered the inputs of JK flip-flop as J = T and K = T in order to utilize the modified JK flip-flop for 2 combinations of inputs. So,
we eliminated the other two combinations of J & K, for which those two values are complement to each other in T flip-flop.
The following table shows the state table of T flip-flop.
D Qt+1t+1
0 Qtt
1 Qtt’
Here, Qtt & Qt+1t+1 are present state & next state respectively. So, T flip-flop can be used for one of these two functions such as
Hold, & Complement of present state based on the input conditions, when positive transition of clock signal is applied. The following
table shows the characteristic table of T flip-flop.
Inputs Present State Next State
T Qtt Qt+1t+1
0 00
0 11
1 01
1 10
From the above characteristic table, we can directly write the next state equation as
Q(t+1)=T′Q(t)+TQ(t)′Q(t+1)=T′Q(t)+TQ(t)′
⇒ Q(t+1)=T⊕Q(t)⇒ Q(t+1)=T⊕Q(t)
The output of T flip-flop always toggles for every positive transition of the clock signal, when input T remains at logic High 11.
Hence, T flip-flop can be used in counters.
SVEC TIRUPATI
In this chapter, we implemented various flip-flops by providing the cross coupling between NOR gates. Similarly, you can implement
these flip-flops by using NAND gates.
3.7 SHIFT REGISTERS
Flip-flop is a 1-bit memory cell which can be used for storing the digital data. To increase the storage capacity in terms of number of
bits, it is required to use a group of flip-flops. Such a group of flip-flops is known as a Register. The n-bit register will consist of n
number of flip-flop and it is
capable of storing an n-bit word. The binary data in a register can be moved within the register from one flip-flop to another. The
registers that allow such data transfers are called as shift registers. There are four mode of operations of a shift register.
Serial Input Serial Output
Serial Input Parallel Output
Parallel Input Serial Output
Parallel Input Parallel Output
Serial Input Serial Output

SVEC TIRUPATI
Let all the flip-flop be initially in the reset condition i.e., Q3 = Q2 = Q1 = Q0 = 0. If an entry of a four-bit binary number 1 1 1 1 is
made into the register, this number should be applied to Din bit with the LSB bit applied first. The D input of FF-3 i.e., D3 is
connected to serial data input Din. Output of FF-3 i.e., Q3 is connected to the input of the next flip-flop i.e., D2 and so on.
Block Diagram
SVEC TIRUPATI
Serial Input Parallel Output

● In such types of operations, the data is entered serially and taken out in parallel fashion.
● Data is loaded bit by bit. The outputs are disabled as long as the data is loading.
● As soon as the data loading gets completed, all the flip-flops contain their required data; the outputs are enabled so that all the
loaded data is made available over all the output lines at the same time.
● 4 clock cycles are required to load a four-bit word. Hence the speed of operation of SIPO mode is same as that of SISO mode.
Parallel Input Serial Output (PISO)
● Data bits are entered in parallel fashion.

SVEC TIRUPATI
● The circuit shown below is a four-bit parallel input serial output register.
● Output of previous Flip Flop is connected to the input of the next one via a combinational circuit.
● The binary input word B0, B1, B2, B3 is applied though the same combinational circuit.
● There are two modes in which this circuit can work namely - shift mode or load mode.
Load mode
When the shift/load bar line is low (0), the AND gate 2, 4 and 6 become active they will pass B1, B2, B3 bits to the corresponding
flip-flops. On the low going edge of clock, the binary input B0, B1, B2, B3 will get loaded into the corresponding flip- flops. Thus,
parallel loading takes place.
Shift mode
When the shift/load bar line is low (1), the AND gate 2, 4 and 6 become inactive. Hence the parallel loading of the data becomes
impossible. But the AND gate 1,3 and 5 become active. Therefore, the shifting of data from left to right bit by bit on application of
clock pulses. Thus, the parallel in serial out operation takes place.
Parallel Input Parallel Output (PIPO)

In this mode, the 4-bit binary input B0, B1, B2, B3 is applied to the data inputs D0, D1, D2, D3 respectively of the four flip-flops. As
soon as a negative clock edge is applied, the input binary bits will be loaded into the flip-flops simultaneously. The loaded bits will
appear simultaneously to the output side. Only clock pulse is essential to load all the bits.
SVEC TIRUPATI
Operation of 4-bit Register

Before application of clock signal, let Q3 Q2 Q1 Q0 = 0000 and apply LSB bit of the number to be entered to Din. So Din = D3 = 1.
Apply the clock. On the first falling edge of clock, the FF-3 is set, and stored word in the register is Q3 Q2 Q1 Q0 = 1000.
Apply the next bit to Din. So Din = 1. As soon as the next negative edge of the clock hits, FF-2 will set and the stored word change to
Q3 Q2 Q1 Q0 = 1100.
SVEC TIRUPATI
Apply the next bit to be stored i.e. 1 to Din. Apply the clock pulse. As soon as the third negative clock edge hits, FF-1 will be set and
output will be modified to Q3 Q2 Q1 Q0 = 1110.
Truth Table
SVEC TIRUPATI
Waveforms:
Universal Shift Register
A shift registers which can shift the data in only one direction is called a unidirectional shift register. A shift registers which can shift
SVEC TIRUPATI
the data in both directions is called a bi-directional shift register. Applying the same logic, a shift registers which can shift the data in
both directions as well as loads it parallelly, is known as a universal shift register. The shift register is capable of performing the
following operation −
Parallel loading
Left Shifting
Right shifting
The mode control input is connected to logic 1 for parallel loading operation whereas it is connected to 0 for serial shifting. With
mode control pin connected to ground, the universal shift register acts as a bidirectional register. For serial left operation, the input is
applied to the serial input which goes to AND gate-1 shown in figure. Whereas for the shift right operation, the serial input is applied
to D input.
Applications of shift Registers

 The shift registers are used for temporary data storage.
 The shift registers are also used for data transfer and data manipulation.
 The serial-in serial-out and parallel-in parallel-out shift registers are used to produce time delay to digital circuits.
 The serial-in parallel-out shift register is used to convert serial data into parallel data thus they are used in communication
lines where demultiplexing of a data line into several parallel line is required.
 A Parallel in Serial out shift register is used to convert parallel data to serial data.
3.8 COUNTERS
 A register that goes through a prescribed sequence of states upon the application of input pulses is called a counter.
 A counter that follows the binary number sequence is called a binary counter.
 An n-bit binary counter consists of n flip-flops and can count in binary from 0 through 2n-1.
 Two categories of counters:
 1. Asynchronous counters (or Ripple counters)
 2. Synchronous counters
 In a ripple counter, a flip-flop outputs transition serves as a source for triggering other flip flops. (i.e) the c‘ input of some or
all flip- flops are triggered, not by the common clock pulses, but rather by the transition that occurs in other flip-flop outputs.
 In a synchronous counter, the c‘ inputs of all flip-flops receive the common clock.
SVEC TIRUPATI
 Clock pulses are applied to the inputs of all flip-flops.

 A common clock triggers all flip-flops simultaneously.
 The design whether a flip-flop is to be complemented is determined from the values of the data inputs such as T or JK at the
time of the clock edge. If T=0 or J=K=0, the flip flop does not change. T=1 or J=K=1, the flip flop complements.
Design a 4 BIT BINARY UP COUNTER State Table:

Present State Next State Flip-Flop Inputs
A B C D A B C D JA KA JB KB JC KC JD KD
0 0 0 0 0 0 0 1 0 X 0 X 0 X 1 X
0 0 0 1 0 0 1 0 0 X 0 X 1 X X 1
0 0 1 0 0 0 1 1 0 X 0 X X 0 1 X
0 0 1 1 0 1 0 0 0 X 1 X X 1 X 1
0 1 0 0 0 1 0 1 0 X X 0 0 X 1 X
0 1 0 1 0 1 1 0 0 X X 0 1 X X 1
0 1 1 0 0 1 1 1 0 X X 0 X 0 1 X
0 1 1 1 1 0 0 0 1 X X 1 X 1 X 1
1 0 0 0 1 0 0 1 X 0 0 X 0 X 1 X
1 0 0 1 1 0 1 0 X 0 0 X 1 X X 1
1 0 1 0 1 0 1 1 X 0 0 X X 0 1 X
1 0 1 1 1 1 0 0 X 0 1 X X 1 X 1
1 1 0 0 1 1 0 1 X 0 X 0 0 X 1 X
1 1 0 1 1 1 1 0 X 0 X 0 1 X X 1
1 1 1 0 1 1 1 1 X 0 X 0 X 0 1 X
1 1 1 1 0 0 0 0 X 1 X 1 X 1 X 1
Excitation table for JK Flip-Flop State Diagram
Q(t Q(t+1 JK
) )
0 0 0 X
0 1 1 X
1 0 X1
SVEC TIRUPATI
 Logic circuits that can store information

🞑 Latches, which store a single bit
🞑 Flip-Flops, which store a single bit
🞑 Registers, which store multiple bits
 Shift registers
 Counters
 Design Examples
SVEC TIRUPATI
Sequential Circuits
3
 Combinational Circuits
🞑 circuits without feedback
🞑 output = f (current inputs)
 Sequential Circuits
🞑 circuits with feedback
🞑 output = f (current inputs, past inputs, past outputs)
🞑 how can we feed the past inputs and outputs into the circuits?
 basis for building “memory” into logic circuits
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Circuits with feedback

4
 How to control feedback?

🞑 what stops values from cycling around endlessly
x1 y1
x2 y2
x3 Sequential y3
. Circuit .
. .
. .
xn ym
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Control of an alarm system

5
Set
Sensor
Memory On  Off
Alarm
element
Reset
 the simplest case of a sequential circuit

🞑 Alarm is on when the sensor generates the “Set” signal in response to some undesirable events
🞑 Once the alarm is on, it can only be turned off manually through a reset button
 Memory is needed to remember that the alarmhas to be active until the reset signal arrives
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A simple memory element

6
The most rudimentary memory element

🞑 Two inverters form a static memory cell
 Assume A=0 and B=1, then the below circuit will maintain these
values indefinitely (as long as it has power applied)
 The state is defined by the value of the memory cell
 Two states
A B
How to get a new value into the memory cell?

🞑 selectively break feedback path
🞑 load new value into cell
SVEC TIRUPATI
A controlled memory element

7
Load
A B
Data Output
TG1
TG2
SVEC TIRUPATI
A memory element with NOR gates

8
Construct a memory cell using ordinary logic gates

🞑 Two NOR gates are connected in cross-coupled style
🞑 Basic Latch
Two inputs
🞑 Set
🞑 Reset
Reset
Set Q
SVEC TIRUPATI
A basic latch built with NOR gates

9
R S R Qa Qb
Qa
0 0 0/1 1/0 (no change)
0 1 0 1
1 0 1 0
1 1 0 0
S Qb
(a) Circuit (b) Truth table or characteristic table
t1 t2 t3 t4 t5 t6 t7 t8 t9
t10
1
R
0
1
S
0 There
1 will be an
oscillation
Qa ?
0
1
Qb ?
0
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Time
(c) Timing diagram
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Timing Waveform
10
R
S
R
Q
S
\Q
Timing Waveform
Reset Hold Set Reset Set Race

100
\ Q
Forbidden State Forbidden State

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State Behavior of R-S Latch
11
S R Q
QQ QQ
0 0 hold 01 10
0 1 0
1 0 1
1 1 unstable
QQ
Truth Table Summary 00
of R-S Latch Behavior
QQ
11
SVEC TIRUPATI
SVEC TIRUPATI
Theoretical R-S Latch State Diagram

12
 State Diagram SR = 00, 01 SR = 00, 10

🞑 state: possible values SR = 1 0
🞑 transitions: changesbased on
QQ QQ
inputs
01 10
SR = 0 1
SR = 0 1 SR = 1 0
SR = 11
SR = 1 1 SR = 1 1
QQ
00
SR = 0 1 SR = 1 0
SR = 0 0
SR = 0 0, 11
QQ
11
SVEC TIRUPATI
Observed R-S Latch Behavior

13
SR = 00, 01 SR = 00, 10
SR = 1 0
QQ QQ
01 10
SR = 0 1
SR = 0 1 SR = 1 0
SR = 11
SR = 1 1 SR = 1 1
QQ
00
SR = 0 0
SR = 0 0
Very difficult to observe R-S Latch in the 1-1 stateAmbiguously returns to state 0-1 or 1-0
A so-called "race condition"

SVEC TIRUPATI
R-S Latch Analysis
14
Derived K-Map:
Truth Table:
Next State = F(S, R, Current State) S
SR
Q(t ) 00 01 11 10
R-S Latch Revisited 0 0
S R Qt Q+ 0
X 1
0 hold reset 0
0 0 0 1
1 0 X 1
0 0 1 1 set 1
0 1 0 0
R
0 1 1 0
1 0 0 1 Characteristic Equation:
not allowed
1 0 1 1
1 1 0 x Q+ = S + R Q
t
1 1 1 x Q+
RS
R-S
Latch
Q
SVEC TIRUPATI
Problems of R-S Latch

15
 The slightest glitch on R or S could causechange in value stored

🞑 R-S Latch has transparent outputs
 Transparent outputs : when the memory element’s outputsimmediately change in response to
input changes
 Want to control when R and S inputs haveeffect on value stored

🞑 Enable Signal (or clock signal)
 R and S inputs are active only when Enable = 1
🞑 Gated Latches or Level sensitive latches
SVEC TIRUPATI
Gated SR latch
16
Control when R and S inputs \S
\Q
matters
🞑 the latch can be modified to respond tothe input
signal S and R only when
Enable =1 \R
Q
output is \enb
changing
output is Set Reset
stable
SVEC TIRUPATI
Gated SR Latch
17
SVEC TIRUPATI
Gated SR latch with NAND gates

18
S
Q
Clk
Q
R
SVEC TIRUPATI
Problems of the Gated S/R Latches

19
 1. Forbidden State and Race condition

🞑 How to eliminate the forbidden state and race condition
🞑 When S=R=1, (forbidden state)
Q Q 0
🞑 Oscillation (Race condition)
 D-type Latch
 JK-Latch (toggling)
 The output toggles forever when J=K=1
 2. When cascading level-sensitive Latches

 Master/Slave F/F’s
 Edge-triggered F/F’s
SVEC TIRUPATI
1. How to eliminate the forbidden state?
20 Gated D-latch
eliminate the troublesome situation
where S=R=1
SVEC TIRUPATI
How to eliminate the forbidden state?cont’d
Idea: use output feedback to guarantee that R and S

arenever both one
21 \Q
K R \Q
J, K both one yields toggle R-S
latch
J-K Latch J S Q
Q+ Q
J(t) K(t) Q(t) 0
hold
0 0 0
0 0 1 1
0 1 0 0 reset 0 Characteristic Equation:Q+ = Q K + Q J
0 1 1 0
1
1 0 0 1 set
1 0 1 1
1 1 0 1 toggle
1 1 1 0
SVEC TIRUPATI
J-K Latch: Toggles forever in thetoggle mode
Set Reset Toggle
22
100
J
K
Q
\Q
Oscillation
Toggle Correctness: Single State change per clocking event
Solution: Master/Slave Flipflop

SVEC TIRUPATI
Master/Slave J-K Flipflop
23 Master Stage Slave Stage
K \P \Q
R \Q R \Q
Delay R-S R-S
(d) Latch Latch
S Q P S Q
J Q
Clk
Sample inputs while clock high Sample inputs while clock low
Uses time to break feedback path from outputs to inputs!

1's
Set Reset Catch Toggle 100
J
Delay
(d) K Correct ToggleOperation
Clk
P Master
outputs
\P
Q Slave
outputs
\Q
SVEC TIRUPATI
2. When cascading Latches

24
R Qa Qb
R Q R Q
S Q S Q
S
clock
 How to stop changes from racing throughchain?

🞑 need to be able to control flow of data from one latch to the next
🞑 move one latch per clock period
🞑 have to worry about logic between latches that is too fast
SVEC TIRUPATI
Master/Slave D Flip-Flop
25
Master Slave
Qm Qs D Q
D D Q D Q Q
Q
Clock Clk Q Clk Q Q
(c) Graphical symbol
(a) Circuit
Clock
D
Qm
Q = Qs
(b) Timing diagram
Qa Qb
D
D Q D Q
Clock Q
Q
SVEC TIRUPATI
Positive-edge-triggered D flip-flop
26
1 • Clock = 0
D 1 P3
1 D • Output of gate 2 and 3 are high -> P1,P2 high
hold • Output is maintained
D hold state • Clock = 1
1
P1 Q • P3 and P4 are transmitted through gate 2 and3 to
0 cause P1 = D’ and P2 = D.
2 D
D 5 • This sets Q = D and Q = D’
• P3 and P4 must be stable when the clock goes from0 to 1.
• After that, the changes in D have no effect.

Clock D
=0 0 P2D
=1 6 Q
3 1
SVEC TIRUPATI
Comparison of level-sensitive and edge-triggered D storage elements
27
D D Q Qa Clock
Clock Clk Q Qa D
Qa
D Q Qb
Qb
Q Qb
Qc
D Q Qc (a) Timing diagram

Q Qc
(a) Circuit
SVEC TIRUPATI
Master-slave D flip-flop with Clearand Preset
28
Preset
0 1 0
Q 1
D
1 1
Clock 1 0 1 Q 0
1 1
Preset
Clear D Q
(a) Circuit Q
Clear
(b) Graphical symbol

SVEC TIRUPATI
Positive-edge-triggered D flip-flopwith Clear and Preset
29
Preset
Q
Preset
Clock D Q
Q
Q
Clear
D (b) Graphical symbol
Clear
SVEC TIRUPATI
Synchronous reset for a D flip-flop

30
Clear
D Q Q
D
Clock Q Q
SVEC TIRUPATI
T Flip-Flop
31
T Qt + 1 Q
T
D Q Q 0 Qt
1 Qt Q
T
Q Q
(b) Truth table (c) Graphical symbol
Clock
(a) Circuit
Clock
(d) Timing diagram

SVEC TIRUPATI
Realizing JK flip-flop with D flip-flop

32
J
D Q Q
K Q Q
Clock
(a) Circuit
SVEC TIRUPATI
JK Q t +1
0 0 Q t J Q
0 1 0
1 0 1
K Q
1 1 Q t
(b) Truth table (c) Graphical symbol

SVEC TIRUPATI
Last time
33
 Memory Cell
🞑 SR Latch
Problems of SR Latches
🞑 Glitch problems
 Transparent output - the memory element’s outputs immediatelychange in response to input
changes
Gated SR Latches (Enable signal or clock)
🞑 Another problems
 Forbidden state and racing problem D-latches, JK-latches
 When cascading latches
 How to stop changes from racing through chain?
Mater slave F/Fs and Edge triggered F/Fs (clock signal)
Memory elements change their states in response to a clock signal
We call these Synchronous systems
SVEC TIRUPATI
Today
34
Timing Methodologies
🞑 To guarantee the correct operation when cascading the Memory blocks
Comparison of Latches and F/Fs
Registers – store multiple bits
🞑 Storage registers
🞑 Shift registers
Counters – count events
🞑 Asynchronous counters
🞑 Synchronous counters
SVEC TIRUPATI
35
Set of rules for interconnecting components and clocks

🞑 When followed, guarantee proper operation of system
Proper operation:
(1) The correct inputs, with respect to time, are provided to the FFs
(2) no FF changes more than once per clocking event
Approach depends on building blocks used for memory elements

🞑 For systems with latches:
 Narrow Width Clocking
 Multiphase Clocking (e.g., Two Phase Non-Overlapping)
🞑 For systems with edge-triggered flip-flops:
 Single Phase Clocking
SVEC TIRUPATI
Definition of Terms
36
Clock:
Periodic Event, causes state of memoryelement to change
Tsu Th
Input rising edge, falling edge, high level, low level
Setup Time (Tsu)

Clock Minimum time before the clocking event bywhich the input must be stable
There is a timing "window" around Hold Time (Th)

theclocking event Minimum time after the clocking event duringwhich the input must remain stable
during which the inputmust remain
stable and unchanged
in order
to be recognized
SVEC TIRUPATI
Setup and Hold times for Latches

37
tsu
th
Clk
tplh tphl
SVEC TIRUPATI
Comparison of latch and F/F
38
Edge triggered device sample inputs on the eventedge
7474
Transparent latches sample inputs as long as theclock is asserted
Timing Diagram:
D Q
Clk
Positive edge-triggeredflip-
flop
D
7476
Clk
D Q
Q
7474
C
Q
7476
Clk Level-
sensitive
latch
Bubble here for negative
edge triggereddevice
Behavior the same unless input changeswhile the clock is high
SVEC TIRUPATI
Comparison of latches and F/Fs

39
Input/Output Behavior of Latches and Flipflops
Type When Inputs are Sampled When Outputs are Valid

unclocked always propagation delay from
latch input change
level clock high propagation delay fromsensitive
(Tsu, Th around input change latch falling
clock edge)
positive edge clock lo-to-hi transition propagation delay fromflipflop

(Tsu, Th around rising edge of clock
rising clock edge)
negative edge clock hi-to-lo transition propagation delay fromflipflop

(Tsu, Th around falling edge of clock
falling clock edge)
master/slave clock hi-to-lo transition propagation delay fromflipflop

(Tsu, Th around falling edge of clock
falling clock edge)
SVEC TIRUPATI
Typical Timing Specifications:Flipflops vs. Latches
40
74LS74 Positive
Edge Triggered Tsu Th T su Th
D Flipflop 20 5 20 5
ns ns ns ns
D
Tw
• Setup time 25
• Hold time ns
• Minimum clock width Clk
T phl
Tplh
• Propagation delays
25 ns 40 ns
(low to high, high to low,
13 ns 25 ns
max and typical) Q
All measurements are made from the clocking eventthat is, the rising edge of the clock
SVEC TIRUPATI
Typical Timing Specifications:Flipflops vs. Latches
74LS76
41
TransparentLatch Tsu Th Tsu Th
• D 20 5 20 5
Setup time ns
• Hold time ns ns ns
• Minimum Clock Width Clk Tw

• Propagation Delays: 20 T
high to low, low to high, ns
phl
Tplh
C» Q C» Q
maximum, typical
data to output Q 27 ns 25 ns
clock to output 15 ns 14 ns
Tplh D Tphl D
»Q »Q
27 ns 16 ns
15 ns 7 ns
Measurements from falling clock edgeor rising or falling data edge

SVEC TIRUPATI
42
IN Q0 Q1
Two F/Fs are cascaded D Q D Q
C Q C Q
New value to first stage CLK
while second stage
obtains current value
of first stage  Shift Register
Cascaded Flipflops and Setup/Hold/Propagation Delays
100
In
Correct Operation, Q0
assuming positive
Q1
edge triggered FF
Clk
SVEC TIRUPATI
Cascaded Flipflops and Setup/Hold/Propagation Delays
Why this works:

43 • Propagation delays far exceed hold times;Clock width constraint
exceeds setup time
• This guarantees following stage will latch current valuebefore it is replaced by new value
• Assumes infinitely fast distribution of the clock
In
Tsu Tsu Timing constraints
20 ns 20 ns guarantee proper
Q0 operation of
cascaded components
T plh T h
13 ns 13 ns
Q1
Clk
Th Th
5 ns 5 ns
SVEC TIRUPATI
The Problem of Clock Skew

44
Correct behavior assumes next state of all storage elements
determined by all storage elements at the same time
Not possible in real systems!
• logical clock driven from more than one physical circuit with
timing behavior
• different wire delay to different points in the circuit
Effect of Skew on Cascaded Flipflops:
FF0 samples IN FF1 samples Q0
100
In CLK2 is a delayed
Q0
version of CLK1
Q1
Clk1
Clk2
Original State: Q0 = 1, Q1 = 1, In = 0
Because of skew, next state becomes: Q0 = 0, Q1 = 0, not Q0 = 0, Q1 = 1
SVEC TIRUPATI
Design Strategies for MinimizingClock Skew
45
Typical propagation delays for LS FFs: 13 ns
Need substantial clock delay (on the order of 13 ns) for skew tobe a problem in this relatively slow technology
Nevertheless, the following are good design practices:
distribute clock signals in general direction of data flows
wire carrying the clock between two communicating componentsshould be as short as possible
for multiphase clocked systems, distribute all clocks in similarwire paths; this minimizes the possibility
of overlap
for the non-overlap clock generate, use the phase feedback signals from the furthest point in the circuit
to which the clockis distributed; this guarantees that the phase is seen as low everywhere before it
allows the next phase to go high
SVEC TIRUPATI
Choosing a Flipflop
46
R-S Clocked Latch:

used as storage element in narrow width clocked systems
its use is not recommended!
however, fundamental building block of other flipflop types
J-K Flipflop: (historically popular, but now not used)

versatile building block
can be used to implement D and T FFs
usually requires least amount of logic to implement
but has two inputs with increased wiring complexity
because of 1's catching, never use master/slave J-K FFs
edge-triggered varieties exist
D Flipflop:
minimizes wires, much preferred in VLSI technologies
simplest design technique
best choice for storage registers
T Flipflops:
don't really exist, constructed from J-K FFs
usually best choice for implementing counters
Preset and Clear inputs highly desirable!!

SVEC TIRUPATI
Registers
47
 Collection of Flip-Flops with similar controls

and logic
🞑 stored values somehow related
🞑 share clocks, reset, and set lines
🞑 similar logic at each stage
 Examples
🞑 storage registers
🞑 shift registers
🞑 counters
SVEC TIRUPATI
Storage Register
48
+
\clr Group of storage elements read/written as a unit
4-bit register constructed from 4 D FFsShared clock and clear lines
Q3
DS
D3 Schematic Shape
R
171
S Q2
D 9
12 Q3
D2 CLK
R 10
13 Q3
CLR 7
Q2 6
Q1 11 Q2 2
DS D3 Q1
5 3
D1 R D2 Q1
4 1
14 D1 Q0 15
D0 Q0 D0 Q0
S
D TTL 74171 Q ad D-type FF with Clear (Small numbers represent pin #s on
package)
R
clk
SVEC TIRUPATI
Kinds of Registers
49
Input/Output Variations
Selective Load Capability
Tri-state or Open Collector OutputsTrue and Complementary
Outputs
377 374
11 11 CLK
1 CLK 18 H QH 19
18 EN 17 16
G QG
17 D7 Q7 19 14
F QF
15
14 D6 Q6 16 15 13
8 E QE
12
9
13 D5 Q5 12 7 D QD 6
8 D4 Q4 9 4 C QC 5
7 D3 Q3 6 3 B QB 2
4 D2 Q2 5 A QA
3 D1 Q1 2 O1E
D0 Q0
74377 Octal D-type FFswith 74374 Octal D-type FFswith
input enable output enable
EN enabled low and lo-to-hiclock transition to OE asserted low presents FFstate to output pins;
load newdata into register otherwise high impedence
SVEC TIRUPATI
A simple shift register

50
In Q1 Q2 Q3 Q4 = Out
Q1 Q2 Q3 Q4 t0 1 0 0 0 0
In D Q D Q D Q D Q Out
t1 0 1 0 0 0
Clock Q Q Q Q t2 1 0 1 0 0
t3 1 1 0 1 0
t4 1 1 1 0 1
(a) Circuit t5 0 1 1 1 0
t6 0 0 1 1 1
t7 0 0 0 1 1
(b) A sample sequence
SVEC TIRUPATI
Parallel-access shift register
51
Parallel output
Q3 Q2 Q1 Q0
D Q D Q D Q D Q
Q Q Q Q
SVEC TIRUPATI
Serial Clock
input Shift/Load Parallel input
SVEC TIRUPATI
Shift Register I/O

52
Serial vs. Parallel Inputs Serial vs. Parallel Outputs Serial Inputs: LSI, RSI Parallel Inputs: D, C,
Shift Direction: Left vs. Right B, A
Parallel Outputs: QD, QC, QB, QAClear Signal
10 S1
9 S0 Positive Edge Triggered Devices
7
LSI 12 S1,S0 determine the shift function
6 D
194 S1 = 1, S0 = 1: Load on rising clk edge
5 C 13
4 synchronous load
B 14
3 A 15 S1 = 1, S0 = 0: shift left on rising clk edge
2 RSI LSI replaces element D
S1 = 0, S0 = 1: shift right on rising clk edge
11
CLK RSI replaces element AS1 = 0, S0 = 0:
1 hold state
CLR
Multiplexing logic on input to each FF!
74194 4-bit UniversalShift
Register
Shifters well suited for serial-to-parallel conversions,

such as terminal to computer communications
SVEC TIRUPATI
Shift Register Application: Parallel toSerial Conversion
53
Sender Receiver
190 S1 10 S1
0 9 S0
7 LSI 7 LSI
D7 6D 12 6 D 12 D7
D6 5 C 194 13 5 C 194 13 D6
D5 4B 14 4B 14D5
D4 32 A 15 3A 15 D4
RSI 2 RSI
Cloc1k1 CLK 11 CLK
1 1 CLR
Parallel CLR Parallel
Inputs Outputs
10 S1 10 S1
9 S0 9 S0
7 LSI 7 LSI
D3 6D 12 6D 12 D3
D2 5 C 194 13 5 C 194 13D2
D1 4B 14 4B 14D1
D0 15 3A 15D0
3A
2 RSI 2 RSI
11 CLK 11 CLK
1 CLR 1 CLR
Serial
transmission
SVEC TIRUPATI
Counters
54
Counters
Proceed through a well-defined sequence of states in response tocount signal
3 Bit Up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ...
3 Bit Down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ...
Binary vs. BCD vs. Gray Code Counters
A counter is a "degenerate" finite state machine/sequential circuit

where the state is the only output
Types of counters
Asynchronous vs. Synchronous Counters

SVEC TIRUPATI
Asynchronous counters
55
Ripple counter
1 T Q T Q T Q
Clock Q Q Q
State transitions are not sharp! Q0 Q1 Q2
Can lead to "spiked outputs" from

combinational logic (a) Circuit
decoding the counter's state
Clock
Q0
Q1
Q2
Count 0 1 2 3 4 5 6 7 0
A three-bit up-counter
(b) Timing diagram
SVEC TIRUPATI
Asynchronous counters, cont’d

56
1 T Q T Q T Q
Clock Q Q Q
A three-bit down-counter Q0 Q1 Q2
(a) Circuit
Clock
Q0
Q1
Q2
Count 0 7 6 5 4 3 2 1 0
(b) Timing diagram

SVEC TIRUPATI
Synchronous counter
57
 Asynchronous counters
🞑 simple, but not very fast
🞑 can build faster counters by clocking all FFs at the same time “synchronous counter”
Clock cycle Q2 Q1 Q0
Q1 changes
Synchronous counterswith T F/F
0 0 0 0 Q2 changes
T0=1
T1=Q0 1 0 0 1
2= 0 1 2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0
SVEC TIRUPATI
A four-bit synchronous up-counter

58
1 T Q T Q T Q T Q
Q0 Q1 Q2 Q3
Clock Q Q Q Q
(a) Circuit
Clock
Q0
Q1
Q2
Q3
Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
(b) Timing diagram

SVEC TIRUPATI
Enable and Clear capability

59
Enable T Q T Q T Q T Q
Clock Q Q Q Q
Clear
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A four-bit counter with D FFs
60
Enable D Q Q0
D Q Q1
D Q Q2
D Q Q3
Q
Clock Output
carry
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A counter with parallel-loadcapability
61
Enable 0
D Q 0
Q1
D0
Q
0 Q
D Q 1
D1
Q
0 Q2
D Q
D2 1
Q
0 Q3
D Q
D3
Q
SVEC TIRUPATI
Catalog Counter
62
7 Synchronous Load and Clear InputsPositive Edge Triggered

P
10 T 163 FFs Parallel Load Data from D, C, B, A
15
CLK RC
2
P, T Enable Inputs: both must be asserted toenable counting
6 D QD 11
RCO: asserted when counter enters its higheststate 1111, used for cascading counters
5 C QC 12 "Ripple Carry Output"
4 B QB 13
3 A 14
QA
9 LOADCLR
741163 Synchronous4-Bit
Upcounter
74161: similar in function, asynchronous load and reset

SVEC TIRUPATI
RCO
12 13 15 0 1 2
14
Clear Load Count Inhibit
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A modulo-6 counter withsynchronous reset
64
1 Enable
0 D0 Q0
0 D1 Q1
0 D2 Q2
Load
Clock
Clock
(a) Circuit
Clock
Q0
Q1
Q2
Count 0 1 2 3 4 5 0 1
(b) Timing diagram

SVEC TIRUPATI
A modulo-6 counter withasynchronous reset
65
1 T Q T Q T Q
Q0 Q1 Q2
Clock
Q Q Q
(a) Circuit
SVEC TIRUPATI
Clock
Q0
Q1
Q2
Count 0 1 2 3 4 5 0 1 2
(b) Timing diagram

SVEC TIRUPATI
Other types of counters

66
 Two-digit BCD counters

🞑 Two modulo-10 counters, one for each digit
🞑 Reset when the counter reaches 9
 Ring counters
🞑 One bit is one while other bits are 0
 one hot encoding
 Johnson counter
🞑 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000, …
SVEC TIRUPATI
A two-digit BCD counter
67
1 Enable
0 D0 Q0
BCD0
0 D1 Q1
0 D2 Q2
0 D3 Q3
Load
Clock Clock
Clear Enable
0 D0 Q0
BCD1
0 D1 Q1
0 D2 Q2
0 D3 Q3
Load
Clock
SVEC TIRUPATI
Ring Counter
68
Q0 Q1 Qn ? 1
Start
D Q
D Q D Q
Q Q Q
Clock
(a) An n-bit ring counter
y0 y1
y2 y3
Q0 Q1 Q2 Q3
2-to-4
decoder
w 1 w 0 En
Q1 Q0
Clock Clock
Two-bit up-counter
Start Clear
(b) A four-bit ring counter
3.3 PART A QUESTIONS & ANSWERS (2 MARKS QUESTIONS)
.No Question & Answers BL CO

1 What is a Logic gate?
1 2
s. Logic gates are the basic elements that make up a digital system.
SVEC TIRUPATI
The electronic gate is a circuit that is able to operate on a number of

binary inputs in order to perform a particular logical function.
Define half adder?
Ans. A combinational circuit that performs the addition of two bits

is called a half adder. A half adder needs two binary inputs and two 2 3
binary outputs. The input variables designate the augend and
addend bits; the output variables produce the sum and carry.
3 Define full adder?
1 3
Ans. A combinational circuit that performs the addition of three bits
is a full adder. It consists of three inputs and two outputs.
4 Define binary adder?
Ans. A binary adder is a digital circuit that produces arithmetic

1 3
sum of two binary numbers. It can be constructed with full adders
constructed in cascade, with output carry from each full adder
connected to the input carry of the next full adder in the chain.
5 Define Counter?
Ans. In digital logic and computing, a counter is a device which
stores (and sometimes displays) the number of times a
particular event or process has occurred, often in relationship 1 2
to a clock. The most common type is a sequential digital
logic circuit with an input line called the clock and multiple
output lines
6 Write logic equation of JK flipflop, D flipflop, SR flipflop and
JK flipflop.
Ans. The logic equation of TFF: Q(t+1)=T’(t)Q(t)+ T(t)Q’(t)
1 3
The logic equation of DFF: Q(t+1)=D(t)
The logic equation of TFF: Q(t+1)=R’(t)Q(t)+ S(t); S(t)R(t)=0
The logic equation of TFF: Q(t+1)=K’(t)Q(t)+ J(t)Q’(t)
7 What is the name of 74X163, 74X194?
Ans.74X163 – Synchronous presentable 4- bit binary counter,
1 2
synchronous clear.
74X194 – 4-bit bidirectional universal shift register.
8 What is IC number of 4 bit register with common clock and
Synchronous clear input?
1 2
Ans. The IC number of 4 bit register with common clock and
Synchronous clear input is 74LS95B.
9 What is the IC number of DFF,JKFF,TFF,SRFF?
Ans.. IC Number of DFF=74LS74
IC Number of JKFF=7476 1 2
IC Number of TFF=7473
IC Number of SRFF=74L71
10 fine Shift Register?
Ans.. A shift register is a type of digital circuit using a cascade of
1 2
flip flops where the output of one flip-flop is connected to the
input of the next. They share a single clock signal, which
SVEC TIRUPATI
causes the data stored in the system to shift from one location
to the next.
3.5 PART B QUESTIONS

S.No Question BL CO
1 Explain about BCD adder? 2 2
2 Explain about Half adder & Full adder? 2 2
3 Explain about Logic gates? 2 1
4 Explain about universal shift register 2 3
5 Design a 3-bit synchronous up counter using T Flip-flops. 6 3
UNIT-IV
Microprocessors-I
History of microprocessor:-
The invention of the transistor in 1947 was a significant development in the world of technology. It
could perform the function of a large component used in a computer in the early years. Shockley, Brattain and
Bardeen are credited with this invention and were awarded the Nobel prize for the same. Soon it was found
that the function this large component was easily performed by a group of transistors arranged on a single
platform. This platform, known as the integrated chip (IC), turned out to be a very crucial achievement and
brought along a revolution in the use of computers. A person named Jack Kilby of Texas Instruments was
honored with the Nobel Prize for the invention of IC, which laid the foundation on which microprocessors
were developed. At the same time, Robert Noyce of Fairchild made a parallel development in IC technology
for which he was awarded the patent.
ICs proved beyond doubt that complex functions could be integrated on a single chip with a highly
developed speed and storage capacity. Both Fairchild and Texas Instruments began the manufacture of
commercial ICs in 1961. Later, complex developments in the IC led to the addition of more complex
functions on a single chip. The stage was set for a single controlling circuit for all the computer functions.
Finally, Intel corporation's Ted Hoff and Frederico Fagin were credited with the design of the first
microprocessor.
The work on this project began with an order from a Japanese calculator company Busicom to Intel, for
building some chips for it. Hoff felt that the design could integrate a number of functions on a single chip
making it feasible for providing the required functionality. This led to the design of Intel 4004, the world's
first microprocessor. The next in line was the 8 bit 8008 microprocessor. It was developed by Intel in 1972 to
perform complex functions in harmony with the 4004.
This was the beginning of a new era in computer applications. The use of mainframes and huge computers
was scaled down to a much smaller device that was affordable to many. Earlier, their use was limited to large
organizations and universities. With the advent of microprocessors, the use of computers trickled down to the
common man. The next processor in line was Intel's 8080 with an 8 bit data bus and a 16 bit address bus.
This was amongst the most popular microprocessors of all time.
Very soon, the Motorola corporation developed its own 6800 in competition with the Intel's 8080. Fagin left
Intel and formed his own firm Zilog. It launched a new microprocessor Z80 in 1980 that was far superior to
the previous two versions. Similarly, a break off from Motorola prompted the design of 6502, a derivative of
the 6800. Such attempts continued with some modifications in the base structure.
The use of microprocessors was limited to task-based operations specifically required for company projects
such as the automobile sector. The concept of a 'personal computer' was still a distant dream for the world
and microprocessors were yet to come into personal use. The 16 bit microprocessors started becoming a
commercial sell-out in the 1980s with the first popular one being the TMS9900 of Texas Instruments.
Intel developed the 8086 which still serves as the base model for all latest advancements in the microprocessor family.
It was largely a complete processor integrating all the required features in it. 68000 by Motorola was one of the first
microprocessors to develop the concept of microcoding in its instruction set. They were further developed to 32 bit
architectures. Similarly, many players like Zilog, IBM and Apple were successful in getting their own products in the
market. However, Intel had a commanding position in the market right through the microprocessor
The 1990s saw a large scale application of microprocessors in the personal computer applications
developed by the newly formed Apple, IBM and Microsoft corporation. It witnessed a revolution in
the use of computers, which by then was a household entity.
This growth was complemented by a highly sophisticated development in the commercial use of
microprocessors. In 1993, Intel brought out its 'Pentium Processor' which is one of the most popular
processors in use till date. It was followed by a series of excellent processors of the Pentium family,
leading into the 21st century. The latest one in commercial use is the Pentium Dual Core technology
and the Xeon processor. They have opened up a whole new world of diverse applications.
Supercomputers have become common, owing to this amazing development in microprocessors.
INTRODUCTION TO MICROPROCESSOR AND MICROCOMPUTER

ARCHITECTURE:
A microprocessor is a programmable electronics chip that has computing and decision making
capabilities similar to central processing unit of a computer. Any microprocessor-based systems
having limited number of resources are called microcomputers. Nowadays, microprocessor can be
seen in almost all types of electronics devices like mobile phones, printers, washing machines etc.
Microprocessors are also used in advanced applications like radars, satellites and flights. Due to the
rapid advancements in electronic industry and large scale integration of devices results in a
significant cost reduction and increase application of microprocessors and their derivatives.
Fig.1 Microprocessor-based system
 Bit: A bit is a single binary digit.

 Word: A word refers to the basic data size or bit size that can be processed by the
arithmetic and logic unit of the processor. A 16-bit binary number is called a word in a
16-bit processor.
 Bus: A bus is a group of wires/lines that carry similar information.
 System Bus: The system bus is a group of wires/lines used for communication between
the microprocessor and peripherals.
 Memory Word: The number of bits that can be stored in a register or memory element is called a
memory word.
 Address Bus: It carries the address, which is a unique binary pattern used to identify
a memory location or an I/O port. For example, an eight bit address bus has eight lines and thus it can
address 28
= 256 different locations. The locations in hexadecimal format can be written as 00H – FFH.
 Data Bus: The data bus is used to transfer data between memory and processor or between
I/O device and processor. For example, an 8-bit processor will generally have an 8-bit data
bus and a 16-bit processor will have 16-bit data bus.
Control Bus: The control bus carry control signals, which consists of signals for selection of
memory or I/O device from the given address, direction of data transfer and synchronization of data
transfer in case of slow devices. A typical microprocessor consists of arithmetic and logic unit
(ALU) in association with control unit to process the instruction execution. Almost all the
microprocessors are based on the principle of store-program concept. In store- program concept,
programs or instructions are sequentially stored in the memory locations that are to be executed. To
do any task using a microprocessor, it is to be programmed by the user. So the programmer must
have idea about its internal resources, features and supported instructions. Each microprocessor has
a set of instructions, a list which is provided by the microprocessor manufacturer. The instruction
set of a microprocessor is provided in two forms: binary machine code and mnemonics.
Microprocessor communicates and operates in binary numbers 0 and 1. The set of instructions in the
form of binary patterns is called a machine language and it is difficult for us to understand.
Therefore, the binary patterns are given abbreviated names, called mnemonics, which forms the
assembly language. The conversion of assembly-level language into binary machine-level language
is done by using an application called assembler.
Classification of Microprocessors:
Based on their specification, application and architecture microprocessors are classified.
Based on size of data bus:
 4-bit microprocessor
2. 8085 MICROPROCESSOR ARCHITECTURE
It is a 8 bit microprocessor.
o It is manufactured with N-MOS technology.
o It has 16-bit address bus and hence can address up to 216 = 65536 bytes (64KB) memory locations
through A0-A15.
o The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0 – AD7.
o Data bus is a group of 8 lines D0 – D7.
o It supports external interrupt request.
o A 16 bit program counter (PC)
o A 16 bit stack pointer (SP)
o Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
o It requires a signal +5V power supply and operates at 3.2 MHZ single phase clock.
o It is enclosed with 40 pins DIP (Dual in line package).
The 8085 microprocessor is an 8-bit processor available as a 40-pin IC package and uses +5 V for
power. It can run at a maximum frequency of 3 MHz. Its data bus width is 8-bit and address bus
width is 16-bit, thus it can address 216 = 64 KB of memory. The internal architecture of 8085 is
shown is Fig. 2.
Fig. 2 Internal Architecture of 8085

Arithmetic and Logic Unit
The ALU performs the actual numerical and logical operations such as Addition (ADD), Subtraction
(SUB), AND, OR etc. It uses data from memory and from Accumulator to perform operations. The
results of the arithmetic and logical operations are stored in the accumulator.
Registers
The 8085 includes six registers, one accumulator and one flag register, as shown in Fig. 3. In
addition, it has two 16-bit registers: stack pointer and program counter. They are briefly described as
follows.
The 8085 has six general-purpose registers to store 8-bit data; these are identified as B, C, D, E, H
and L. they can be combined as register pairs - BC, DE and HL to perform som16-bit operations.
The programmer can use these registers to store or copy data into the register by using data copy
instructions
Fig. 3 Register organisation
Accumulator
The accumulator is an 8-bit register that is a part of ALU. This register is used to store 8-bit data and to perform
arithmetic and logical operations. The result of an operation is stored in the accumulator. The accumulator is also
identified as register A.
Flag register
The ALU includes five flip-flops, which are set or reset after an operation according to data condition of the result in
the accumulator and other registers. They are called Zero (Z), Carry (CY), Sign (S), Parity (P) and Auxiliary Carry
(AC) flags. Their bit positions in the flag register are shown in Fig. 4. The microprocessor uses these flags to test data
conditions.
For example, after an addition of two numbers, if the result in the accumulator is larger than 8-bit,
the flip-flop uses to indicate a carry by setting CY flag to 1. When an arithmetic operation results in zero, Z flag is set
to 1. The S flag is just a copy of the bit D7 of the accumulator. A negative number has a 1 in bit D7 and a positive
number has a 0 in 2’s complement representation. The AC flag is set to 1, when a carry result from bit D3 and passes
to bit D4. The P flag is set to 1, when the result in accumulator contains even number of 1s
Program Counter (PC)
This 16-bit register deals with sequencing the execution of instructions. This register is a memory
pointer. The microprocessor uses this register to sequence the execution of the instructions. The
function of the program counter is to point to the memory address from which the next byte is to be
fetched. When a byte is being fetched, the program counter is automatically incremented by one to
point to the next memory location.
Stack Pointer (SP)
The stack pointer is also a 16-bit register, used as a memory pointer. It points to a memory location
in R/W memory, called stack. The beginning of the stack is defined by loading 16-bit address in the
stack pointer.
Instruction Register/Decoder
It is an 8-bit register that temporarily stores the current instruction of a program. Latest instruction
sent here from memory prior to execution. Decoder then takes instruction and decodes or interprets
the instruction. Decoded instruction then passed to next stage.
Control Unit
Generates signals on data bus, address bus and control bus within microprocessor to carry out the
instruction, which has been decoded. Typical buses and their timing are described as follows:
 Data Bus: Data bus carries data in binary form between microprocessor and other external units such as
memory.
It is used to transmit data i.e. information, results of
arithmetic etc between memory and the microprocessor. Data bus is bidirectional in nature.
The data bus width of 8085 microprocessor is 8-bit i.e. 28 combination of binary digits and
are typically identified as D0 – D7. Thus size of the data bus determines what arithmetic can
be done. If only 8-bit wide then largest number is 11111111 (255 in decimal). Therefore,
larger numbers have to be broken down into chunks of 255. This slows microprocessor.
 Address Bus: The address bus carries addresses and is one way bus from microprocessor to
the memory or other devices. 8085 microprocessor contain 16-bit address bus and are
generally identified as A0 - A15. The higher order address lines (A8 – A15) are
unidirectional and the lower order lines (A0 – A7) are multiplexed (time- shared) with the
eight data bits (D0 – D7) and hence, they are bidirectional.
 Control Bus: Control bus are various lines which have specific functions for coordinating
and controlling microprocessor operations. The control bus carries control signals partly
unidirectional and partly bidirectional. The following control and status signals are used by
8085 processor:
I. ALE (output): Address Latch Enable is a pulse that is provided when an address
appears on the AD0 – AD7 lines, after which it becomes 0.
II. RD (active low output): The Read signal indicates that data are being read from the
selected I/O or memory device and that they are available on the data bus.
III. WR (active low output): The Write signal indicates that data on the data bus are to be
written into a selected memory or I/O location.
IV. IO/M (output): It is a signal that distinguished between a memory operation
and an I/O operation. When IO/M = 0 it is a memory operation and IO/M = 1 it is an I/O
operation.
V. S1 and S0 (output): These are status signals used to specify the type of
operation being performed; they are listed in Table 1.
Table 1 Status signals and associated operations
S1 S0 States
0 0 Halt
0 1 Write
1 0 Read
1 1 Fetch
The schematic representation of the 8085 bus structure is as shown in Fig. 5. The microprocessor
performs primarily four operations:
1. Memory Read: Reads data (or instruction) from memory.

2. Memory Write: Writes data (or instruction) into memory.
3. I/O Read: Accepts data from input device.
4. I/O Write: Sends data to output device.
The 8085 processor performs these functions using address bus, data bus and control bus as shown in Fig. 5.
Fig. 5 The 8085 bus structure

3. 8085 PIN DESCRIPTION
Properties:
 It is a 8-bit microprocessor
 Manufactured with N-MOS technology
 40 pin IC package
 It has 16-bit address bus and thus has 216 = 64 KB addressing capability.
 Operate with 3 MHz single-phase clock
 +5 V single power supply
The logic pin layout and signal groups of the 8085nmicroprocessor are shown in Fig. 6. All the
signals are classified into six groups:
 Address bus
 Data bus
 Control & status signals
 Power supply and frequency signals
 Externally initiated signals
 Serial I/O signals
Fig. 6 8085 microprocessor pin layout and signal groups
Address and Data Buses:
 A8 – A15 (output, 3-state): Most significant eight bits of memory addresses and the
eight bits of the I/O addresses. These lines enter into tri-state high impedance state
during HOLD and HALT modes.
 AD0 – AD7 (input/output, 3-state): Lower significant bits of memory addresses and the
eight bits of the I/O addresses during first clock cycle. Behaves as data bus
during third and fourth clock cycle. These lines enter into tri-state high
impedance state during HOLD and HALT modes.
Control & Status Signals:
 ALE: Address latch enable

 RD : Read control signal.
 WR : Write control signal.
 IO/M , S1 and S0 :
Status signals. Power Supply
& Clock Frequency:
 Vcc: +5 V power supply
 Vss: Ground reference
 X1, X2: A crystal having frequency of 6 MHz is connected at these two pins
 CLK: Clock output
Externally Initiated and Interrupt Signals:
 RESET IN : When the signal on this pin is low, the PC is set to 0, the buses are tri-stated and
the processor is reset.
 RESET OUT: This signal indicates that the processor is being reset. The
signal can be used to reset other devices.
 READY: When this signal is low, the processor waits for an integral number of clock cycles
until it goes high.
 HOLD: This signal indicates that a peripheral like DMA (direct memory
access) controller is requesting the use of address and data bus.
 HLDA: This signal acknowledges the HOLD request.

 INTR: Interrupt request is a general-purpose interrupt.
 INTA : This is used to acknowledge an interrupt.
 RST 7.5, RST 6.5, RST 5,5 – restart interrupt: These are vectored interrupts
and have highest priority than INTR interrupt.
 TRAP: This is a non-maskable interrupt and has the highest priority.
Serial I/O Signals:
 SID: Serial input signal. Bit on this line is loaded to D7 bit of register A using RIM
instruction.
 SOD: Serial output signal. Output SOD is set or reset by using SIM instruction.


Introduction to 8086 Microprocessor
 It is a 16-bit μp.
 8086 has a 20 bit address bus can access up to 220 memory locations (1 MB).
•It can support up to 64K I/O ports.
 It provides 14, 16 -bit registers.
 It has multiplexed address and data bus AD0- AD15 and A16 – A19.
 It requires single phase clock with 33% duty cycle to provide internal
timing. •8086 is designed to operate in two modes, Minimum and
Maximum.
 It can prefetches upto 6 instruction bytes from memory and queues them in
order to speed up instruction execution.
 It requires +5V power supply. •A 40 pin dual in line package
Minimum and Maximum Modes:

 The minimum mode is selected by applying logic 1 to the MN / MX input
pin. This is a single microprocessor configuration.
 The maximum mode is selected by applying logic 0 to the MN / MX input
pin. This is a multi micro processors configuration

Internal Architecture of 8086
 The BIU performs all bus operations such as instruction fetching, reading and writing
operands for memory and calculating the addresses of the memory operands. The
instruction bytes are transferred to the instruction queue.
 EU executes instructions from the instruction system byte queue.
 Both units operate asynchronously to give the 8086 an overlapping instruction fetch and
execution mechanism which is called as Pipelining. This results in efficient use of the
system bus and system performance.
 BIU contains Instruction queue, Segment registers, Instruction pointer, and Address
adder.
 EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag
register.
BUS INTERFACR UNIT:

 It provides a full 16 bit bidirectional data bus and 20 bit address bus.
 The bus interface unit is responsible for performing all external bus operations.
Execution Unit (EU)
 The functions of execution unit are
 To tell BIU where to fetch the instructions or data from.
 To decode the instructions
 To execute the instructions
The EU contains the control circuitry to perform various internal operations. A decoder in EU decodes the
instruction fetched memory to generate different internal or external control signals required to perform
the operation. EU has 16-bit ALU, which can perform arithmetic and logical operations on 8-bit as well
as 16-bit
Register organization or General Purpose Registers of 8086
1. AX Register: AX register is also known as accumulator register that stores operands for
arithmetic operation like divided, rotate
2. BX Register: This register is mainly used as a base register. It holds the starting base location of
a memory region within a data segment
3. CX Register: It is defined as a counter. It is primarily used in loop instruction to store loop

counter
4. DX Register: DX register is used to contain I/O port address for I/O instruction.
Segment Registers
Additional registers called segment registers generate memory address when combined with other in the
microprocessor. In 8086 microprocessor, memory is divided into 4 segments as follow
Fig 1.18 Memory Segments of 8086

Fig.Block Diagram of 8086
1. Code Segment (CS): The CS register is used for addressing a memory location in the Code Segment of
the memory, where the executable program is stored.
2. Data Segment (DS): The DS contains most data used by program. Data are accessed in the Data
Segment by an offset address or the content of other register that holds the offset address.
3. Stack Segment (SS): SS defined the area of memory used for the stack.
4. Extra Segment (ES): ES is additional data segment that is used by some of the string to hold the
destination data.
Flag Registers of 8086
Fig. Flag Register of 8086
Flags Register determines the current state of the processor. They are modified automatically by CPU
after mathematical operations, this allows to determine the type of the result, and to determine conditions
to transfer control to other parts of the program. 8086 has 9 flags and they are divided into two categories:
1. Conditional Flags
2. Control Flags
(1) Conditional Flags
Conditional flags represent result of last arithmetic or logical instruction executed. Conditional flags are
as follows:
Carry Flag (CF)
This flag indicates an overflow condition for unsigned integer arithmetic. It is also used in multiple-
precision arithmetic.
Auxiliary Flag (AF):
If an operation performed in ALU generates a carry/barrow from lower nibble (i.e. D0 D3) to upper
nibble (i.e. D4 – D7), the AF flag is set i.e. carry given by D3 bit to D4 is AF flag. This is not a general-
purpose flag, it is used internally by the processor to perform Binary to BCD conversion.
Parity Flag (PF):

This flag is used to indicate the parity of result. If lower order 8-bits of the
result contains even number of 1‟s, the Parity Flag is set and for odd number of 1‟s, the Parity Flag is
reset.
Zero Flag (ZF):
It is set; if the result of arithmetic or logical operation is zero else it is reset.
Sign Flag (SF):
In sign magnitude format the sign of number is indicated by MSB bit. If the result of operation is negative, sign flag is
set.
Overflow Flag (OF):
It occurs when signed numbers are added or subtracted. An OF indicates that the result has exceeded the capacity of
machine.
Control Flags
Control flags are set or reset deliberately to control the operations of the execution unit.
Control flags are as follows:
1. Trap Flag (TP):
a. It is used for single step control.
b. It allows user to execute one instruction of a program at a time for debugging.
c. When trap flag is set, program can be run in single step mode.
2. Interrupt Flag (IF):

a. It is an interrupt enable/disable flag.
b. If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the interrupt is
disabled.
c. It can be set by executing instruction sit and can be cleared by executing CLI instruction.
3. Direction Flag (DF):
a. It is used in string operation.
b. If it is set, string bytes are accessed from higher memory address to lower memory address.
c. When it is reset, the string bytes are accessed from lower memory address to higher memory
address.
ADDRESSING MODES OF 8086

According two the flow of instructions may be categorized as
1. Sequential Control flow instructions
2. Control transfer instructions
Sequential control flow instructions are the instructions which after execution transfer control to the next instruction
appearing immediately. The control transfer instructions transfer control to some predefined address or the address
somehow specified in the instruction after their execution.
What is addressing mode?
The different ways in which a source operand is denoted in an instruction are known as addressing mode the addressing
modes for sequential control flow instructions are
1. Immediate Addressing Mode

2. Direct Addressing mode
3. Register Addressing mode
4. Register Indirect Addressing mode
5. Indexed Addressing Mode
6. Register Relative addressing mode
7. Based indexed addressing mode
8. Relative based indexed Addressing mode
IMMEDIATE ADDRESSING MODE
The addressing mode in which the data operand is a part of the instruction itself is known as immediate addressing
mode.
Example
MOV DL, 08H
The 8-bit data (08H) given in the instruction is moved to DL (DL) 08H
MOV AX, 0A9FH
The 16-bit data (0A9FH) given in the instruction is moved to AX register (AX) 0A9FH
DIRECT ADDRESSING MODE

The addressing mode in which the effective address of the memory location at which the data operand is stored is given
in the instruction. The effective address (Offset) is just a 16-bit number written directly in the instruction.
Example:MOV BX, [1354H] MOV BL, [0400H]
The square brackets around the 1354H denote the contents of the memory location. When executed, this instruction will
copy the contents of the memory location into BX register. This addressing mode is called direct because the
displacement of the operand from the segment base is specified directly in the instruction.
REGISTER ADDRESSING MODE
The instruction will specify the name of the register which holds the data to be operated by the instruction. All registers
except IP may be used in this mode
Example:
MOV CL, DH
The content of 8-bit register DH is moved to another 8-bit register CL (CL) (DH)
REGISTER INDIRECT ADDRESSING MODE

This addressing mode allows data to be addressed at any memory location through an offset address held in any of the
following registers: BP, BX, DI & SI.
Example
MOV AX, [BX]; suppose the register BX contains 4895H, then the contents
; 4895H are moved to AX
ADD CX, {BX}
INDEXED ADDRESSING MODE
In this addressing mode, the operands offset address is found by adding the contents of SI or DI register and 8-bit/16-bit
displacements. DS and ES are the default segments for index registers SI and DI respectively. This is the special case of
the of register indirect addressing mode.
Example
MOV BX, [SI+16], ADD AL, [DI+16]
REGISTER RELATIVE ADDRESSING MODE

In register relative Addressing, BX, BP, SI and DI is used to hold the base value for effective address and a signed 8-bit
or unsigned 16-bit displacement will be specified in the instruction. In case of 8-bit displacement, it is sign extended to
16-bit before adding to the base value. When BX holds the base value of EA, 20-bit physical address is calculated from
BX and DS.When BP holds the base value of EA, BP and SS is used.
Example:
MOV AX, [BX + 08H] MOV AX, 08H [BX]
BASED INDEXED ADDRESSING MODE
In this addressing mode, the offset address of the operand is computed by summing the base register to the contents of
an Index register. The default segment registers may be ES or DS
Example:
MOV DX, [BX + SI] MOV DX, [BX][SI]
RELATIVE BASED INDEXED ADDRESSING MODE

In this addressing mode, the operands offset is computed by adding the base register contents. An Index registers
contents and 8 or 16-bit displacement.
Example
MOV AX, [BX+DI+08] ADD CX, [BX+SI+16]
CONTROL TRANSFER INSTRUCTIONS ADDRESSING MODES /BRANCH ADDRESSING MODE

The control transfer instructions transfer control to some predefined address or the address somehow specified in the
instruction after their execution
Examples : INT , CALL ,RET and JUMP instructions
The control transfer instruction the addressing modes depend upon whether destination location is within the same
segment or a different one .It also depends on the method of passing the destination address to the processor
Basically there are two methods for passing control transfer instructions
1. Intersegment addressing mode
2. Intrasegment addressing mode
INTRASEGMENT ADDRESSING MODE
If the destination location is within the same segment the mode is called intrasegment addressing mode
There are two types
1. Intrasegement direct mode
2. Intrasegment indirect mode
INTRASEGMENT DIRECT MODE:
In this mode the address to which the control is to be transferred lies within the segment in which the control transfer
instruction lies and appears directly in the instruction as an immediate displacement value .The displacement is
computed relative to the content of the instruction pointer IP.
JMP SHORT LABEL;
is a control transfer instruction following intra segment direct mode. Here, SHORT LABEL represents a signed
displacement.
INTRASEGMENT INDIRECT MODE :
In this mode the displacement to which the control is to be transferred is in the same segment in which the control
transfer instruction lies but it is passed to the instruction indirectly Here the branch address is found as the content of a
register or a memory location .
Example JMP [AX]
INTERSEGMENT ADDRESSING MODE

If the destination location is in the different segment the mode is called intersegment addressing mode
There are two types
1. Intersegment direct mode
2. Intersegment indirect mode
INTERSEGMENT DIRECT MODE:
In this mode the address to which the control is to be transferred is in a different segment this addressing mode provides
a means of branching from one code segment to another code segment. Here the CS and IP of the destination address
are specified directly in the instruction.
Example
JMP 2000H: 3000H;
INTERSEGMENT INDIRECT MODE :
In this the address to which the control is to be transferred lies in a different segment and it is passed to the instruction
indirectly .Content of memory block containing four bytes IP(LSB) ,IP(MSB),CS(LSB) and CS(MSB) sequentially The
starting address of the memory block may be referred using any of the addressing mode except immediate mode .
Example
JMP [5000H]
8086 was the first 16-bit microprocessor available in 40-pin DIP (Dual Inline Package) chip. Let us now
discuss in detail the pin configuration of a 8086 Microprocessor.
8086 Pin Diagram

Here is the pin diagram of 8086 microprocessor
Let us now discuss the signals in detail −

Power supply and frequency signals
It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its operation.
Clock signal
Clock signal is provided through Pin-19. It provides timing to the processor for operations. Its
frequency is different for different versions, i.e. 5MHz, 8MHz and 10MHz.
Address/data bus
AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data and
AD8AD15 carries higher order byte data. During the first clock cycle, it carries 16-bit address
and after that it carries 16-bit data.
Address/status bus
A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle, it carries 4-
bit address and later it carries status signals.
S7/BHE
BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer of
data using data bus D8-D15. This signal is low during the first clock cycle, thereafter it is
active.
Read($\overline{RD}$)
It is available at pin 32 and is used to read signal for Read operation.
Ready
It is available at pin 22. It is an acknowledgement signal from I/O devices that data is
transferred. It is an active high signal. When it is high, it indicates that the device is ready to
transfer data. When it is low, it indicates wait state.
RESET
It is available at pin 21 and is used to restart the execution. It causes the processor to
immediately terminate its present activity. This signal is active high for the first 4 clock cycles
to RESET the microprocessor.
INTR
It is available at pin 18. It is an interrupt request signal, which is sampled during the last clock
cycle of each instruction to determine if the processor considered this as an interrupt or not.
NMI
It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input,
which causes an interrupt request to the microprocessor.
$\overline{TEST}$
This signal is like wait state and is available at pin 23. When this signal is high, then the
processor has to wait for IDLE state, else the execution continues.
MN/$\overline{MX}$
It stands for Minimum/Maximum and is available at pin 33. It indicates what mode the
processor is to operate in; when it is high, it works in the minimum mode and vice-aversa.
INTA
It is an interrupt acknowledgement signal and id available at pin 24. When the microprocessor
receives this signal, it acknowledges the interrupt.
ALE
It stands for address enable latch and is available at pin 25. A positive pulse is generated each
time the processor begins any operation. This signal indicates the availability of a valid address
on the address/data lines.
DEN
It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver 8286. The
transreceiver is a device used to separate data from the address/data bus.
S2 S1 S0 Status
0 0 0 Interrupt acknowledgement
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive
DT/R
It stands for Data Transmit/Receive signal and is available at pin 27. It decides the direction of data flow
through the transreceiver. When it is high, data is transmitted out and vice-a-versa.
M/IO
This signal is used to distinguish between memory and I/O operations. When it is high, it indicates I/O
operation and when it is low indicates the memory operation. It is available at pin 28.
WR
It stands for write signal and is available at pin 29. It is used to write the data into the memory or the
output device depending on the status of M/IO signal.
HLDA
It stands for Hold Acknowledgement signal and is available at pin 30. This signal acknowledges the
HOLD signal.
HOLD
This signal indicates to the processor that external devices are requesting to access the address/data
buses. It is available at pin 31.
QS1 and QS0
These are queue status signals and are available at pin 24 and 25. These signals provide the status of
instruction queue. Their conditions are shown in the following table −
QS0 QS1 Status
0 0 No operation
0 1 First byte of opcode from the queue
1 0 Empty the queue
1 1 Subsequent byte from the queue
S0, S1, S2
These are the status signals that provide the status of operation, which is used by the Bus Controller
8288 to generate memory & I/O control signals. These are available at pin 26, 27, and 28. Following is
the table showing their status −
LOCK
When this signal is active, it indicates to the other processors not to ask the CPU to leave the system
bus. It is activated using the LOCK prefix on any instruction and is available at pin 29.
RQ/GT1 and RQ/GT0
These are the Request/Grant signals used by the other processors requesting the CPU to release the
system bus. When the signal is received by CPU, then it sends acknowledgment. RQ/GT 0 has a higher
priority than RQ/GT1.
8086-Minimum mode of operation
Fig 1.20 Minimum mode of 8086

Minimum Mode Interface
 Address/Data bus: 20 bits vs 8 bits multiplexed
 Status signals: A16-A19 multiplexed with status signals S3-S6 respectively
– S3 and S4 together form a 2 bit binary code that identifies which of the internal segment registers was
used to generate the physical address that was output on the address bus during the current bus cycle.
– S5 is the logic level of the internal interrupt enable flag, s6 is always logic 0.
 Control Signals
Address Latch Enable (ALE) is a pulse to logic 1 that signals external circuitry when a valid address is
on the bus. This address can be latched in external circuitry on the 1-to-0 edge of the pulse at ALE.
– IO/M line: memory or I/O transfer is selected (complement for 8086)
– DT/R line: direction of data is selected
– SSO (System Status Output) line: =1 when data is read from memory and =0 when
code is read from memory (only for 8088)
– BHE (Bank High Enable) line : =0 for most significant byte of data for 8086 and also
carries S7
– RD line: =0 when a read cycle is in progress
– WR line: =0 when a write cyle is in progress
– DEN line: (Data enable) Enables the external devices to supply data to the processor.
– Ready line: can be used to insert wait states into the bus cycle so that it is extended by a number of clock
periods
 Interrupt signals:
– INTR (Interrupt request) :=1 shows there is a service request, sampled at the final clock cycle of each
instruction acquisition cycle.
– INTA : Processor responds with two pulses going to 0 when it services the interrupt and waits for the
interrupt service number after the second pulse.
– TEST: Processor suspends operation when =1. Resumes operation when=0. Used to syncronize the
processor to external events.
– NMI (Nonmaskable interrupt) : A leading edge transition causes the processor go to the interrupt
routine after the current instruction is executed.
– RESET : =0 Starts the reset sequence.
Maximum Mode Interface
•When the 8086 is set for the maximum-mode configuration, it provides signals for implementing a
multiprocessor / coprocessor system environment.
•By multiprocessor environment we mean that one microprocessor exists in the system and that each
processor is executing its own program.
•Usually in this type of system environment, there are some system resources that are common to all
processors.
•They are called as global resources. There are also other resources that are assigned to specific
processors. These are known as local or private resources.
•Coprocessor also means that there is a second processor in the system. In this two processor does not
access the bus at the same time.
•One passes the control of the system bus to the other and then may suspend its operation. •In the
maximum-mode 8086 system, facilities are provided for implementing allocation of global resources and
passing bus control to other microprocessor or coprocessor
•8288 Bus Controller – Bus Command and Control Signals:

8086 does not directly provide all the signals that are required to control the memory, I/O and interrupt
interfaces.
•Specially the WR, M/IO, DT/R, DEN, ALE and INTA, signals are no longer produced by the 8086.
Instead it outputs three status signals S0, S1, S2 prior to the initiation of
each bus cycle. This 3- bit bus status code identifies which type of bus cycle is to follow.
•S2S1S0 are input to the external bus controller device, the bus controller generates the
appropriately timed command and control signals.
SVEC TIRUPATI
Interrupt is the method of creating a temporary halt during program execution and allows peripheral devices to access
the microprocessor. The microprocessor responds to that interrupt with an ISR (Interrupt Service Routine), which is a short
program to instruct the microprocessor on how to handle the interrupt.
The following image shows the types of interrupts we have in a 8086 microprocessor −
1.Hardware Interrupts
Hardware interrupt is caused by any peripheral device by sending a signal through a specified pin to the microprocessor.
The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable interrupt and INTR is a maskable
interrupt having lower priority. One more interrupt pin associated is INTA called interrupt acknowledge.
 (A) NMI (Non Maskable Interrupt) – It is a single pin non maskable hardware interrupt which cannot be disabled. It
is the highest priority interrupt in 8086 microprocessor. After its execution, this interrupt generates a TYPE 2
interrupt. IP is loaded from word location 00008 H and CS is loaded from the word location 0000A H.
 (B) INTR (Interrupt Request) – It provides a single interrupt request and is activated by I/O port. This interrupt can
be masked or delayed. It is a level triggered interrupt. It can receive any interrupt type, so the value of IP and CS will
change on the interrupt type received.
2.Software Interrupts – These are instructions that are inserted within the program to generate interrupts. There are 256
software interrupts in 8086 microprocessor. The instructions are of the format INT type where type ranges from 00 to FF.
The starting address ranges from 00000 H to 003FF H. These are 2 byte instructions. IP is loaded from type * 04 H and CS is
loaded from the next address give by (type * 04) + 02 H. Some important software interrupts are:
 (A) TYPE 0 corresponds to division by zero(0).
 (B) TYPE 1 is used for single step execution for debugging of program.
 (C) TYPE 2 represents NMI and is used in power failure conditions.
 (D) TYPE 3 represents a break-point interrupt.
 (E) TYPE 4 is the overflow interrupt.
SVEC TIRUPATI
4.4 MARKS QUESTION AND ANSWERES
1. What is the purpose of BIU?

Ans. The purpose of BIU is to interface 8086 with the outside world. It provides a 16-bit bidirectional data bus and 20-bit
address bus. This unit is responsible for performing external bus operations.
Functions
1. It fetches instruction from memory.
2. It reads data from port/memory.
3. It writes data into port/memory.
4. It supports instruction queuing.
5. It provides address relocation facility
2. What is the need for ALE signal ?
Ans. The ALE signal is used to demultiplex the address /data line. It is needed to latch the lower half of an address
throughout the machine cycle.
3.What is the function of accumulator?
Ans. Accumulator is a tri-state eight bit register. It is extensively used in arithmetic, logic, load and store operations, as well
as in input/output (I/O) operations. The result of arithmetic and logical operations is stored in the register A. Hence it is also
identified as accumulator.
4. What is memory segmentation?
Ans. Memory segmentation is dividing the linear memory space into “chunks” called segments. 8086 segmented memory
system has four segments Code segment, Data segment, Extra segment, and Stack segment.
5. What is an interrupt? How the interrupts are classified
Ans. Interrupt is a signal send by an external device to the processor so as to request the processor to perform a particular a
task or work. The interrupts are classified into hardware and software interrupts, vectored and non-vectored interrupts and
maskable and nonmaskable interrupts.
6. Write the special functions carried by the general purpose registers of 8086.
Ans.The special functions carried by the registers of 8086 are the following.
1. AX 16-bit Accumulator
2. AL 8-bit Accumulator
3. BX Base Register
4. CX Count Register
5. DX .Data Register
7. How the physical address for fetching the next instruction to be executed, is obtained in 8086?
Ans: The physical address is obtained by appending four zeros to the content present in CS register and then adding the
content of IP register with the above value .
For example, assuming the content of CS = 1200 H
IP = 0345 H
CS= 0001 0010 0000 0000 0000 0000 0011 0100 0101
0001 0010 0011 0100 0101 – Physical address=12345 H
8. Explain how a microprocessor services an interrupt request?
Ans: When the processor recognizes an interrupt, it saves the processor status in stack. Then it call and execute an interrupt
service routine (ISR). At the end of ISR, it restores the processor status and the program control is transferred to main
program
9. What are the features of 8086 microprocessor?
Ans. It is a 16-bit microprocessor It operates in both single processor and multi processor configuration to achieve high
performance levels It is a single chip IC implemented with approximately 29000 transistors. It has 20 address lines therefore
can address 220 address locations
10. What are the advantages of memory segmentation?
Ans. Allows the memory capacity to be 1MB although actual addresses to be handled are of 16-bit size. Allows the placing
of code, data and stack portions of the same program in different parts (segments) of the memory, for data and code
protection.
11. What is microprocessor?
A microprocessor is a multipurpose, programmable, clock-driven , register-based electronic device that reads binary
information from a storage device called memory, accepts binary data as input and processes data according to those
instructions, and provides result as output.
12. What is Accumulator?
SVEC TIRUPATI
The Accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU). This register is used to store 8-bit data
and to perform arithmetic and logical operations. The result of an operation is stored in the accumulator. The accumulator is
also identified as register A.
13. What is stack?
The stack is a group of memory locations in the R/W memory that is used for temporary storage of binary information
during the execution of a program
14. Define addressing mode.
Addressing mode is used to specify the way in which the address of the operand is specified within the instruction
15. Define instruction cycle.
It is defined as the time required to complete the execution of an instruction.
16. What is a subroutine program?
A subroutine is a group of instructions written separately from the main program to perform a function that occurs
repeatedly in the main program. Thus subroutines avoid the repetition of same set of instructions in the main program.
17. What are the different types of addressing modes of 8086 instruction set? The different addressing modes are:
i. Immediate
ii. Direct
iii. Register
iv.Register indirect
v. Indexed
vi.Register relative
vii.Based indexed
viii. Relative based indexed
18. What are the different types of instructions in 8086 microprocessor? The different types of instructions in 8086
microprocessor are:
i. Data copy / transfer instructions
ii. Arithmetic and logical instructions
iii. Branch instructions
iv. Loop instruction
v. Machine control instruction
vi.Flag manipulation instruction
vii.Shift and rotate instruction
19. What is assembly level programming?
A program called assembler is used to convert the mnemonics of instruction and data into their equivalent object code
modules. The object code modules are further converted into executable code using linker and loader programs. This type of
programming is called assembly level programming.
20. What is a stack?
Stack is a top-down data structure, whose elements are accessed using a pointer that is implemented using the SS and SP
registers. It is a LIFO data segment.
SVEC TIRUPATI
S.N Question BL CO
o
(i)Explain briefly about 8085 microprocessor

(ii) Explain briefly about 8086 microprocessor BL2 CO3
1
(i)Explain about Flag registers of 8086 and pin diagram of 8086
(ii)Explain about Addressing modes of 8086 microprocessor
2 BL2 CO3
(i)Explain minimum mode and maximum mode operation of 8086
microprocessor
(ii)Explain interrupts in 8086 BL2 CO3
3
SVEC TIRUPATI
UNIT-V
MICROPROCESSOR-II
Microprocessor - 8086 Instruction Sets

The 8086 microprocessor supports 8 types of instructions −
 Data Transfer Instructions

 Arithmetic Instructions
 Bit Manipulation Instructions
 String Instructions
 Program Execution Transfer Instructions (Branch & Loop Instructions)
 Processor Control Instructions
 Iteration Control Instructions
 Interrupt Instructions
Let us now discuss these instruction sets in detail.
Data Transfer Instructions

These instructions are used to transfer the data from the source operand to the destination operand. Following are the
list of instructions under this group −
Instruction to transfer a word
 MOV − Used to copy the byte or word from the provided source to the provided destination.
 PPUSH − Used to put a word at the top of the stack.
 POP − Used to get a word from the top of the stack to the provided location.
 PUSHA − Used to put all the registers into the stack.
 POPA − Used to get words from the stack to all registers.
 XCHG − Used to exchange the data from two locations.
 XLAT − Used to translate a byte in AL using a table in the memory.
Instructions for input and output port transfer
 IN − Used to read a byte or word from the provided port to the accumulator.
 OUT − Used to send out a byte or word from the accumulator to the provided port.
Instructions to transfer the address
 LEA − Used to load the address of operand into the provided register.
 LDS − Used to load DS register and other provided register from the memory
 LES − Used to load ES register and other provided register from the memory.
Instructions to transfer flag registers
 LAHF − Used to load AH with the low byte of the flag register.
SVEC TIRUPATI
 SAHF − Used to store AH register to low byte of the flag register.
 PUSHF − Used to copy the flag register at the top of the stack.
 POPF − Used to copy a word at the top of the stack to the flag register.
Arithmetic Instructions
These instructions are used to perform arithmetic operations like addition, subtraction, multiplication, division, etc.
Following is the list of instructions under this group −
Instructions to perform addition
 ADD − Used to add the provided byte to byte/word to word.

 ADC − Used to add with carry.
 INC − Used to increment the provided byte/word by 1.
 AAA − Used to adjust ASCII after addition.
 DAA − Used to adjust the decimal after the addition/subtraction operation.
Instructions to perform subtraction
 SUB − Used to subtract the byte from byte/word from word.

 SBB − Used to perform subtraction with borrow.
 DEC − Used to decrement the provided byte/word by 1.
 NPG − Used to negate each bit of the provided byte/word and add 1/2’s complement.
 CMP − Used to compare 2 provided byte/word.
 AAS − Used to adjust ASCII codes after subtraction.
 DAS − Used to adjust decimal after subtraction.
Instruction to perform multiplication
 MUL − Used to multiply unsigned byte by byte/word by word.

 IMUL − Used to multiply signed byte by byte/word by word.
 AAM − Used to adjust ASCII codes after multiplication.
Instructions to perform division
 DIV − Used to divide the unsigned word by byte or unsigned double word by word.
 IDIV − Used to divide the signed word by byte or signed double word by word.
 AAD − Used to adjust ASCII codes after division.
 CBW − Used to fill the upper byte of the word with the copies of sign bit of the lower byte.
 CWD − Used to fill the upper word of the double word with the sign bit of the lower word.
Bit Manipulation Instructions

These instructions are used to perform operations where data bits are involved, i.e. operations like logical, shift, etc.
Instructions to perform logical operation

SVEC TIRUPATI
 NOT − Used to invert each bit of a byte or word.
 AND − Used for adding each bit in a byte/word with the corresponding bit in another byte/word.
 OR − Used to multiply each bit in a byte/word with the corresponding bit in another byte/word.
 XOR − Used to perform Exclusive-OR operation over each bit in a byte/word with the corresponding bit in
another byte/word.
 TEST − Used to add operands to update flags, without affecting operands.
Instructions to perform shift operations
 SHL/SAL − Used to shift bits of a byte/word towards left and put zero(S) in LSBs.
 SHR − Used to shift bits of a byte/word towards the right and put zero(S) in MSBs.
 SAR − Used to shift bits of a byte/word towards the right and copy the old MSB into the new MSB.
Instructions to perform rotate operations
 ROL − Used to rotate bits of byte/word towards the left, i.e. MSB to LSB and to Carry Flag [CF].
 ROR − Used to rotate bits of byte/word towards the right, i.e. LSB to MSB and to Carry Flag [CF].
 RCR − Used to rotate bits of byte/word towards the right, i.e. LSB to CF and CF to MSB.
 RCL − Used to rotate bits of byte/word towards the left, i.e. MSB to CF and CF to LSB.
String Instructions
String is a group of bytes/words and their memory is always allocated in a sequential order.
 REP − Used to repeat the given instruction till CX ≠ 0.
 REPE/REPZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.
 REPNE/REPNZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.
 MOVS/MOVSB/MOVSW − Used to move the byte/word from one string to another.
 COMS/COMPSB/COMPSW − Used to compare two string bytes/words.
 INS/INSB/INSW − Used as an input string/byte/word from the I/O port to the provided memory location.
 OUTS/OUTSB/OUTSW − Used as an output string/byte/word from the provided memory location to the I/O
port.
 SCAS/SCASB/SCASW − Used to scan a string and compare its byte with a byte in AL or string word with a
word in AX.
 LODS/LODSB/LODSW − Used to store the string byte into AL or string word into AX.
Program Execution Transfer Instructions (Branch and Loop Instructions)

These instructions are used to transfer/branch the instructions during an execution. It includes the following
instructions −
Instructions to transfer the instruction during an execution without any condition −
 CALL − Used to call a procedure and save their return address to the stack.
 RET − Used to return from the procedure to the main program.
 JMP − Used to jump to the provided address to proceed to the next instruction.
Instructions to transfer the instruction during an execution with some conditions −
 JA/JNBE − Used to jump if above/not below/equal instruction satisfies.
SVEC TIRUPATI
 JAE/JNB − Used to jump if above/not below instruction satisfies.
 JBE/JNA − Used to jump if below/equal/ not above instruction satisfies.
 JC − Used to jump if carry flag CF = 1
 JE/JZ − Used to jump if equal/zero flag ZF = 1
 JG/JNLE − Used to jump if greater/not less than/equal instruction satisfies.
 JGE/JNL − Used to jump if greater than/equal/not less than instruction satisfies.
 JL/JNGE − Used to jump if less than/not greater than/equal instruction satisfies.
 JLE/JNG − Used to jump if less than/equal/if not greater than instruction satisfies.
 JNC − Used to jump if no carry flag (CF = 0)
 JNE/JNZ − Used to jump if not equal/zero flag ZF = 0
 JNO − Used to jump if no overflow flag OF = 0
 JNP/JPO − Used to jump if not parity/parity odd PF = 0
 JNS − Used to jump if not sign SF = 0
 JO − Used to jump if overflow flag OF = 1
 JP/JPE − Used to jump if parity/parity even PF = 1
 JS − Used to jump if sign flag SF = 1
Processor Control Instructions

These instructions are used to control the processor action by setting/resetting the flag values.
Following are the instructions under this group −
 STC − Used to set carry flag CF to 1
 CLC − Used to clear/reset carry flag CF to 0
 CMC − Used to put complement at the state of carry flag CF.
 STD − Used to set the direction flag DF to 1
 CLD − Used to clear/reset the direction flag DF to 0
 STI − Used to set the interrupt enable flag to 1, i.e., enable INTR input.
 CLI − Used to clear the interrupt enable flag to 0, i.e., disable INTR input.
Iteration Control Instructions

These instructions are used to execute the given instructions for number of times. Following is the list of instructions
under this group −
 LOOP − Used to loop a group of instructions until the condition satisfies, i.e., CX = 0
 LOOPE/LOOPZ − Used to loop a group of instructions till it satisfies ZF = 1 & CX = 0
 LOOPNE/LOOPNZ − Used to loop a group of instructions till it satisfies ZF = 0 & CX = 0
 JCXZ − Used to jump to the provided address if CX = 0
Interrupt Instructions
These instructions are used to call the interrupt during program execution.
 INT − Used to interrupt the program during execution and calling service specified.
 INTO − Used to interrupt the program during execution if OF = 1
SVEC TIRUPATI
 IRET − Used to return from interrupt service to the main program
ASSEMBLER DIRECTIVES
Assembler directives are the Instructions to the Assembler, linker and loader
regarding the program being executed. also called ‘pseudo instructions. Control
the generation of machine codes and organization of the program; but no machine
codes are generated for assembler directives.
They are used to
› specify the start and end of a program
› attach value to variables
› allocate storage locations to input/ output data
› define start and end of segments, procedures, macros etc..
ASSUME
Used to tell the assembler the name of the logical segment it should use for
a specified segment. You must tell the assembler that what to assume for
any segment you use in the program.
Example
ASSUME: CODE
Tells the assembler that the instructions for the program are in segment named CODE.
DB – Defined Byte
Used to declare a byte type variable or to set aside one or more locations of type byte in
memory.
Example
PRICES DB 49H, 98H, 29H:
Declare array of 3 bytes named PRICES and initialize 3 bytes as shown.
DD – Define Double Word
Used to declare a variable of type doubleword or to reserve a memory location which can be
accessed as doubleword.
DQ – Define Quadword
Used to tell the assembler to declare the variable as 4 words of storage in memory.
DT – Define Ten Bytes
Used to tell the assembler to declare the variable which is 10 bytes in length or reserve
10 bytes of storage in memory.
DW – Define Word
Used to tell the assembler to define a variable type as word or reserve word in memory.
DUP: used to initialize several locations and to assign values to location
END – End the Program
To tell the assembler to stop fetching the instruction and end the program execution.
ENDP – it is used to end the procedure.
SVEC TIRUPATI
ENDS – used to end the segment.
EQU – EQUATE
Used to give name to some value or symbol.
EVEN – Align On Even Memory Address
Tells the assembler to increment the location counter to the next even address if it is not
already at an even address.
EXTRN
Used to tell the assembler that the name or labels following the directive are in some other assembly
module.
GLOBAL – Declares Symbols As Public Or Extrn
Used to make the symbol available to other modules.It can be used in place of
EXTRN or PUBLIC keyword.
GROUP – Group related segment
Used to tell the assembler to group the logical segments named after the directive into one
logical segment. This allows the content of all the segments to be accessed from the same
group.
INCLUDE – include source code from file

Used to tell the assembler to insert a block of source code from the named file into the current
source module. This shortens the source code.
LABEL
Used to give the name to the current value in the location counter. The LABEL
directive must be followed by a term which specifies the type you want associated with
that name.
LENGTH
Used to determine the number of items in some data such as string or array.
NAME
Used to give a specific name to a module when the programs consisting of
several modules.
OFFSET
It is an operator which tells the assembler to determine the offset or displacement of
named data item or procedure from the start of the segment which contains it.
ORG – Originate
Tells the assembler to set the location counter value.
Example, ORG 7000H sets the location counter value to point to 7000H location
in memory.
$ is often used to symbolically represent the value of the location counter. It is used
with ORG to tell the assembler to change the location according to the current value in
the location counter. E.g. ORG $+100.
Difference between Macro and Procedure
Assembly language is a common intermediate level programming

language which is used for microprocessor programming. This
macro and procedure are two concepts in assembly by which
modular programming is implemented. So now let’s understand
how macro and procedure are different from each other.
SVEC TIRUPATI
1. Macro :
Macro is a set of instruction and the programmer can use it
anywhere in the program by using its name. It is mainly used to
achieve modular programming. So same set of instructions can be
used multiple times when ever required by the help of macro.
Wherever macro’s identifier is used, it is replaced by the actual
defined instructions during compilation thereby no calling and
return occurs.
Syntax of macro :
%macro macro_name number_of_parameters
<macro body>
%endmacro
2. Procedure :
Procedures are also like macro, but they are used for large set of
instruction when macro is useful for small set of instructions. It
contains a set of instructions which performs a specific task. It
contains three main parts i.e Procedure name to identify the
procedure, procedure body which contains set of instructions, and
RET statement which denotes return statement. Unlike macros,
procedures follow call-return method thereby achieving true
modularity.
Syntax of Procedure :
SVEC TIRUPATI
procedure_name :
procedure body
….......................
RET
To call a procedure
CALL procedure_name
After execution of procedure control passes to the calling

procedure using RET statement.
S.No. MACRO PROCEDURE

Procedure contains a set of
Macro definition contains a set instructions which can be
of instruction to support called repetitively which can
01. modular programming. perform a specific task.
It is used for small set of It is used for large set of
instructions mostly less than instructions mostly more than
02. ten instructions. ten instructions.
In case of macro memory In case of procedure memory
03. requirement is high. requirement is less.
CALL and RET CALL and RET
instruction/statements are not instruction/statements are
04. required in macro. required in procedure.
Assembler directive MACRO Assembler directive PROC is
is used to define macro and used to define procedure and
assembler directive ENDM is assembler directive ENDP is
used to indicate the body is used to indicate the body is
05. over. over.
Execution time of macro is Execution time of procedures
less than it executes faster is high as it executes slower
06. than procedure. than macro.
Here machine code is created Here machine code is created
07. multiple times as each time only once, it is generated only
SVEC TIRUPATI
machine code is generated once when the procedure is
when macro is called. defined.
In a macro parameter is In a procedure parameters are
passed as part of statement passed in registers and
08. that calls macro. memory locations of stack.
Overhead time takes place
Overhead time does not take during calling procedure and
place as there is no calling returning control to calling
09. and returning. program.
SVEC TIRUPATI
Introduction to Microcontrollers:
 Overview of 8051 Microcontroller

 Architecture
 I/O Ports
 Memory Organization
 Addressing Modes and Instruction set of 8051
 Simple Programs
 memory interfacing to 8051
The necessary tools for a microprocessor/controller:
• CPU: Central Processing Unit

• I/O: Input /Output
• Bus: Address bus & Data bus
• Memory: RAM & ROM
• Timer
• Interrupt
• Serial Port
• Parallel Port
•
Microprocessors:
General-purpose microprocessor :
• CPU for Computers

• No RAM, ROM, I/O on CPU chip itself
• Example：Intel’s x86, Motorola’s 680x0
SVEC TIRUPATI
Microcontroller :
• A smaller computer
• On-chip RAM, ROM, I/O ports...
• Example：Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16X
Microprocessor vs.
Microcontroller :
SVEC TIRUPATI
8051 Microcontroller Hardware:

The 8051 microcontroller actually includes a whole family of microcontrollers that have
numbers ranging from 8031 to 8751 and are available in N-Channel Metal Oxide Silicon
(NMOS) and Complementary Metal Oxide Silicon (CMOS) construction in a variety of housed
in a 40-pin DIP, and direct the investigation of a particular type to the data books.
The block diagram of the 8051 in Figure 2. la shows all of the features unique to
microcontrollers:
0. Internal ROM and RAM
1. I/O ports with programmable pins
2. Timers and counters
3. Serial data communication
The figure also shows the usual CPU components: program counter, ALU,
working registers, and clock circuits.'
SVEC TIRUPATI
INTRODUCTION TO 8051:
The Intel MCS-51 (commonly referred to as 8051) is a Harvard architecture, single chip
microcontroller (μC) series which was developed by Intel in 1980 for use in embedded
systems. The 8051 architecture provides many functions (CPU, RAM, ROM, I/O, interrupt
logic, timer,etc.) in a single package Features of 8051:  8-bit ALU, Accumulator, 8-bit
Registers and 8-bit data bus; hence it is an 8-bit microcontroller
 16-bit program counter
 8-bit Processor Status Word(PSW)  8-bit Stack Pointer
 Internal RAM of128bytes

 On chip ROM is4KB
 Special Function Registers (SFRs) of 128bytes
 32 I/O pins arranged as four 8-bit ports (P0 -P3)
 Two 16-bit timer/counters : T0 andT1
 Two external and three internal vectored interrupts
 Full duplex UART (serialport)
INTERNAL ARCHITECTURE OF 8051 MICROCONTROLLER

The Internal architecture is shown in Figure 4.1.4 and the various Registers and
SVEC TIRUPATI
units are described below.
Accumulator (Acc):
•Operand register
• Implicit or specified in the instruction
•Has an address in on chip SFR bank
B Register:
Used to store one of the operands for multiplication and division, otherwise,
scratch pad considered as a SFR.
Stack Pointer (SP):
8 bit wide register. Incremented before data is stored on to the stack using PUSH
or CALL instructions. Stack defined anywhere on the 128 byte RAM.
Data Pointer (DPTR):
16 bit register contains DPH and DPL Pointer to external RAM address. DPH and
DPL allotted separate addresses in SFR bank
Port 0 To 3 Latches & Drivers:
Each I/O port allotted a latch and a driver Latches allotted address in SFR. User
can communicate via these ports P0, P1, P2, and P3.
Serial Data Buffer:
Internally had TWO independent registers, TRANSMIT buffer (parallel in serial
out – PISO) and RECEIVE buffer (serial in parallel out –SIPO) identified by SBUF and
allotted an address in SFR.
Program Status Word (PSW):

Set of flags contains status information as detailed below in the Figure 4.1.3.
SVEC TIRUPATI
Timer
Registers: for Timer0 (16 bit register – TL0 & TH0) and for Timer1 (16 bitregister – TL1 &
TH1) four addresses allotted in SFR
Control Registers: Control registers are IP, IE, TMOD, TCON, SCON, and PCON.
timers/counters
These registers contain control and status information for interrupts,
and serial port. Allotted separate address in SFR.
Timing and Control Unit: This unit derives necessary timing
and control signals for internal circuit and external system bus.
Oscillator: generates basic timing clock signal using crystal
oscillator.
Instruction Register: Decodes the opcode and gives

information to timing and control unit.
EPROM & program address Register: provide on chip

EPROM and mechanism to
SVEC TIRUPATI
address it. All versions don’t have EPROM.
Ram & Ram Address Register: provide internal 128 bytes
RAM and a mechanism to address internally
ALU: Performs 8 bit arithmetic and logical operations over the
operands held by TEMP1 and TEMP 2.
User cannot access temporary registers. SFR Register Bank: set
of special function registers address range: 80 H to FF H.
Interrupt, serial port and timer units control and perform specific
functions under the control of timing and control unit.
8051 Addressing Modes

An Addressing Mode is a way to locate a target Data, which is also called as Operand. The
8051 Family of Microcontrollers allows five types of Addressing Modes for addressing the
Operands. They are
 Immediate Addressing
 Register Addressing
 Direct Addressing
 Register – Indirect Addressing
 Indexed Addressing
Immediate Addressing
In Immediate Addressing mode, the operand, which follows the Opcode, is a constant data of
either 8 or 16 bits. The name Immediate Addressing came from the fact that the constant data
to be stored in the memory immediately follows the Opcode.
The constant value to be stored is specified in the instruction itself rather than taking from a
register. The destination register to which the constant data must be copied should be the
same size as the operand mentioned in the instruction.
Example: MOV A, #030H
Here, the Accumulator is loaded with 30 (hexadecimal). The # in the

operand indicates that it is a data and not the address of a Register.
SVEC TIRUPATI
Immediate Addressing is very fast as the data to be loaded is given
in the instruction itself.
Register Addressing
In the 8051 Microcontroller Memory Organization Tutorial, we have
seen the organization of RAM and four banks of Working Registers
with eight Registers in each bank.
In Register Addressing mode, one of the eight registers (R0 – R7) is

specified as Operand in the Instruction.
It is important to select the appropriate Bank with the help of PSW

Register. Let us see a example of Register Addressing assuming
that Bank0 is selected.
Example: MOV A, R5
Here, the 8-bit content of the Register R5 of Bank0 is moved to the

Accumulator.
Direct Addressing
In Direct Addressing Mode, the address of the data is specified as
the Operand in the instruction. Using Direct Addressing Mode, we
can access any register or on-chip variable. This includes general
purpose RAM, SFRs, I/O Ports, Control registers.
SVEC TIRUPATI
Example: MOV A, 47H
Here, the data in the RAM location 47H is moved to the

Accumulator.
Register Indirect Addressing

In the Indirect Addressing Mode or Register Indirect Addressing
Mode, the address of the Operand is specified as the content of a
Register. This will be clearer with an example.
Example: MOV A, @R1
The @ symbol indicates that the addressing mode is indirect. If the

contents of R1 is 56H, for example, then the operand is in the
internal RAM location 56H. If the contents of the RAM location 56H
is 24H, then 24H is moved into accumulator.
Only R0 and R1 are allowed in Indirect Addressing Mode. These

register in the indirect addressing mode are called as Pointer
registers.
Indexed Addressing Mode

With Indexed Addressing Mode, the effective address of the
Operand is the sum of a base register and an offset register. The
Base Register can be either Data Pointer (DPTR) or Program
Counter (PC) while the Offset register is the Accumulator (A).
In Indexed Addressing Mode, only MOVC and JMP instructions can

be used. Indexed Addressing Mode is useful when retrieving data
from look-up tables.
SVEC TIRUPATI
Example: MOVC A, @A+DPTR
Here, the address for the operand is the sum of contents of DPTR
and Accumulator.
NOTE: Some authors and textbooks add few other Addressing

Modes like Absolute Addressing Mode, Relative Addressing Mode
and Long Addressing Mode.
Also read: 8051 MICROCONTROLLER ARCHITECTURE.Types

of Instructions in 8051 Microcontroller
Instruction Set
Introduction to 8051 Microcontroller Instruction Set
DATA ARITHMETIC LOGICAL BOOLEAN PROGRAM

TRANSFER BRANCHING
MOV ADD ANL CLR LJMP
MOVC ADDC ORL SETB AJMP
MOVX SUBB XRL MOV SJMP
PUSH INC CLR JC JZ
POP DEC CPL JNC JNZ
XCH MUL RL JB CJNE
XCHD DIV RLC JNB DJNZ
DA A RR JBC NOP
RRC ANL LCALL
SWAP ORL ACALL
CPL RET
RETI
JMP
Before seeing the types of instructions, let us see the structure of
the 8051 Microcontroller Instruction. An 8051 Instruction consists of
an Opcode (short of Operation – Code) followed by Operand(s) of
size Zero Byte, One Byte or Two Bytes.
The Op-Code part of the instruction contains the Mnemonic, which

specifies the type of operation to be performed. All Mnemonics or
the Opcode part of the instruction are of One Byte size.
Coming to the Operand part of the instruction, it defines the data

being processed by the instructions. The operand can be any of the
following:
 No Operand
 Data value
 I/O Port
 Memory Location
 CPU register
There can multiple operands and the format of instruction is as

follows:
MNEMONIC DESTINATION OPERAND, SOURCE OPERAND

A simple instruction consists of just the opcode. Other instructions
may include one or more operands. Instruction can be one-byte
instruction, which contains only opcode, or two-byte instructions,
where the second byte is the operand or three byte instructions,
where the operand makes up the second and third byte.
Based on the operation they perform, all the instructions in the 8051
Microcontroller Instruction Set are divided into five groups. They
are:
 Data Transfer Instructions

 Arithmetic Instructions
 Logical Instructions
 Boolean or Bit Manipulation Instructions
 Program Branching Instructions
We will now see about these instructions briefly.
Data Transfer Instructions
The Data Transfer Instructions are associated with transfer of data

between registers or external program memory or external data
memory. The Mnemonics associated with Data Transfer are given
below.
 MOV
 MOVC
 MOVX
 PUSH
 POP
 XCH
 XCHD
Mnemonic Description
MOV Move Data
MOVC Move Code
MOCX Move External Data
PUSH Move Data to Stack
POP Copy Data from Stack
XCH Exchange Data between two Registers
XCHD Exchange Lower Order Data between two

Registers
Arithmetic Instructions
Using Arithmetic Instructions, you can perform

addition, subtraction, multiplication and division. The
arithmetic instructions also include increment by one,
decrement by one and a special instruction called
Decimal Adjust Accumulator.The Mnemonics
associated with the Arithmetic Instructions of the 8051
Microcontroller Instruction Set are:
 ADD
 ADDC
 SUBB
 INC
 DEC
 MUL
 DIV
 DA A
Logical Instructions
The next group of instructions are the Logical Instructions,
which perform logical operations like AND, OR, XOR, NOT,
Rotate, Clear and Swap. Logical Instruction are performed
on Bytes of data on a bit-by-bit basis.
Mnemonics
ADD Addition without Carry associated with
ADDC Addition with Carry Logical
SUBB Subtract with Carry Instructions are
INC Increment by 1
as follows:
DEC Decrement by 1
MUL Multiply
DIV Divide
DA A Decimal Adjust the Accumulator (A Register)
ANL Logical AND
ORL Logical OR
XRL Ex-OR
CLR Clear Register
CPL Complement the
Register
RL Rotate a Byte to Left
RLC Rotate a Byte and Carry
Bit to Left
RR Rotate a Byte to Right
RRC Rotate a Byte and Carry
Bit to Right
SWAP Exchange lower and
higher nibbles in a Byte
 ANL
 ORL
 XRL
 CLR
 RLC
 RR
 RRC
 SWAP
 CPL
 RL
Boolean or Bit Manipulation Instructions

As the name suggests, Boolean or Bit Manipulation
Instructions deal with bit variables. We know that there
is a special bit-addressable area in the RAM and some
of the Special Function Registers (SFRs) are also bit
addressable.
The Mnemonics corresponding to the Boolean or Bit

Manipulation instructions are
 CLR
 SETB
 MOV
 JC
 JNC
 JB
 JNB
 JBC
 ANL
 ORL
 CPL
CLR Clear a Bit (Reset to 0)
SETB Set a Bit (Set to 1)
MOV Move a Bit
JC Jump if Carry Flag is Set
JNC Jump if Carry Flag is Not Set
JB Jump if specified Bit is Set
JNB Jump if specified Bit is Not Set
JBC Jump if specified Bit is Set and also
clear the Bit
ANL Bitwise AND
ORL Bitwise OR
CPL Complement the Bit
Program Branching Instructions

The last group of instructions in the 8051 Microcontroller
Instruction Set are the Program Branching Instructions.
These instructions control the flow of program logic. The
mnemonics of the Program Branching Instructions are as
follows.
 LJMP
 AJMP
 SJMP
 JZ
 JNZ
 CJNE
 DJNZ
 NOP, LCALL
 ACALL
 RET
 RETI
 JM
nemonic Description
LJMP Long Jump (Unconditional)
AJMP Absolute Jump (Unconditional)
SJMP Short Jump (Unconditional)
JZ Jump if A is equal to 0
JNZ Jump if A is not equal to 0
CJNE Compare and Jump if Not Equal
DJNZ Decrement and Jump if Not Zero
NOP No Operation
LCALL Long Call to Subroutine
ACALL Absolute Call to Subroutine (Unconditional)
RET Return from Subroutine
RETI Return from Interrupt
JMP Jump to an Address (Unconditional)
5.4 MARKS QUESTION AND ANSWERS
1. What are the special function register?
The special function register are stack pointer, index pointer (DPL and DPH), I/O port addresses, status(PSW) and
accumulator.
2. What are the uses of accumulator register?
The accumulator registers (A and B at addresses OEOh and OFOh, respectively) are used to store temporary values
and the results of arithmetic operations.
3. What is PSW?
Program status word (PSW) is the set of flags that contains the status information and is considered as one of the
special function register.
4.What is stack pointer (sp)?
Stack pointer (SP) is a 8 bit wide register and is incremented before the data is stored into the stack using PUSH or
CALL instructions.
It contains 8-bit stack top address. It is defined anywhere in the on-chip 128-byte RAM. After reset, the SP register is
initialized to 07.
After each write to stack operation, the 8-bit contents of the operand are stored onto the stack, after incrementing the
SP register by one.
It is not a top-down data structure. It is allotted an address in the special function register bank.
5. What is data pointer (DTPR)?
It is a 16-bit register that contains a higher byte (DPH) and lower byte (DPL) of a 16-bit external data RAM address.
It is accessed as a 16-bit register or two 8-bit registers. It has been allotted two addresses in the special function register
bank, for its two bytes DPH and DPL.
6. Why oscillator circuit is used?
Oscillator circuit is used to generate the basic timing clock signal for the operation of the circuit using crystal
oscillator.
7. What is the purpose of using instruction register?
Instruction register is used for the purpose of decoding the opcode of an instruction to be executed and gives
information to the timing and control unit generating necessary signals for the execution of the instruction.
8. Give the purpose of ale/prog signal.
ALE/PROG is an address latch enable output pulse and indicates that valid address bits available on the respective
pins.
The ALE pulses are emitted at a rate of one-sixth of the oscillator frequency. The signal is valid only for external
memory accesses.
It may be used for external timing or clockwise purpose. One ALE pulse is skipped during each access to external data
memory.
9. Explain the two power saving mode of operation.
The two power saving modes of operation are:
I. Idle mode:
In this mode, the oscillator continues to run and the interrupt, serial port and timer blocks are active, but the clock to
the CPU is disabled. The CPU status is preserved. This mode can be terminated with a hardware interrupt or hardware
reset signal. After this, the CPU resumes program execution from where it left off.
II. Power down mode:
In this mode, the on-chip oscillator is stopped. All the functions of the controller are held maintaining the contents of
RAM. The only way to terminate this mode is hardware reset. The reset redefines all the SFRs but the RAM contents
are left unchanged.
10. Differentiate between program memory and data memory.
i. In stores the programs to be executed.
ii. It stores only program code which is to be executed and thus it need not be written, so it is implemented using
EPROM It stores the data, line intermediate results, variables and constants required for the execution of the program.
The data memory may be read from or written to and thus it is implemented using RAM.
11.What are addressing modes?
The various ways of accessing data are called addressing modes.
12. Give the addressing modes of 8051?
There are six addressing modes in 8051.They are
Direct addressing Indirect addressing Register instruction
Register specific (register implicit)
Immediate mode Indexed addressing
13. What is direct addressing mode?
The operands are specified using the 8-bit address field, in the instruction format. Only internal data Ram and SFRS
can be directly addressed. This is known as direct addressing mode.
Eg: Mov R0, 89H
14. What is indirect addressing mode?
In this mode, the 8-bit address of an operand is stored in a register and the register, instead of the 8-bit address, is
specified in the instruction. The registers R0 and R1 of the selected bank of registers or stack
pointer can be used as address registers for storing the 8-bit addresses.
The address register for 16-bit addresses can only be „data pointer‟ (DPTR). Eg: ADD A, @ R0.
15. What is meant by register instructions addressing mode?
The operations are stored in the registers R0 – R7 of the selected register bank. One of these eight registers (R0 – R7) is
specified in the instruction using the 3-bit register specification field of the opcode format. A register bank can be
selected using the two bank select bits of the PSN. This is called as register instruction addressing mode
Eg: ADD A, R7.
16. What is immediate addressing mode?
An immediate data ie., a constant is specified in the instruction, after the opcode byte.
Eg: MOV A, #100
The immediate data 100 (decimal) is added to the contents of the accumulator. For specifying a hex number, it should
be followed by H. These are known as immediate addressing mode.
17. What is indexed addressing?
This addressing mode is used only to access the program memory. It is accomplished in 8051 for look-up table
manipulations. Program counter or data pointer are the allowed 16-bit address storage registers, in this mode of
addressing. These 16-bit registers point to the base of the look-up table and the ACC register contains a code to be
converted using the look-up table. The look-up table data address is found out by adding the contents of register ACC
with that of the program counter or data pointer.
In case of jump instruction, the contents of accumulator are added with one of the specified 16-bit registers to form the
jump destination address.
Eg: MOV C, A @ A + DPTP JMP @ A + DPTR
18. List the five addressing modes of 8051 microcontroller.
The five addressing modes are,
I. Immediate addressing
II. Register addressing
III. Direct addressing
IV. Register indirect addressing.
V. Indexed addressing.
19. MOV R4, R7 is invalid. Why?
The movement of data between the accumulator and Rn (for n = 0 to 7) is valid. But movement of data between Rn
register is not allowed. That is why MOV R4, R7 is invalid.
20. What Is SFR?

In the 8051 microcontroller registers A, B, PSW and DPTR are part of the group of registers commonly referred to as
special function registers (SFR).
21. What are the two main features of SFR Addresses?
The following two points should be noted SFR addresses. The special function registers have addresses between 80H
and FFH. These addresses are above 80H, since the addresses 00 to 7FH are addresses of RAM memory inside the
8051.
II. Not all the address space of 80 to FH is used by the SFR. The unused locations 80Hto FFH are reserved and must
not used by the 8051 programmer.
22. What is the difference between direct and register indirect addressing mode?
Loop is most efficient and is possible only in register indirect addressing whereas looping is not direct addressing
mode.
23. List out some compare instructions.
The compare instructions are:
a. CJNE
b. CLR
S.N Question BL CO
o
(i)Explain briefly about Instruction set of 8086 microprocessor.

(ii) Explain briefly about Assembler Directives of 8086 BL2 CO4
1 microprocessor.
(i)Write ALP to sort the given numbers in Ascending order.
(ii)Explain about architecture of 8051 microcontroller.
2 BL3 CO4
(i)Explain the addressing modes of 8051 microcontroller.
(ii)Explain instruction set of 8051 microcontroller.
BL2 CO4
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SRI VENKATESWARA ENGINEERING COLLEGE

KARAKAMBADI ROAD, TIRUPATI-517507

DEPARTMENT OF ELECTRONICS AND COMMUNICATIONENGINEERING

20A04304T- DIGITAL ELECTRONICS &

Academic Year : 2021- 2022

Head of the Department

Course Code DIGITAL ELECTRONICS L T P C

Pre-requisite Basic Electronics Semester III

1 Unit-I : Number Systems and Code Conversion Page NO

have weights of 10-1, 10-2 and 10-3 respectively.

1358.246 = (1 × 103) + (3 × 102) + (5 × 101) + (8 × 100) + (2 × 10-1) +

weights of 8-1, 8-2, 8-3 respectively. Mathematically, we can

1457.236 = (1 × 83) + (4 × 82) + (5 × 81) + (7 × 80) + (2 × 8-1) +

4 have weights of 16-1, 16-2 and 16-3 respectively.

(12 × 16-2) + (4 × 16-3)

B inary Digits Operation Decimal Result Operation Decimal Result

00000 +0 112 ×2 224

0000 +0 224 ×2 448

000 +0 448 ×2 896

1.3.4 Decimal to Binary

1.3.5 Decimal to Octal Conversion

1.3.7 Octal to Decimal Conversion

products of all the bits with its weight. (152.25)8=(1×82)+(5×81)+(2×80)+(2×8-

We write the three-bit binary digit for 1, 5, 2, and 5.

So, the binary number of the octal number 152.25 is (001101010.010101)2

1.3.9. Octal to hexadecimal conversion

We write the three-bit binary digit for 1, 5, 2, and 5.

So, the binary number of the octal number 152.25 is (001101010.010101)2Step 2:

0000 0110 1010.0101 0100

1.3.10. Hexa-decimal to Decimal Number System

So, the decimal number of the hexadecimal number 152A.25 is5418.14453125

1.3.11 Hexadecimal to Binary Conversion

The process of converting hexadecimal to binary is the reverse process of binary to

1.3.12 Hexadecimal to Octal Conversion

Fig 1.1 Classification of Binary Number Representation

Positive Signed Binary Numbers

Negative Signed Binary Numbers

+5 is represented as it is represented in sign magnitude method. -5 is representedusing the following

MSB is always 1 in case of negative numbers.

1.4.1 Addition and Subtraction using 1's complement

The addition of these two numbers is

+710 ++410 = 001112+001002

⇒ +710 ++410 = 010112.

The addition of these two numbers is

−710 + −410 = 110012 + 111002

Resultant sum after removing carry is −710 + −410 = 101012.

Subtraction of two Signed Binary Numbers

The subtraction of these two numbers is

⇒ +710 + +410 = 001112 + 111002

+710 + +410 = 000112

The subtraction of these two numbers is

+410 − +710 = +410 + −7

⇒ +410 + −710 = 001002 + 110012 = 111012

1.5.1 Binary Addition

The table of adding two binary numbers 0 and 1 is given below:

1 1 0 (where 1 is carried over)

Example 1: 10001 + 11101

1.5.2 Binary Subtraction

Thus the rules of binary subtraction are as follows: