STP80NE03L-06

N - CHANNEL ENHANCEMENT MODE

” SINGLE FEATURE SIZE ” POWER MOSFET
PRELIMINARY DATA
T YPE V DSS R DS(o n) ID
ST P80NE03L-06 30 V < 0.006 Ω 80 A
■ TYPICAL RDS(on) = 0.005 Ω
■ EXCEPTIONAL dv/dt CAPABILITY
■ 100% AVALANCHE TESTED
■ LOW GATE CHARGE 100 oC
■ APPLICATION ORIENTED
CHARACTERIZATION
3
2
DESCRIPTION 1
This Power Mosfet is the latest development of
SGS-THOMSON unique ”Single Feature Size” TO-220
strip-based process. The resulting transistor
shows extremely high packing density for low on-
resistance, rugged avalance characteristics and
less critical alignment steps therefore a remark-
able manufacturing reproducibility.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ SOLENOID AND RELAY DRIVERS
■ MOTOR CONTROL, AUDIO AMPLIFIERS
■ DC-DC & DC-AC CONVERTERS
■ AUTOMOTIVE ENVIRONMENT (INJECTION,
ABS, AIR-BAG, LAMPDRIVERS, Etc. )

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Uni t
V DS Drain-source Voltage (V GS = 0) 30 V
V DGR Drain- gate Voltage (R GS = 20 kΩ) 30 V
V GS Gate-source Voltage ± 15 V
o
ID Drain Current (continuous) at Tc = 25 C 80 A
o
ID Drain Current (continuous) at Tc = 100 C 60 A
IDM (•) Drain Current (pulsed) 320 A
o
P t ot Total Dissipation at Tc = 25 C 150 W
o
Derating F actor 1 W/ C
dv/dt Peak Diode Recovery voltage slope 7 V/ ns
o
T stg Storage T emperature -65 to 175 C
o
Tj Max. O perating Junction Temperature 175 C
(•) Pulse width limited by safe operating area ( 1) ISD ≤ 80 A, di/dt ≤ 300 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX

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STP80NE03L-06

THERMAL DATA
o
R t hj-ca se Thermal Resistance Junction-case Max 1 C/W
Rthj -amb Thermal Resistance Junction-ambient Max 62.5 oC/W
o
R thc- si nk Thermal Resistance Case-sink Typ 0.5 C/W
o
Tl Maximum Lead Temperature For Soldering Purpose 300 C

AVALANCHE CHARACTERISTICS
Symb ol Parameter Max Valu e Unit
I AR Avalanche Current, Repetitive or Not-Repetitive 80 A
(pulse width limited by Tj max, δ < 1%)
E AS Single Pulse Avalanche Energy 600 mJ
(starting Tj = 25 o C, I D = IAR , VDD = 15 V)

ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified)

OFF
Symb ol Parameter Test Cond ition s Min. Typ . Max. Un it
V (BR)DSS Drain-source I D = 250 µA V GS = 0 30 V
Breakdown Voltage
I DSS Zero G ate Voltage V DS = Max Rating 1 µA
Drain Current (VGS = 0) V DS = Max Rating T c =125 oC 10 µA
I GSS Gate-body Leakage V GS = ± 15 V ± 100 nA
Current (V DS = 0)

ON (∗)
Symb ol Parameter Test Cond ition s Min. Typ . Max. Un it
V GS(th) Gate Threshold V DS = VGS ID = 250 µA 1 1.7 2.5 V
Voltage
R DS( on) Static Drain-source On V GS = 10V ID = 40 A 0.005 0.006 Ω
Resistance V GS = 5V ID = 40 A 0.009
ID(o n) On State Drain Current V DS > I D(on) x R DS(on) max 80 A
V GS = 10 V

DYNAMIC
Symb ol Parameter Test Cond ition s Min. Typ . Max. Un it
g fs (∗) Forward V DS > I D(on) x R DS(on) max I D =40 A 30 50 S
Transconductance
C iss Input Capacitance V DS = 25 V f = 1 MHz VGS = 0 6500 8700 pF
C oss Output Capacitance 1500 2000 pF
C rss Reverse T ransfer 500 700 pF
Capacitance

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 STP80NE03L-06

ELECTRICAL CHARACTERISTICS (continued)

SWITCHING ON
Symb ol Parameter Test Cond ition s Min. Typ . Max. Un it
t d(on) Turn-on Time V DD = 15 V ID = 40 A 40 55 ns
tr Rise Time R G =4.7 Ω V GS = 5 V 260 350 ns
(see test circuit, figure 3)
Qg Total Gate Charge V DD = 24 V I D = 80 A V GS = 5 V 95 130 nC
Q gs Gate-Source Charge 30 nC
Q gd Gate-Drain Charge 44 nC

SWITCHING OFF
Symb ol Parameter Test Cond ition s Min. Typ . Max. Un it
t r(Vof f) Off-voltage Rise Time V DD = 24 V I D = 80 A 70 95 ns
tf Fall Time R G =4.7 Ω VGS = 5 V 165 220 ns
tc Cross-over Time (see test circuit, figure 5) 250 340 ns

SOURCE DRAIN DIODE

Symb ol Parameter Test Cond ition s Min. Typ . Max. Un it
I SD Source-drain Current 80 A
I SDM (•) Source-drain Current 320 A
(pulsed)
V SD (∗) Forward On Voltage I SD = 80 A V GS = 0 1.5 V
t rr Reverse Recovery I SD = 80 A di/dt = 100 A/µs 75 ns
o
Time V DD = 15 V Tj = 150 C
Q rr Reverse Recovery (see test circuit, figure 5) 0.14 µC
Charge
I RRM Reverse Recovery 4 A
Current
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area

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STP80NE03L-06

Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform

Fig. 3: Switching Times Test Circuits For Fig. 4: Gate Charge test Circuit
Resistive Load

Fig. 5: Test Circuit For Inductive Load Switching

And Diode Recovery Times

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 STP80NE03L-06

TO-220 MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.40 4.60 0.173 0.181
C 1.23 1.32 0.048 0.051
D 2.40 2.72 0.094 0.107
D1 1.27 0.050
E 0.49 0.70 0.019 0.027
F 0.61 0.88 0.024 0.034
F1 1.14 1.70 0.044 0.067
F2 1.14 1.70 0.044 0.067
G 4.95 5.15 0.194 0.203
G1 2.4 2.7 0.094 0.106
H2 10.0 10.40 0.393 0.409
L2 16.4 0.645
L4 13.0 14.0 0.511 0.551
L5 2.65 2.95 0.104 0.116
L6 15.25 15.75 0.600 0.620
L7 6.2 6.6 0.244 0.260
L9 3.5 3.93 0.137 0.154
DIA. 3.75 3.85 0.147 0.151
E
A

D
C

D1

L2
F1

G1

H2
G

Dia.
F
F2

L5
L9
L7

L6 L4
P011C

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STP80NE03L-06

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.

 1997 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved

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