STP60NS04Z
STP60NS04Z
STP60NS04Z
DESCRIPTION 3
2
This fully clamped Mosfet is produced by using 1
the latest advanced Company’s Mesh Overlay
process which is based on a novel strip layout. TO-220
The inherent benefits of the new technology
coupled with the extra clamping capabilities make
this product particularly suitable for the harshest
operation conditions such as those encountered
in the automotive environment. Any other INTERNAL SCHEMATIC DIAGRAM
application requiring extra ruggedness is also
recommended.
APPLICATIONS
■ ABS, SOLENOID DRIVERS
■ MOTOR CONTROL
■ DC-DC CONVERTERS
THERMAL DATA
o
R thj -case Thermal Resistance Junction-case Max 1.07 C/W
o
R thj -case Thermal Resistance Junction-case Typ 0.85 C/W
o
R thj -amb Thermal Resistance Junction-ambient Max 62.5 C/W
o
R thc-sink Thermal Resistance Case-sink Typ 0.5 C/W
o
Tl Maximum Lead Temperature F or Soldering Purpose 300 C
AVALANCHE CHARACTERISTICS
Symbo l Parameter Max Value Unit
IAR Avalanche Current, Repetitive or Not-Repetitive 60 A
(pulse width limited by Tj max, δ < 1%)
E AS Single Pulse Avalanche Energy 400 mJ
(starting Tj = 25 o C, ID = IAR , V DD = 30 V)
ON (∗)
Symbo l Parameter Test Con ditions Min. Typ. Max. Unit
V GS(th) Gate Threshold Voltage V DS =V GS ID = 1 mA 1.7 3 4.2 V
-40 < Tj < 150 o C
R DS(on) Static Drain-source On V GS = 10V ID = 30 A 11 15 mΩ
Resistance V GS = 16V ID = 30 A 10 14 mΩ
I D(o n) On State Drain Current V DS > ID(o n) x R DS(on )ma x 60 A
V GS = 10 V
DYNAMIC
Symbo l Parameter Test Con ditions Min. Typ. Max. Unit
g f s (∗) Forward V DS > ID(o n) x R DS(on )ma x I D =30 A 20 30 S
Transconductance
C iss Input Capacitance V DS = 25 V f = 1 MHz V GS = 0 2500 3400 pF
C os s Output Capacitance 800 1100 pF
C rss Reverse Transfer 150 200 pF
Capacitance
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STP60NS04Z
SWITCHING OFF
Symbo l Parameter Test Con ditions Min. Typ. Max. Unit
tr (Voff) Off-voltage Rise T ime V CLAMP = 30 V I D = 60 A 25 35 ns
tf Fall T ime R G =4.7 Ω V GS = 10 V 110 150 ns
tc Cross-over Time (see test circuit, figure 5) 150 200 ns
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STP60NS04Z
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STP60NS04Z
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STP60NS04Z
Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Fig. 4: Gate Charge test Circuit
Resistive Load
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STP60NS04Z
mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.40 4.60 0.173 0.181
C 1.23 1.32 0.048 0.051
D 2.40 2.72 0.094 0.107
D1 1.27 0.050
E 0.49 0.70 0.019 0.027
F 0.61 0.88 0.024 0.034
F1 1.14 1.70 0.044 0.067
F2 1.14 1.70 0.044 0.067
G 4.95 5.15 0.194 0.203
G1 2.4 2.7 0.094 0.106
H2 10.0 10.40 0.393 0.409
L2 16.4 0.645
L4 13.0 14.0 0.511 0.551
L5 2.65 2.95 0.104 0.116
L6 15.25 15.75 0.600 0.620
L7 6.2 6.6 0.244 0.260
L9 3.5 3.93 0.137 0.154
DIA. 3.75 3.85 0.147 0.151
E
A
D
C
D1
L2
F1
G1
H2
G
Dia.
F
F2
L5
L9
L7
L6 L4
P011C
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STP60NS04Z
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibil ity for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specific ation mentioned in this publication are
subjec t to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a trademark of STMicroelectronics
http://www.st.com
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