Dunna Sravan Kumar21BCE5726 Exp-2

DESIGN AND IMPLEMENTATION OF ADDERS AND SUBTRACTORS USING
HARDWARE AND SOFTWARE
EXPERIMENT NO.(HW/SW): 2
REGISTER NO: 21BCE5726
NAME: Dunna Sravan Kumar
DATE: 18th September 2022
AIM:
(a) Design and construct half adder circuits and verify the truth table using logic gates.
(b) Do design and construct half subtractor circuits and verify the truth table using logic gates.
(c) Design a partial simplified Arithmetic Logic Unit (ALU) using basic logic gates, which can
perform the 1-bit arithmetic addition operation with the inclusion of carry as an additional input.
(d) Design a partial simplified Arithmetic Logic Unit (ALU) using basic logic gates, which can
perform the 1-bit arithmetic subtraction operation with the inclusion of borrow as an additional
input.
TRAINER KIT/EDA TOOL: DIGITAL IC TRAINER/MODELSIM
IC PIN DIAGRAM:
i) GATE LEVEL MODELING:
1. HALF ADDER:
module ha_g(A,B,S,CA);
input A,B;
output S,CA;
xor(S,A,B);
and(CA,A,B);
endmodule
TESTBENCH:
module ha_g_tb;
reg A,B;
wire S,CA;
ha_g UUT(A,B,S,CA);
initial
begin
A=0;B=0;
#10 A=0;B=1;
#10 A=1;B=0;
#10 A=1;B=1;
#10 $stop;
end
initial
begin
$monitor($time,"A=%b,B=%b,S=%b,CA=%b",A,B,S,CA);
$dumpfile("dump.vcd");
$dumpvars();
end
endmodule
2. HALF SUBTRACTOR:
module hs_g(A,B,D,BO);
input A,B;
output D,BO;
wire W1;
xor(D,A,B);
not(W1,A);
and(BO,B,W1);
endmodule
TESTBENCH:
module hs_g_tb;
reg A,B;
wire D,BO;
hs_g UUT(A,B,D,BO);
initial
begin
A=0;B=0;
#10 A=0;B=1;
#10 A=1;B=0;
#10 A=1;B=1;
#10 $stop;
end
initial
begin
$monitor($time,"A=%b,B=%b,D=%b,BO=%b",A,B,D,BO);
$dumpvars();
end
endmodule
3. FULL ADDER:
module fa_g(A,B,C,S,CA);
input A,B,C;
output S,CA; wire
W1,W2,W3;
xor(W1,A,B);
xor(S,W1,C);
and(W2,A,B);
and(W3,W1,C);
or(CA,W3,W2);
endmodule
TESTBENCH:
module fa_g_tb;
reg A,B,C;
wire S,CA;
fa_g UUT(A,B,C,S,CA);
initial
begin
A=0;B=0;C=0; #10
A=0;B=0;C=1;
#10 A=0;B=1;C=0;
#10 A=0;B=1;C=1;
#10 A=1;B=0;C=0;
#10 A=1;B=0;C=1;
#10 A=1;B=1;C=0;
#10 A=1;B=1;C=1;
#10 $stop;
end
initial
begin
$monitor($time,"A=%b,B=%b,C=%b,S=%b,CA=%b",A,B,C,S,CA);
$dumpvars();
end
endmodule
4. FULL SUBTRACTOR:
module fs_g(A,B,C,D,BO);
input A,B,C;
output D,BO;
wire W1,W2,W3,W4,W5;
xor(W1,A,B);
xor(D,W1,C);
not(W2,A);
and(W3,W2,B);
not(W4,W1);
and(W5,W4,C);
or(BO,W5,W3);
endmodule
TESTBENCH:
module fs_g_tb;
reg A,B,C;
wire D,BO;
fs_g UUT(A,B,C,D,BO);
initial
begin
A=0;B=0;C=0; #10
A=0;B=0;C=1;
#10 A=0;B=1;C=0;
#10 A=0;B=1;C=1;
#10 A=1;B=0;C=0;
#10 A=1;B=0;C=1;
#10 A=1;B=1;C=0;
#10 A=1;B=1;C=1;
#10 $stop;
end
initial
begin
$monitor($time,"A=%b,B=%b,C=%b,D=%b,BO=%b",A,B,C,D,BO);
$dumpvars();
end
endmodule
ii) DATAFLOW MODELLING:
1. HALF ADDER: module
ha_d(A,B,S,CA); input
A,B;
output S,CA;
assign S=A^B;
assign CA=A&B;
endmodule
TESTBENCH:
module ha_d_tb;
reg A,B;
wire S,CA;
ha_d UUT(A,B,S,CA);
initial
begin
A=0;B=0;
#10 A=0;B=1;
#10 A=1;B=0;
#10 A=1;B=1;
#10 $stop;
end
initial
begin
$dumpvars();
end
endmodule
2. HALF SUBTRACTOR:
module hs_d(A,B,D,BO);
input A,B;
output D,BO; assign
D=A^B; assign
BO=(~A)&B;
endmodule
TESTBENCH:
module hs_d_tb;
reg A,B;
wire D,BO;
hs_d UUT(A,B,D,BO);
initial
begin
A=0;B=0;
#10 A=0;B=1;
#10 A=1;B=0;
#10 A=1;B=1;
#10 $stop;
end
initial
begin
$dumpvars();
end
endmodule
3. FULL ADDER:
module fa_d(A,B,C,S,CA);
input A,B,C;
output S,CA; assign
S=A^(B^C);
assign CA=(A^B)&C|(A&B);
endmodule
TESTBENCH:
module fa_d_tb;
reg A,B,C;
wire S,CA;
fa_d UUT(A,B,C,S,CA);
initial
begin
A=0;B=0;C=0; #10
A=0;B=0;C=1;
#10 A=0;B=1;C=0;
#10 A=0;B=1;C=1;
#10 A=1;B=0;C=0;
#10 A=1;B=0;C=1;
#10 A=1;B=1;C=0;
#10 A=1;B=1;C=1;
#10 $stop;
end
initial
begin
$dumpvars();
end
endmodule
4. FULL SUBTRACTOR:
module fs_d(A,B,C,D,BO);
input A,B,C;
output D,BO; assign
D=A^(B^C);
assign BO=((~A)&B)|(C&(~(A^B)));
endmodule
TESTBENCH:
module fs_d_tb;
reg A,B,C;
wire D,BO;
fs_d UUT(A,B,C,D,BO);
initial
begin
A=0;B=0;C=0; #10
A=0;B=0;C=1;
#10 A=0;B=1;C=0;
#10 A=0;B=1;C=1;
#10 A=1;B=0;C=0;
#10 A=1;B=0;C=1;
#10 A=1;B=1;C=0;
#10 A=1;B=1;C=1;
#10 $stop;
end
initial
begin
$dumpvars();
end
endmodule
iii) BEHAVIOURAL MODELLING:
1. HALF ADDER: module
ha_b(A,B,S,CA); input
A,B;
output S,CA;
reg S,CA;
always @(A or B)
begin
case({A,B})
2'b00: begin S=0; CA=0; end
endcase
end endmodule
TESTBENCH:
module ha_b_tb;
reg A,B;
wire S,CA;
ha_b UUT(A,B,S,CA);
initial
begin
A=0;B=0;
#10 A=0;B=1;
#10 A=1;B=0;
#10 A=1;B=1;
#10 $stop;
end
initial
begin
$dumpvars();
end
endmodule
2. HALF SUBTRACTOR:
module hs_b(A,B,D,BO);
input A,B;
output D,BO;
reg D,BO;
always @(A or B)
begin
case({A,B})
2'b00: begin D=0; BO=0; end
endcase
end endmodule
TESTBENCH:
module hs_b_tb;
reg A,B;
wire D,BO;
hs_b UUT(A,B,D,BO);
initial
begin
A=0;B=0;
#10 A=0;B=1;
#10 A=1;B=0;
#10 A=1;B=1;
#10 $stop;
end
initial
begin
$dumpvars();
end
endmodule
3. FULL ADDER:
module fa_b(A,B,C,S,CA);
input A,B,C;
output S,CA;
reg S,CA;
always @(A or B or C)
begin
case({A,B,C})

endcase
end endmodule
TESTBENCH:
module fa_b_tb;
reg A,B,C;
wire S,CA;
fa_b UUT(A,B,C,S,CA);
initial
begin
A=0;B=0;C=0; #10
A=0;B=0;C=1;
#10 A=0;B=1;C=0;
#10 A=0;B=1;C=1;
#10 A=1;B=0;C=0;
#10 A=1;B=0;C=1;
#10 A=1;B=1;C=0;
#10 A=1;B=1;C=1;
#10 $stop;
end
initial
begin
$dumpvars();
end
endmodule
4. FULL SUBTRACTOR:
module fs_b(A,B,C,D,BO);
input A,B,C;
output D,BO;
reg D,BO;
always @(A or B or C)
begin
case({A,B,C})
endcase
end
endmodule
TESTBENCH:
module fs_b_tb;
reg A,B,C;
wire D,BO;
fs_b UUT(A,B,C,D,BO);
initial
begin
A=0;B=0;C=0; #10
A=0;B=0;C=1;
#10 A=0;B=1;C=0;
#10 A=0;B=1;C=1;
#10 A=1;B=0;C=0;
#10 A=1;B=0;C=1;
#10 A=1;B=1;C=0;
#10 A=1;B=1;C=1;
#10 $stop;
end
initial
begin
$dumpvars();
end
endmodule
RESULT/INFERENCE: The half adder, half subtractor, full adder and full subtractor have been
constructed and their truth tables are verified.

Dunna Sravan Kumar21BCE5726 Exp-2

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Dunna Sravan Kumar21BCE5726 Exp-2

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DESIGN AND IMPLEMENTATION OF ADDERS AND SUBTRACTORS USING

HARDWARE AND SOFTWARE

REGISTER NO: 21BCE5726

NAME: Dunna Sravan Kumar

DATE: 18th September 2022

TRAINER KIT/EDA TOOL: DIGITAL IC TRAINER/MODELSIM

1. HALF ADDER: module

output D,BO; assign

output S,CA; assign

output D,BO; assign

1. HALF ADDER: module

2'b00: begin S=0; CA=0; end

2'b01: begin S=1; CA=0; end

2'b10: begin S=1; CA=0; end

2'b11: begin S=0; CA=1; end

2'b00: begin D=0; BO=0; end

2'b01: begin D=1; BO=1; end

2'b10: begin D=1; BO=0; end

2'b11: begin D=0; BO=0; end

3'b000: begin S=0; CA=0; end

3'b001: begin S=1; CA=0; end

3'b010: begin S=1; CA=0; end

3'b011: begin S=0; CA=1; end

3'b100: begin S=1; CA=0; end

3'b101: begin S=0; CA=1; end

3'b111: begin S=1; CA=1; end

3'b000: begin D=0; BO=0; end

3'b001: begin D=1; BO=1; end

3'b010: begin D=1; BO=1; end

3'b011: begin D=0; BO=1; end

3'b100: begin D=1; BO=0; end

3'b101: begin D=0; BO=0; end

3'b110: begin D=0; BO=0; end

3'b111: begin D=1; BO=1; end

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