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    DLD Lab Manual 15

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    Sana gull
    The document describes an experiment to implement and verify half adders and full adders in Verilog. It includes the procedures, code for a half adder module, a test module for the half adder, and code for a full adder module and test bench. The lab tasks are to write Verilog code for a half adder using data flow modeling and a full adder using gate level modeling.

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    DLD Lab Manual 15

    Uploaded by

    Sana gull
    28 views6 pages
    The document describes an experiment to implement and verify half adders and full adders in Verilog. It includes the procedures, code for a half adder module, a test module for the half adder, and code for a full adder module and test bench. The lab tasks are to write Verilog code for a half adder using data flow modeling and a full adder using gate level modeling.

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    The document describes an experiment to implement and verify half adders and full adders in Verilog. It includes the procedures, code for a half adder module, a test module for the half adder, and code for a full adder module and test bench. The lab tasks are to write Verilog code for a half adder using data flow modeling and a full adder using gate level modeling.

    Copyright:

    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    28 views6 pages

    DLD Lab Manual 15

    Uploaded by

    Sana gull
    The document describes an experiment to implement and verify half adders and full adders in Verilog. It includes the procedures, code for a half adder module, a test module for the half adder, and code for a full adder module and test bench. The lab tasks are to write Verilog code for a half adder using data flow modeling and a full adder using gate level modeling.

    Copyright:

    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    of 6

    Digital Logic Design, EE Department, Wah Engineering College

    EXPERIMENT NO. : 15

    (a) Implementation and verification of Half adder in Verilog


    (b) Implementation and verification of Full adder in Verilog

    Objective:
    To understand how to implement half adder and full adder using Verilog.

    PROCEDURE:
    Write and draw the Digital logic system.
    Write the Verilog code for above system.
    Enter the Verilog code in Model Sim software.
    Check the syntax and simulate the above Verilog code (using Model Sim or
    Xilinx) and verify the output waveform as obtained.

    Half adder module:


    module halfAdd(sum, cOut, a, b);
    output sum, cOut;
    input a, b;
    xor (sum, a, b);
    and (cOut, a, b);
    endmodule

    Test Module:

    The Verilog module defined above is not executable in any sense. In order to use the
    module, it must be combined with additional Verilog code. We will now create another
    Verilog module that generates test cases for the half-adder. We implement the test case
    generator within a Verilog test module. The test module is written using Verilogs
    behavioral constructs, shown below:

    module testAdd(a, b, sum, cOut);


    input sum, cOut;
    output a, b;
    reg a, b;
    initial begin
    $monitor($time, ,"a= %b, b= %b, sum= %b, cOut= %b", a, b, sum, cOut);
    a = 0; b = 0;
    #10 b = 1;
    #10 a = 1;
    #10 b = 0;
    #10 $finish;
    end
    endmodule
    Digital Logic Design, EE Department, Wah Engineering College

    $monitor generates printed output, in a fashion similar to a printf statement in C. Unlike


    C, however, the output from $monitor is generated whenever any of the input variables
    changes value.
    The $monitor argument $time outputs the current simulation time.
    $finish, terminates the simulation and halts Verilog.

    Output:
    Digital Logic Design, EE Department, Wah Engineering College

    PART (B)
    Implementation and verification of Full adder in Verilog

    Full Adder

    module fulladder(a,b,c,sum,carry);
    input a,b,c;
    output sum,carry;
    wire sum,carry;

    assign sum=a^b^c; // sum bit


    assign carry=((a&b) | (b&c) | (a&c)); //carry bit

    endmodule

    Test bench:

    module main;
    reg a, b, c;
    wire sum, carry;
    fulladder add(a,b,c,sum,carry);
    always @(sum or carry)
    begin
    $display("time=%d:%b + %b + %b = %b, carry =
    %b\n",$time,a,b,c,sum,carry);
    end
    initial
    begin
    a = 0; b = 0; c = 0;
    #5
    a = 0; b = 1; c = 0;
    #5
    a = 1; b = 0; c = 1;
    #5
    a = 1; b = 1; c = 1;
    end
    endmodule
    Digital Logic Design, EE Department, Wah Engineering College

    Output:
    Digital Logic Design, EE Department, Wah Engineering College

    Lab task:
    1. Write a Verilog code for half adder using data flow modelling. (Give the first
    two alphabets followed by ha to the identifier of module e.g ad_ha(portlist);)

    2. Write a Verilog code for full adder using Gate Level modelling. Draw the
    logic diagram depicting the following information. (Give the first two
    alphabets followed by fa to the identifier of module e.g ad_fa(portlist); Also use
    the first two alphabets as an optional name for gate instantiation. ).
    Digital Logic Design, EE Department, Wah Engineering College

    Comments:

    Conclusion:

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