LTC2600/LTC2610/LTC2620

Octal 16-/14-/12-Bit
Rail-to-Rail DACs in 16-Lead SSOP
FEATURES DESCRIPTION
n Smallest Pin-Compatible Octal DACs: The LTC®2600/LTC2610/LTC2620 are octal 16-, 14- and
LTC2600: 16 Bits 12-bit, 2.5V-to-5.5V rail-to-rail voltage-output DACs in
LTC2610: 14 Bits 16-lead narrow SSOP and 20-lead 4mm × 5mm QFN
LTC2620: 12 Bits packages. They have built-in high performance output
n Guaranteed 16-Bit Monotonic Over Temperature buffers and are guaranteed monotonic.
n Wide 2.5V to 5.5V Supply Range
n
These parts establish new board-density benchmarks for
Low Power Operation: 250μA per DAC at 3V
n
16- and 14-bit DACs and advance performance standards for
Individual Channel Power-Down to 1μA, Max
n
output drive, crosstalk and load regulation in single-supply,
Ultralow Crosstalk Between DACs (<10μV)
n
voltage-output multiples.
High Rail-to-Rail Output Drive (±15mA, Min)
n Double-Buffered Digital Inputs The parts use a simple SPI/MICROWIRE compatible 3-wire
n Pin-Compatible 10-/8-Bit Versions (LTC1660/LTC1665) serial interface which can be operated at clock rates up
n Tiny 16-Lead Narrow SSOP to 50MHz. Daisychain capability and a hardware CLR
and 20-Lead 4mm × 5mm QFN Packages function are included.

APPLICATIONS The LTC2600/LTC2610/LTC2620 incorporate a power-on

reset circuit. During power-up, the voltage outputs rise less
n Mobile Communications than 10mV above zero-scale; and after power-up, they stay
n Process Control and Industrial Automation at zero-scale until a valid write and update take place.
n Instrumentation L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
n Automatic Test Equipment Technology Corporation. All other trademarks are the property of their respective owners.

BLOCK DIAGRAM
(20) GND 1 16 VCC (17)
REGISTER

REGISTER

REGISTER

REGISTER

(1) VOUTA 2 DAC A DAC H 15 VOUTH (16)

Differential Nonlinearity (LTC2600)

REGISTER

REGISTER

REGISTER

REGISTER

DAC B DAC G 1.0

(2) VOUTB 3 14 VOUTG (15) VCC = 5V
0.8 VREF = 4.096V
0.6
REGISTER

REGISTER

REGISTER

REGISTER

0.4
(3) VOUTC 4 DAC C DAC F 13 VOUTF (14) 0.2
DNL (LSB)

0
–0.2
REGISTER

REGISTER

REGISTER

REGISTER

–0.4
(4) V DAC D DAC E (13)
OUTD 5 12 VOUTE
–0.6
–0.8
(5) REF 6 11 CLR (11) –1.0
POWER-ON 0 16384 32768 49152 65535
RESET
CONTROL CODE
DECODE
LOGIC 2600 G21
(7) CS/LD 7 10 SDO (10)

(8) SCK 8 32-BIT SHIFT REGISTER 9 SDI (9)

2600 BD

NOTE: NUMBERS IN PARENTHESIS REFER TO THE UFD PACKAGE

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This datasheet has been downloaded from http://www.digchip.com at this page

1
LTC2600/LTC2610/LTC2620
ABSOLUTE MAXIMUM RATINGS (Note 1)

Any Pin to GND ........................................... –0.3V to 6V Storage Temperature Range.................. –65°C to 150°C
Any Pin to VCC ............................................ –6V to 0.3V Maximum Junction Temperature........................... 125°C
Operating Temperature Range Lead Temperature (Soldering, 10 sec) ................. 300°C
LTC2600C/LTC2610C/LTC2620C ............. 0°C to 70°C
LTC2600I/LTC2610I/LTC2620I............. –40°C to 85°C

PIN CONFIGURATION
TOP VIEW

GND
DNC
DNC
VCC
TOP VIEW
20 19 18 17
GND 1 16 VCC
VOUTA 1 16 VOUTH
VOUTA 2 15 VOUTH
VOUTB 2 15 VOUTG
VOUTB 3 14 VOUTG
VOUTC 3 14 VOUTF
VOUTC 4 13 VOUTF 21
VOUTD 4 13 VOUTE
VOUTD 5 12 VOUTE REF 5 12 DNC
REF 6 11 CLR DNC 6 11 CLR
CS/LD 7 10 SDO
7 8 9 10
SCK 8 9 SDI

CS/LD
SCK
SDI
SDO
GN PACKAGE
16-LEAD PLASTIC SSOP
UFD PACKAGE
TJMAX = 125°C, θJA = 150°C/W 20-LEAD (4mm s 5mm) PLASTIC QFN
TJMAX = 150°C, θJA = 43°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2600CUFD#PBF LTC2600CUFD#TRPBF 2600 20-Lead (4mm × 5mm) Plastic DFN 0°C to 70°C
LTC2600IUFD#PBF LTC2600IUFD#TRPBF 2600 20-Lead (4mm × 5mm) Plastic DFN –40°C to 85°C
LTC2600CGN#PBF LTC2600CGN#TRPBF 2600 16-Lead Plastic SSOP 0°C to 70°C
LTC2600IGN#PBF LTC2600IGN#TRPBF 2600I 16-Lead Plastic SSOP –40°C to 85°C
LTC2610CUFD#PBF LTC2610CUFD#TRPBF 2610 20-Lead (4mm × 5mm) Plastic DFN 0°C to 70°C
LTC2610IUFD#PBF LTC2610IUFD#TRPBF 2610 20-Lead (4mm × 5mm) Plastic DFN –40°C to 85°C
LTC2610CGN#PBF LTC2610CGN#TRPBF 2610 16-Lead Plastic SSOP 0°C to 70°C
LTC2610IGN#PBF LTC2610IGN#TRPBF 2610I 16-Lead Plastic SSOP –40°C to 85°C
LTC2620CUFD#PBF LTC2620CUFD#TRPBF 2620 20-Lead (4mm × 5mm) Plastic DFN 0°C to 70°C
LTC2620IUFD#PBF LTC2620IUFD#TRPBF 2620 20-Lead (4mm × 5mm) Plastic DFN –40°C to 85°C
LTC2620CGN#PBF LTC2620CGN#TRPBF 2620 16-Lead Plastic SSOP 0°C to 70°C
LTC2620IGN#PBF LTC2620IGN#TRPBF 2620I 16-Lead Plastic SSOP –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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2
 LTC2600/LTC2610/LTC2620
ELECTRICAL CHARACTERISTICS The l denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.5V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
LTC2620 LTC2610 LTC2600
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
DC Performance
Resolution l 12 14 16 Bits
Monotonicity VCC = 5V, VREF = 4.096V (Note 2) l 12 14 16 Bits
DNL Differential Nonlinearity VCC = 5V, VREF = 4.096V (Note 2) l ±0.5 ±1 ±1 LSB
INL Integral Nonlinearity VCC = 5V, VREF = 4.096V (Note 2) l ±0.75 ±4 ±3 ±16 ±12 ±64 LSB
Load Regulation VREF = VCC = 5V, Mid-Scale
IOUT = 0mA to 15mA Sourcing l 0.025 0.125 0.1 0.5 0.3 2 LSB/mA
IOUT = 0mA to 15mA Sinking l 0.025 0.125 0.1 0.5 0.3 2 LSB/mA
VREF = VCC = 2.5V, Mid-Scale
IOUT = 0mA to 7.5mA Sourcing l 0.05 0.25 0.2 1 0.8 4 LSB/mA
IOUT = 0mA to 7.5mA Sinking l 0.05 0.25 0.2 1 0.8 4 LSB/mA
ZSE Zero-Scale Error VCC = 5V, VREF = 4.096V Code = 0 1 9 1 9 1 9 mV
VOS Offset Error VCC = 5V, VREF = 4.096V (Note 7) ±1 ±9 ±1 ±9 ±1 ±9 mV
VOS Temperature ±3 ±3 ±3 μV/°C
Coefficient
GE Gain Error VCC = 5V, VREF = 4.096V ±0.2 ±0.7 ±0.2 ±0.7 ±0.2 ±0.7 %FSR
Gain Temperature ±6.5 ±6.5 ±6.5 ppm/°C
Coefficient

The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 2.5V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
LTC2600/LTC2610/LTC2620
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PSR Power Supply Rejection VCC = ±10% –80 dB
ROUT DC Output Impedance VREF = VCC = 5V, Mid-Scale; –15mA ≤ IOUT ≤ 15mA l 0.025 0.15 Ω
VREF = VCC = 2.5V, Mid-Scale; –7.5mA ≤ IOUT ≤ 7.5mA l 0.030 0.15 Ω
DC Crosstalk (Note 4) Due to Full-Scale Output Change (Note 5) ±10 μV
Due to Load Current Change ±3.5 μV/mA
Due to Powering Down (per Channel) ±7.3 μV
ISC Short-Circuit Output Current VCC = 5.5V, VREF = 5.6V
Code: Zero-Scale; Forcing Output to VCC l 15 34 60 mA
Code: Full-Scale; Forcing Output to GND l 15 34 60 mA
VCC = 2.5V, VREF = 5.6V
Code: Zero-Scale; Forcing Output to VCC l 7.5 18 50 mA
Code: Full-Scale; Forcing Output to GND l 7.5 24 50 mA
Reference Input
Input Voltage Range l 0 VCC V
Resistance Normal Mode l 11 16 20 kΩ
Capacitance 90 pF
IREF Reference Current, Power-Down All DACs Powered Down l 0.001 1 μA
Mode

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LTC2600/LTC2610/LTC2620
ELECTRICAL CHARACTERISTICS The l denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.5V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
LTC2600/LTC2610/LTC2620
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply
VCC Positive Supply Voltage l 2.5 5.5 V
ICC Supply Current VCC = 5V (Note 3) l 2.6 4 mA
VCC = 3V (Note 3) l 2.0 3.2 mA
All DACs Powered Down (Note 3) VCC = 5V l 0.35 1 μA
All DACs Powered Down (Note 3) VCC = 3V l 0.10 1 μA
Digital I/O
VIH Digital Input High Voltage VCC = 2.5V to 5.5V l 2.4 V
VCC = 2.5V to 3.6V l 2.0 V
VIL Digital Input Low Voltage VCC = 4.5V to 5.5V l 0.8 V
VCC = 2.5V to 5.5V l 0.6 V
VOH Digital Output High Voltage Load Current = –100μA l VCC – 0.4 V
VOL Digital Output Low Voltage Load Current = +100μA l 0.4 V
ILK Digital Input Leakage VIN = GND to VCC l ±1 μA
CIN Digital Input Capacitance (Note 6) l 8 pF

The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 2.5V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
LTC2620 LTC2610 LTC2600
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
AC Performance
tS Settling Time (Note 8) ±0.024% (±1LSB at 12 Bits) 7 7 7
±0.006% (±1LSB at 14 Bits) 9 9 μs
±0.0015% (±1LSB at 16 Bits) 10 μs
Settling Time for 1LSB Step ±0.024% (±1LSB at 12 Bits) 2.7 2.7 2.7 μs
(Note 9) ±0.006% (±1LSB at 14 Bits) 4.8 4.8 μs
±0.0015% (±1LSB at 16 Bits) 5.2 μs
Voltage Output Slew Rate 0.80 0.80 0.80 V/μs
Capacitive Load Driving 1000 1000 1000 pF
Glitch Impulse At Mid-Scale Transition 12 12 12 nV • s
Multiplying Bandwidth 180 180 180 kHz
en Output Voltage Noise Density At f = 1kHz 120 120 120 nV/√Hz
At f = 10kHz 100 100 100 nV/√Hz
Output Voltage Noise 0.1Hz to 10Hz 15 15 15 μVP-P

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 LTC2600/LTC2610/LTC2620
TIMING CHARACTERISTICS The l denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1) (Note 6)
LTC2600/LTC2610/LTC2620
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC = 2.5V to 5.5V
t1 SDI Valid to SCK Setup l 4 ns
t2 SDI Valid to SCK Hold l 4 ns
t3 SCK High Time l 9 ns
t4 SCK Low Time l 9 ns
t5 CS/LD Pulse Width l 10 ns
t6 LSB SCK High to CS/LD High l 7 ns
t7 CS/LD Low to SCK High l 7 ns
t8 SDO Propagation Delay from SCK Falling Edge CLOAD = 10pF
VCC = 4.5V to 5.5V l 20 ns
VCC = 2.5V to 5.5V l 45 ns
t9 CLR Pulse Width l 20 ns
t10 CS/LD High to SCK Positive Edge l 7 ns
SCK Frequency 50% Duty Cycle l 50 MHz

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 5: RL = 2kΩ to GND or VCC.
may cause permanent damage to the device. Exposure to any Absolute Note 6: Guaranteed by design and not production tested.
Maximum Rating condition for extended periods may affect device Note 7: Inferred from measurement at code 256 (LTC2600),
reliability and lifetime. code 64 (LTC2610) or code 16 (LTC2620), and at full-scale.
Note 2: Linearity and monotonicity are defined from code kL to code Note 8: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4-scale to 3/4-scale
2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF), and 3/4-scale to 1/4-scale. Load is 2k in parallel with 200pF to GND.
rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL =
Note 9: VCC = 5V, VREF = 4.096V. DAC is stepped ±1LSB between half-
256 and linearity is defined from code 256 to code 65,535.
scale and half-scale – 1. Load is 2k in parallel with 200pF to GND.
Note 3: Digital inputs at 0V or VCC.
Note 4: DC crosstalk is measured with VCC = 5V and VREF = 4.096V,
with the measured DAC at mid-scale, unless otherwise noted.

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LTC2600/LTC2610/LTC2620
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2600

Integral Nonlinearity (INL) Differential Nonlinearity (DNL) INL vs Temperature

32 1.0 32
VCC = 5V VCC = 5V
VREF = 4.096V 0.8 VREF = 4.096V VCC = 5V
24 24
VREF = 4.096V
0.6
16 16
0.4
8 0.2 8 INL (POS)

DNL (LSB)
INL (LSB)

INL (LSB)
0 0 0

–8 –0.2 –8
–0.4 INL (NEG)
–16 –16
–0.6
–24 –0.8 –24

–32 –1.0 –32

0 16384 32768 49152 65535 0 16384 32768 49152 65535 –50 –30 –10 10 30 50 70 90
CODE CODE TEMPERATURE (°C)
2600 G20 2600 G21 2600 G22

DNL vs Temperature INL vs VREF DNL vs VREF

1.0 32 1.5
0.8 VCC = 5V VCC = 5.5V VCC = 5.5V
24
VREF = 4.096V 1.0
0.6
16
0.4
DNL (POS) INL (POS) 0.5
0.2 8 DNL (POS)
DNL (LSB)

DNL (LSB)
INL (LSB)

0 0 0
–0.2 DNL (NEG)
DNL (NEG) –8 INL (NEG) –0.5
–0.4
–16
–0.6
–1.0
–0.8 –24

–1.0 –32 –1.5

–50 –30 –10 10 30 50 70 90 0 1 2 3 4 5 0 1 2 3 4 5
TEMPERATURE (°C) VREF (V) VREF (V)
2600 G23 2600 G24 2600 G25

Settling to ±1LSB Settling of Full-Scale Step

VOUT VOUT
100μV/DIV 100μV/DIV 12.3μs
9.7μs

CS/LD CS/LD
2V/DIV 2V/DIV

2600 G27
2μs/DIV 2600 G26
5μs/DIV
VCC = 5V, VREF = 4.096V SETTLING TO ±1LSB
1/4-SCALE TO 3/4-SCALE STEP VCC = 5V, VREF = 4.096V
RL = 2k, CL = 200pF CODE 512 TO 65535 STEP
AVERAGE OF 2048 EVENTS RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS

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 LTC2600/LTC2610/LTC2620
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2610

Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Settling to ±1LSB

8 1.0
VCC = 5V VCC = 5V
6 VREF = 4.096V 0.8 VREF = 4.096V
0.6
4
0.4
2 VOUT
0.2

DNL (LSB)
INL (LSB)

100μV/DIV
0 0
–0.2 CS/LD
–2
2V/DIV 8.9μs
–0.4
–4
–0.6 2600 G30
2μs/DIV
–6 –0.8 VCC = 5V, VREF = 4.096V
–8 –1.0 1/4-SCALE TO 3/4-SCALE STEP
0 4096 8192 12288 16383 0 4096 8192 12288 16383 RL = 2k, CL = 200pF
CODE CODE AVERAGE OF 2048 EVENTS
2600 G28 2600 G29

LTC2620

Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Settling to ±1LSB

2.0 1.0
VCC = 5V VCC = 5V
1.5 VREF = 4.096V 0.8 VREF = 4.096V
0.6
1.0
0.4 6.8μs
0.5 VOUT
0.2
DNL (LSB)
INL (LSB)

1mV/DIV
0 0
–0.2 CS/LD
–0.5
2V/DIV
–0.4
–1.0
–0.6 2600 G33
2μs/DIV
–1.5 –0.8 VCC = 5V, VREF = 4.096V
–2.0 –1.0 1/4-SCALE TO 3/4-SCALE STEP
0 1024 2048 3072 4095 0 1024 2048 3072 4095 RL = 2k, CL = 200pF
CODE CODE AVERAGE OF 2048 EVENTS
2600 G31 2600 G32

LTC2600/LTC2610/LTC2620

Current Limiting Load Regulation Offset Error vs Temperature

0.10 1.0 3
CODE = MIDSCALE CODE = MIDSCALE
0.08 0.8
VREF = VCC = 5V
2
0.06 0.6
VREF = VCC = 3V
OFFSET ERROR (mV)

0.04 0.4
1
$VOUT (mV)

0.02 0.2
$VOUT (V)

0 0 0
VREF = VCC = 5V
–0.02 –0.2
VREF = VCC = 3V –1
–0.04 –0.4
VREF = VCC = 5V VREF = VCC = 3V
–0.06 –0.6
–2
–0.08 –0.8
–0.10 –1.0 –3
–40 –30 –20 –10 0 10 20 30 40 –35 –25 –15 –5 5 15 25 35 –50 –30 –10 10 30 50 70 90
IOUT (mA) IOUT (mA) TEMPERATURE (°C)
2600 G01 2600 G02 2600 G03

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LTC2600/LTC2610/LTC2620
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2600/LTC2610/LTC2620

Zero-Scale Error vs Temperature Gain Error vs Temperature Offset Error vs VCC

3 0.4 3

0.3
2.5 2
ZERO-SCALE ERROR (mV)

0.2

GAIN ERROR (%FSR)

OFFSET ERROR (mV)

2.0 1
0.1

1.5 0 0

–0.1
1.0 –1
–0.2
0.5 –2
–0.3

0 –0.4 –3
–50 –30 –10 10 30 50 70 90 –50 –30 –10 10 30 50 70 90 2.5 3 3.5 4 4.5 5 5.5
TEMPERATURE (°C) TEMPERATURE (°C) VCC (V)
2600 G04 2600 G05 2600 G06

Gain Error vs VCC ICC Shutdown vs VCC Large-Signal Response

0.4 450
0.3 400

0.2 350
GAIN ERROR (%FSR)

0.1 300
VOUT
ICC (nA)

250 0.5V/DIV
0
200
–0.1
150 VREF = VCC = 5V
–0.2 1/4-SCALE TO 3/4-SCALE
100
–0.3 2.5μs/DIV 2600 G09
50
–0.4
0
2.5 3 3.5 4 4.5 5 5.5 2.5 3 3.5 4 4.5 5 5.5
VCC (V) VCC (V)
2600 G07 2600 G08

Headroom at Rails
Mid-Scale Glitch Impulse Power-On Reset Glitch vs Output Current
5.0
4.5 5V SOURCING

4.0
VOUT 3.5
10mV/DIV VCC
3V SOURCING
12nV-s TYP 1V/DIV 3.0
VOUT (V)

2.5
4mV
4mVPEAK
PEAK
CS/LD 2.0
5V/DIV VOUT 1.5
10mV/DIV 5V SINKING
1.0
2.5μs/DIV
2600 G10
250μs/DIV
2600 G11 3V SINKING
0.5
0
0 1 2 3 4 5 6 7 8 9 10
IOUT (mA)
2600 G12

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 LTC2600/LTC2610/LTC2620
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2600/LTC2610/LTC2620

Supply Current vs Logic Voltage Exiting Power-Down to Mid-Scale Hardware CLR

2.4
VCC = 5V VCC = 5V
2.3 SWEEP SCK, SDI VREF = 2V
AND CS/LD
2.2 0V TO VCC
VOUT VOUT
2.1 0.5V/DIV 1V/DIV
ICC (mA)

2.0 DACs A TO G IN
POWER-DOWN MODE
1.9
CS/LD
5V/DIV CLR
1.8
5V/DIV
1.7
2600 G15
2.5μs/DIV 2600 G14 1μs/DIV
1.6

1.5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
LOGIC VOLTAGE (V)
2600 G13

Output Voltage Noise,

Multiplying Bandwidth 0.1Hz to 10Hz
0
–3
–6
–9
–12
VOUT
–15
10μV/DIV
dB

–18
–21
–24
VCC = 5V
–27 VREF (DC) = 2V
–30 VREF (AC) = 0.2VP-P
CODE = FULL SCALE 0 1 2 3 4 5 6 7 8 9 10
–33 SECONDS
–36 2600 G17
1k 10k 100k 1M
FREQUENCY (Hz)
2600 G16

Short-Circuit Output Current Short-Circuit Output Current

vs VOUT (Sinking) vs VOUT (Sourcing)
0mA
10mA/DIV

10mA/DIV

0mA

VCC = 5.5V 1V/DIV 2600 G18 1V/DIV 2600 G19

VCC = 5.5V
VREF = 5.6V
VREF = 5.6V
CODE = 0
CODE = FULL SCALE
VOUT SWEPT 0V TO VCC
VOUT SWEPT VCC TO 0V
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LTC2600/LTC2610/LTC2620
PIN FUNCTIONS (GN/UFD)

GND (Pin 1/Pin 20): Analog Ground. SDO (Pin 10/Pin 10): Serial Interface Data Output. This pin
is used for daisychain operation. The serial output of the
VOUTA to VOUTH (Pins 2-5 and 12-15/Pins 1-48 and
13-16): DAC Analog Voltage Outputs. The output range shift register appears at the SDO pin. The data transferred
is 0 – VREF. to the device via the SDI pin is delayed 32 SCK rising
edges before being output at the next falling edge. SDO
REF (Pin 6/Pin 5): Reference Voltage Input. 0V ≤ VREF is an active output and does not go high impedance, even
≤ VCC. when CS/LD is taken to a logic high level.
CS/LD (Pin 7/Pin 7): Serial Interface Chip Select/Load CLR (Pin 11/Pin 11): Asynchronous Clear Input. A logic
Input. When CS/LD is low, SCK is enabled for shifting low at this level-triggered input clears all registers and
data on SDI into the register. When CS/LD is taken high, causes the DAC voltage outputs to drop to 0V. CMOS and
SCK is disabled and the specified command (see Table 1) TTL compatible.
is executed.
VCC (Pin 16/Pin 17): Supply Voltage Input. 2.5V ≤ VCC
SCK (Pin 8/Pin 8): Serial Interface Clock Input. CMOS ≤ 5.5V.
and TTL compatible.
DNC (Pins 6, 12, 18, 19 UFD Only): Do Not Connect.
SDI (Pin 9/Pin 9): Serial Interface Data Input. Data is ap-
Exposed Pad (Pin 21 UFD Only): Ground. The exposed
plied to SDI for transfer to the device at the rising edge
pad must be soldered to the PCB.
of SCK. The LTC2600, LTC2610 and LTC2620 accept input
word lengths of either 24 or 32 bits.

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 LTC2600/LTC2610/LTC2620
BLOCK DIAGRAM
(20) GND 1 16 VCC (17)

REGISTER

REGISTER

REGISTER

REGISTER
INPUT

INPUT
DAC

DAC
(1) VOUTA 2 DAC A DAC H 15 VOUTH (16)

REGISTER

REGISTER

REGISTER

REGISTER
INPUT

INPUT
DAC

DAC
(2) VOUTB 3 DAC B DAC G 14 VOUTG (15)

REGISTER

REGISTER

REGISTER

REGISTER
INPUT

INPUT
DAC

DAC
(3) VOUTC 4 DAC C DAC F 13 VOUTF (14)
REGISTER

REGISTER

REGISTER

REGISTER
INPUT

INPUT
DAC

DAC
(4) VOUTD DAC D DAC E (13)
5 12 VOUTE

(5) REF 6 11 CLR (11)

POWER-ON
RESET
CONTROL DECODE
LOGIC
(7) CS/LD 7 10 SDO (10)

(8) SCK 8 32-BIT SHIFT REGISTER 9 SDI (9)

2600 BD02

NOTE: NUMBERS IN PARENTHESIS REFER TO THE UFD PACKAGE

TIMING DIAGRAM
t1
t2 t3 t4 t6

SCK 1 2 3 23 24

t10

SDI

t5 t7

CS/LD

t8

SDO
2600 F01

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11
LTC2600/LTC2610/LTC2620
OPERATION
Power-On Reset Serial Interface
The LTC2600/LTC2610/LTC2620 clear the outputs to The CS/LD input is level triggered. When this input is taken
zero-scale when power is first applied, making system low, it acts as a chip-select signal, powering on the SDI and
initialization consistent and repeatable. SCK buffers and enabling the input shift register. Data (SDI
input) is transferred at the next 24 rising SCK edges. The
For some applications, downstream circuits are active during
4-bit command, C3-C0, is loaded first; then the 4-bit DAC
DAC power-up, and may be sensitive to nonzero outputs
address, A3-A0; and finally the 16-bit data word. The data
from the DAC during this time. The LTC2600/2610/2620
word comprises the 16-, 14- or 12-bit input code, ordered
contain circuitry to reduce the power-on glitch: the analog
MSB-to-LSB, followed by 0, 2 or 4 don’t-care bits (LTC2600,
outputs typically rise less than 10mV above zero-scale
LTC2610 and LTC2620 respectively). Data can only be
during power on if the power supply is ramped to 5V in 1ms
transferred to the device when the CS/LD signal is low.The
or more. In general, the glitch amplitude decreases as the
rising edge of CS/LD ends the data transfer and causes the
power supply ramp time is increased. See Power-On Reset
device to carry out the action specified in the 24-bit input
Glitch in the Typical Performance Characteristics section.
word. The complete sequence is shown in Figure 2a.
Power Supply Sequencing The command (C3-C0) and address (A3-A0) assignments
The voltage at REF (Pin 6) should be kept within the are shown in Table 1. The first four commands in the table
range –0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum consist of write and update operations. A write operation
Ratings). Particular care should be taken to observe these loads a 16-bit data word from the 32-bit shift register
limits during power supply turn-on and turn-off sequences, into the input register of the selected DAC, n. An update
when the voltage at VCC (Pin 16) is in transition. operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
Transfer Function data word becomes the active 16-, 14- or 12-bit input
code, and is converted to an analog voltage at the DAC
The digital-to-analog transfer function is:
output. The update operation also powers up the selected
⎛ k ⎞ DAC if it had been in power-down mode. The data path
VOUT(IDEAL) = ⎜ N ⎟ VREF and registers are shown in the Block Diagram.
⎝2 ⎠
While the minimum input word is 24 bits, it may optionally
where k is the decimal equivalent of the binary DAC be extended to 32 bits. To use the 32-bit word width, 8
input code, N is the resolution and VREF is the voltage at don’t-care bits are transferred to the device first, followed
REF (Pin 6). by the 24-bit word as just described. Figure 2b shows the

Table 1. ADDRESS (n)*

COMMAND* A3 A2 A1 A0
C3 C2 C1 C0 0 0 0 0 DAC A
0 0 0 0 Write to Input Register n 0 0 0 1 DAC B
0 0 0 1 Update (Power Up) DAC Register n 0 0 1 0 DAC C
0 0 1 0 Write to Input Register n, Update (Power Up) All n 0 0 1 1 DAC D
0 0 1 1 Write to and Update (Power Up) n 0 1 0 0 DAC E
0 1 0 0 Power Down n 0 1 0 1 DAC F
1 1 1 1 No Operation 0 1 1 0 DAC G
*Command and address codes not shown are reserved and should not be used. 0 1 1 1 DAC H
1 1 1 1 All DACs

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12
 LTC2600/LTC2610/LTC2620
OPERATION
INPUT WORD (LTC2600)

COMMAND ADDRESS DATA (16 BITS)

C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB
2600 TBL01

INPUT WORD (LTC2610)

COMMAND ADDRESS DATA (14 BITS + 2 DON’T-CARE BITS)

C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X

MSB LSB
2600 TBL02

INPUT WORD (LTC2620)

COMMAND ADDRESS DATA (12 BITS + 4 DON’T-CARE BITS)

C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
MSB LSB
2600 TBL03

32-bit sequence. The 32-bit word is required for daisy- are thus connected in series, effectively forming a single
chain operation, and is also available to accommodate input shift register which extends through the entire
microprocessors which have a minimum word width of chain. Because of this, the devices can be addressed and
16 bits (2 bytes). controlled individually by simply concatenating their input
words; the first instruction addresses the last device in
Daisychain Operation the chain and so forth. The SCK and CS/LD signals are
The serial output of the shift register appears at the SDO common to all devices in the series.
pin. Data transferred to the device from the SDI input is In use, CS/LD is first taken low. Then the concatenated
delayed 32 SCK rising edges before being output at the input data is transferred to the chain, using SDI of the
next SCK falling edge. first device as the data input. When the data transfer is
The SDO output can be used to facilitate control of multiple complete, CS/LD is taken high, completing the instruction
serial devices from a single 3-wire serial port (i.e., SCK, sequence for all devices simultaneously. A single device
SDI and CS/LD). Such a “daisychain” series is configured can be controlled by using the no-operation command
by connecting SDO of each upstream device to SDI of the (1111) for the other devices in the chain.
next device in the chain. The shift registers of the devices

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13
LTC2600/LTC2610/LTC2620
OPERATION
Power-Down Mode Voltage Outputs
For power-constrained applications, power-down mode Each of the 8 rail-to-rail amplifiers contained in these parts
can be used to reduce the supply current whenever less has guaranteed load regulation when sourcing or sinking
than eight outputs are needed. When in power-down, the up to 15mA at 5V (7.5mA at 3V).
buffer amplifiers and reference inputs are disabled, and Load regulation is a measure of the amplifier’s ability to
draw essentially zero current. The DAC outputs are put maintain the rated voltage accuracy over a wide range of
into a high impedance state, and the output pins are pas- load conditions. The measured change in output voltage
sively pulled to ground through individual 90k resistors. per milliampere of forced load current change is expressed
When all eight DACs are powered down, the master bias in LSB/mA.
generation circuit is also disabled. Input- and DAC-register
contents are not disturbed during power-down. DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
Any channel or combination of channels can be put into units from LSB/mA to Ohms. The amplifiers’ DC output
power-down mode by using command 0100b in combi- impedance is 0.025Ω when driving a load well away from
nation with the appropriate DAC address, (n). The 16-bit the rails.
data word is ignored. The supply and reference currents
are reduced by approximately 1/8 for each DAC powered When drawing a load current from either rail, the output
down; the effective resistance at REF (Pin 6) rises accord- voltage headroom with respect to that rail is limited by
ingly, becoming a high impedance input (typically > 1GΩ) the 25Ω typical channel resistance of the output devices;
when all eight DACs are powered down. e.g., when sinking 1mA, the minimum output voltage =
25Ω • 1mA = 25mV. See the graph Headroom at Rails vs
Normal operation can be resumed by executing any Output Current in the Typical Performance Characteristics
command which includes a DAC update, as shown in section.
Table 1. The selected DAC is powered up as its voltage
output is updated. The amplifiers are stable driving capacitive loads of up
to 1000pF.
There is an initial delay as the DAC powers up before it
begins its usual settling behavior. If less than eight DACs Board Layout
are in a powered-down state prior to the update command,
the power-up delay is 5μs. If, on the other hand, all eight The excellent load regulation and DC crosstalk performance
DACs are powered down, then the master bias genera- of these devices is achieved in part by keeping “signal”
tion circuit is also disabled and must be restarted. In this and “power” grounds separated internally and by reducing
case, the power-up delay is greater: 12μs for VCC = 5V, shared internal resistance to just 0.005Ω.
30μs for VCC = 3V.

2600fe

14
 LTC2600/LTC2610/LTC2620
OPERATION
The GND pin functions both as the node to which the refer- add directly to the effective DC output impedance of the
ence and output voltages are referred and as a return path device (typically 0.025Ω), and will degrade DC crosstalk.
for power currents in the device. Because of this, careful Note that the LTC2600/LTC2610/LTC2620 are no more
thought should be given to the grounding scheme and susceptible to these effects than other parts of their type;
board layout in order to ensure rated performance. on the contrary, they allow layout-based performance
The PC board should have separate areas for the analog improvements to shine rather than limiting attainable
and digital sections of the circuit. This keeps digital signals performance with excessive internal resistance.
away from sensitive analog signals and facilitates the use
Rail-to-Rail Output Considerations
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each In any rail-to-rail voltage output device, the output is limited
other. to voltages within the supply range.
Digital and analog ground planes should be joined at only Since the analog outputs of the device cannot go below
one point, establishing a system star ground as close to ground, they may limit for the lowest codes as shown
the device’s ground pin as possible. Ideally, the analog in Figure 3b. Similarly, limiting can occur near full scale
ground plane should be located on the component side of when the REF pin is tied to VCC. If VREF = VCC and the DAC
the board, and should be allowed to run under the part to full-scale error (FSE) is positive, the output for the highest
shield it from noise. Analog ground should be a continuous codes limits at VCC as shown in Figure 3c. No full-scale
and uninterrupted plane, except for necessary lead pads limiting can occur if VREF is less than VCC – FSE.
and vias, with signal traces on another layer. Offset and linearity are defined and tested over the region
The GND pin of the part should be connected to analog of the DAC transfer function where no output limiting can
ground. Resistance from the GND pin to system star occur.
ground should be as low as possible. Resistance here will

2600fe

15
16
CS/LD

SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

SDI C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

OPERATION

YYYY F02a

COMMAND WORD ADDRESS WORD DATA WORD

24-BIT INPUT WORD

Figure 2a. LTC2600 24-Bit Load Sequence (Minimum Input Word).

LTC2610 SDI Data Word: 14-Bit Input Code + 2 Don’t-Care Bits;
LTC2620 SDI Data Word: 12-Bit Input Code + 4 Don’t-Care Bits
LTC2600/LTC2610/LTC2620

CS/LD

SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

SDI X X X X X X X X C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DON’T CARE COMMAND WORD ADDRESS WORD DATA WORD

SDO X X X X X X X X C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

PREVIOUS 32-BIT INPUT WORD CURRENT

t1 32-BIT
t2 INPUT WORD
YYYY F02b
SCK 17 18
t3 t4
SDI D15 D14
t8
SDO PREVIOUS D15 PREVIOUS D14

Figure 2b. LTC2600 32-Bit Load Sequence (Required for Daisy-Chain Operation).
LTC2610 SDI/SDO Data Word: 14-Bit Input Code + 2 Don’t-Care Bits;
LTC2620 SDI/SDO Data Word: 12-Bit Input Code + 4 Don’t-Care Bits

2600fe
 LTC2600/LTC2610/LTC2620
OPERATION
POSITIVE
VREF = VCC FSE

VREF = VCC
OUTPUT
VOLTAGE

OUTPUT
VOLTAGE
INPUT CODE
(c)
OUTPUT
VOLTAGE

0 32, 768 65, 535

INPUT CODE
(a)
0V
NEGATIVE INPUT CODE
OFFSET
(b) 2600 F03

Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect
of Negative Offset for Codes Near Zero-Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale

PACKAGE DESCRIPTION
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)

.045 ±.005 .189 – .196*

(4.801 – 4.978)
.009
(0.229)
16 15 14 13 12 11 10 9 REF

.254 MIN .150 – .165

.229 – .244 .150 – .157**

(5.817 – 6.198) (3.810 – 3.988)

.0165 ± .0015 .0250 BSC

RECOMMENDED SOLDER PAD LAYOUT
1 2 3 4 5 6 7 8

.015 ± .004
× 45° .0532 – .0688 .004 – .0098
(0.38 ± 0.10)
(1.35 – 1.75) (0.102 – 0.249)
.007 – .0098
0° – 8° TYP
(0.178 – 0.249)

.016 – .050 .008 – .012 .0250 GN16 (SSOP) 0204

(0.406 – 1.270) (0.203 – 0.305) (0.635)
NOTE: TYP BSC
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

2600fe

17
LTC2600/LTC2610/LTC2620
PACKAGE DESCRIPTION
UFD Package
20-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1711 Rev B)

0.70 p0.05

2.65 p 0.05
4.50 p 0.05 1.50 REF
3.10 p 0.05
3.65 p 0.05

PACKAGE OUTLINE

0.25 p0.05
0.50 BSC
2.50 REF
4.10 p 0.05
5.50 p 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED PIN 1 NOTCH
R = 0.20 OR
0.75 p 0.05 1.50 REF C = 0.35
4.00 p 0.10 R = 0.05 TYP
(2 SIDES) 19 20

0.40 p 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2

5.00 p 0.10
2.50 REF
(2 SIDES)

3.65 p 0.10

2.65 p 0.10

(UFD20) QFN 0506 REV B

0.200 REF R = 0.115 0.25 p 0.05

0.00 – 0.05 TYP 0.50 BSC
BOTTOM VIEW—EXPOSED PAD

NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE

2600fe

18
 LTC2600/LTC2610/LTC2620
REVISION HISTORY (Revision history begins at Rev D)

REV DATE DESCRIPTION PAGE NUMBER

D 03/10 Revise GN Part Markings in Order Information 2
E 05/10 Changed “No Connect” pins to “Do Not Connect” in Pin Configuration and Pin Functions sections 2, 10

2600fe

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19
LTC2600/LTC2610/LTC2620
TYPICAL APPLICATION
Schematic for LTC2600 Demonstration Circuit DC579. The Outputs Are Measured by an Onboard LTC2428
1 1 VCC VREF VCC
TP1 TP2
C1
R1, R3, R4 0.1μF
4 5 R1 are 4.99k, 1%
VSS SDA R2
R3 7.5k C2
3 6 6
A2 SCL 0.1μF
2 7 R4 11 REF 16
A1 WP CLR VCC
C3
1 8 0.1μF 2 1 1
A0 VCC VOUTA TP3 TP14
3 DAC A GND
U1 VOUTB
24LC025 4 1 TP4 1 TP15
VOUTC
SCK 8 5 DAC B GND
SCK VOUTD
CS 7 12 1 TP5
LS/LD VOUTE
13 DAC C
14 + + 13 VOUTF
12 11 9 14 1 TP6
+ + SDI VOUTG
10 9 10 15 DAC D
+ + SDO VOUTH
8 + + 7 MOSI 1 TP7
GND
6 + + 5 MISO DAC E VREF VCC VCC
4 3 1 U2
+ + 1 1 TP8
2 1 TP16 LTC2600CGN
5V + + VIN DAC F
C4 C5
J1 1 TP9 0.1μF 0.1μF
HD2X7 DAC G R5
7.5k
1 TP10 JP1
C10 R8 3 ON/OFF
DAC H
100pF 22Ω 2
DISABLE
VIN 7 4 3 2 8 ADC
U4 1
LT1236ACS8-5 MUXOUT ADCIN FSSET VCC VCC
2 6 VREF
VIN VOUT
1 9 CH0
5V 1 TP11 10 CH1 23 R6
GND CSADC
2 VREF 7.5k
4 4.096V 11 CH2 20 CS
C6 3 JP2 C7 CSMUX
4.7μF 12 CH3 25
0.1μF VREF 4-/8-CHANNEL 20-BIT SCK
6.3V 13 CH4 + 19 SCK
MUX ADC CLK
U5 14 CH5 21
DIN
LT1461ACS8-4 15 CH6 – 24
2 6 SD0
VCC 17 CH7 LTC2424/LTC2428
VIN VOUT
3 1 26
SHDN 5VREF 1 TP12 FO
GND 5 ZSSET
2 VCC GND GND GND GND GND GND GND R7
C9 4 C8 REGULATOR
3 JP3 U3 1 6 16 18 22 27 28 7.5k
0.1μF 1μF 1 TP13
16V VCC LTC2428CG
GND

5V

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
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LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1654 Dual 14-Bit Rail-to-Rail VOUT DAC Programmable Speed/Power, 3.5μs/750μA, 8μs/450μA
LTC1655/LTC1655L Single 16-Bit VOUT DAC with Serial Interface in SO-8 VCC = 5V(3V), Low Power, Deglitched
LTC1657/LTC1657L Parrallel 5V/3V 16-Bit VOUT DAC Low Power, Deglitched, Rail-to-Rail VOUT
LTC1660/LTC1665 Octal 10/8-Bit VOUT DAC in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output
LTC1821 Parallel 16-Bit Voltage Output DAC Precision 16-Bit Settling in 2μs for 10V Step

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LT 0510 REV E • PRINTED IN USA

20 Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2003