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Weltrend Semiconductor, Inc.

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WT7518 / WT7518D
PC POWER SUPPLY SUPERVISOR

Data Sheet

REV. 3.00

May 05, 2004

The information in this document is subject to change without notice.

Weltrend Semiconductor, Inc. All Rights Reserved.

新竹市科學工業園區工業東九路24號2樓
2F, No. 24, Industry E. 9 th RD., Science-Based Industrial Park, Hsin-Chu, Taiwan
TEL:886-3-5780241 FAX:886-3-5794278.5770419
Email:support@weltrend.com.tw
 WT7518 / WT7518D
Rev. 3.00

GENERAL DESCRIPTION
The WT7518 series provides four or two protection circuits for over current detector (OCD), fault
voltage level output and external delay control signal glitches for 14pins package.
The current detector level setting by ISn and RI pin.

FEATURES
• The Over Current Detector (OCD) monitors IS1~IS4 input current sense.
• Fault protection (FPOB) are Open Drain Output.
• 75 ms time delay for OCD.
• 38 ms for PSONB input signal De–bounce.
• Adjustable internal signal De–glitches by DELAY pin only for 14pins package.
• Under voltage lockout with hysteresis

PIN ASSIGNMENT AND PACKAGE TYPE

Pin assignment

WT7518 WT7518D

GND 1 14 VCC GND 1 8 VCC

DELAY 2 13 FPOB RI 2 7 FPOB
PSONB 3 12 VS1 3 6
IS4 IS2
RI 4 11 VS4 IS1 4 5 VS2
VS1 5 10 IS3
IS1 6 9 VS3
VS2 7 8 IS2

ORDERING INFORMATION
PACKAGE 14–Pin Plastic DIP 14–Pin Plastic SOP
WT7518–N144WT WT7518–S144WT
Lead–Free（Pb） WT7518–N144WT Pb WT7518–S144WT Pb

PACKAGE 8–Pin Plastic DIP 8–Pin Plastic SOP

WT7518D–N080WT WT7518D–S080WT
Lead–Free（Pb） WT7518D–N080WT Pb WT7518D–S080WT Pb
※ The Top-Side Marking would been added a dot（●）in the right side for lead-free package.

Weltrend Semiconductor, Inc.

Page 2
 WT7518 / WT7518D
Rev. 3.00

PIN DESCRIPTION
Pin Name TYPE Description
GND P Ground
DELAY IO Adjust OCD de–glitch time by connect CAP. to ground
PSONB I On/Off switch input
RI I Current sense adjust input
st
VS1 I 1 over current protection sense input
st
IS1 I 1 over current protection sense input
nd
VS2 I 2 over current protection sense input
nd
IS2 I 2 over current protection sense input
rd
VS3 I 3 over current protection sense input
rd
IS3 I 3 over current protection sense input
th
VS4 I 4 over current protection sense input
th
IS4 I 4 over current protection sense input
FPOB O Fault protection output pin, open drain output
VCC P Power supply

FUNCTION DESCRIPTION
ORDERING UVLO LATCH FPL power on state
WT7518 N144/S144 4.5V/3.3V un–latch Low
WT7518D N080/S080 10V/8V un–latch Low

ABSOLUTE MAXIMUM RAT INGS

Parameter Min. Max. Unit
Supply voltage, VCC WT7518, WT7518D –0.3 16 V
Input voltage PSONB –0.3 7 V
VS1, VS2, VS3, VS4 –0.3 VCC+0.3 V
IS1, IS2, IS3, IS4 –0.3 VCC+0.3 V
Output voltage FPOB –0.3 VCC+0.3 V
Operating temperature -40 125 ℃
Storage temperature -55 150 ℃
*Note: Stresses above those listed may cause permanent damage to the devices

Weltrend Semiconductor, Inc.

Page 3
 WT7518 / WT7518D
Rev. 3.00

RECOMMENDED OPERATING CONDITIONS

Parameter Conditions Min. Typ. Max. Unit
Supply voltage, VCC 12 15 V
Input voltage PSONB 7 V
VS1, VS2, VS3, VS4 VCC V
IS1, IS2, IS3, IS4 VCC V
Output voltage FPOB 7 V
Output sink current FPOB 30 mA
VCC rising time 1 ms
Output current for RI RI 10 65 uA

ELECTRICAL CHARACTERISTICS, at Ta=25°C and V CC=12V

PSONB
Parameter Condition Min. Typ. Max. Unit
Input pull–up current PSONB= 0V 150 uA
High–level input voltage 2.0 V
Low–level input voltage 0.8 V

UNDER VOLTAGE LOCKOUT

Parameter Condition Min. Typ. Max. Unit
Start voltage 144 4.2 4.5 4.8 V
080 9.3 10.0 10.7 V
Min. operating voltage after turn on 144 3.0 3.3 3.6 V
080 7.3 8.0 8.7 V

TOTAL DEVICE
Parameter Condition Min. Typ. Max. Unit
Icc Supply current PSONB= 5V 1 mA
ILEAKAGE Leakage current (FPOB) V(FPOB) = 5V 5 uA
VOL Low level output voltage (FPOB) Isink =10mA 0.3 V
Isink =30mA 0.7
Input offset voltage of OCP comparators -5 5 mV

SWITCHING CHARACTERISTICS
Parameter Condition Min. Typ. Max. Unit
tdb1 De–bounce time (PSONB) 32 38 61 ms
tdb2 De–bounce time (PSONB) 32 38 61 ms
tg1 De–glitch time for OCD state active WT7518
64 80 96 us
DELAY=47pF, note1
WT7518D 120 150 180 us
tg2 De–glitch time for OCD state release WT7518
128 160 192 us
DELAY=47pF, note1
WT7518D 240 300 360 us
tdelay3 Internal OCD delay time after FPOB go low 65 75 122 ms
note1：Please refer to Fig.1 for the relation of OCD De–glitch time and delay cap.

Weltrend Semiconductor, Inc.

Page 4
 WT7518 / WT7518D
Rev. 3.00

BLOCK DIAGRAM
144 ( without latch and FPL power on state “low”)

Internal Power
UVLO

Preset Reset

PSONB 38mS 75mS

De–bounce Delay

VS1
–
+
IS1

8*IREF

VS2
–
+ FPOB
IS2
De–bounce

8*IREF

VS3 DELAY
–
+
IS3

8*IREF

1.2V
VS4
– +
IREF
+ –
IS4

RI
8*IREF

Weltrend Semiconductor, Inc.

Page 5
 WT7518 / WT7518D
Rev. 3.00

BLOCK DIAGRAM
080 ( without latch and FPL power on state “low”)

VCC

UVLO

Reset Reset FPOB

75mS 150uS/300uS
Delay De–bounce

VS1
–
+
IS1

8*IREF
1.2V

+
VS2 IREF
– –
+
IS2
RI

8*IREF

Weltrend Semiconductor, Inc.

Page 6
 WT7518 / WT7518D
Rev. 3.00

APPLICATION CIRCUIT VCC

WT7518

5VSB 1 14
GND VCC VCC

10K 2 13
DELAY FPOB
300
3 12
PSONB PSONB IS4
–
0.01uF 4 11 +
RI VS4

5 10
VS1 IS3
+ –
– 6 9 +
IS1 VS3

7 8
VS2 IS2
+
–

VCC

WT7518D

1 14
GND VCC VCC

2 13
RI FPOB

3 12
VS1 IS2
+ –
– 4 11 +
IS1 VS2

Weltrend Semiconductor, Inc.

Page 7
 WT7518 / WT7518D
Rev. 3.00

APPLICATION NOTE

When the current cross inductor raised, inductor voltage raised.

And when inductor voltage exceeded resistor voltage, the OCP active.
We can setup OCP point by the following equation

Let VR = VL
R * IR = RL * IL
∵ IR = 8 * IREF
R * (8 * VREF / RI) = RL * IL
R = (RL * IL) / (8 * VREF / RI) ––––– (1)

OCD de-glitch time vs delay cap. tg1 (us) tg2 (us)

350
OCD de-glitch time ( uS )

300

250

200

150

100

50

0
1 10 100
delay Cap. ( pF )

Fig.1 OCD de–glitch time vs delay cap.

Weltrend Semiconductor, Inc.

Page 8
 WT7518 / WT7518D
Rev. 3.00

APPLICATION TIMMING

For 144 – FPOB without lacth and FPL power on state “low”

PSONB

OCD
tdb1 tdelay3 tg1
FPOB
tg2

For 080 – FPOB without lacth and FPL power on state “low”

VCC Start voltage=10V Stop voltage=8V

UVLO

OCD
tdelay3 tg1
FPOB
tg2

Enable OCD

Weltrend Semiconductor, Inc.

Page 9
 WT7518 / WT7518D
Rev. 3.00

MECHANICAL INFORMATION
PLASTIC DUAL–IN–LINE PACKAGE

NOTE 1：All linear dimensions are in inches（millimeters）.

NOTE 2：This drawing is subject to change without notice.
NOTE 3：Falls within JEDEC MS–001

Weltrend Semiconductor, Inc.

Page 10
 WT7518 / WT7518D
Rev. 3.00

PLASTIC DUAL–IN–LINE PACKAGE

NOTE 1：All linear dimensions are in inches（millimeters）.

NOTE 2：This drawing is subject to change without notice.
NOTE 3：Falls within JEDEC MS–001

Weltrend Semiconductor, Inc.

Page 11
 WT7518 / WT7518D
Rev. 3.00

PLASTIC SMALL–OUTLINE PACKAGE

NOTE 1：All linear dimensions are in inches（millimeters）.

NOTE 2：This drawing is subject to change without notice.
NOTE 3：Falls within JEDEC MS–012

Weltrend Semiconductor, Inc.

Page 12