EEL 4783: HDL in Digital System Design: Lecture 2: The Verilog Language
EEL 4783: HDL in Digital System Design: Lecture 2: The Verilog Language
EEL 4783: HDL in Digital System Design: Lecture 2: The Verilog Language
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Behavioral Modeling
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How Verilog Is Used
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Two Main Components of Verilog
• Structure (Plumbing)
– Verilog program build from modules with I/O interfaces
– Modules may contain instances of other modules
– Modules contain local signals, etc.
– Module configuration is static and all run concurrently
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Two Main Data Types
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Four-valued Data
• 0, 1
– Obvious
• Z
– Output of an undriven tri-state driver
– Models case where nothing is setting a wire’s value
• X
– Models when the simulator can’t decide the value
– Initial state of registers
– When a wire is being driven to 0 and 1 simultaneously
– Output of a gate with Z inputs
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Four-valued Logic
0 1 X Z
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Structural Modeling
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Nets and Registers
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Modules and Instances
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Instantiating a Module
• Instances of
• look like
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Gate-level Primitives
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Delays on Primitive Instances
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User-Defined Primitives
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A Carry Primitive
?00 : 0;
11? : 1;
1?1 : 1;
?11 : 1;
endtable
endprimitive
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A Sequential Primitive
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Behavioral Modeling
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Initial and Always Blocks
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Initial and Always
initial begin
#10 a = 1; b = 0;
#10 a = 0; b = 1;
end
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Procedural Assignment
sum = a + b + cin;
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Imperative Statements
if (select == 1) y = a;
else y = b;
case (op)
2’b00: y = a + b;
2’b01: y = a – b;
2’b10: y = a ^ b;
default: y = ‘hxxxx;
endcase
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For Loops
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While Loops
i = 0;
while (I <= 15) begin
output = i;
#10 i = i + 1;
end
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Modeling A Flip-Flop With Always
reg q;
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Blocking vs. Nonblocking
• Fundamental problem:
– In a synchronous system, all flip-flops sample
simultaneously
– In Verilog, always @(posedge clk) blocks run in some
undefined sequence
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A Flawed Shift Register
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Non-blocking Assignments
Nonblocking rule:
RHS evaluated when
• This version does work: assignment runs
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Nonblocking Can Behave Oddly
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Nonblocking Looks Like Latches
1 a
a <= 1;
b <= a;
c <= b; “ b ”
c
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Building Behavioral Models
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Modeling FSMs Behaviorally
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FSM with Combinational Logic
Output o is declared a reg
because it is assigned
procedurally, not because it
module FSM(o, a, b, reset); holds state
output o;
reg o;
input a, b, reset;
Combinational block must be
reg [1:0] state, nextState; sensitive to any change on
any of its inputs
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FSM from Combinational Logic
Nonblocking assignments
always @(posedge clk or reset) used throughout to ensure
if (reset) state <= 2’b00; coherency.
else case (state) RHS refers to values
calculated in previous clock
2’b00: begin cycle
state <= a ? 2’b00 : 2’b01;
o <= a & b;
end
2’b01: begin state <= 2’b10; o <= 0; end
endcase 39
Simulating Verilog
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How Are Simulators Used?
Stimulus
Response
Result
checker
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Writing Testbenches
Inputs to device under test
module test;
Device under test
reg a, b, sel;
initial begin
$monitor($time,, “a = %b b=%b sel=%b y=%b”,
a, b, sel, y); Stimulus generated by sequence
a = 0; b= 0; sel = 0; of assignments and delays
#10 a = 1;
#10 sel = 1;
#10 b = 1;
end
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Simulation Behavior
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Two Types of Events
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Simulation Behavior
• #42
– Schedule process to resume 42 time units from now
• wait(cf & of)
– Resume when expression “cf & of” becomes true
• @(a or b or y)
– Resume when a, b, or y changes
• @(posedge clk)
– Resume when clk changes from 0 to 1
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Simulation Behavior
while (~ready)
count = count + 1;
• Instead, use
wait(ready);
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Simulation Behavior
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Simulation Behavior
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Verilog and Logic Synthesis
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Logic Synthesis
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Logic Synthesis
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Translating Verilog into Gates
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What Can Be Translated
• Structural definitions
– Everything
• Behavioral blocks
– Depends on sensitivity list
– Only when they have reasonable interpretation as
combinational logic, edge, or level-sensitive latches
– Blocks sensitive to both edges of the clock, changes on
unrelated signals, changing sensitivity lists, etc. cannot be
synthesized
• User-defined primitives
– Primitives defined with truth tables
– Some sequential UDPs can’t be translated (not latches or
flip-flops)
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What Isn’t Translated
• Initial blocks
– Used to set up initial state or describe finite testbench stimuli
– Don’t have obvious hardware component
• Delays
– May be in the Verilog source, but are simply ignored
• A variety of other obscure language features
– In general, things heavily dependent on discrete-
event simulation semantics
– Certain “disable” statements
– Pure events
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Register Inference
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Register Inference
• Combinational:
Sensitive to changes on all of
the variables it reads
reg y;
always @(a or b or sel)
if (sel) y = a; Y is always assigned
else y = b;
• Sequential:
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Register Inference
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Latch Vs Flip-Flop Registers in Digital
Design & FPGA Synthesis
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Register Inference
always @(a or b)
case ({a, b})
2’b00: f = 0; f is always assigned
2’b01: f = 1;
2’b10: f = 1;
default: f = 0;
endcase
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Inferring Latches with Reset
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Simulation-synthesis Mismatches
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Compared to VHDL
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Lecture schedule
See Webpage:
www.eecs.ucf.edu/~mingjie/EEL4783_2012
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Final issues
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