AWR Microwave Office MMIC Getting Started Guide: Product Version 16

AWR Microwave Office MMIC
Getting Started Guide

Product Version 16
AWR Microwave Office MMIC Getting Started Guide
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Table of Contents
1. Introduction .................................................................................................................................... 1–1
Introducing the AWR Design Environment Platform .......................................................................... 1–1
About This Guide ....................................................................................................................... 1–2
Prerequisites ...................................................................................................................... 1–2
Contents of this Guide ......................................................................................................... 1–2
Conventions Used in This Guide ............................................................................................ 1–2
Getting Additional Information ...................................................................................................... 1–3
Cadence AWR Knowledge Base ............................................................................................ 1–3
Documentation ................................................................................................................... 1–3
Online Help ....................................................................................................................... 1–4
Online Support ................................................................................................................... 1–4
2. AWR Design Environment Platform .................................................................................................... 2–1
Starting AWR Software Programs .................................................................................................. 2–2
AWR Design Environment Platform Components ............................................................................. 2–3
Basic Operations ......................................................................................................................... 2–4
Working with Projects ......................................................................................................... 2–4
Project Contents ......................................................................................................... 2–5
Creating, Opening, and Saving Projects ........................................................................... 2–5
Opening Example Projects ........................................................................................... 2–5
Importing Test Benches ................................................................................................ 2–6
Working with Schematics and Netlists in AWR Microwave Office ............................................... 2–7
Adding Data to Netlists ................................................................................................ 2–8
Working with System Diagrams in VSS .................................................................................. 2–8
Connecting Element and System Block Nodes .......................................................................... 2–9
Using the Elements Browser ................................................................................................ 2–10
Adding Subcircuits to Schematics ................................................................................ 2–11
Adding Subcircuits to System Diagrams ........................................................................ 2–12
Adding Ports to Schematics and System Diagrams .......................................................... 2–12
Creating EM Structures ...................................................................................................... 2–12
Adding EM Structure Drawings ................................................................................... 2–13
Creating a Layout with AWR Microwave Office .................................................................... 2–14
Modifying Layout Attributes and Drawing Properties ....................................................... 2–15
Using the Layout Manager .......................................................................................... 2–16
Creating Output Graphs and Measurements ........................................................................... 2–17
Setting Simulation Frequency and Performing Simulations ........................................................ 2–18
Tuning and Optimizing Simulations .............................................................................. 2–19
Using Command Shortcuts ................................................................................................. 2–19
Using Scripts and Wizards .......................................................................................................... 2–20
Using Online Help ..................................................................................................................... 2–20
3. MMIC: Designing MMICs ................................................................................................................ 3–1
Opening the Design ..................................................................................................................... 3–1
Organizing the Design ................................................................................................................. 3–1
4. MMIC: Layout Features ................................................................................................................... 4–1
Enabling Two Click Entry Mode .................................................................................................... 4–1
Specifying Line Types ................................................................................................................. 4–1
Using Automatic Interconnect ....................................................................................................... 4–5
Using Layout Snapping ................................................................................................................ 4–7
Snapping to Fit ......................................................................................................................... 4–16
Using Intelligent Parameter Syntax ............................................................................................... 4–18
Getting Started Guide iii

Contents
5. MMIC: Extraction and EM Simulation ................................................................................................ 5–1

Extracting Across Hierarchy ......................................................................................................... 5–1
Configuring Groups .................................................................................................................... 5–3
Using Incremental Extraction ........................................................................................................ 5–5
Using Data Sets .......................................................................................................................... 5–9
Simplifying Geometry ................................................................................................................ 5–14
6. MMIC: Verifying Designs ................................................................................................................. 6–1
Using the Connectivity Highlighter ................................................................................................ 6–1
Using the Connectivity Checker ..................................................................................................... 6–4
Using Layout Vs Schematic (LVS) ................................................................................................. 6–8
Design Rule Checking (DRC) ....................................................................................................... 6–8
Completing the MMIC Example .................................................................................................. 6–13
7. MMIC: Supplemental Topics ............................................................................................................. 7–1
Navigating Design Hierarchy: Schematic and Layout ......................................................................... 7–1
Cross-selecting Between Schematic and Layout ................................................................................ 7–5
Using Intelligent Parameter Syntax ................................................................................................ 7–7
Layout: Using Automatic Interconnect .......................................................................................... 7–10
Using More Than Two Connections at a Node ........................................................................ 7–10
Working Through Hierarchy ................................................................................................ 7–13
Artwork Cells and EM Structures ......................................................................................... 7–15
Discontinuities Without Lines .............................................................................................. 7–16
Layout: Changing Background Color ............................................................................................ 7–17
Layout: Snapping Strategy .......................................................................................................... 7–17
Layout: Adding Text .................................................................................................................. 7–18
Index .......................................................................................................................................... Index–1
iv AWR Design Environment

Chapter 1. Introduction
The following AWR Design Environment Getting Started Guides are available:
• The AWR Microwave Office Getting Started Guide provides step-by-step examples that show you how to use AWR
Microwave Office software to create circuit designs.
• The AWR Analyst Getting Started Guide provides step-by-step examples that show you how to use Analyst software
to create and simulate 3D EM structures from the AWR Microwave Office program.
• AWR Microwave Office MMIC Getting Started Guide provides step-by-step examples that show you Monolithic
Microwave Integrated Circuit (MMIC) features and designs.
• AWR Visual System Simulator Getting Started Guide provides step-by-step examples that show you how to use AWR
VSS software to create system simulations and to incorporate AWR Microwave Office software circuit designs.
To set up the AWR Design Environment software for PCB style design, choose Tools > Create New Process to display
the Create New Process dialog box, then click the Help button for details on using this tool.
Introducing the AWR Design Environment Platform

This platform comprises two powerful tools that can be used together to create an integrated system or RF design
environment: AWR VSS and AWR Microwave Office software. These powerful tools are fully integrated in the AWR
Design Environment platform and allow you to incorporate circuit designs into system designs without leaving the design
environment.
AWR VSS software enables you to design and analyze end-to-end communication systems. You can design systems
composed of modulated signals, encoding schemes, channel blocks and system level performance measurements. You
can perform simulations using the AWR VSS software predefined transmitters and receivers, or you can build customized
transmitters and receivers from basic blocks. Based on your analysis needs, you can display BER curves, ACPR
measurements, constellations, and power spectrums, to name a few. AWR VSS software provides a real-time tuner that
allows you to tune the designs and then see your changes immediately in the data display.
AWR Microwave Office software enables you to design circuits composed of schematics and electromagnetic (EM)
structures from an extensive electrical model database, and then generate layout representations of these designs. You
can perform simulations using any of the Cadence AWR simulation engines, such as a linear simulator; the Cadence®
AWR® APLAC® HB simulator for nonlinear frequency-domain simulation and analysis; the AWR AXIEM 3D-planar
EM simulator; the Analyst 3D-FEM simulator; or transient circuit simulators (the APLAC transient simulator or an
optional Spectre simulator), and display the output in a wide variety of graphical forms based on your analysis needs.
You can then tune or optimize the designs and your changes are automatically and immediately reflected in the layout.
Statistical analysis allows you to analyze responses based on statistically varying design components.
The tool set spans the entire IC design flow, from system-level to circuit-level design and verification, including design
entry and schematic capture, time- and frequency-domain simulation and analysis, physical layout with automated
device-level place and route and integrated design rule checker (DRC), 3D full-field solver-based extraction with industry
gold standard high-speed extraction technology from OEA International, and a comprehensive set of waveform display
and analysis capabilities supporting complex RF measurements.
OBJECT ORIENTED TECHNOLOGY
At the core of the AWR Design Environment platform capability is advanced object-oriented technology. This technology
results in software that is compact, fast, reliable, and easily enhanced with new technology as it becomes available.
Getting Started Guide 1–1

About This Guide
About This Guide

Through working examples, this Getting Started Guide is designed to familiarize you with AWR Microwave Office,
AWR VSS, and Analyst software; and MMIC capabilities.
Prerequisites
You should be familiar with Microsoft® Windows® and have a working knowledge of basic circuit and/or system design
and analysis.
This document is available as a download from the Cadence AWR Knowledge Base.
If you are viewing this guide as online Help and intend to work through the examples, you can download and print out
the PDF version for ease of use.
Contents of this Guide

Chapter 2 provides an overview of the AWR Design Environment platform including the basic menus, windows,
components and commands.
In the AWR Microwave Office Getting Started Guide the subsequent chapters take you through hands-on examples that
show you how to use AWR Microwave Office software to create circuit designs including layout and AWR AXIEM 3D
planar EM layout and simulation.
In the Analyst Getting Started Guide the subsequent chapters take you through hands-on examples that show use of the
Analyst 3D Electromagnetic simulator for 3D EM simulation within AWR Microwave Office software. Use of 3D
parametric layout cells and a 3D Layout Editor is included.
In the AWR Microwave Office MMIC Getting Started Guide the subsequent chapters take you through hands-on examples
that allow you to work with Monolithic Microwave Integrated Circuit (MMIC) features and designs.
In the AWR Visual System Simulator Getting Started Guide the subsequent chapters take you through hands-on examples
that show you how to use AWR VSS software to create system simulations and to incorporate AWR Microwave Office
software circuit designs.
Conventions Used in This Guide

This guide uses the following typographical conventions:
Item Convention
Anything that you select (or click on) in the AWR Design Shown in a bold alternate font. Nested menu selections are
Environment program, such as menus, nested submenus, shown with a ">" to indicate that you select the first menu
menu options, dialog box options, buttons, and tab names item and then select the submenu item:
Choose File > New Project.

Text that you enter using the keyboard Shown in a bold within quotation marks:
Enter "my_project" in Project Name.

Keys or key combinations that you press Shown in a bold alternate font with initial capitals. Key
combinations using a "+" indicate that you press and hold
the first key while pressing the second key:
1–2 AWR Design Environment

Getting Additional Information
Item Convention
Press Alt+F1.
File names and directory paths Shown in italics:
See the DEFAULTS.LPF file.

There are multiple resources available for additional information and technical support for Cadence products.
Cadence AWR Knowledge Base

The Cadence AWR Knowledge Base includes these and other resources:
• Application Notes - Technical papers on various topics written by Cadence or our partners.
• Examples - Pages explaining project examples in the installed software or available for download.
• Licensing - A step-by-step guide to resolving most licensing problems.
• Questions - Frequently Asked Questions (FAQs) and answers for common customer issues.
• Scripts - Scripted utilities to help solve specific problems.
• Documentation - Downloadable copies of the latest released documentation.
• Videos - Short technical videos on how to accomplish specific tasks.
Documentation
Documentation for the AWR Design Environment platform includes:
• What's New in AWR Design Environment v16? presents the new or enhanced features, elements, system blocks, and
measurements for the current release. This document is available in the Help by clicking the Windows Start button
and choosing AWRDE 16 > AWR Design Environment Help and then expanding the Cadence AWR Design Environment
node on the Contents tab, or by choosing Help > What's New while in the program.
• The AWR Design Environment Installation Guide describes how to install the AWR Design Environment platform
and configure it for locked or floating licensing options. It also provides licensing configuration troubleshooting tips.
This document is downloadable from the Cadence AWR Knowledge Base.
• The AWR Design Environment User Guide provides an overview of the AWR Design Environment platform including
chapters on the user interface; using schematics/system diagrams, data files, netlists, graphs, measurements, and output
files; using variables and equations in projects, and more. In addition, an appendix providing guidelines for starting a
new design is included.
• The AWR Design Environment Simulation and Analysis Guide discusses simulation basics such as swept parameter
analysis, tuning/optimizing/yield, and simulation filters; and provides simulation details for DC, linear, AC, harmonic
balance, transient, and EM simulation/extraction theory and methods.
• The AWR Design Environment Dialog Box Reference provides a reference of many program dialog boxes with dialog
box graphics, overviews, option details, and information on how to access each dialog box.
• The AWR API Scripting Guide explains the basic concepts of AWR Design Environment scripting and includes coding
examples. It also provides information on the most useful objects, properties, and methods for creating scripts in the
AWR Script Development Environment (AWR SDE). In addition, this guide contains the AWR Design Environment
Component API list.

• The Quick Reference document lists keyboard shortcuts, mouse operations, and tips and tricks to optimize your use
of the AWR Design Environment platform. This document is available within the program by choosing Help > Quick
Reference. This is an excellent document to print and keep handy at your desk.
• Context sensitive Help is available for most operations or phases of design creation. To view an associated Help topic,
press the F1 key during design creation.
Documentation for AWR Microwave Office software includes:
• The AWR Microwave Office Layout Guide, which contains information on creating and viewing layouts for schematics
and EM structures, including use of the Layout Manager, Layout Process File, artwork cell creation/editing/properties,
Design Rule Checking, and other topics.
• The AWR Microwave Office Element Catalog, which provides complete reference information on all of the electrical
elements that you use to build schematics.
• The AWR Microwave Office Measurement Catalog, which provides complete reference information on the
"measurements" (for example, computed data such as gain, noise, power, or voltage) that you can choose as output
for your simulations.
Documentation for AWR VSS software includes:
• The AWR Visual System Simulator System Block Catalog, which provides complete reference information on all of
the system blocks that you use to build systems.
• The AWR Visual System Simulator Measurement Catalog, which provides complete reference information on the
measurements you can choose as output for your simulations.
• The AWR Visual System Simulator Modeling Guide, which contains information on simulation basics, RF modeling
capabilities, and noise modeling.
Documentation for the 3D Editor and Cadence® AWR® Analyst™-MP multi-physics simulator (stand-alone product
for multi-physics types of EM problems) includes:
• The What's New in Analyst-MP v16 (Analyst_Whats_New.pdf), which presents the new or enhanced features for both
the 3D Layout Editor and Analyst-MP simulator software.
• The Analyst-MP Getting Started Guide (Analyst_Getting_Started.pdf), which provides step-by-step examples that
show you how to use Analyst-MP simulator software.
• The Analyst User Guide (Analyst_User_Guide.pdf), which provides an overview of the 3D Editor and Analyst-MP
simulator software; including chapters on the user interface, structures, simulations, post-processing, variables, data
files, and scripting.
Online Help
All AWR Design Environment documentation is available as on-line Help.
To access online Help, choose Help from the menu bar or press F1 anywhere in the program. Context sensitive help is
available for elements and system blocks in the Elements Browser and within schematics or system diagrams, and for
measurements from the Add/Modify Measurement dialog box.
Online Support
The Cadence Learning and Support System is available from the Cadence Support website. You can navigate to this site
from the AWR Design Environment platform by choosing Help > Get Technical Support.

Chapter 2. AWR Design Environment Platform
The basic design flow in the Cadence ® AWR Design Environment® platform is shown in the following flow chart.
Create Project
File > New Project or File > New with Library
Set Units, Environment Options

Options > Project Options
Create Schematics/Diagrams (Microwave Office) Create Layout

Project > Add Schem./Sys. Diagram View > View Layout
View > View Schematic
Set Frequency, Simulation Options

(Microwave Office) Options > Def. Circuit Options
(VSS) Options > Def. System Options
Create Graphs/Measurements
Project > Add Graph
Project > Add Measurement
Simulate Circuit
(Microwave Office) Simulate > Analyze
(VSS) Simulate > Run Sys. Sim.
(Microwave Office) Optimizing Tuning

Simulate > Optimize Simulate > Tune
Set Optimization Goals Manually Vary Parameters

Project > Add Opt Goal Simulate > Tune Tool
Automatically: Automatically:
*Updates Schem./Sys. Diagrams *Updates Schem./Sys. Diagrams
*(Microwave Office) Updates Layout *(Microwave Office) Updates Layout
*Simulates *Simulates
*Updates Results/Graphs *Updates Results/Graphs
This chapter describes the windows, menus and basic operations for performing the following tasks in the AWR Design
Environment platform:
• Creating projects to organize and save your designs

• Creating system diagrams, circuit schematics, and EM structures
• Placing circuit elements into schematics
• Placing system blocks into system diagrams

Starting AWR Software Programs
• Incorporating subcircuits into system diagrams and schematics

• Creating layouts
• Creating and displaying output graphs
• Running simulations for schematics and system diagrams
• Tuning simulations
NOTE: The Quick Reference document lists keyboard shortcuts, mouse operations, and tips and tricks to optimize your
use of the AWR Design Environment platform. Choose Help > Quick Reference to access this document.
Starting AWR Software Programs

To start the AWR Design Environment platform:
1. Click the Windows Start button.

2. Choose All Programs > AWRDE 16 > AWR Design Environment 16.
The following main window displays.

AWR Design Environment Platform Components
Title bar
Menu bar
Toolbar
Project Browser
System diagrams
Circuit schematics
Workspace
Tabs
Status Window
Status bar
If the AWR Design Environment platform was not configured during installation to display in your Start menu, start the
application by double-clicking the This PC icon on your desktop, opening the drive and folder where you installed the
program, and double-clicking on MWOffice.exe, the AWR Design Environment platform application.
AWR Design Environment Platform Components

The AWR Design Environment platform contains the windows, components, menu selections and tools you need to
create linear and nonlinear schematics, set up EM structures, generate circuit layouts, create system diagrams, perform
simulations, and display graphs. Most of the basic procedures apply to Cadence® AWR® Microwave Office® software,
Cadence® AWR® Visual System Simulator™ and (VSS) communications and radar systems design software. The major
components of the AWR Design Environment platform are:

Basic Operations
Component Description
Title bar The title bar displays the name of the open project and any Process Design Kit (PDK) used with
the project.
Menu bar The menu bar comprises the set of menus located along the top of the window for performing
a variety of AWR Microwave Office and AWR VSS tasks.
Toolbar The toolbar is the row of buttons located just below the menu bar that provides shortcuts to
frequently used commands such as creating new schematics, performing simulations, or tuning
parameter values or variables. The buttons available depend on the functions in use and the
active window within the design environment (as well as any customization of toolbar button
groups). Position the cursor over a button to view the button name/function.
Workspace The workspace is the area in which you design schematics and diagrams, draw EM structures,
view and edit layouts, and view graphs. You can use the scrollbars to move around the workspace.
You can also use the zoom in and zoom out options from the View menu.
Project Browser Located by default in the left column of the window, this is the complete collection of data and
(Project tab) components that define the currently active project. Items are organized into a tree-like structure
of nodes and include schematics, system diagrams and EM structures, simulation frequency
settings, output graphs, user folders and more. The Project Browser is active when the AWR
Design Environment platform first opens, or when you click the Project tab. Right-click a node
in the Project Browser to access menus of relevant commands.
Elements Browser The Elements Browser contains a comprehensive inventory of circuit elements for building your
(Elements tab) schematics, and system blocks for building system diagrams for simulations. The Elements
Browser displays by default in the left column in place of the Project Browser when you click
the Elements tab.
Layout Manager The Layout Manager contains options for viewing and drawing layout representations, creating
(Layout tab) new layout cells, and working with artwork cell libraries. The Layout Manager displays by
default in the left column in place of the Project Browser when you click the Layout tab.
Status Window (Status The Status Window displays error, warning, and informational messages about the current
Window tab) operation or simulation. The Status Window displays by default at the bottom of the workspace
when you click the Status Window tab.
Status bar The bar along the very bottom of the design environment window that displays information
dependent on what is highlighted. For example, when an element in a schematic is selected, the
element name and ID displays. When a polygon is selected, layer and size information displays,
and when a trace on a graph is selected, the value of a swept parameter displays.
You can invoke many of the functions and commands from the menus and on the toolbar, and in some cases by
right-clicking a node in the Project Browser. This guide may not describe all of the ways to invoke a specific task.
Basic Operations
This section highlights the windows, menu choices, and commands available for creating simulation designs and projects
in the AWR Design Environment platform. Detailed use information is provided in the chapters that follow.
Working with Projects

The first step in building and simulating a design is to create a project. You use a project to organize and manage your
designs and everything associated with them in a tree-like structure.

Basic Operations
Project Contents
Because AWR Microwave Office software and AWR VSS software are fully integrated in the AWR Design Environment
platform, you can start a project based on a system design using AWR VSS software, or on a circuit design using AWR
Microwave Office software. The project may ultimately combine all elements. You can view all of the components and
elements in the project in the Project Browser. Modifications are automatically reflected in the relevant elements.
A project can include any set of designs and one or more linear schematics, nonlinear schematics, EM structures, or
system level blocks. A project can include anything associated with the designs, such as global parameter values, imported
files, layout views, and output graphs.
Creating, Opening, and Saving Projects
When you first start the AWR Design Environment platform, a default empty project titled "Untitled Project" is loaded.
Only one project can be active at a time. The name of the active project displays in the main window title bar.
After you create (name) a project, you can create your designs. You can perform simulations to analyze the designs and
see the results on a variety of graphical forms. Then, you can tune or optimize parameter values and variables as needed
to achieve the desired response. You can generate layout representations of the designs, and output the layout to a DXF,
GDSII, or Gerber file. See Appendix B, New Design Considerations in AWR Design Environment User Guide in the
AWR Design Environment User Guide for advanced guidelines on starting a new design. You can also transfer technology
and design information with Virtuoso and DE-HDL/Allegro platforms through a Cadence Unified Library. See Appendix E,
AWR Design Environment Interoperability with Virtuoso and Allegro in AWR Design Environment User Guide in the
AWR Design Environment User Guide for details.
To create a project choose File > New Project. Name the new project and the directory you want to write it to by choosing
File > Save Project As. The project name displays in the title bar.
To open an existing project, choose File > Open Project. To save the current project, choose File > Save Project. When you
save a project, everything associated with it is automatically saved. Cadence AWR projects are saved as *.emp files.
Opening Example Projects
Cadence provides a number of project examples (*.emp files) in the installation directory to demonstrate key concepts,
program functions and features, and show use of specific elements.
To search for and open example projects referenced in this guide:
1. Choose File > Open Example.
The Open Example Project dialog box displays with columns for the project name and keywords associated with each
example project.
2. Filter the list using "getting_started" as a keyword by Ctrl-clicking the Keywords column header and typing
"getting_started" in the text box at the bottom of the dialog box.
As shown in the following figure, the example list is filtered to display only those projects that have the "getting_started"
keyword associated with them.

Basic Operations
NOTE: You can filter examples by keyword or by file name. An inverted triangle in the column header indicates the
column on which your search is filtered. Press the Ctrl key while clicking a column header to change which column is
used to filter.
Importing Test Benches
Cadence provides several test bench examples that can serve as design guides for various applications such as mixers,
amplifiers, and oscillators. These test benches are set up for import into your working project.
To import a test bench into your project:
1. Choose File > Import Project.

2. Browse to C:\Program Files\AWR\AWRDE\16\Examples\ or C:\Program Files (x86)\AWR\AWRDE\16\Examples\
and import the desired test bench. The test bench project file names are prefaced with "TESTBENCH" as shown in
the following figure.

Basic Operations
Working with Schematics and Netlists in AWR Microwave Office

A schematic is a graphical representation of a circuit, while a netlist is a text-based description.
To create a schematic, right-click Circuit Schematics in the Project Browser, choose New Schematic, and then specify a
schematic name.
To create a netlist, right-click Netlists in the Project Browser, choose New Netlist, and then specify a netlist name and
type.
After you name the schematic or netlist, a window for it opens in the workspace and the Project Browser displays the
new item as a subnode under Circuit Schematics or Netlists. In addition, the menu bar and toolbar display new command
choices and buttons particular to building and simulating schematics or netlists.

Basic Operations
A Schematic window or
Netlist window opens in
the workspace
Right-click and choose

New Schematic
or

New Netlist
Adding Data to Netlists
When you create a netlist, an empty netlist window opens into which you type a text-based description of a schematic.
Netlist data is arranged in blocks in a particular order, where each block defines a different attribute of an element such
as units, equations, or element connections. For more information about creating netlists, see “Creating a Netlist” in AWR
Design Environment User Guide.
Working with System Diagrams in VSS

To create a system diagram, right-click System Diagrams in the Project Browser and choose New System Diagram, and
then specify a system diagram name.

Basic Operations
A System Diagram window

opens in the workspace

New System Diagram
After you name the system diagram, a window for it opens in the workspace and the Project Browser displays the new
item as a subnode under System Diagrams. In addition, the menu bar and toolbar display new command choices and
buttons particular to building and simulating systems.
Connecting Element and System Block Nodes

You can connect elements or system blocks directly by positioning them so their nodes touch. Small green boxes display
to indicate the connection. You can also connect elements with wires.
• To connect element or system block nodes with a wire, position the cursor over a node. The cursor displays as a wire
coil symbol. Click at this position to mark the beginning of the wire and drag the mouse to a location where a bend is
needed. Click again to mark the bend point. You can make multiple bends.
• Right-click to undo the last wire segment added.

Basic Operations
• To start a wire from another wire, select the wire, right-click and choose Add wire, then click to mark the beginning
of the wire.
• To terminate a wire, click on another element node or on top of another wire.
• To cancel a wire, press the Esc key.
• When placing or positioning an element, alignment guidelines automatically display when the element nodes align
with another element. To automatically add a wire between the nodes, press the Shift key when placing the element.
Using the Elements Browser

The Elements Browser gives you access to a comprehensive database of hierarchical groups of circuit elements for
schematics and system blocks for system diagrams. The Libraries folder in the Elements Browser provides a wide range
of electrical models and S-parameter files from manufacturers.
Circuit elements include models, sources, ports, probes, measurement devices, data libraries, and model libraries that
can be placed in a circuit schematic for linear and non-linear simulations.
System blocks include channels, math tools, meters, subcircuits, and other models for system simulations.
• To view elements or system blocks, click the Elements tab. The Elements Browser replaces the Project Browser
window.
• To expand and collapse the model categories, click the + or - symbol to the left of the category name to view or hide
its subcategories. When you click on a category/subcategory, the available models display in the lower window pane.
If there are more models than the window can show, a vertical scroll bar displays to allow you to scroll down to see
all of the models.
• To place a model into a schematic or system diagram, simply click and drag it into the window, release the mouse
button, right-click to rotate it if needed, position it, and click to place it.
• To edit model parameters, double-click the element graphic in the schematic or system diagram window. An Element
Options dialog box displays for you to specify new parameter values. You can also edit individual parameter values
by double-clicking the value in the schematic or system diagram and entering a new value in the text box that displays.
Press the Tab key to move to the next parameter when editing.

Basic Operations
Buttons for adding

Expand, then click
ground and ports
desired subcategory
Drag the desired

model into schematic
or system diagram
window
Elements tab diplays the

Elements Browser
NOTE: Choose Draw > More Elements to display the Add Circuit Element or Add System Block dialog box to search for
elements. Press the Ctrl key while clicking a column header to change which column is used to filter.
Adding Subcircuits to Schematics
Subcircuits allow you to construct hierarchical circuits by including a subcircuit block in a schematic (insert a schematic
inside of another schematic). The circuit block can be a schematic, a netlist, an EM structure, or a data file.
• To add a subcircuit to a schematic, click Subcircuits in the Elements Browser. The available subcircuits display in the
lower window pane. These include all of the schematics, netlists, and EM structures associated with the project, as
well as any imported data files defined for the project.
• To use a data file as a subcircuit, you must first create or add it to the project. To create a new data file, choose Project
> Add Data File > New Data File. To import an existing data file, choose Project > Add Data File > Import Data File. Any
new or imported data files automatically display in the list of available subcircuits in the Elements Browser.
• To place the desired subcircuit, simply click it and drag it into the schematic window, release the mouse button, position
it, and click to place it.

Basic Operations
• To edit subcircuit parameters, select the subcircuit in the schematic window, right-click, and choose Edit Subcircuit.
Either a schematic, netlist, EM structure, or data file opens in the workspace. You can edit it in the same way that you
would edit the individual circuit block types.
Adding Subcircuits to System Diagrams
Subcircuits allow you to construct hierarchical systems and to import results of circuit simulation directly into the system
block diagram.
• To create a subcircuit to a system diagram, choose Project > Add System Diagram > New System Diagram or Import
System Diagram and then click Subcircuits under System Blocks in the Element Browser. The available subcircuits
display in the lower window pane.
• To place the desired subcircuit, simply click and drag it into the system diagram window, release the mouse button,
position it, and click to place it.
• To edit subcircuit parameters, select the subcircuit in the system diagram window, right-click, and choose Edit Subcircuit.
• To add a system diagram as a subcircuit to another system diagram, you must first add ports to the system that is
designated as a subcircuit.
Adding Ports to Schematics and System Diagrams
To add ports to a schematic or system diagram, expand the Ports category in the Elements Browser. Under Circuit Elements
or System Blocks, click Ports or one of its subgroups, for example, Harmonic Balance. The available models display in
the lower window pane.
Drag the port into the schematic or system diagram window, right-click to rotate it if needed, position it, and click to
place it.
For a shortcut when placing ports and ground, click the Ground or Port buttons on the toolbar, position the ground or
port, and click to place it.
To edit port parameters, double-click the port in the schematic or system diagram window to display an Element Options
dialog box.
NOTE: You can change the port type after placing it by double-clicking the port and selecting a Port type on the Port
tab of the dialog box.
Creating EM Structures
EM structures are arbitrary multi-layered electrical structures such as spiral inductors with air bridges.
To create an EM structure, right-click the EM Structures node in the Project Browser, and choose New EM Structure.
After you specify an EM structure name and select a simulator, an EM structure window opens in the workspace and
the Project Browser displays the new EM structure under EM Structures. In addition, the menu and toolbar display new
choices particular to drawing and simulating EM structures.

Basic Operations
An EM structure window
opens in the workspace

New EM Structure
NOTE: The EM structure examples presented in this guide use Cadence® AWR® AXIEM® 3D planar EM analysis.
Adding EM Structure Drawings
Before you draw an EM structure, you must define an enclosure. The enclosure specifies things such as boundary
conditions and dielectric materials for each layer of the structure.
To define an enclosure, double-click Enclosure under your new EM structure in the Project Browser to display a dialog
box in which you can specify the required information.
After you define the enclosure, you can draw components such as rectangular conductors, vias, and edge ports in the
Layout Manager.
You can view EM structures in 2D (double-click the EM structure node in the Project Browser) and 3D (right-click the
EM structure node in the Project Browser and choose View 3D EM Layout), and you can view currents and electrical fields
using the Animate buttons on the EM 3D Layout toolbar.

Basic Operations
Display 2D and 3D
views of the structure
Double-click to define
an Enclosure
Click to open the

Layout Manager
Creating a Layout with AWR Microwave Office

A layout is a view of the physical representation of a circuit, in which each component of the schematic is represented
by a layout cell. In the object-oriented AWR Design Environment platform software, layouts are tightly integrated with
the schematics and EM structures that they represent, and are simply another view of the same circuits. Any modifications
to a schematic or EM structure are automatically and instantly reflected in their corresponding layouts.
To create a layout representation of a schematic, click the schematic window to make it active, then choose View > Layout.
A layout window tab opens with an automatically-generated layout view of the schematic.

Basic Operations
With a schematic window active, you can also click the View Layout button on the toolbar to view the layout of a schematic.
The resulting layout contains layout cells representing electrical components floating in the layout window. Choose Edit
> Select All then choose Edit > Snap Objects > Snap Together to snap the faces of the layout cells together. The following
figure shows the layout view from the previous figure after a snap together operation.
When you choose View > View Layout, corresponding schematic components with default layout cells are automatically
generated for common electrical components such as microstrip, coplanar waveguide, and stripline elements. After the
layout is generated, the schematic window displays in blue the components that do not map to default layout cells, and
displays in magenta the components that do have default layout cells. You must use the Layout Manager to create or
import layout cells for components without them. For more information see “Using the Layout Manager”.
You can draw in the schematic layout window using the Draw tools to build substrate outlines, draw DC pads for biasing,
or to add other details to the layout. In this mode, the layout is not part of a schematic element and therefore does not
move as part of the snapping process.
Modifying Layout Attributes and Drawing Properties
To modify layout attributes and drawing properties, and to create new layout cells for elements without default cells,
click the Layout tab to open the Layout Manager.

Basic Operations
Right-click to import an LPF
Right-click to modify layout

attributes
Right-click to import a cell

library or create your own
using a Cell editor
Active layers for viewing

and drawing
Click the Layout tab to

display the Layout Manager
Using the Layout Manager
The Layer Setup node in the Layout Manager defines layout attributes such as drawing properties (for example, line color
or layer pattern), 3D properties such as thickness, and layer mappings. To modify layer attributes, double-click the node
(named "default.lpf" in the previous figure) below the Layer Setup node. You can also import a layer process file (LPF)
to define these attributes by right-clicking Layer Setup and choosing Import Process Definition.
The Cell Libraries node in the Layout Manager allows you to create artwork cells for elements that do not have default
layout cells. The powerful Cell Editor includes such features as Boolean operations for subtracting and uniting shapes,
coordinate entry, array copy, arbitrary rotation, grouping, and alignment tools. You can also import artwork cell libraries
such as GDSII or DXF into the AWR Design Environment platform by right-clicking the Cell Libraries node and choosing
Import GDSII Library or Import DXF Library.
After creating or importing cell libraries, you can browse through the libraries and select the desired layout cells to
include in your layout. Click the + and - symbols to expand and contract the cell libraries, and click the desired library.
The available layout cells display in the lower window pane.

Basic Operations
Expand and contract,

click desired library
Drag layout cell into

layout window
After you define a cell library, you can assign cells to schematic elements. You can also use a cell directly in a schematic
layout by clicking and dragging the cell into an open schematic layout window, releasing the mouse button, positioning
it, and clicking to place it.
To export a schematic layout to GDSII, DXF, or Gerber formats, click the layout window to make it active, and choose
Layout > Export Layout. To export a layout cell from the cell libraries, select the cell node in the Layout Manager, right-click
and choose Export Layout Cell.
Creating Output Graphs and Measurements

You can view the results of your circuit and system simulations in various graphical forms. Before you perform a
simulation, you can create a graph, specifying the data or measurements (for example, gain, noise or scattering coefficients)
that you want to plot.
To create a graph, right-click Graphs in the Project Browser and choose New Graph to display a dialog box in which to
specify a graph name and graph type. An empty graph displays in the workspace and the graph name displays under
Graphs in the Project Browser. The following graph types are available:
Graph Type Description

Rectangular Displays the measurement on an x-y axis, usually over frequency.

Basic Operations
Graph Type Description

Rectangular - Real/Imag Displays real versus imaginary components of complex data on a
rectangular graph.
Smith Chart Displays passive impedance or admittances in a reflection coefficient
chart of unit radius.
Polar Displays the magnitude and angle of the measurement.
Histogram Displays the measurement as a histogram.
Antenna Plot Displays the sweep dimension of the measurement as the angle and
the data dimension of the measurement as the magnitude.
Tabular Displays the measurement in columns of numbers, usually against
frequency.
Constellation Displays the in-phase (real) versus the quadrature (imaginary)
component of a complex signal.
3D Plot Displays the measurement in a 3D graph.
To specify the data that you want to plot, right-click the new graph name in the Project Browser and choose Add
Measurement. An Add Measurement dialog box similar to the following displays to allow you to choose from a
comprehensive list of measurements.
Setting Simulation Frequency and Performing Simulations

To set the AWR Microwave Office simulation frequency, double-click the Project Options node in the Project Browser,
or choose Options > Project Options and then specify frequency values on the Frequencies tab in the Project Options dialog
box. By default, all the schematics use this frequency for simulation. You can overwrite this frequency with an individual
schematic frequency by right-clicking the schematic name under Circuit Schematics in the Project Browser and choosing
Options. Click the Frequencies tab, clear the Use project defaults check box and then specify frequency values.

Basic Operations
To set AWR VSS system simulation frequency, double-click the System Diagrams node in the Project Browser or choose
Options > Default System Options, and then specify frequency values on the Basic tab in the System Simulator Options
dialog box.
To run a simulation on the active project, choose Simulate > Analyze. The simulation runs automatically on the entire
project, using the appropriate simulator (for example, linear simulator, harmonic balance nonlinear simulator, or 3D-planar
EM simulator) for the different documents of the project.
When the simulation is complete, you can view the measurement output on the graphs and easily tune and/or optimize
as needed.
You can perform limited simulations by right-clicking the Graphs node or its subnodes to simulate only the graphs that
are open, only a specific graph, or simulate for just one measurement on a graph.
Tuning and Optimizing Simulations
The real-time tuner lets you see the effect on the simulation as you tune. The optimizer lets you see circuit parameter
values and variables change in real-time as it works to meet the optimization goals that you specified. These features are
shown in detail in the linear simulator chapter.
You can also click the Tune Tool button on the toolbar. Select the parameters you want to tune and then click the Tune
button to tune the values. As you tune or optimize, the schematics and associated layouts are automatically updated!
When you re-run the simulation, only the modified portions of the project are recalculated.
Using Command Shortcuts

The use of keyboard command shortcuts (or hotkeys) can greatly increase efficiency within the AWR Design Environment
platform. Default menu command shortcuts are available for many common actions such as simulation, optimization,

Using Scripts and Wizards
and navigating between the Project Browser, Elements Browser and Layout Manager. Default shortcuts display on menus
or by choosing Tools > Hotkeys to display the Customize dialog box where you can also create custom hotkeys.
Using Scripts and Wizards

Scripts and wizards allow you to automate and extend AWR Design Environment platform functions through customization.
These features are implemented via the AWR Microwave Office API, a COM automation-compliant server that can be
programmed in any non-proprietary language such as C, Visual Basic™, or Java.
Scripts are Visual Basic programs that you can write to do things such as automate schematic-building tasks within the
AWR Design Environment platform software. To access scripts, choose Tools > Scripting Editor or any of the options on
the Scripts menu.
Wizards are Dynamic Link Library (DLL) files that you can author to create add-on tools for the AWR Design Environment
platform; for example, a filter synthesis tool or load pull tool. Wizards display under the Wizards node in the Project
Browser.
Using Online Help

Online Help provides information on the windows, menu choices, and dialog boxes in the AWR Design Environment
platform, as well as for design concepts.
To access online Help, choose Help from the main menu bar or press the F1 key anytime during design creation. The
Help topic that displays is context sensitive-- it depends on the active window and/or type of object selected. The following
are examples:
• Active window = graph, Help topic = "Working with Graphs" topic.

• Active window = schematic (with nothing selected), Help topic = "Schematics and System Diagrams in the Project
Browser".
• Active window = schematic (with an element selected), Help topic = the Help page for that element.
• Active window = schematic (with an equation selected), Help topic = "Equation Syntax".
• Active window = schematic layout (with nothing selected), Help topic = "Layout Editing".
Context sensitive Help is also available by:
• clicking the Help button in most dialog boxes

• right-clicking a model or system block in the Elements Browser and choosing Element Help, or selecting an element
in a schematic or a system block in a system diagram and pressing F1, or clicking the Element Help button in the Element
Options dialog box.
• clicking the Meas Help button in the Add/Modify Measurement dialog box

Chapter 3. MMIC: Designing MMICs
This chapter covers topics related to Monolithic Microwave Integrated Circuit (MMIC) design. The Cadence® AWR
Design Environment® platform has many unique features to enable efficient and accurate simulation for this type of
design. These features allow you to focus on design tasks instead of design task management. Process Design Kits (PDKs)
available for the program should have all of the features described here enabled. This guide contains links to other AWR
Design Environment platform documents that are online. When reading the print version of this document you can follow
links by choosing Help > Getting Started to open the guide electronically, or you can find the linked document in the
Cadence AWR® Knowledge Base at www.awrcorp.com/download/kb.aspx.
The examples in this chapter use a simple MMIC low noise amplifier design to demonstrate MMIC features. MMIC
technologies typically have multi-layer lines that differentiate MMIC from other types of high-frequency design. Most
MMIC processes have at least two metal layers on top of the substrate used for routing signals. These metal layers can
be used as the bottom and top plate of a capacitor, or the dielectric in between can be etched away to form a metal line
that has the thickness of both metal layers to reduce loss, handle more current, and increase coupling between structures.
The proper manufacturing drawing for these layers typically has small offsets between the layers. For example, in this
process, the multi-layer line draws as shown in the following figure.
Metal1 and Metal2 are the same size, and the Dielectric Via is inset 2um from the other layers.
Opening the Design

The example used in this chapter is named MMIC_Getting_Started.emp. To access this file from a list of Getting Started
example projects, choose File > Open Example to display the Open Example Project dialog box, then Ctrl-click the Keywords
column header and type "getting started mmic" in the text box at the bottom of the dialog box.
use of the AWR Design Environment platform. Choose Help > Quick Reference to access this document.
Organizing the Design

The goal of the design is to achieve 1 dB noise figure and greater than 10 dB gain at 10 GHz. The 2D layout of this
design is shown in the following figure.

The electrical response of this design is shown in the following figure.
Gain and Noise Figure

20 4
DB(NF()) (R) DB(|S(2,1)|) (L)
15 3
Gain (dB)
NF (dB)
10 2
5 1
0 0
0.1 5.1 10.1 15.1 20
Frequency (GHz)
The purpose of this example is to show MMIC-related features, not the design performance of this low noise amplifier.
The design technology is a Cadence process created to build example circuits. The parts have realistic values but the
circuits cannot be fabricated anywhere.
This design is completed in three stages. The relevant schematics and graphs for each stage are organized under the
Project Browser User Folders node. User folders are an optional way to group related window types together for a design.
In large designs, it is helpful to organize your graphs, schematics, EM structures and other project items in a folder to
easily see which items are related. User folders are used in this example because certain exercises need specific graphs
and schematics open, and referencing their user folder simplifies these references.

First, the device is characterized for its noise and gain characteristics. The documents used for this stage of the design
are in the "Device_Characterize" user folder. Source feedback is added to move the optimal noise match closer to the
ideal input match of the device. The device and its feedback are done in separate schematics for use hierarchically. This
allows only one instance of the model in the entire design, reducing the potential for error if changes are made. Additionally,
the gate and drain bias voltages are defined with variables in the "Global Definitions" document for the same reason that
the device hierarchy is done separately-- so there is one master value for each. Several different topologies of the circuit
are built (lumped versus distributed) and hierarchy is not as straightforward as using global variables to keep the bias
values consistent through different versions of the design.
Next, the input and output matching networks are designed using lumped elements first. The documents used for this
stage of the design are in the "Circuit" user folder. Both matching networks are done in their own schematics and then
used hierarchically in the total circuit design. This allows you to easily measure the impedance looking into any port of
the matching network. For LNA design, this is necessary to make sure the impedance presented to the device is near the
optimal noise match impedance. The design is then converted from lumped elements to distributed elements. These are
kept as separate top level schematics for comparison of the lumped and distributed performances.
Finally, the metal for the design is EM-simulated using the extraction flow. The documents used for this stage of the
design are in the "Extraction" user folder. An additional level of hierarchy is created so the results with and without EM
results are easily compared. In general, adopting a test bench approach to your designs is beneficial. Your designs are
completed in one level of schematic hierarchy while all of the different ways to measure results are done one level up
in hierarchy, so copies of design pieces are never made.
Hierarchy is typically used in MMIC design to help organize and reduce errors. There are various ways to navigate
through hierarchical designs. See “Navigating Design Hierarchy: Schematic and Layout” for details. Additionally, MMIC
design generally requires working in both Schematic and Layout Views. It is helpful to know the proper ways to cross-select
from one view to the other. See “Cross-selecting Between Schematic and Layout” for details.


Chapter 4. MMIC: Layout Features
This chapter describes several powerful layout features for MMIC design using the MMIC_Getting_Started.emp project
opened in the “MMIC: Designing MMICs” chapter.
Enabling Two Click Entry Mode

With Two click entry mode, you click once to start a draw or view window, then click a second time to define the window
size, rather than clicking and dragging the mouse to define the window. To enable this mode:
1. Choose Options > Environment Options and click the Mouse tab.
2. Select Two click as the Entry mode.
3. Click OK.
Specifying Line Types

When working with layouts for elements like lines, tees, and bends, you can easily change the metallization used. Every
element that draws a line has a Line Type setting. These line types are configured for each PDK. Changing the line type
also changes the electrical characteristics of the lines, specifically the metal thickness. If the PDK is set up correctly,
changing the line type also changes the substrate used for that model. For this to work, the line type names and substrate
names must match. For this process, there are three substrates whose names match the names of the line types available:
"Plated_Metal_Line", "Metal_1", and "Metal_2".
Vg = -1.3
MSUB MSUB MSUB
Vd = 6.5
Er=12.9 Er=12.9 Er=12.9
H=100 um H=100 um H=100 um
T=2.5 um T=0.5 um T=2 um
Rho=1 Rho=1 Rho=1
STACKUP STACKUP Tand=0 Tand=0 Tand=0
Name=Thick_Metal Name=Thin_Metal ErNom=12.9 ErNom=12.9 ErNom=12.9
Name=Plated_Metal_Line Name=Metal_1 Name=Metal_2
To change an element line type:
1. Select the item in the layout.

2. Right-click and choose Shape Properties.
3. In the Cell Options dialog box, change the Line Type.
To change line types:
1. Open the 2D and 3D layouts for the "Distributed_input_match" schematic. Tile the windows vertically for easy viewing
by choosing Window > Tile Vertical.
2. In the 2D layout, choose Draw > 3D Clip Area and then click, move the mouse, and click again to create a box around
the upper left capacitor and lines, as shown in the following figure.

With this object drawn, the 3D layout view shows only the shapes in this region. The remainder of this example is
easier if you zoom into this same area in the 2D view.
The 3D layout displays as follows.

3. In the schematic, select the line immediately to the right of the capacitor as shown in the following figure. Note the
MSUB.
MLIN
ID=TL5
W=40 um
L=50 um
MSUB=Metal_2
Open the Layout View, right-click and choose Shape Properties to display the Cell Options dialog box. Change the
Line Type from Metal 2 to Plated Metal Line and click OK.


Using Automatic Interconnect
Notice that the line is using all three processing layers for the layout instead of just one as shown in the previous
figures. Also note that the MSUB parameter name has changed to the proper substrate. NOTE: You can change the
MSUB model parameter to a different line and see the line type change in the layout.
MLIN
ID=TL5
W=40 um
L=50 um
MSUB=Plated_Metal_Line

Using multiple line types in a process adds design complexity when connecting between lines that use different Line
Types, or between lines and devices like capacitors, resistors, inductors and transistors. For example, consider how lines
connect to a capacitor in the provided example: The top plate of the capacitor uses Metal 2 and the bottom plate uses Metal
1. There are three line types in this process, Metal 1 (just Metal 1 layer), Metal 2 (just Metal 2 layer), and Plated Metal Line
(Metal 1, Metal 2, and Dielectric Via layers). If you connect a line on Metal 1 to the Metal 2 side of the capacitor, you
must draw additional shapes to make a proper connection. This is handled automatically in the Cadence AWR® PDKs.
Each PDK has automatic interconnect (sometimes called "Bridge Code"), that draws the correct connecting shapes at
the ends of lines (for example, MLIN, MTRACE2, or MCTRACE). The goal of the automatic interconnect is to handle
connections between every combination of Line Type and from every Line Type to every component, so that all of these
connections are design rule correct. Note that automatic interconnect is drawn from the top down. If, for example, a line
in the lower level of a hierarchy connects to the cap in the higher level, no automatic interconnect is drawn, which is
why you must connect a line to the cap at the higher level also. See “Working Through Hierarchy” for details on automatic
interconnect and hierarchy.
The following example starts with the same 2D and 3D layouts used previously and shows the use of automatic
interconnect.
1. Notice that the line on the left side of the capacitor is drawing on Metal 2, which is the same metal for the top plate of
the capacitor, so no special drawing is needed.

2. Change the Line Type of that line to Metal 1 and view the layout.
Notice that the layout changed on the line to the left of the capacitor. A via is drawn for the proper transition from
Metal 2 to Metal 1.
3. Change the Line Type of the line on the right side of the capacitor to Metal 2 and view the layout.
Notice that the layout changed on the line right to the of the capacitor. This time the proper transition is drawn from
Metal 1 to Metal 2.
4. Open the "Distributed_input_match" schematic and zoom in near port 1. Select both port 1 and the MLIN connected
to it. Press the Ctrl key while dragging the elements to the left to break the connection between the line and the capacitor.
The schematic should display as follows.

Using Layout Snapping
AWR_MESFET_TFCM
ID=TL3
W=140 um
L=140 um
C=5.88 pF
W1=40 um
W2=40 um MLIN
CA=0.0003 ID=TL5
MSUB=Plated_Metal_Line W=40 um
PORT L=50 um
P=1 MSUB=Metal_2
Z=50 Ohm
MLIN
ID=TL16
W=40 um
L=25 um
MSUB=Metal_1
Since there is no electrical connection between the capacitor and the line, there is no transition from Metal 1 to Metal
2, so the automatic interconnect does not draw the connection.
This proves that the layout draws properly, based on how the elements are connected in the schematic.
5. Change both line types on either side of the capacitor back to Metal 2 and reconnect the port and MLIN to the schematic
before continuing.

In the Cadence® AWR Design Environment® platform, layouts are automatically generated for models that are configured
with layout cells. For MMIC design using PDKs, each element should have a layout configured. The layout does not
automatically know how to position each model's layout cell relative to the others, so the snapping process is required
to move the individual components together to connect them. To understand snapping, you must first understand layout
faces.
Each layout cell must define where connections are allowed. There are two types of connection locations allowed: area
pins and faces. Area pins allow connections at any location within an area and are not used often in MMIC design. Faces
allow a connection at various locations along the face. The location depends on settings for each face. Connecting to the
center is the most common setting. Faces have numbers that correspond to model node numbers. When nodes of models
are connected in a schematic, the layout knows which faces must be connected. If the faces properly overlap, no rat line
displays in the layout. If they do not properly overlap, a rat line displays in the layout to indicate which element faces
must be snapped together to correct the layout.

With layout snapping, layout objects are automatically moved to minimize rat lines in the layout. You snap a layout
together by first selecting the items to snap (if Manual snap for selected objects only is selected as the Snap together option
on the Layout Options dialog box Layout tab), and then choosing Edit > Snap Objects > Snap Together or clicking the Snap
Together button on the toolbar. There are several issues to consider when using snapping:
• There are different snapping modes, manual and automatic. See “Layout: Snapping Strategy” for details on choosing
the correct snapping mode, which is typically determined by the completeness of your layout. This project uses the
Manual snap for selected objects only option.
• The order in which objects are moved during snapping depends on several issues:
1. You can specify any layout object as the anchor by selecting the object, right-clicking and choosing Shape Properties
to display the Cell Options dialog box. Click the Layout tab and select the Use for anchor check box.
When an item is anchored, it displays with a red circle with crosshairs through it as shown in the following figure.

Snapping starts with any anchored items. If a layout has only one anchor, that item does not move during snapping.
2. For either of the snapping modes where all elements are snapped (Auto snap on parameter changes and Manual snap
for all objects), the anchored items remain fixed and all others can potentially move. If there is no anchor, the first
item found is fixed. In the snapping mode for selected items (Manual snap for selected objects only), if there are no
anchored items in the selected items, the first item selected stays fixed.
• When faces are snapped together, by default they snap to the center of each face. Settings for each face determine the
location in which that face snaps. You can access these settings by selecting a layout object, right-clicking and choosing
Shape Properties to display the Cell Options dialog box. Click the Faces tab and select the face you want to specify
from the Face drop-down menu, then in the Face Justification section you change the face snapping location. When
changing the face, position the dialog box so you can view the layout for the effects of the different settings. For
example, the following figure shows Face 1 of an MLIN with Center justification.

The blue line in the layout with the small vertical line in the middle of the face shows the face currently selected, and
the small vertical line shows the face justification. For example, the following figure shows the same face with Bottom
justification.

Notice how the vertical line is now on the right side of the face.
The following figure shows the Face set to "2". The blue line is now drawn on the other side of the MLIN.

• Snapping can also be used hierarchically by choosing Edit > Snap Objects > Snap All Hierarchy. This command starts
at the lowest level of hierarchy for the current layout, snaps those layouts together, and then progressively works up
through the hierarchy. A layout setting controls whether or not rat lines from lower levels of hierarchy display at the
current level. To specify this setting, choose Layout > Layout Mode Properties to display the Layout Editor Mode Settings
dialog box. In the Drawing options section of the dialog box, select Draw all rat lines, as shown in the following figure.
• In some situations more than two elements are connected to a node. In this case, snapping moves all of the faces to
the same location, which is typically not the correct location for each item. Fortunately, there are face settings to
control how snapping functions in this scenario. See “Using More Than Two Connections at a Node” for details. In
this example, this technique is used for the capacitors in the bias networks for the input and output distributed matching
network layouts as well as in the "device" schematic for the two lines connecting to the source of the transistor.
Many of the snapping and faces concepts can be further explained with an example. In the "Distributed_output_match"
layout, there is a narrow line feeding a capacitor after an inductor in the bias path.

Instead of centering this line on the cap, you can align it with the left edge of the capacitor. To align the capacitor and
line:
1. Open the layout for the "Distributed_output_match" schematic.

2. Select the line between the capacitor and inductor, right-click and choose Shape Properties to display the Cell Options
dialog box, then click the Faces tab.
3. Make sure your options match those in the following figure.

Notice that the vertical line showing the face justification displays on the left side of the line.
4. Click OK to accept this change.
5. You must also change the capacitor face by selecting the capacitor, right-clicking and choosing Shape Properties to
display the Cell Options dialog box.
6. Click the Faces tab and make sure your options match those in the following figure.

Notice that the vertical line showing the face justification displays on the left side of the line.
7. Click OK to accept this change.
At this point, you can snap this subcircuit together, although the top level also needs to be snapped together. Instead,
you can do this all from the top level.
8. Open the "Distributed Design" schematic layout. Press Ctrl + A to select all of the layout items, then choose Edit >
Snap Objects > Snap All Hierarchy to snap together the top layout, with the capacitor moved. The
"Distributed_output_match" schematic layout is also snapped together and the line and capacitor are aligned along
their left edge.

Snapping to Fit
You can close this project without saving, and reopen it to continue with the remaining examples. If you do not do so,
the following steps still work, however some of the figures are slightly different due to the alignment of the line and the
capacitor.
Snapping to Fit
In general, when a layout has a rat line, you can select an element on either side of the rat line and perform a "Snap to
fit" operation by choosing Edit > Snap to fit or clicking the Snap to fit button on the Schematic Layout toolbar. During
this operation the element attempts to adjust its parameters to resolve the rat line. Only certain elements can change their
length with this command. The toolbar button is grayed if the item you select does not support this mode. The common
models supported for snap to fit operations are single lines, trace elements, and iNets.
In this example, the MTRACE2 elements feeding the bias pads are a good place to demonstrate the usefulness of a "Snap
to fit" operation.
1. In the "Distributed Design" layout, select the layout for the input matching network, right-click and choose Edit in
Place.

Snapping to Fit
2. Drag the bond pad to the right, as shown in the following figure.
Notice the rat line that displays between the MTRACE and the bond pad.
3. Select the MTRACE2 line feeding the bond pad and then click the Snap to fit button on the toolbar to see the layout
change to fill in the space between the line and pad. Additionally, the length of the MTRACE2 also changes, so the
simulation results reflect this changed length. (NOTE: The "Snap to fit" operation cannot change the shape of a
TRACE element, it only adjusts segment lengths.)

Using Intelligent Parameter Syntax

Sometimes when designing, you want to make symmetrical layouts. You can use hierarchy to accomplish this, however,
hierarchy can be excessive. You can also use variables to tie two components to the same value, although this presents
other problems, including:
1. Variables are prone to mistakes (typing in the wrong values results in errors).
2. Variables can be difficult to find, especially in a complex design. Typically, groups of equations are created and they
might be placed far away from the component that uses them.
3. Parameters tied to variables cannot be edited in layout.
Intelligent parameter syntax can help solve this problem. See “Using Intelligent Parameter Syntax” for details on setting
up this syntax.
The lines feeding the vias on the source of the FET are a good example of this case. The "device" schematic uses this
syntax for the right MTRACE2 element in the schematic, as shown in the following figures (NOTE: For the MTRACE2
elements, the secondary parameters RB and DB must also use this syntax).

MLIN
ID=TL4
W=20 um
L=10 um PORT
MSUB=Plated_Metal_Line P=2
Z=50 Ohm
MLIN
ID=TL3
PORT W=10 um 2
P=1 L=10 um
Z=50 Ohm MSUB=Plated_Metal_Line AWR_MESFET_FET_HF
1 ID=FET1
W=60 um
NG=4
MTRACE2 MTRACE
ID=TL2 ID=TL1
W=10 um W=W@MTRACE2.TL2um
L=448 um L=L@MTRACE2.TL2um
BType=1 BType=BType@MTRACE2.TL2
M=0 M=M@MTRACE2.TL2
MSUB=Plated_Metal_Line MSUB=Plated_Metal_Line
AWR_MESFET_GROUND_VIA AWR_MESFET_GROUND_VIA
ID=GV1 ID=GV2
Now, you need only edit the shape (for example, length and bends) of the master element, just as you would edit any
element. The slave element (with parameters that match the master) automatically matches any changes in the master.
To edit the master and see the effect on the slave element:
1. Double-click the master MTRACE2 element, which is the line above the FET.

2. Click the center of the middle horizontal line and drag it up, as shown in the following figure.

3. Release the mouse, and both the top and bottom lines are changed, as shown in the following figure.


Chapter 5. MMIC: Extraction and EM Simulation
This chapter describes the power of the EM extraction process as well as the Cadence® AWR® patented geometry
simplification for EM analysis using the MMIC_Getting_Started.emp project opened in the “MMIC: Designing MMICs”
chapter and continued in the MMIC layout chapter. To begin this section, close all windows (choose Window > Close All)
and in the Project Browser under the User Folders node, open all of the documents under "Extraction".
The "Extract Test Bench" schematic uses the previously completed design schematic named "Distributed Design" as a
subcircuit. This lets you easily compare the results with EM extraction versus the non-extracted design. The graphs in
this folder are plotting results with and without extraction.
EM extraction is a generic process where the extracted circuit models' electrical model is replaced with EM analysis of
the layout for that element. See “EM: Creating EM Structures with Extraction” in AWR Design Environment Simulation
and Analysis Guide for details on using extraction. You must configure which models to extract and which EM simulator
to use. The AWR Design Environment platform performs the following:
1. Creates an EM structure based on the layout of the elements specified for extraction.
2. Runs the EM simulation(s) necessary to get the EM-based performance of those parts.
3. Sends the EM results back to the schematic by replacing the circuit model.
This process saves design time because EM layouts are automatically created, ports are added, and no resulting S-parameter
files have to be wired up in the schematic.
The following sections include information on specific extraction features.
Extracting Across Hierarchy

Previous sections explain the design advantage of building a hierarchical design. In the "Extract Test Bench" schematic,
the elements used in extraction are located one level down in hierarchy in the "Distributed Design" for ground signal
ground pads at the input and output, and two levels down for the elements in the "device", "Distributed_input_match",
and "Distributed_output_match" schematics.
To see the extraction process work across hierarchy:
1. Select the right-most EXTRACT block on the schematic, right-click and choose Toggle Enable.

Extracting Across Hierarchy
2. Click elsewhere and then select the enabled EXTRACT block to highlight the shapes in the layout to extract when
the EM simulation runs.
3. Now when you simulate, the extraction process occurs (the shapes are extracted in the EM document and simulated).
However, many times you want to visually inspect the EM structures created (for example, view mesh and view port
properties) before simulation. Right-click the enabled EXTRACT block and choose Add Extraction. A new EM
document named "EX_All" is created for your inspection, although it is not automatically simulated.

Configuring Groups
4. You can now simulate to view the effects of all the metal simulated with Cadence® AWR® AXIEM® 3D planar EM
analysis software. However, you do not need to simulate to continue with this example. If you do not simulate, disable
the same EXTRACT block by selecting it, right-clicking and choosing Toggle Enable. Also, delete the "EX_All" EM
document so it does not simulate the next time simulation is run.
Configuring Groups
You might often want to segment your extraction into smaller sections. For example, you might want to extract the entire
layout, you might want to extract the input and output matching network as separate EM documents, or maybe just extract
parts of the individual matching networks. Each EXTRACT block specifies a Name parameter for the group name. When
you enable an element for extraction, you also specify the group name. For example:
1. Enable the left-most EXTRACT block. Notice in the layout the elements that are extracted for this block.

Configuring Groups
2. Open the "Distributed_input_match" schematic, double-click the right-most inductor to display the Element Options
dialog box, and click the Model Options tab as shown in the following figure.
Notice that the Enable check box is selected and the Group name is set to "in_inds". This matches the Name parameter
on the enabled EXTRACT block.
Three different groups of EXTRACT blocks are configured in this example. Each group is surrounded by a box, and
text describes the function of each group in the "Extract Test Bench" schematic. The three blocks in the left-most group
are for each individual group name. Notice on each EXTRACT block that the Name parameter is the name of the "Group
name" set for the groups of models.
EXTRACT
ID=EX1
EM_Doc="EX_Input_Inductors"
Name="in_inds"
Simulator=AXIEM
X_Cell_Size=2 um
Y_Cell_Size=2 um
STACKUP="Thick_Metal"
Override_Options=Yes
Hierarchy=Off
SweepVar_Names=""

Using Incremental Extraction
The middle group of EXTRACT blocks has the input and output matching network as one EM document. Enable each
of these to see the shapes that extract. For these blocks, the EXTRACT block Name parameter is a vector of group names.
EXTRACT
ID=EX3
EM_Doc="EX_Input_All"
Name={"in_inds", "in_other"}
Simulator=AXIEM
X_Cell_Size=10 um
Y_Cell_Size=10 um
STACKUP="Thick_Metal"
Override_Options=Yes
Hierarchy=Off
SweepVar_Names=""
Note that the Name parameter lists several names, each in quotes, separated by commas and enclosed in brackets. This
syntax tells extraction to include all models or shapes in all of the group names listed.

In the previous section, the upper left-most EXTRACT block is enabled, which extracts the elements in the input matching
network. Sometimes you might want more insight into your circuit to see where coupling is occurring. You can achieve
this by incrementally adding elements to, or removing elements from, your EXTRACT group. This is best demonstrated
by an example. To incrementally extract the input matching network:
1. Ensure that the upper left-most EXTRACT block is enabled to extract any elements in the "in_inds" groups.
2. Open the layout for the "Distributed_input_match" schematic and select all of the shapes, as shown in the following
figure. You can quickly select all of the shapes by clicking and dragging the mouse to select all of the parts above the
lower capacitor, and then holding down the Shift key while selecting the smaller inductor and lines to remove them
from the selection.

3. Right-click over any of the selected shapes and choose Element Properties to display the Element Options dialog box.
Click the Model Options tab and clear the Enable check box to turn off those elements for extraction.

4. Right-click the currently enabled EXTRACT block and choose Add Extraction to create a new EM document named
"EX_Input_Inductors". Ensure that the EM document matches that shown in the following figure.
Simulate the project. The following simulation results show that the answer for the circuit is not changed much.

Extraction Sparameters
0
-5
-10
DB(|S(1,1)|)
-15 Extract_Test_Bench
DB(|S(2,2)|)
Extract_Test_Bench
-20 DB(|S(1,1)|)
Distributed_Design
-25 DB(|S(2,2)|)
Distributed_Design
-30
0.1 5.1 10.1 15.1 20
Frequency (GHz)
5. On the schematic layout, select the remaining original elements in this extract group. Right-click over any of the
selected shapes and choose Element Properties to display the Element Options dialog box. Click the Model Options tab
and select the Enable check box to turn back on those elements for extraction. Right-click the currently enabled
EXTRACT block and choose Add Extraction to update the EM document named "EX_Input_Inductors". The EM
structure now displays as follows when all of the original elements are enabled for extraction.

Using Data Sets
Simulate the project. The following simulation results show that the answer for the circuit still looks reasonable.
0
-10
-20
DB(|S(1,1)|)
Extract_Test_Bench
DB(|S(2,2)|)
-30 Extract_Test_Bench
DB(|S(1,1)|)
Distributed_Design
-40 DB(|S(2,2)|)
Distributed_Design
-50
0.1 5.1 10.1 15.1 20
Frequency (GHz)
Using Data Sets

When you extract elements, different configurations can cause simulation differences due to:
• Simulator settings such as mesh settings and port configurations.

• Layout objects in different configurations.
In these situations you can use data sets, which contain the results from EM simulations, to help you compare different
simulation runs. See “Data Sets” in AWR Design Environment User Guide for details on using data sets. By default, the
data sets from up to the last five simulations are stored in a project. The program always uses the most recent EM
simulation results unless you specify a different data set. The process of specifying a different data set is call "pinning"
and it is controlled by right-click menus on individual data sets.
Using data sets is best shown with an example that starts from the extractions and simulations performed in the previous
section. Notice in the "Distributed_input_match" layout that the inductors are close together and that you can flip the
smaller inductor to move it further away from the other inductor.
To use data sets to compare EM results:
1. In the Data Sets node of the Project Browser under the EM structure named "EX_Input_Inductors", right-click the
current (green icon) data set and choose Rename Data Set.

Using Data Sets
NOTE: The data set names you see might be different depending on the number of simulations you have done. If
you have simulated the extraction once and have one data set, you can continue with the following steps.
The green data set is the most recently simulated; the others are from previous simulations of this structure. Data sets
are given default names and you can rename them. Here, you want to rename the current data set since this is the
simulation result you compare with a different configuration.
2. Change the data set name to "inductor normal" and then click Rename.
3. Open the layout for the "Distributed_input_match" schematic and select the small inductor and the line to the right
of the inductor, as shown in the following figure.

Using Data Sets
4. Right-click the selected shapes and choose Flip,then click and drag the mouse from left to right to flip the layout
objects about the x-axis, as shown in the following figure.
5. Snap the layout together by pressing Ctrl + A to select all of the layout items, and then click the Snap Together button
on the toolbar to snap the layout together, as shown in the following figure.

Using Data Sets
6. Now when you simulate, the extracted EM document displays as follows.

Using Data Sets
The following simulation results show that the answer for the circuit still looks reasonable.
0
-10
DB(|S(1,1)|)
-20 ExtractTest Bench
DB(|S(2,2)|)
ExtractTest Bench
DB(|S(1,1)|)
-30
DistributedDesign
DB(|S(2,2)|)
DistributedDesign
-40
0.1 5.1 10.1 15.1 20
Frequency (GHz)
The response looks reasonable, but it is hard to compare with the inductor flipped the other way. This is where data
sets are helpful.
7. First, you rename the new data set by right-clicking the current (green icon) data set and choosing Rename Data Set.

Simplifying Geometry
8. Change the data set name to "inductor flipped" and then click Rename.
9. Right-click on the "inductor normal" data set and choose Pin 'Results to Document'. The Project Browser now displays
as follows.
The green dot indicates a pinned data set, so when the circuit simulation runs it uses this data set for the EM structure
instead of the most recent set. Right-click a pinned data set and choose Unpin 'Results to Document' to remove the pin.
(NOTE: To verify which set is which, you can view the geometry used to create a data set by right-clicking the data
set and choosing View Geometry.)
Additionally, you can freeze graph traces and change a data set pin to see the plots on top of one another. To do so,
you first simulate with the "inductor normal" data set pinned, then, with a graph active, choose Graph > Freeze Traces
to freeze the current data to the graph, then unpin the data set and resimulate. The graph now shows both results as
follows.
0
-10
DB(|S(1,1)|)
-20 ExtractTest Bench
DB(|S(2,2)|)
ExtractTest Bench
DB(|S(1,1)|)
-30
DistributedDesign
DB(|S(2,2)|)
DistributedDesign
-40
0.1 5.1 10.1 15.1 20
Frequency (GHz)
The results shifted very little. You can see some small differences for the S(1,1) result in the null. This demonstrates
that the orientation of the inductor has little effect on the simulation results.
Previously this guide discussed the concept of plated lines. The small insets for plated lines have a very minimal effect
on the electrical results of MMIC circuits. From an EM simulation perspective, typical meshing processes need to resolve

the plated line insets, causing a far more complex problem to solve than necessary. Additional aspects of geometry, such
as circular or arced shapes, or arrays of small vias, can cause meshing to be less efficient.
Fortunately, the AWR Design Environment platform has an automated approach to simplify geometry before performing
EM simulation. For example, consider a plated line. With no simplification, a cross-section of the mesh displays as
follows.
Notice the inset notch that requires significant numbers of mesh cells to mesh that geometry. With simplification, a
cross-section of the mesh displays as follows.
Notice that the inset is removed, creating a much more efficient mesh. For a simple line in this process, the geometry
simplification rules result in approximately a 3x improvement in the number of unknowns.
When you view the geometry of an EM structure, you are seeing the Layout View of the document (the non-simplified
geometry). You can view the simplified geometry by right-clicking the EM structure and choosing Preview Geometry.
This creates a new EM document where you can change visibility by layers and see the 3D view. The following figure
is an example of the original Layout View for an EM structure.

The following figure shows the same structure viewing the simplified geometry. Reference plane extensions are added
because of the auto ports. For more information on auto ports, see the Simulation and Analysis Guide.

See “Geometry Simplification” in AWR Design Environment Simulation and Analysis Guide for details on how geometry
simplification functions. (NOTE: PDKs for the program should all be configured for geometry simplification.)


Chapter 6. MMIC: Verifying Designs
This chapter shows various ways of verifying whether your design is ready for manufacturing using the
MMIC_Getting_Started.emp project opened in the “MMIC: Designing MMICs” chapter and continued in the MMIC
layout and extraction/simulation chapters.
Using the Connectivity Highlighter

The Connectivity Highlighter displays a layout with different colors, one color for all electrically connected metal. This
tool is intended for visual inspection of the layout. Note that this example has several levels of hierarchy and the
Connectivity Checker runs through all of them. See “Connectivity Highlighting ” in AWR Microwave Office Layout
Guide for details on the Connectivity Checker. To view this feature:
1. Open the layout for the "Distributed Design" schematic.
2. Run the Connectivity Highlighter by choosing Verify > Highlight Connectivity All. The layout displays similar to the
following.

Each electrically connected group of shapes displays in one color. There is a fixed set of colors, so if shapes near each
other have similar colors, you can rerun the Verify > Highlight Connectivity All to change the layout connectivity colors.
Your colors may differ from those displayed because each time the check is run, the colors displayed are different.
The connectivity display also applies to the 3D layout view.

3. Turn off the connectivity display by choosing Verify > Highlight Connectivity Off.
At times, you might only want to highlight the connectivity of parts of your layout. For a MMIC, you may commonly
want to highlight all metal that is connected to ground. You can do this with the Connectivity Probe mode. To run this
mode, choose Verify > Highlight Connectivity Probe. Click a shape to toggle its connectivity. You are in Connectivity Probe
mode until you press the Esc key. For example:
1. With the "Distributed Design" window active, choose Verify > Highlight Connectivity Probe.
2. Click on a via to highlight all the grounds in the circuit, as shown in the following figure.

Using the Connectivity Checker
3. Click over a via again to turn off the highlighting for all the grounds.
4. Click over the left-most capacitor, and both connected nets for either side of the capacitor display highlighted, as
shown in the following figure.
NOTE: If you use these commands often, you should set up hotkeys to run them.

The Connectivity Checker expands on the Connectivity Highlighter by checking the layout connectivity versus the
schematic connectivity for differences. (NOTE: The Connectivity Checker assumes that the layout for the device

components (for example, transistors, capacitors, and resistors) are correct, so the Connectivity Checker is not a replacement
for LVS for final verification). See “Connectivity Checking ” in AWR Microwave Office Layout Guide for details on the
Connectivity Checker. To use the Connectivity Checker:
1. Open the layout for the "Distributed_input_match" schematic and select the left-most line in the design connected to
the input capacitor.
2. Right-click and choose Shape Properties to display the Cell Options dialog box, then click the Layout tab and change
the Line Type from Metal_2 to Metal_1.

This change causes a connectivity problem in layout due to the way Bridge Code works through hierarchy. (See
“Layout: Using Automatic Interconnect” and “Working Through Hierarchy” for more information on Bridge Code
and hierarchy issues). The Connectivity Highlighter in the "Distributed Design" schematic layout displays this problem
as follows.
Visual inspection, however, is not a good strategy for finding connectivity problems in complex designs.
3. Choose Verify > Run Connectivity Check to compare the layout versus schematic connectivity. When the check is
complete, an error window displays.
4. Click an error to open both the layout and the schematic and highlight where the error is found.

The different views open as you navigate through the errors.
NOTE: Right-click on any error in the error window and choose Error Marker Options to open the Error Marker Options
dialog box to control error display and navigation. See “Error Marker Options Dialog Box ” in AWR Design Environment
Dialog Box Reference for more information.
5. When you are done viewing errors, choose Verify > Clear LVS Errors.

Using Layout Vs Schematic (LVS)
Using Layout Vs Schematic (LVS)

Each foundry develops its own LVS flow, so you should contact the foundry for information on using LVS. Many LVS
flows use the error viewer (see “Using the Connectivity Checker” for details). This section shows you how to navigate
when using the foundry-supplied LVS flow. See “LVS (Layout vs Schematic) ” in AWR Microwave Office Layout Guide
for full details on using LVS in the Cadence® AWR Design Environment® platform.
Design Rule Checking (DRC)

The AWR Design Environment platform has its own simple DRC engine as well as the capability to run the foundry
specified "sign-off" DRC engine. You should contact the foundry for information on using their "sign-off" DRC engine.
Many DRC flows use the DRC error viewer used by the Cadence AWR® DRC engine. This section introduces information
on how to navigate and find errors, rather than focusing on the specific DRC engine or rules run. See “Design Rule
Checking (DRC) ” in AWR Microwave Office Layout Guide for details on using DRC in the program. To view an example:
1. Open the layout for the "Distributed Design" schematic.
2. Choose Verify > Design Rule Check to display the following window.

NOTE: If your rules list does not match this figure you need to load the proper rule deck for this example. To locate
the folder in which the example PDK is located, choose Help > Show Files/Directories.
Find “Libraries” in the Name column and double-click it to open the Windows Explorer. Navigate to the
…\example_pdks\mesfet\Library\ directory. The DRC rule deck is a file named drc_rules.txt, and you now have the
path to the folder it is in.
Back in the DRC window, click the Load Rules File button and browse to the folder that contains the drc_rules.txt file.
Double-click the file and your rules list should now match the list in the previous figure.

3. Select only the MINWIDTH rules (clear all other rule check boxes) and then click the Run DRC button to run the DRC
check. When the check is complete, the Design rule violations error window displays.
4. Double-click an error to magnify it in the Layout View.

5. Double-click a rule group header.
The layout zooms to show all of the errors in that group.

6. Double-click an individual error and the layout zooms to that error. For example, click on the top failure.
The layout zooms to show the individual error.

7. You can move each error into a Checked Errors or False Errors category by right-clicking the individual rule and
choosing the appropriate option.
NOTE: Right-click on any error in the error window and choose Error Marker Options to open the Error Marker Options
dialog box to control error display and navigation. See “Error Marker Options Dialog Box ” in AWR Design Environment
Dialog Box Reference for more information.

Completing the MMIC Example

The following chapter includes additional information about MMIC design related topics. Cadence highly recommends
that you review this material to further your understanding of MMIC design in the AWR Design Environment platform.


Chapter 7. MMIC: Supplemental Topics
This section provides additional MMIC design related information.
use of the Cadence® AWR Design Environment® platform. Choose Help > Quick Reference to access this document.
Navigating Design Hierarchy: Schematic and Layout

There are several useful concepts to understand when working with hierarchical designs.
You have different options for accessing schematics at various levels of hierarchy, including:
• In the Project Browser you can view a design's hierarchy and double-click on any schematic node to open that schematic
in a separate window. For example, the "Distributed Design" schematic has three subcircuits.
• You can open a subcircuit in its own window by selecting it in the schematic, right-clicking, and choosing View
Referenced Doc.
• You can push down into a subcircuit from the current schematic and a new window opens. Select the subcircuit,
right-click, and choose Edit Subcircuit, or click the Edit Subcircuit button on the toolbar. The subcircuit replaces the
schematic in the schematic window.
• To go back up one level, with nothing selected, right-click in the schematic and choose Exit Subcircuit, or click the
Exit Subcircuit button on the toolbar.
For schematic annotations, there is an important difference when pushing into a subcircuit versus opening the subcircuit
in a new window. Schematic annotations are simulation results that display directly on the schematic, such as DC bias
values. (NOTE: To add a schematic annotation to a schematic, right-click the schematic in the Project Browser and
choose Add Annotation, then select an annotation.) To view the top level schematic annotation in a lower level, you use
the Edit Subcircuit command. In this mode, the subcircuit knows which top level schematic is referencing it and can
display the annotations.
For example, the following figure shows the "Lumped Element Design" schematic after simulation. Notice that the DC
currents display on the schematic.

Navigating Design Hierarchy: Schematic and
Layout
SUBCKT
ID=S3 PORT
SUBCKT NET="lumped_output_match" P=2
Z=50 Ohm
ID=S2
NET="lumped_input_match" 1 2
PORT 10.3 mA 0 mA 0 mA
2
P=1
Z=50 Ohm 3
SUBCKT
1 2 1 ID=S1 10.3 mA
0 mA 0 mA NET="device"
3 DCVS
ID=VD
0 mA V=Vd V
DCVS
ID=Vg
V=Vg V
If you open a new window for "lumped_output_match", the schematic does not display the annotation, as shown on the
left in the following figure. If you push into the subcircuit, the schematic does display the annotation, as shown on the
right of the figure.
MLIN MLIN
PORT ID=TL2 CAP PORT ID=TL2 CAP
P=1 W=40 um ID=C4 P=1 W=40 um ID=C4
Z=50 Ohm L=690 um C=1.31pF C=1.31pF
Z=50 Ohm L=690 um
10.3 mA 0 mA
PORT PORT
P=2 P=2
IND Z=50 Ohm IND Z=50 Ohm
ID=L3 ID=L3
PORT L=0.97 nH PORT L=0.97 nH
P=3 P=3
Z=50 Ohm Z=50 Ohm
0 mA
10.3 mA
CAP CAP
ID=C2 ID=C2
C=5 pF C=5 pF
Note also that the schematic title bar shows which mode is used. In a new window, the title bar displays only the schematic
name.
When pushing into the schematic, the title bar shows the hierarchy path.
You have similar options for accessing schematic layouts at various levels of hierarchy, including:
• In the Project Browser you can view a design's hierarchy and you can right-click on a schematic and choose View
Layout to open that schematic layout in a separate window.
• You can open a subcircuit layout in its own window by double-clicking the subcircuit in the layout.

Layout
• You can push down into a subcircuit layout from the current schematic layout, allowing you to edit the subcircuit
while still viewing the entire layout. Select the subcircuit, right-click, and choose Edit in Place or click the Edit in Place
button on the toolbar.
• To go back up one level, with nothing selected, right-click in the schematic layout and choose Ascend In Place Edit, or
click the Ascend in Place Edit button on the toolbar.
The following "Distributed Design" schematic layout shows an example of "edit in place".
When you select the "distributed_input_match" subcircuit on the left, right-click it and choose Edit in Place, the layout
displays as follows.

Layout
The layout for the subcircuit displays in normal colors. You can edit those shapes in context from the rest of the layout,
which is dimmed and not editable.
NOTE: You can use layout modes to change how subcircuit layouts display in the top level layout. Choose Layout >
Layout Mode Properties to display the Layout Editor Mode Settings dialog box. The outlined options in the following
figure apply to hierarchical layout viewing.

Cross-selecting Between Schematic and Layout

When working on a design, you may want to access the electrical element properties from the layout, or the layout
properties from the schematic. When you select an item in the schematic, that item is highlighted in the layout, as shown
in the following figure.

Similarly, when you select an item in the layout, that item is shown with a cross in the schematic, as shown in the following
figure.

These displays are only visuals of what is selected. To access properties you use different commands. In a layout, you
can select the item, right-click and choose Element Properties to display the Element Options dialog box. You can also
open this dialog box by double-clicking an element in the schematic.
Accessing layout options from a schematic is not as simple. There are various licensing configurations that enable circuit
design, but not all of them have layout enabled. Every Cadence® AWR® Microwave Office® software license has a
schematic, but not all have layout capability, so the layout options are not available from the schematic. To access layout
options from a schematic:
1. Select the item in the schematic.

2. Right-click and choose Select in Layout.
3. Choose View > View Selected to zoom in on the selected element.
4. Right-click the selected shape and choose Shape Properties to display the shape properties.
There is an additional command for placing an element selected in a schematic into the layout:
1. Select the item in the schematic.

2. Right-click and choose Place in Layout.
3. The layout opens if not already opened, and the layout for that item is selected so you can move the cursor and click
to place the item in the desired location.

Intelligent Parameter Syntax is a way to have models get their parameter values from other models' parameters. This
syntax gives you more flexibility and ease of use than using variables to tie two or more parameters to the same value.
There are two variations of this syntax.
The first intelligent syntax format is setting an element parameter value to be equal to the parameter of a specific model
parameter connected to a specific node of the current model. The simplest form of this syntax is used with intelligent
discontinuity models (whose names end with a $ symbol) where the models are already set up to use this syntax. The
syntax used is "P@N", which specifies to look at the model connected at node "N" of this model and use the parameter
"P". For example, the following is the parameter listing for the MTEE$ model (after you press the Show Secondary button.

Each of the model parameters is getting the W parameter from the model connected at the node listed. This works most
of the time because lines should always be connected to discontinuity models. In some cases, this model produces an
error if there is no W parameter for the model connected at a specific node. This typically happens if the model has some
other width parameter, such as W1 or W2, and is easy to fix by correcting the width parameter. In the previous example,
if an M2CLIN port 1 is attached at port2 of the MTEE$, the model parameters appear as follows.
The second intelligent syntax format is used to assign one parameter to use the same value as another parameter. The
syntax is "P@EL.ID", where "P" is the parameter name, "EL" is the element name and "ID" is the ID of that element.
This syntax is commonly used to get one model to match another, typically called master-slave syntax. Additionally, it

is common for TRACE elements to use this syntax to be able to edit the shape of the master, while the slave follows
automatically to build a system that is always symmetric. An example is a Wilkinson power divider. The following
schematic shows an example of MTRACE2 elements connected to the source of a FET. In this design is it critical that
each path is identical.
MLIN
ID=TL4
W=20 um
L=10 um PORT
MSUB=Plated_Metal_Line P=2
Z=50 Ohm
MLIN
ID=TL3
PORT W=10 um 2
P=1 L=10 um
Z=50 Ohm MSUB=Plated_Metal_Line AWR_MESFET_FET_HF
1 ID=FET1
W=60 um
NG=4
MTRACE2 MTRACE
ID=TL2 ID=TL1
W=10 um W=W@MTRACE2.TL2um
L=448 um L=L@MTRACE2.TL2um
BType=1 BType=BType@MTRACE2.TL2
M=0 M=M@MTRACE2.TL2
MSUB=Plated_Metal_Line MSUB=Plated_Metal_Line
AWR_MESFET_GROUND_VIA AWR_MESFET_GROUND_VIA
ID=GV1 ID=GV2
Notice how TL2 is the master and TL1 is the slave. The following shows the model parameters including the secondary
parameters for the slave.
(NOTE: Intelligent syntax cannot be used for any substrate definition parameter. The MSUB parameter in this case is
using a globally defined substrate definition. See “Intelligent Cells (iCells)” in AWR Microwave Office Layout Guide
for details.

Layout: Using Automatic Interconnect

Automatic interconnect (also called "Bridge Code") is part of a Cadence AWR PDK that changes how lines draw when
connected to other components (for example, capacitors and transistors). While the automatic interconnect is very powerful
for ensuring your layout is DRC correct, there are issues to consider when creating your design.
Using More Than Two Connections at a Node

There are several scenarios in which you connect more than two elements to a node during MMIC design, for example:
• Using a 3-node transistor model where vias need to be placed on either side of the transistor, as shown in the following
figure.
• Using a bias line where the bias flows over one of the plates of the capacitor, as shown in the following sample
schematic.

AWR_MESFET_TFCM
ID=TL1
W=100 um
L=100 um
C=3 pF MLIN
W1=40 um ID=TL2
W2=40 um W=10 um
CA=0.0003 L=100 um
MLIN
ID=TL4
W=40 um MLIN
L=20 um ID=TL3
W=10 um
ID=GV1 L=100 um
The 3D layout shows that the via is connected to the bottom of the cap and the two lines are properly connected to the
top layer of the cap.
The automatic interconnect does its best to determine how to draw the proper connections; however, this is an ambiguous
situation. The line is connected to both another line and a capacitor, so it must determine which connection to use to
draw its automatic interconnect. There are rules that prioritize certain component types.
In these situations, Cadence strongly recommends that you configure the layout to specify which layout connection to
make. There are layout specific settings to force faces for individual elements to connect properly. An added benefit of
configuring these faces is that the settings also determine the proper face to use when snapping. This is demonstrated
with the previous capacitor example.
To configure face connections:
1. Select a shape in layout, right-click and choose Shape Properties to display the Cell Options dialog box. In this example,
you select the lower line in the layout.

2. Click the Faces tab.

3. Position the dialog box on the screen so you can view it next to the schematic layout in which you are working.
4. Select the proper Face. You can determine which face is correct by viewing the layout; the selected face draws in
blue. The following figure shows the dialog box and layout with face 2 selected.
5. In Snap to, select the appropriate face to snap to. You can determine which face is correct by viewing the layout; the
selected face draws in red. In this example there are five possible Snap to locations because there is one other line and
one capacitor connected to that node.
The capacitor has four possible connection locations: one on each side of the capacitor. In this example, you try the
capacitor connections until you find the correct one, where the red line matches up with the blue line.

The same steps are repeated for the other line connected at this node. When complete, the automatic interconnect is
guaranteed to draw correctly and the layout snapping uses the requested faces.
Working Through Hierarchy

Automatic interconnect can work through hierarchy, but there are limitations. Automatic interconnect can look down
through a hierarchy, but not up. If an element is connected to a subcircuit, that element can change its drawing. However,
an element down in a subcircuit cannot change its layout based on what is connected at a higher level. The subcircuit
can be used in many places, so the automatic interconnect may be different for each instance of the subcircuit.
The following example of plated lines connected to either side of a capacitor illustrates this issue. The automatic
interconnect changes the line drawing on each side of the capacitor to make the proper connections. The following figure
shows a 3D view of proper connections.
The first possibility is to put the capacitor in a lower level of hierarchy.

ID=TL1
W=100 um
L=100 um
C=3 pF
W1=40 um
PORT W2=40 um
P=1 CA=0.0003
Z=50 Ohm
PORT
P=2
Z=50 Ohm
and then connect the lines at a higher level.
MLIN SUBCKT MLIN

PORT ID=TL1 ID=S1 ID=TL2 PORT
P=1 W=40 um NET="bottom_cap" W=40 um P=2
Z=50 Ohm L=100 um L=100 um Z=50 Ohm
1 2
The following figure shows the 3D layout with the Connectivity Highlighter on, where each connected shape displays
in a different color.
The second possibility is to put the lines in a lower level of hierarchy
MLIN
PORT ID=TL2 PORT
P=1 W=10 um P=2
Z=50 Ohm L=100 um Z=50 Ohm
and then connect the capacitor at a higher level.

ID=TL1
W=100 um
L=100 um
C=3 pF
SUBCKT W1=40 um SUBCKT
PORT ID=S2 W2=40 um ID=S1 PORT
P=1 NET="bottom_line" CA=0.0003 NET="bottom_line" P=2
Z=50 Ohm Z=50 Ohm
1 2 1 2
The following figure shows the 3D layout with the Connectivity Highlighter on. The capacitor is now shorted out due
to improper automatic interconnect.
Artwork Cells and EM Structures

When using artwork cells as layout cells for elements, or using EM subcircuits as building blocks, you can configure
how automatic interconnect works when connecting lines to these elements. For artwork cells, you create cell ports that
define the connectivity locations. For EM structures, you add ports for simulation purposes. For both cell ports and EM
ports, select the port, right-click and choose Shape Properties to display the Properties dialog box and then click on the
Cell Port or Cell Pin tabs. In the AWR Design Environment platform Dialog Box Reference, see “Properties Dialog Box:
Cell Pin Tab ” in AWR Design Environment Dialog Box Reference for details on this dialog box.
The correct setting may not be obvious because you cannot easily determine the connect type for the built-in parametrized
cells in a PDK. To determine the connect types for a given cell:
1. Place an element using the parametrized cell in which you are interested.
2. Select the element in the layout.
3. Choose Layout > Make GDSII Cell to display the Make New GDS Cell dialog box.
4. Specify a Library name and Cell name and click OK to open an artwork cell window with cell ports added for each face
location.
5. Select the desired face, right-click, and choose Shape Properties to display the Properties dialog box.
6. Click the Cell Port tab to view the Connection Type the face uses.

Discontinuities Without Lines

In microwave design, discontinuity models should not be connected directly to one another. Electrically, these
discontinuities produce evanescent modes that decay some distance from the discontinuity. The models account for these
modes only if there is enough line connected to these discontinuities-- typically two substrate thicknesses.
In addition, the automatic interconnect does not function properly when there are discontinuities hooked together. The
following figures demonstrates this issue.
MTEE
ID=TL4
MLIN MBEND90X
W1=40um
ID=TL5 ID=TL1
W2=40um
W=40um W=40um
W3=40um
L=20um M=0.5
MSUB=Plated_
Metal_Line
1 2
The following is the layout for this schematic.
Notice that all of the proper line offsets are drawing correctly in the area where the line connects to the bend at the top.
If you remove the line, the schematic displays as follows.
MTEE
ID=TL4 MBEND90X
W1=40 um ID=TL1
W2=40 um W=40 um
W3=40 um M=0.5
1 2

Layout: Changing Background Color
The following is the layout for this schematic.
Notice the area where the line connects to the bend at the top. The layer offset from the MTEE model is pushing outside
of the layers for the MBEND, which might cause DRC errors.
Besides the layout being incorrect, the electrical results using these circuit models is wrong because there is no line
between the discontinuities. If you must simulate this geometry, EM simulators such as the Cadence® AWR® AXIEM®
3D planar EM analysis software or Cadence® AWR® Analyst™ 3D FEM EM analysis software can properly model
them.
Layout: Changing Background Color

By default, the layout background color is white with black grid markers. You may prefer a black background, as the
fill patterns for some PDKs may be optimized for a black background. The simplest way to switch background colors is
to choose Scripts > Layout > Toggle_Background_Color to toggle both the background and grid colors. If you want to
manually change these colors, choose Options > Environment Options to display the Environment Options dialog box,
click the Colors tab and then select the desired display colors.
Layout: Snapping Strategy

The AWR Design Environment platform has two very different layout snapping modes. You can access these modes in
the Layout Options dialog box (choose Options > Layout Options) on the Layout tab in Layout Cell Snap Options . Auto
snap on parameter changes snaps the objects for that layout whenever you change a parameter, or through tuning or
optimization. The manual snap settings (Manual snap for selected objects only and Manual snap for all objects) only snap
together when you use the snap commands for the entire layout or for only the selected object.
If you use Manual snap for selected objects only at the beginning of the design, you can complete the initial placement of
layouts without encountering errors in the layout every time a parameter changes. After the initial placement of elements
you can switch to Auto snap on parameter changes. With this approach, as you change parameters, tune, or optimize, the
layout stays connected.
NOTE: Regardless of the Snap together setting, when using extraction and optimization, the layout always snaps together
so the proper shapes can be EM simulated.

Layout: Adding Text
Layout: Adding Text

Creating DRC clean text in layout can be problematic. The proper approach depends on how each individual foundry
addresses the problem. You should ask your foundry provider what is recommended for adding layout text. There are
several possible solutions to the problem, including:
• A specific text element that creates DRC clean layout. This block is added to a schematic and the text is typed as a
parameter of the element and then it draws DRC clean in the layout.
• Included with the PDK is a GDSII library that has each individual letter and number drawn as a cell. You can use
these cells in your schematic layout to create your text.
• Some processes do not care about DRC rules in text. Cadence recommends using “Arial Rounded MT Bold” font. It
looks good and is easily read under a microscope when viewing the fabricated MMIC. The following steps explain
how to add this text.
To add text objects:
1. Click in a layout window to make it active.

2. Click the Layout tab to open the Layout Manager. In the Drawing Layers pane, select the proper layer.
3. Choose Draw > Text or press Ctrl + T to add a text object.
4. Click in the layout to place the origin of the text object.
5. Type your text and press Enter or click outside the text box when done.
To edit existing text:
1. Select the text object, right-click and choose Shape Properties to display the Properties dialog box.
2. Click the Layout tab to change the Draw Layers used for the text.
3. Click the Font tab to change the Font type, the font Height and attributes, and the Draw as polygons setting. This option
determines whether the text is drawn as polygon shapes on a given layer (the shapes are included on that layer during
fabrication) or if the text remains a text object that is visible on the layout but not on any layer for fabrication.
4. To edit the text itself, double-click the text to enter edit mode and make changes.

Index H
Help
A online, 1–4, 2–20
Hotkeys, 2–19
Adding
measurements, 2–18
ports, 2–12 K
subcircuits to diagrams, 2–12 Keyboard shortcuts, 2–19
subcircuits to schematics, 2–11 Knowledge Base; AWR, 1–3
AWR Design Environment
components, 2–3 L
design flow, 2–1 Layer process file (LPF); importing, 2–16
overview, 2–1 Layout
starting, 2–2 creating, 2–14
Layout Manager, 2–4, 2–16
B LPF; importing, 2–16
Basic operations, 2–4
M
C Measurements
Cell adding, 2–18
libraries, 2–16 MMIC
Command design verification, 6–1
shortcuts, 2–19 designing, 3–1
Connecting nodes, 2–9 extraction, 5–1
Conventions; typographical, 1–2 layout, 4–1
Creating supplemental detail, 7–1
layout, 2–14
N
D Netlists
Documentation; AWR, 1–3 creating, 2–4, 2–8
Nodes
E connecting, 2–9
Elements
adding to schematics, 2–10 O
Elements Browser, 2–4, 2–10 Online Help, 1–4, 2–20
EM structures Online support, 1–4
creating, 2–12 Optimizing
drawings, 2–13 simulations, 2–19
Examples
opening, 2–5 P
Ports
G adding, 2–12
Geometry editing, 2–12
simplification, 5–1 Project
Graph creating, 2–4
adding measurements, 2–17 examples, 2–5
creating, 2–17 opening, 2–4
types, 2–17 saving, 2–4
Project Browser, 2–4
Getting Started Guide Index–1

Index
Q
Quick Reference document, 2–2
R
Resources; AWR, 1–3
S
Scripts, 2–20
Simulation
frequency, 2–18
optimizing, 2–19
running, 2–18
tuning, 2–19
Starting the AWR Design Environment, 2–2
Status Window, 2–4
Subcircuits
adding to diagram, 2–12
adding to schematic, 2–4, 2–11
importing, 2–11
Support
online, 1–4
System diagram
creating, 2–8
T
Tuning
simulations, 2–19
W
Wizard, 2–20
Index–2 AWR Design Environment

AWR Microwave Office MMIC Getting Started Guide: Product Version 16

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Getting Started Guide iii

5. MMIC: Extraction and EM Simulation ................................................................................................ 5–1

iv AWR Design Environment

Introducing the AWR Design Environment Platform

OBJECT ORIENTED TECHNOLOGY

Getting Started Guide 1–1

About This Guide

Contents of this Guide

Conventions Used in This Guide

Choose File > New Project.

Enter "my_project" in Project Name.

1–2 AWR Design Environment

See the DEFAULTS.LPF file.

Getting Additional Information

Cadence AWR Knowledge Base

Getting Started Guide 1–3

Documentation for AWR Microwave Office software includes:

Documentation for AWR VSS software includes:

1–4 AWR Design Environment

Set Units, Environment Options

Create Schematics/Diagrams (Microwave Office) Create Layout

Set Frequency, Simulation Options

(Microwave Office) Optimizing Tuning

Set Optimization Goals Manually Vary Parameters

• Creating projects to organize and save your designs

Getting Started Guide 2–1

• Incorporating subcircuits into system diagrams and schematics

Starting AWR Software Programs

1. Click the Windows Start button.

The following main window displays.

2–2 AWR Design Environment

AWR Design Environment Platform Components

Getting Started Guide 2–3

Working with Projects

2–4 AWR Design Environment

Creating, Opening, and Saving Projects

Opening Example Projects

To search for and open example projects referenced in this guide:

1. Choose File > Open Example.

Getting Started Guide 2–5

Importing Test Benches

To import a test bench into your project:

1. Choose File > Import Project.

2–6 AWR Design Environment

Working with Schematics and Netlists in AWR Microwave Office

Getting Started Guide 2–7

Right-click and choose

Right-click and choose

Adding Data to Netlists

Working with System Diagrams in VSS

2–8 AWR Design Environment

A System Diagram window

Right-click and choose

Connecting Element and System Block Nodes

Getting Started Guide 2–9

Using the Elements Browser