3 Placement

Learning Objectives

During this lab you will perform perform scan-chain aware

placement and optimization for timing, area and power.

After completing this lab, you should be able to:

 Perform setup for placement and timing optimization
 Perform setup for DFT and power optimization
 Perform standard cell placement
 Analyze congestion, timing and power
 Perform incremental placement and optimization

Placement Lab 3-1

Lab 3

Introduction

In this lab you are provided with a floorplanned design called ORCA_floorplanned
which is ready for the placement phase. You will execute the appropriate pre-
placement setup steps and then perform standard cell placement. After placement
you will analyze the results and execute additional appropriate steps to improve the
results.

Answers / Solutions
There is an ANSWERS / SOLUTIONS section at the back of each lab. You are
encouraged to refer often to this section to verify your answers, or to obtain help
with the execution of some steps.

Relevant Files and Directories

All files for this lab are located in the lab3_placement directory under your home
directory.
lab3_placement/
orca_lib.mw/CEL
ORCA_floorplanned The ORCA design after design planning,
saved in Milkyway format
scripts/
inputs_toggle_rate.tcl A script used to set statistical toggle rates for
the input ports.
ndr.tcl A script containing commands to define
non-default clock routing rules.
opt_ctrl.tcl Timing and optimization controls

design_data/
ORCA_TOP.scandef Scan chain information used during scan-
chain re-ordering.

.synopsys_dc.setup Setup variables.

Lab 3-2 Placement

 Lab 3

Instructions

Task 1. Pre-placement Settings and Checks

1. Invoke the IC Compiler “GUI” from the lab3_placement directory.

UNIX$ cd lab3_placement
UNIX$ icc_shell -gui -shared_license

2. Open the design library, open the ORCA_floorplanned design cell:

open_mw_lib orca_lib.mw
open_mw_cel ORCA_floorplanned

Note: In the previous Design Planning lab a larger, more complex

full-chip version of ORCA was used in order to illustrate IC
Compiler’s design planning capabilities and features. From
this lab on, we will be using a simpler block-level version of
ORCA. This block-level design will enable us to explore the
key steps of placement, CTS and routing while keeping run
times reasonable.

3. Apply timing and optimization controls:

source scripts/opt_ctrl.tcl

4. Macro placement is usually defined and “fixed” during design planning. It is,
however, possible that a last minute change is made to the macro placement
while forgetting to “fix” the new location. It is therefore a good idea to repeat
the “fixing” step prior to placement to ensure that no macros are moved
during the placement phase:

set_dont_touch_placement [all_macro_cells]

5. Verify that all process metal layers are available for routing - there should be
no ignored layers:

report_ignored_layers

6. Verify that standard cells are allowed to be placed under the METAL2 –
METAL4 power nets, as long as no DRC violations occur (partial blockage):

report_pnet_options

Placement Lab 3-3

Lab 3

7. During design planning both soft and hard placement keepouts were applied.
Verify that these variables are still set and are not the default value of zero:

printvar physopt_hard_keepout_distance
printvar placer_soft_keepout_channel_width

Question 1. Since the above are variable settings, which are

not saved with a design cell, how did these
variables retain their non-default values?

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Question 2. How will these variables affect placement?

.............................................................................

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8. The clock nets will be constrained to be routed on METAL3 – METAL6, with

double-spacing rules. Non-default routing (NDR) rules affect congestion,
which can affect placement. Apply the non-default routing rules for all clock
nets, as shown below, by sourcing the ndr.tcl file provided to you:

# Source this file: scripts/ndr.tcl

define_routing_rule 2X_SPACING -spacings {METAL2 0.6 \
METAL3 0.6 METAL4 0.8 METAL5 1.2 METAL6 1.4}
set_clock_tree_options -clock_tree [all_clocks] \
-routing_rule 2X_SPACING -layer_list "METAL3 METAL6"

9. Verify that the floorplanned design is ready for placement:

check_physical_design –stage pre_place_opt

Note: There should be no errors or warnings.

10. Execute a different pre-placement check:

check_physical_constraints

Lab 3-4 Placement

 Lab 3

Note: The messages about “Narrow Placement Area” can be

ignored for this design.

11. This design includes scan chains, which were inserted during synthesis. The
netlist that was read into IC Compiler during the data setup phase was a
Verilog netlist.
Question 3. Does the SCANDEF information transfer into IC
Compiler through the Verilog netlist?

.............................................................................

12. Execute the following command to confirm that no scan chain information
exists:

report_scan_chain

The report is empty, which means that no scan chain annotation exists.
13. Load the SCANDEF file (which was generated during synthesis, after scan
insertion):

read_def design_data/ORCA_TOP.scandef

Question 4. How many scan chains exist in the design?

.............................................................................

14. Generate another scan chain report. Use the “view” TCL procedure:

v report_scan_chain

You should see scan chains now! This information will be used during
place_opt to optimize the scan chain ordering.
Question 5. What place_opt option is required to perform
scan chain re-ordering during placement?

.............................................................................

Close the report_scan_chain view window: Close Window

Placement Lab 3-5

Lab 3

15. We do not have a simulator-generated SAIF file, which is preferred, so instead

we will read in a user-generated toggle-rate file.

report_saif
source scripts/inputs_toggle_rate.tcl
report_saif

Notice that the toggle-rate coverage is reported under the “User Annotated”
column.

18. Save the current design with its pre-placement settings:

save_mw_cel -as ORCA_preplace_setup

Lab 3-6 Placement

 Lab 3

Task 2. Placement and Optimization

1. Invoke placement and optimization using the appropriate options - congestion

was not an issue during design planning:

place_opt –area_recovery -optimize_dft -power

While place_opt is running you may observe the output on the screen
to get an idea of the optimizations that occur.

2. Save the current design:

save_mw_cel -as ORCA_place_opt

3. Generate a congestion map from the LayoutWindow:

Global Route Congestion  Reload  OK

The GUI step is the same as executing the following command:
report_congestion –grc_based –by_layer \
–routing_stage global
The congestion level is marginal and is probably ok since they are scattered
and not concentrated in a single area.
4. Close the congestion map by clicking on the small x in the Global Route
Congestion panel.
5. Generate a physical design report and scroll to the top of the output:

report_design –physical

Question 6. What is the reported standard cell utilization?

.............................................................................

6. Generate a QoR (quality of results) report:

report_qor

Question 7. Are there any user-defined path groups?

.............................................................................

Question 8. Why are we not concerned about hold time

violations?

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Placement Lab 3-7

Lab 3

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7. Report the power dissipation:

report_power

Task 3. Incremental Optimization

From the previous analysis steps we have determined that we have some
congestions issues and no significant timing violations. We should perform an
incremental optimization to improve the design’s area and power utilization.

1. Perform incremental logic optimization, using appropriate options:

psynopt -area_recovery –power

2. Generate a congestion map and verify that it is about the same as before:

Global Route Congestion  Reload  OK

Close the congestion map by clicking on the small x in the Global Route
Congestion panel.
3. Generate a physical design report and scroll to the top of the output:

report_design –physical

Question 9. Has the utilization changed significantly?

.............................................................................

4. Generate a QoR report and check for any setup timing violation:

report_qor

There should not be any setup timing violation.

5. Report the power dissipation:

Lab 3-8 Placement

 Lab 3

report_power

While there is not much improvement in power optimization since we do not

have SAIF annotations and also we are not providing multi-Vt libraries. In
your production design, you should expect a good improvement at this stage.
6. Save the design and exit IC Compiler:

save_mw_cel -as ORCA_placed

exit

You have completed the placement and power optimization lab.

Placement Lab 3-9

Lab 3 Answers / Solutions

Answers / Solutions

Question 1. Since the above are variable settings, which are not saved
with a design cell, how did these variables retain their non-
default values?

Since we just started a new IC Compiler session and we did

not explicitly re-apply these variables ourselves, they must
be in the .synopsys_dc.setup file, which is
automatically applied whenever IC Compiler is invoked.
Take a look and verify that this is indeed the case.
Question 2. How will these variables affect placement?

physopt_hard_keepout_distance = "5" ensures

that no cells are ever placed within 5 microns of any
macro’s border during placement, or any subsequent
optimizations.
placer_soft_keepout_channel_width = "15"
ensures that during coarse placement no cells are placed in
“channels” (the distance between any two macros, or
between a macro and the core boundary) of 15 microns or
less. Cells are allowed to be placed in these areas during
placement legalization and subsequent optimization.
Question 3. Does the SCANDEF information transfer into IC Compiler
through the Verilog netlist?

No. SCANDEF is only captured and automatically

transferred into IC Compiler if reading in a ddc netlist.
Question 4. How many scan chains exist in the design?

11.
Question 5. What place_opt option is required to perform scan chain
re-ordering during placement?

-optimize_dft
What place_opt option is required to perform power
optimization during placement?

-power
Question 6. What is the reported standard cell utilization?

The utilization percentage is around 81%.

Question 7. Are there any user-defined path groups?

Lab 3-10 Placement

Answers / Solutions Lab 3

Yes. From the path group names COMBO, INPUTS and

OUTPUTS we can assume that these are user-defined I/O
path groups.
Question 8. Why are we not concerned about hold time violations?

By default place_opt optimizes only setup timing

violations. It ignores hold timing. We will address hold
timing during clock tree synthesis.
Question 9. Has the utilization changed significantly?

No.

Placement Lab 3-11

Lab 3 Answers / Solutions

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Lab 3-12 Placement