15ECL48 Linear ICs and Communication Lab

VTU Syllabus

LINEAR ICs AND COMMUNICATION LAB

Subject Code: 15ECL48 IA Marks: 20

No. of Practical hrs per week: 03 Exam Marks: 80
Total no. of Practical hrs: 42 Exam Hours: 03

LABORATORY EXPERIMENTS:

1. Design an Instrumentation amplifier of a differential mode gain of ‘A’ using three

amplifiers.
2. Design of RC Phase Shift and Wein’s Bridge Oscillators using Op-Amp.
3. Design active second order Butterworth LPF and HPF.
4. Design 4 bit R-2R Op-Amp DAC (i)using 4 bit binary input from toggle switches and
(ii) by generating digital inputs using mod-16 counter.
5. Design Adder, Integrator and Differentiator using Op-Amp
6. Design of Monostable and Astable Multivibrator using 555 Timer.
7. Demonstrate Pulse sampling, flat top sampling and reconstruction.
8. Amplitude modulation using transistor/FET (Generation and detection).
9. Frequency modulation using IC 8038/2206 and demodulation.
10. Design BJT/FET Mixer.
11. DSBSC generation using Balance Modulator IC 1496/1596.
12. Frequency synthesis using PLL.

COURSE LEARNING OBJECTIVES:

1. Design, Demonstrate and Analyze instrumentation amplifier, filters, DAC, adder,

differentiator and integrator circuits, using op-amp.
2. Design, Demonstrate and Analyze multivibrators and oscillator circuits using Op-amp.
3. Design, Demonstrate and Analyze analog systems for AM, FM and Mixer operations.
4. Design, Demonstrate and Analyze balance modulation and frequency synthesis.
5. Demonstrate and Analyze pulse sampling and flat top sampling.

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15ECL48 Linear ICs and Communication Lab

COURSE OUTCOMES:

At the end of the course the students will be able to:

1. Examine AM, FM techniques and frequency synthesis.
2. Design and analyze the performance of instrumentation amplifier, LPF, HPF, DAC and
oscillators using linear IC
3. Examine the flat top sampling techniques and reconstruction of signals.
4. Understand the applications of Linear IC for addition, integration, differentiation and
555 timer operation to generate signals/pulses.

TABLE OF CONTENTS

EXP. NO. TITLE OF THE EXPERIMENT PAGE NO.

1 Instrumentation Amplifier 3
2(a) RC Phase Shift Oscillator 5
2(b) Wein Bridge Oscillator 7
3(a) Second Order Active Low-Pass Filter 9
3(b) Second Order Active High-Pass Filter 11
4 R-2R DAC 13
5(a) Summing Amplifier 16
5(b) Integrator 18
5(c) Differentiator 20
6(a) Astable multivibrator 22
6(b) Monostable multivibrator 25
7 Flat-Top Sampling 27
8 Amplitude Modulation and Demodulation 29
9 Frequency Modulation and Demodulation 32
10 BJT/FET Mixer 34
11 DSBSC generation 36
12 Frequency synthesis using PLL 38

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15ECL48 Linear ICs and Communication Lab

Experiment No. 1

INSTRUMENTATION AMPLIFIER

AIM: To design an instrumentation amplifier of a differential mode gain of 1.2 using three
amplifiers

APPARATUS:
Name Description Qty
Op-amp μA-741 3
10 KΩ 1
Resistors
1 KΩ 6
Dual mode DC Power Supply 0–30 V 1
AFO - 1
CRO - 1
DC Power Supply 0-30V 2

CIRCUIT DIAGRAM:

DESIGN:
Overall gain=A=ACL1×ACL2
ACL1 = Voltage gain of differential input/output amplifier
ACL2 = Voltage gain of difference amplifier

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15ECL48 Linear ICs and Communication Lab

ACL1=(2R1+R2)/R2
ACL2= R5/R4
Assume R1=R3=R4=R5=R6=R7=1kΩ
Given A= 1.2
ACL2=1
ACL1= (2R1+R2)/R2=1.2
Simplifying R2=10kΩ

PROCEDURE:
1. Rig up the circuit as shown in the figure.
2. Apply input V1=V2 and measure the output.
3. Apply inputs V1= 2V and V2 = 4V and measure the output.

TABULER COLUMN:

SL.NO INPUT V1 INPUT V2 THEORITICAL VOUT PRACTICAL VOUT

1 2V 2V 0V
2 2V 4V

CONCLUSION:

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15ECL48 Linear ICs and Communication Lab

Experiment No. 2(a)

RC PHASE SHIFT OSCILLATOR

AIM: To design a RC Phase Shift Oscillator to produce a 3 kHz output frequency.

APPARATUS:
Name Description Qty
Op-amp μA-741 1
6.8 KΩ 3
Resistors
220 KΩ 2
Capacitor 3300 pF 3
Dual mode DC power supply 0–30 V 1
AFO - 1
CRO - 1

CIRCUIT DIAGRAM:

DESIGN:
Select I1= =100*500nA=50µA
V0=+ =+(12V-1V) = +11V
Vi= =+11V/29 =+379mV
R1 =379mV/ 50µA=7.6kΩ (Use 6.8kΩ standard value)

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R1=R4=R5
R2 = =29*6.8kΩ=197kΩ (Use 220kΩ standard value)
R2=R3
f= √
C= √ =3185 pF (Use 3300 pF standard value)

PROCEDURE:
1. Rig up the circuit as shown in the figure.
2. Observe the output on CRO and measure the output frequency.

EXPECTED GRAPH:

RESULT:
Theoretical value of output frequency:
Practical value of output frequency:

CONCLUSION:

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15ECL48 Linear ICs and Communication Lab

Experiment No. 2(b)

WEIN BRIDGE OSCILLATOR

AIM: To design a RC Wein’s Bridge Oscillator to produce a 1 kHz output frequency.

APPARATUS:
Name Description Qty
Op-amp μA-741 1
15KΩ 3
Resistors
33 KΩ 1
Capacitor 0.01 µF 2
Dual mode DC power supply 0–30 V 1
AFO - 1
CRO - 1

CIRCUIT DIAGRAM:

DESIGN:
Condition for balance is
For , R1=R2 and C1=C2
Select C1=C2=0.01 µF

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15ECL48 Linear ICs and Communication Lab

w.k. =1 kHz
=15.9 kΩ (use15 kΩ standard value)
R1=R2= 15 kΩ
Select R4=R2= 15 kΩ
R3=2R4=30 kΩ (use 33 kΩ standard value)

PROCEDURE:
1. Rig up the circuit as shown in the figure.
2. Observe the output on CRO and measure the output frequency.

EXPECTED GRAPH:

RESULT:
Theoretical value of output frequency:
Practical value of output frequency:

CONCLUSION:

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15ECL48 Linear ICs and Communication Lab

Experiment No. 3(a)

SECOND ORDER ACTIVE LOW-PASS FILTER

AIM: To designa second order active low-pass Butterworth filter for cut off frequency of 1
KHz with a pass-band gain of 2 and to determine its frequency response, cut-off frequency
and roll-off rate.

APPARATUS:
Name Description Qty
Op-amp μA-741 1
10 KΩ 2
Resistors
15 KΩ 2
Capacitor 0.01 μF 2
Dual mode DC power supply 0–30 V 1
AFO - 1
CRO - 1

CIRCUIT DIAGRAM:

DESIGN:
High cut-off frequency fH= 1KHz
1
Pass-band gain = A = 1  R F = 2fH =
R3 2 R1 R2 C1C 2
Choose C1 = C2 = 0.01µF then R1=R2=15.9KΩ
Choose R1 = R2 = 16KΩ

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If RF= 10KΩ then R3=10KΩ

Roll-Off rate = (Gain at 10 fH in dB) - (Gain at fH in dB)

PROCEDURE:
1. Set the signal generator input to 1V.
2. Vary the input frequency from 100Hz to 100 KHz and note down the corresponding
outputvoltage.
3. Plot frequency response on a graph with Gain in dB on Y-axis andFrequency on X -
axis.
4. Calculate 3dB frequency and Roll-Off rate.

EXPECTED GRAPH:

TABULAR COLUMN:
Vin = 1V
Frequency (Hz) Vo (Volts) Vo/Vin Gain in dB= 20 log(Vo/Vin)

RESULTS:
Theoretical cut-off frequency: 1 KHz Practical cut-off frequency:
Theoretical pass-band gain: 2 Practical pass-band gain:
Theoretical Roll-Off rate:-40 dB/decadePractical Roll-off rate:

CONCLUSION:

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15ECL48 Linear ICs and Communication Lab

Experiment No. 3(b)

SECOND ORDER ACTIVE HIGH-PASS FILTER

AIM: To design a second order active high-pass Butterworth filter for cut-off frequency of 1
KHz with a pass-band gain of 2 and to determine its frequency response, cutoff frequency
and roll of rate.

APPARATUS:
Name Description Qty
Op-amp μA-741 1
10KΩ. 2
Resistors
15KΩ 2
Capacitors 0.01μF 2
Dual mode DC power supply 0–30V 1
AFO - 1
CRO - 1

CIRCUIT DIAGRAM:

DESIGN:
Low cut-off frequency fL= 1KHz

Pass band gain = A = 1  R F =2

R3
1
fL =
2 R1 R2 C1C 2

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Choose C1 = C2 = 0.01µF, then R1 = R2 = 15.9KΩ

Choose R1 = R2 = 16KΩ
Choose RF= 10KΩ, then R3 = 10KΩ
Roll-Off rate = (Gain atfL in dB) - (Gain at 0.1fL in dB)

PROCEDURE:
1. Set the signal generator to 1 V.
2. Vary input frequency from 100Hz to 100 KHz and note down correspondingoutput
voltage
3. Plot frequency response on a graph with Gain in dB on Y-axis and Frequency on X-
axis.
4. Calculate 3dB frequency and Roll-Off rate.

EXPECTED GRAPH:

TABULAR COLUMN:
Vin = 1V
Frequency (Hz) Vo (Volts) Vo/Vin Gain in dB= 20 log(Vo/Vin)

RESULTS:
Theoretical cut-off frequency: 1 KHz Practical cut-off frequency:
Theoretical pass-band gain: 2 Practical pass-band gain:
Theoretical Roll-Off rate: 40 dB/decade Practical Roll-off rate:

CONCLUSION:

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15ECL48 Linear ICs and Communication Lab

Experiment No. 4

R-2R DAC USING OP-AMP

AIM: To Design 4 bit R-2R Op-Amp DAC (i) using 4 bit binary input from toggle switches
and (ii) by generating digital inputs using mod-16 counter.

APPARATUS:
Name Description Qty
Op-amp μA-741 1
Resistors 1 KΩ 4
2 KΩ 5
JK FLIP FLOP IC7476 2
Digital Trainer Kit - 1
AND IC 7408 1

CIRCIUT DIAGRAM:

Pin diagram of IC 7493

i) 4 bit binary input from toggle switches

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15ECL48 Linear ICs and Communication Lab

PROCEDURE:
1. Connect the circuit as shown in figure.
2. Vary the values of D0, D1, D2 & D3 as shown in tabular column.
3. Note down the corresponding output voltage.
4. Plot a graph of analog voltage vs. digital inputs.

(ii) Digital inputs using mod-16 counter.

DESIGN:
Select R = 1 kΩ, then 2R =2 kΩ
J3=K3=Q2Q1Q0, J2=K2=Q1Q0 , J1=K1=Q0 and J0=K0=1.

PROCEDURE:
1. Connect the circuit as shown in figure.
2. Apply pulse as clock with amplitude of 5V(P-P) at a frequency of 1kHz(pin no 14)
and apply Vcc of 5V
3. Vary the values of D0, D1, D2 & D3 as shown in tabular column.
4. Note down the corresponding output voltage.
5. Plot a graph of analog voltage vs. digital inputs.

Theoretical Vout= Vref *(8D3+4D2+2D1+D0) / 24

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TABULAR COLUMN:
D3 D2 D1 D0 Theoretical Vout Practical Vout
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

EXPECTED WAVEFORM:

CONCLUSION:

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15ECL48 Linear ICs and Communication Lab

Experiment No. 5(a)

SUMMING AMPLIFIER

AIM: To design Summing Amplifier (Adder) using Op-Amp

APPARATUS:
Name Description Qty
Op Amp µA741 1

Resistors 1 KΩ 3

DC Power Supply - 3

CIRCUIT DIAGRAM:

DESIGN:

Let
PROCEDURE:
1. Rig up the circuit as shown in figure.
2. Apply input V1=0.5V and V2=0.5V
3. Measure the output using multimeter and compare it with theoretical value

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15ECL48 Linear ICs and Communication Lab

RESULT:

Sl no Input V1(V) Input V2(V) Theoretical Practical

output(V) output(V)
1 0.5 0.5 1
2 1 1.5 2.5

CONCLUSION:

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15ECL48 Linear ICs and Communication Lab

Experiment No. 5(b)

INTEGRATOR

AIM: To design Integrator using Op-Amp

APPARATUS:
Name Description Qty
Op Amp µA741 1
100 KΩ 1
Resistors
10 KΩ 1

Capacitor 0.01 µF 1

AFO - 1
CRO - 1
DC Power Supply - 1

CIRCUIT DIAGRAM:

DESIGN:
VO= ∫
For an Integrator, ,
Assume C= 0.01µF and T= 0.1 ms then R1=10kΩ

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15ECL48 Linear ICs and Communication Lab

Gain limiting can be produced by shunting the integrator capacitor with a resistor
This resistor sets the upper limit voltage gain to Amax=
Choose RF= 10 R1 then RF= 100 kΩ
Critical frequency is that frequency above which the circuit act like an integrator and it is
given by flow= .

PROCEDURE:
1. Rig up the circuit as shown in figure.
2. Apply the input Square wave of 0.5 V, 1KHz
3. Observe the output on CRO

EXPECTED WAVEFORMS:

CONCLUSION:

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15ECL48 Linear ICs and Communication Lab

Experiment No. 5(c)

DIFFERENTIATOR
AIM:
To design Differentiator using Op-Amp

APPARATUS:
Name Description Qty
Op Amp µA741 1
100 Ω 1
Resistors
5 KΩ 1
0.01 µF 1
Capacitor
1nF 1
AFO - 1
CRO - 1
DC Power Supply - 1

CIRCUIT DIAGRAM:

DESIGN:
VO=

For an Differentiator, ,

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15ECL48 Linear ICs and Communication Lab

Assume C= 0.01µF and T= 0.5 s then Rf= 5 kΩ

Choose R1= then R1= 100Ω

FHIGH = . Where FHIGH is the highest frequency for differentiator .

Hence choose Cf= 1nF

PROCEDURE:
1. Rig up the circuit as shown in figure.
2. Apply the input Square wave of 0.5 V, 1KHz
3. Observe the output on CRO

EXPECTED WAVEFORMS:

CONCLUSION:

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15ECL48 Linear ICs and Communication Lab

Experiment No. 6 (a)

ASTABLE MULTIVIBRATOR

AIM: To design and study the Astable Multivibrator circuit using 555 timer.

APPARATUS:
Name Description Qty
IC-555 - 1
Resistors 2.8 K, 5.7 K, 7.2 K 1 each
Capacitors 100 µF, 0.1 µF, 0.01 µF 1 each
Diode IN4001 1
Digital Trainer Kit - 1
Patch cords - -

CIRCUIT DIAGRAM:

1 Gnd555Vcc 8
2 Trg Dis 7
3 Out Thr 6
4 Rst Ctl 5

(a) ASYMMETRIC ASTABLE MULTIVIBRATOR:

Vc
5V
RA 100µF
2.8K
7 8
6 555 4
RB 2 3
5.7K 1 5 Output

C
0.1µF
0.01µF

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15ECL48 Linear ICs and Communication Lab

DESIGN:
Frequency = 1 KHz
T = TON + TOFF = 1 ms
TON
Duty Cycle = 60%, i.e.  0.6
TON  TOFF
i.e., TON = 0.6 ms and TOFF = 0.4 ms
TON = 0.693(RA + RB)C TOFF = 0.693RBC
Choose C = 0.1µF
RA = 2.8 KΩ
RB = 5.7 KΩ

(b) SYMMETRIC ASTABLE MULTIVIBRATOR:

Vc
5V
RA 100µF
7.2K
7 8
6 555 4
RB 2 3
1N4001 7.2K 1 5 Output

C
0.1µF
0.01µF
DESIGN:
Frequency = 1 KHz
T = TON + TOFF = 1 ms
TON
Duty Cycle = 50%, i.e.  0.5
TON  TOFF
i.e., TON = 0.5 ms and TOFF = 0.5 ms
TON = 0.693RA C
TOFF = 0.693RBC
RA =7.2KΩ(or 10k pot)
RB =7.2KΩ

PROCEDURE:
1. Design the circuit for practical time period oscillation.
2. Connect the circuit with accurate value of components.
3. Observe the rectangular wave output at pin 3.
4. Check the charging and discharging voltage across the 0.1 µF capacitor and note
down the values of 2Vcc/3 and Vcc/3.

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 15ECL48 Linear ICs and Communication Lab

EXPECTED WAVEFORMS:

Output
(Pin3)

TON TOFF

+Vcc

Capacitor t
Voltage

2Vcc/3

Vcc/3

RESULT:
Asymmetric Astable Multivibrator: Symmetric Astable Multivibrator:
Theoretical Practical Theoretical Practical
Parameters Parameters
Value value Value value
TON TON
TOFF TOFF
Vcc Vcc
2 Vcc/3 2 Vcc/3
Vcc/3 Vcc/3
Frequency Frequency

CONCLUSION:

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10ECL58 Analog Communication & LIC Lab

Experiment No. 6 (b)

MONOSTABLE MULTIVIBRATOR

AIM: To design and study the monostable multivibrator circuit using 555 timer.

APPARATUS:
Name Description Qty
IC-555 - 1
Resistors 9.1 KΩ 1
0.1 µF 1
Capacitors
0.01 µF 1
Digital Trainer Kit - 1
Patch Cords - -

CIRCUIT DIAGRAM:

DESIGN:
Let the time for which output remaining high, Tp= 1 ms
Tp= 1.1RAC, where C=0.1µF. So, RA= 9.1 KΩ

PROCEDURE:
1. Connect the circuit as shown above.
2. Give a trigger input to pin 2 and observe the output at pin 3.
3. Observe the charging and discharging waveforms across 0.1 µF.
4. Note down the value of 2Vcc/3.
5. Verify the charging period and the ON period for which it is designed.

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 10ECL58 Analog Communication & LIC Lab

EXPECTED WAVEFORMS:

Trigger
Input

+Vcc

Output

+5v

Vc

2Vcc/3

RESULT:
Theoretical Practical
Value value
Tp
Vcc
2 Vcc/3

CONCLUSION:

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10ECL58 Analog Communication & LIC Lab

Experiment No. 7
FLAT –TOP SAMPLING

AIM: To Demonstrate Pulse sampling, flat top sampling and reconstruction.

APPARATUS:
Name Description Qty
Op-amp μA-741 2
Capacitor 0.1µF 2
Resistors 1.5 KΩ 2
10 KΩ 4
Transistor SL100 1
SK100 1
CRO - 1
AFO - 2

CIRCIUT DIAGRAM:

PROCEDURE:
1. Connect the circuit as shown in figure.
2. Apply sine wave with amplitude of 5V(P-P) at a frequency of fm<1kHz as message
signal m(t) .
3. Apply pulse as carrier signal c(t) with amplitude of 8- 10V(P-P) at a frequency of
fc >2fm(oversampling).
4. Observe the Sampled signal on CRO.
5. Compare the reconstructed signal with original message signal.
6. Repeat the above steps for fc=2fm(sampling at nyquist rate) and
fc<2fm(undersampling).

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EXPECTED WAVEFORM:

TABULAR COLUMN:

Sampling Parameter Message Carrier Sampled Reconstructed

methods signal signal signal signal
Oversampling Amplitude
fc>2fm Frequency
Nyquist rate Amplitude
fc=2fm Frequency
Undersampling Amplitude
fc<2fm Frequency

CONCLUSION:

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10ECL58 Analog Communication & LIC Lab

Experiment No. 8

AMPLITUDE MODULATION AND DEMODULATION

AIM: To study the Amplitude Modulation and Demodulation circuits and determine the
modulation index

APPARATUS:
Name Description Qty
Transistor BC107 1
22 KΩ 1
6.8KΩ 1
Resistors
10 KΩ 1
1 KΩ 1
Capacitor 0.01µF 1
Inductor 130 mH 1
AFO - 2
CRO - 1

CIRCUIT DIAGRAM:
(a) MODULATION

%Modulation Index (µ) = ((Amax – Amin)/(Amax + Amin)) × 100

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(b) DEMODULATION:

DESIGN:
1
Tmod>> RLC >>Tcarr, Fmod=
2R LC 
PROCEDURE:
1. Rig up the circuit as shown in the circuit diagram
2. Apply a carrier of 11 KHz with amplitude of 15Vp-p.
3. Apply a message signal of 1 KHz with amplitude of 2 VP-P.
4. Observe AM wave on CRO and note down Amax and Amin.
5. Calculate percentage modulation (µ).
6. Apply AM output to demodulation circuit and observe demodulation waveform on
CRO.
7. Compare demodulation output with the original message signal.

EXPECTED WAVEFORMS:

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10ECL58 Analog Communication & LIC Lab

TABULAR COLUMN:

(a) MODULATION:

Carrier signal Modulating signal

Amax Amin
Ac fc Am fm µ (%)
(V) (V)
(V) (Hz) (V) (Hz)

(b) DEMODULATION:

Am (V) fm(Hz) Am’ (V) fm’ (Hz) Phase shift between m(t) and m’(t)

CONCLUSION:

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10ECL58 Analog Communication & LIC Lab

Experiment No. 9

FREQUENCY MODULATION AND DEMODULATION

AIM: To study the Frequency Modulation and Demodulation using trainer kit

APPARATUS:
FM Trainer Kit, AFO, CRO, Patch cords

CIRCUIT DIAGRAM:
(a) MODULATION

(b) DEMODULATION

PROCEDURE:
1. Make the input/output connection for the trainer kit as shown the figure.
2. Set the modulating signal frequency and amplitude.
3. Make adjustment till the FM signal is obtained.

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10ECL58 Analog Communication & LIC Lab

4. Note down the minimum and maximum frequency fmin and fmax
5. Calculate modulation index β and bandwidth.
6. Connect the modulated output to the demodulator.
7. Compare the demodulated output with original message signal.

EXPECTED WAVEFORM:

m(t)

TABULAR COLUMN:
(a) MODULATION:

Input signal Input frequency

fmin fmax ∆f=(fmax-fmin)/2
(V) (Hz)
Sine
wave

(b) DEMODULATION
Input signal Demodulated signal
Amplitude Frequency Amplitude frequency

CONCLUSION:

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10ECL58 Analog Communication & LIC Lab

Experiment No. 10
BJT MIXER

AIM:To design and verify the output of mixer.

APPARATUS:
Name Description Qty
Transistor BC107 1
10k 1
1k 2
Resistors
6.8 k 1
22 k 1
Capacitor 0.01µF 1

Inductor 1 mH 1
AFO - 2
CRO - 1
RPS - 1

CIRCUIT DIAGRAM:

DESIGN:
Assume C =0.1
Calculate value of L1 using f= where f=7 KHz
√

PROCEDURE:
1. Rig up the circuit as shown in the figure.

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10ECL58 Analog Communication & LIC Lab

2. Apply the input signals

3. Note down the frequency of the output signal, which is same as difference frequency of
given signals.

TABULAR COLUMN:
Parameter Input signal 1 Input signal 2 Output signal
Amplitude(V)
Frequency(Hz)

CONCLUSION:

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10ECL58 Analog Communication & LIC Lab

Experiment No. 11
DSBSC MODULATION

AIM: To study the Frequency Modulation and Demodulation using trainer kit

APPARATUS:
Name Description Qty
Balance Modulator IC1496 1
10 k 2
1 k 4
3.9 k 2
Resistors
6.8 k 1
51 k 3
100 k POT 1

Capacitor 0.1µF 2
AFO - 2
CRO - 1
RPS - 1

CIRCUIT DIAGRAM:

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10ECL58 Analog Communication & LIC Lab

Pin diagram of IC1496

PROCEDURE:
1. Rig up the circuit as shown in the figure.
2. Apply a carrier signal of amplitude 0.5 V and frequency of 83 kHz .
3. Apply a message signal of amplitude 0.25 V and frequency of 5 kHz .
4. Observe the DSBSC waveform at pin no. 12.

EXPECTED WAVEFORM:

CONCLUSION:

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10ECL58 Analog Communication & LIC Lab

Experiment No. 12

FREQUENCY MULTIPLIER USING PLL

AIM: To design and construct a frequency multiplier circuit using PLL IC NE565 and to
verify it’s working.

APPARATUS:
IC NE565, IC7490, Resistors, Capacitors, transistor-BC107, dual power supply, AFO,
CRO, +5V Supply.

CIRCUIT DIAGRAM:

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10ECL58 Analog Communication & LIC Lab

DESIGN:
The free running frequency of VCO is (1)

Choose, ,
R2=R3=
, ,

Therefore,

The lock range ‘ ’ is given by

So the upper (max) lock frequency

And lower (min) lock frequency

The capture range,

[ ]

=
The lower and upper capture frequencies are
And

PROCEDURE:
1. Rig up the circuit as shown in the figure.
2. Initially, disconnect pin 11of 7490(decade counter) and connect pin 4 and 5 of PLL.
3. Observe the free running VCO frequency at pin 4 by keeping input off.
4. Switch on the input and increase the input (say from 1 KHz) until lower capture
frequency where PLL output starts tracking (following) the input frequency. Now
PLL are said to be in phase-locked state.
5. Further increase the input frequency and note down the upper lock frequency ( ) at
which PLL output just loses the track with input.
6. Now decrease input slowly until PLL again gets locked. Note down this frequency as
upper capture frequency .
7. Further decrease the input and note down the lower lock frequency ( ) at which PLL
output just loses the track with input.
8. Now reconnect to the circuit as shown in figure and measure the input and output
frequency when the PLL is in lock range.

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10ECL58 Analog Communication & LIC Lab

RESULT:

Case 1
Free running frequency,

Therefore, capture range

Lock range,
Case 2
When PLL is lock range,

CONCLUSION:

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