EE530L Lecture Notes

230103: Basic circuits theory

An analog/continuous quantity is one that is represented using Real numbers. In contrast, a
digital/discrete quantity is represented using Integers.

Very Large Scale Integrated (VLSI) circuits are fabricated using modern semiconductor wafer
fabs. They present several advantageous features relative to discrete components, which has
enabled the exponential growth of computational power and storage capacity, accuracy and
precision, while simultaneously making them more efficient with respect to size and energy
consumption.

Design is the process of iteratively building a system so that it satisfies specified constraints and
provides optimal performance with respect to a given metric. Design problems typically have a
set of several solutions satisfying the constraints, rather than a unique solution, and part of the
design process is choosing from among this set of solutions in order to optimize with respect to
the given performance metric. The optimization is typically performed iteratively, but in a
select-few simple cases, it can be done analytically.

Some basic Network theorems are reviewed below:

1. Kirchoff’s Current Law (KCL) for sum of the currents at any junction:

2. Kirchoff’s Voltage Law (KVL) for sum of the voltage drop around any loop:

3. Thevenin’s Theorem: A two-terminal network may be replaced with a single voltage

source of strength equal to the open-circuit voltage across the two-terminals, and
impedance equal to the looking-in impedance.
4. Norton’s Theorem: A two-terminal network may be replaced with a single current source
of strength equal to the short-circuit current across the two-terminals, and impedance
equal to the looking-in impedance.
5. Millman’s theorem for the equivalent voltage of a parallel connection of several voltage
sources:
 6. Tellegen’s theorem for sum of instantaneous power dissipated across all the branches in a
network:

7. Euler’s Formula relating the number of nodes/junctions/vertices , edges/branches ,

and loops/faces , in a network:

It may be noted that the above network has branch voltages and branch currents. To
solve for these unknowns, we have device characteristics, KCL
equations, and KVL equations. But 1 node KCL is redundant (each branch current
appears with a positive sign at one node and a negative sign at the other node, so that the
sum of all currents at all nodes is zero anyway), and therefore we obtain another
independent equations. Thus we have a total of equations to obtain
a unique solution for unknown variables.

Symbols and notation:

Ground rail: ,

Power rail: ,

Voltage source: ,

Current source: ,
Resistor: ,

Capacitor: ,
Inductor: ,
Diode: ,

n-MOSFET: ,

p-MOSFET: .
230117: Device physics relevant to circuits
The contact potential of a pn-junction diode is

where , is the absolute temperature, is the

electronic charge, and are the acceptor and donor atom concentrations on the p- and
n-sides,

is the product of the hole and electron concentration in pure Silicon, is the Silicon
bandgap, is Planck's constant, and and are the effective electron
and hole masses. At room temperature, .

The large signal diode current and small-signal conductance and capacitance of a diode are given
by:

where is the external forward bias from the p-type semiconductor to the n-type
semiconductor, is the reverse saturation current, and is the average carrier transit time at
the junction before recombination. and are typically of the order of 100s of pA and ps
respectively.

The large-signal drain current and small-signal transconductance and output impedance models
for an n-channel MOSFET in the active region ( ) are given below:

The channel-length modulation parameter is inversely proportional to the channel length and
may be expressed as
where is the channel length. In typical sub-micron semiconductor technologies,
.
The subthreshold current for small positive is given by

Note that the voltage in the exponent is and not .

The circuit equations for a p-channel MOSFET in the active region ( ) are very
similar, with the only difference being that the drain and gate potentials must be lower than the
source potential ( ) to form a channel of holes and
conduct, and that the drain current is negative (that is, channel holes flow out of the drain
terminal, rather than into the drain terminal):

The subthreshold conduction is also similar to that in an n-channel MOSFET:

230124: Linear two-port networks

A single-port device can only provide a single equation relating its voltage to its current and vice
versa. It is therefore not possible to specify a non-dimensional gain parameter for a single-port
device. We need at least two ports to do so.

Consider a general two-port network with an

input port voltage and current and , and an
output port voltage and current and . If the
network is primarily a voltage-controlled
current source, the network equations may be
written in terms of a y-parameter matrix (see
adjacent figure) as

Conventionally, the primary output comes at the bottom left, and the primary input at the top
right. The port voltages may be expressed in terms of the source and load equations as
Eliminating the voltages and , we obtain

Since we are interested in input-to-output gain, we extract out of the above equation and
compute the load voltage .

As can be see from the above expression for the gain, we would like to maximize in the
numerator, minimize and in the denominator, and null in the denominator. The last
requirement is so that the denominator does not cross over zero, and flip the polarity of the gain
from a large positive number to a large negative number.

For nonlinear circuits, the y-parameters are defined with respect to small-signal parameters as

For the small-signal model of a MOSFET (see adjacent figure)

working as a VCCS with a resistive load , we obtain the
correspondence

yielding a gain of
230127: Common-source amplifier design example

Application specifications: Consider a typical analog application like measuring the strain in a
beam using a piezo-resistive transducer (see above figure). The raw output of the transducer in
such applications is of the order of tens of mV. Measuring such a small signal using an
Analog-to-Digital converter (ADC) would introduce relatively large errors of the order of a few
mV. A good design for the measurement system would therefore first amplify the small signal at
the output of the transducer before feeding it to the input of the ADC, while itself not
contributing to significant errors. Suppose the maximum output from the transducer is 30 mV,
and the acquisition system works off a 3.0V to 3.6V battery supply , which is a common
supply voltage for mixed-signal electronics. We are then interested in amplifying a signal of the
order of 30 mV to around 3 V, that is by a factor of nearly 100. Let us therefore design a
common-source amplifier which works off 3V to provide a voltage amplification of around 100.
Device specifications: Given a supply voltage around 3 V, the gate-oxide thickness must be
to prevent gate-oxide dielectric breakdown, yielding for an
n-channel MOSFET in typical semiconductor technologies. The channel length must be at least
in order to prevent drain-to-source channel breakdown, and we may assume the
minimum channel width is also going to be close by that number, say . Let the
channel length modulation parameter be given by . Finally let the uncertainty
in the MOSFET threshold voltage be rms , which is going to
determine the accuracy of this amplifier design.

Problem statement: Design a common-source amplifier constrained by the above device

specifications and providing a gain of at least 100.

Design:
We will look at the simplest possible amplifier configuration with the most rudimentary active
device, namely an n-channel MOSFET operating as a voltage controlled current source, with the
gate-to-source voltage controlling the drain-to-source current. This amplifier configuration is
called the common source amplifier since the source terminal of the MOSFET is common to the
input and the output ports. Let the load of the amplifier be a simple linear resistor as shown
below.
We have to determine the following circuit parameters for a
common-source amplifier design:
1. The and of the MOSFET,
2. the gate bias overdrive , and
3. the load resistance .
We have the MOS transconductance and output impedance given
by

and the quiescent current and load resistance given by

where the last equation follows from the requirement that the
output be biased at mid-supply voltage under nominal conditions in order to maximize swing in
both directions.
The overall gain of the amplifier is

which we wish to be around 100. Given that , must be less than 30 mV in order
to have any solution for the length at all. We could therefore choose, for example,

so that the amplifier gain is

Having obtained the and , we may now derive the value of to obtain an rms threshold
voltage uncertainty of 0.1 mV:

The value of the load resistance must be 2.7 k-Ohms as expressed previously.

The above common-source amplifier still has several issues/questions that need to be addressed:
1. The design value of for meeting the gain specification is a tad bit too low to justify
the square-law model. We would like it to be around 100 mV typically, or our models of
and will be widely off.
2. How do we feed the differential output of the transducer to the amplifier gate so as to bias
it at a desired ? What about the variation of the threshold voltage with process and
temperature?
3. What about the dynamic performance of the amplifier? Its settling time should be
sufficiently small so that the output to the ADC settles to within tolerable margins in the
sampling time.
4. What about the noise performance of the amplifier? This is also going to limit the
accuracy of the amplifier.
5. Is the amplifier output a linear reproduction of the input signal?
6. How much additional power would be dissipated by introducing the amplifier in the
signal chain?
230201: Achieving the intrinsic amplifier gain with a
nonlinear load
The primary limitation on the gain of the previous amplifier design is on account of the linear
load resistance which leads to the second term of the denominator in the expression for gain.
This limitation may be circumvented by the use of a nonlinear load. The nonlinearity must be of
a particular kind, which is that the load must have a sublinear I-V characteristic, like the ID-VDS
characteristic of a MOSFET, and not a super-linear characteristic, like the I-V characteristic of a
diode. That is, the load current should quickly ramp up for small voltages across it and then stay
nearly constant as the output voltage swings across the remainder of the supply. An ideal load
would be one whose current is a step function of the voltage across it, with the amplitude of the
step controlled to match the nominal current of the amplifying n-channel MOSFET device. A
more realistic load would be a complementary p-channel MOSFET, as displayed in the circuit
below.

The drain current of a p-channel MOSFET is given in terms of its gate-voltage by a very similar
expression as for the n-channel MOSFET:

where we note that and are both negative for a p-channel MOSFET. The
threshold gate-to-source voltage for the formation of the p-channel is . Following
the convention that positive currents flow in, the drain current of a p-channel MOSFET is also
negative. The source terminal is at a higher potential than the drain terminal as it supplies holes
to the channel. Thus, is also negative.

The first-order small-signal parameters of the p-channel MOSFET are

The output impedance of the common-source n-channel MOSFET

amplifier with a p-channel MOSFET as the load is given by

where the subscripts n and p indicate the quantities corresponding

to the n-channel and p-channel MOSFETs respectively.
Furthermore, the currents of the n-channel and p-channel
MOSFETs must be equal to each other:
This yields an overall amplifier gain of magnitude

We could now choose the length of the p-channel MOSFET independently such that the second
term in the denominator is no larger than the first, so that the overall gain is at least
230202: Differential input gain stage
The operating input voltage of the common-source amplifier is not well-defined since the
threshold voltage varies with the manufacturing process, temperature, body bias etc. This makes
it difficult to use in a real application, where the operating voltage may be determined by other
constraints. In order to bias the input MOSFET and also to convert the differential output of the
transducer to a single-ended input, we use a differential input stage with a current bias, as shown
in the below schematic. Let the differential input voltages be on one side and on the
other, the differential output voltages be and , and let the common node connecting
both MOSFETs’ source terminals to the current sink be at a voltage of , all voltages being
specified relative to some common reference ground terminal.
The MOSFET drain currents may be expressed in terms of the input as:

The low frequency small signal model for the differential input stage opens the current sink and
shorts the input common-mode voltage source.
The small signal drain currents and output voltages are
Solving the above equations, we obtain for the sink and output nodes

The last equation may be rearranged to obtain the differential gain of the amplifier as

which is the same expression as for the simple common-source amplifier. The advantage with
this circuit is that its operation is, by design, independent of absolute quantities such as the input
common-mode and the threshold voltage. Consequently, the input stages of VLSI amplifiers are
invariably designed in this form as differential input gain stages.
230214: MOSFET Current mirror
The MOSFET current mirror is essentially a Current Controlled Voltage Source (CCVS)
connected in series with a Voltage Controlled Current Source (VCCS), so that the overall circuit
becomes a Current Controlled Current Source (CCCS). The CCVS is obtained by applying
negative feedback and connecting the drain of a transistor to its gate. Such a connection is
referred to as a diode-connected transistor. When an input current is fed into the drain of the
diode-connected MOSFET, any residual current is used to charge or discharge the gate
capacitance so as to eventually establish a voltage that exactly supports the input current at the
drain. On account of the zero low-frequency gate current of the MOSFET, the negative feedback
of this circuit is perfect (at dc), and the gate voltage is established so that the drain current is
exactly equal to the input current.

Once we obtain a 1:1 MOSFET current mirror, a

simple improvisation yields fractional ratios. We
basically use multiple fingers of the MOSFETs in the
two branches. To obtain , we use
fingers in the CCVS branch and fingers in the
VCCS branch. It is important to note that the
individual MOSFET devices still have the same width
and length, so as to ensure there is no systematic
fabrication mismatch between the two devices. In fact,
more advanced techniques like interleaving and dummy placement are used to obtain
high-quality current mirrors. Typical current mirrors in a CMOS technology with
can achieve matching accuracy of the order of .

The diode-connected transistor can be seen as a

two-terminal one-port device. It has a low-frequency
small-signal model consisting of a conductance of
(since gate is connected to drain) in parallel with the
output impedance . At high frequencies it additionally
presents the drain-to-bulk and gate-to-source capacitances,
and , across the terminals as shown in the
adjacent figure.

The output portion (VCCS) of the current mirror, that is the right branch in the above figure,
presents infinite impedance to the driving CCVS at low-frequencies. At high frequencies, the
output transistor presents the gate capacitance in addition, some of it to the ground and some to
the transistor’s drain which could be carrying signal. For most designs, the load can simply be
approximated as a single capacitance to ground. The small-signal model for the diode-connected
MOSFET is therefore

where is the effective capacitance seen across the terminals of the device.
230216: MOSFET high-frequency model
The diode-connected MOSFET has also helped introduce us
to the high-frequency model for the MOSFET in general. The
high frequency model basically adds capacitances across all
possible terminal pairs. For a four-terminal MOSFET, that
would yield six capacitances.

Among these, the drain-to-source capacitance is typically

ignored at the device level since the terminals are electrically
separated by the gate and the channel or substrate. The
drain-to-bulk and source-to-bulk capacitances are nothing but the depletion capacitances of the
reverse-biased drain-to-bulk and source-to-bulk junctions.

The remaining three capacitances in the small-signal model depend upon the region of operation.
In the active region, the MOSFET presents a gate-to-channel capacitance, gate-to-source and
drain-to-source overlap capacitances, and source-to-bulk and drain-to-bulk junction capacitances.
Since the channel is effectively shorted to the source terminal in the active region, most (around
3/4ths) of the gate-to-channel capacitance is modelled as an additional gate-to-source
capacitance, while the remainder is added to the gate-to-drain capacitance.

In deep triode region, the gate-to-channel capacitance is equally distributed between the source
and drain contributions:

For drain-to-source voltages between 0 and cutoff, the channel capacitance gradually splits more
in favour of the source region compared to the drain region.
In the cutoff region, there is no channel, and we have

Of course, the channel capacitance comes in series with the bulk resistance. In accumulation
cutoff , the resistance is small enough to be ignored. In depletion cutoff (
), the resistance is big enough to affect circuit operation. We will mostly ignore
that complication in this course and simply assume that it is infinite and that there is no
gate-to-bulk capacitance in depletion cutoff.
230216: Feedback
The MOSFET current mirror can also be used to introduce a fundamental idea in circuits,
namely, feedback. In particular, negative feedback with a large loop gain can be used to invert
circuit functions.

Suppose we wish to invert some function .

That is, we wish to implement , given a
subsystem which can perform the operation .
This can be accomplished by placing the function in
the feedback path of a feedback loop as shown in
the adjacent figure. In this system, we have

Note that the magnitude of the loop gain must

be dimensionless and much larger than the identity
function. As long as the feedback is negative and the loop-gain is large, the exact nature of the
gain in the forward block is not very important. This was the crucial insight that led Harold
Black to suggest negative feedback for stabilizing amplifiers in radio transmission.
Note: For vector quantities and transfer function matrix, the magnitude of the loop gain may be
replaced by the smallest eigenvalue of the matrix .

As an application of negative feedback,

consider the example of a diode-connected
MOSFET, where the forward path is a
through connection, and the feedback path
contains the MOSFET VCCS. The circuit
overall contains 6 pairs of voltages and
currents, a pair at the source, a pair at the
load, and two pairs each at the forward and
feedback two-port networks. By applying
KVL for the shunt-connections at the
source and load, we can eliminate 2
currents and 4 voltages to obtain a system described using 6 variables, , , , , , and ,
as depicted in the figure above. The forward path provides two more equations:

the feedback provides two more equations:

where is the equivalent gate-capacitance of the MOSFET, and gives the
MOSFET drain current as a function of the gate and drain voltages with respect to the source.
The source and the load provide two more equations:

With these six equations, we can eliminate five unknowns and solve for the output voltage as

Since the MOSFET current is monotonic with respected to a shorted gate-drain voltage, the
function is invertible and we can take the inverse Laplace transformation of the
above to formally solve for . At low frequencies, when the capacitance provides infinite
impedance, the above may alternatively be expressed as

The equation for may be expressed in the form of a differential equation as

Clearly, the above differential equation has an equilibrium at

Moreover, the equilibrium is stable, which can be proved by considering the positive-definite
Lyapunov function

whose derivative with respect to time is

As long as is a strictly increasing function of , the above is a negative definite function, and
hence the system is asymptotically stable to the equilibrium point.

Alternatively, for a linearized system,

which has a loop gain of

Clearly, the loop gain is negative and approaches infinity at low frequencies.
230220: Differential input single-ended output amplifier
The differential amplifier presented two
sections ago takes a differential input and also
produces a differential output. Sometimes, it
is more convenient to obtain a single-ended
output from a gain stage. A current mirror can
help us achieve this objective as shown in the
adjacent circuit.

The small-signal analysis for this circuit

follows.

The above circuit not only performs the differential-to-single-ended conversion, but also
provides an active p-MOSFET load impedance, and hence higher gain, when compared to the
amplifier with resistive loads.
230221: Common-drain and Common-gate amplifiers
The envisioned MOSFET VCCS can also operate as a VCVS or CCCS by changing the input
and output terminals from the gate and drain respectively. When the output is taken at the source
terminal (with the drain grounded), it is called the source follower or common-drain
configuration. If the output remains at the drain but the input is fed through the source terminal,
it is called the common-gate configuration. The “common” terminal is essentially the signal
ground or reference: it is the source terminal in the common-source configuration, and it is the
drain and the gate in the common-drain and common-gate configurations respectively.

The low-frequency small signal model of the MOSFET when

the source terminal is not grounded is shown in the adjacent
figure. The main change from the common-source model is
the inclusion of the additional transconductance which
models the body-effect on the transistor’s threshold voltage.
Since an increase in the source voltage causes a positive
movement in the threshold (p-MOSFET threshold takes a
smaller negative value, while n-MOSFET threshold takes a larger positive value), which causes a
negative movement in the drain current and a positive movement in the source current, the
direction of this transconductance is from the source to the drain terminals:
In typical sub-micron CMOS technologies,
is of the order of 1/4th or 1/5th of .

The low frequency small-signal gain and output

impedance of the common-drain configuration
may be determined by considering the model in
the adjacent figure. The voltage gain is always
lesser than 1, and is typically of the order of 0.6 to
0.8 for high-impedance loads on account of the
body-effect. However, the output impedance is
low (compared to the common-source
configuration) and can therefore drive larger loads (smaller impedances) better. The input
impedance at the gate terminal is still high at low frequencies. The high input impedance and low
output impedance therefore make this configuration useful as a VCVS, or more precisely, as a
voltage buffer, since the voltage gain is always less than unity.
For the gain of the common-drain amplifier, we obtain:
For its output impedance, we zero the signal and apply a test current at the source terminal to
obtain:

where the subscript CD indicates common-drain configuration. The plain is the output
impedance in the common-source configuration. As may be seen, the output impedance of the
common-drain configuration is the reciprocal of the MOSFET gate and bulk transconductances.

The common-gate configuration can be

analyzed using the current source driven
model as shown in the adjacent figure. In
this configuration, the MOSFET primarily
functions as a unity gain CCCS, since the
input impedance is low (hence current
control) and the output impedance is high
(hence current source). At low frequencies
when the gate current is negligible, the
current gain is (negative) unity. For the current gain in the common-gate
configuration, we obtain a near-unity buffering action as derived below.

which is 3 equations in terms of the four variables , , , and . Eliminating the voltages
from two equations and substituting in the third, we obtain:

The disadvantage of the common-gate configuration is of course the fact that the input is no
longer high impedance. It is in fact relatively low impedance, and hence not easily controlled by
a non-ideal voltage source. The voltage gain may be obtained as below:

which is a wee-bit larger in magnitude than that obtained in the common-source configuration,
primarily thanks to the body-effect.
The input and output impedances may again be determined using test currents at the source and
drain terminals respectively, while removing signal sources. For the input impedance, we obtain:

which is relatively low for MOSFET circuits, since impedances in MOSFET circuits typically lie
between and the reciprocal of . For the output impedance, we obtain:

So the output impedance, , of the current source is amplified by the MOSFET intrinsic gain
plus one. The MOSFET working as a current buffer is also called a cascode transistor.
220224: Source-degenerated MOSFET
The current buffering action of the cascode transistor can also be understood as a consequence of
feedback at the source terminal. If changes in load voltage cause an increase in the transistor
current, this is sensed by the degenerating resistor which generates a positive source voltage,
which in turn reduces the transistor current. As seen above, the source impedance at the source
terminal is amplified and the load impedance at the drain terminal is attenuated by the
common-gate amplifier as seen from the other side. This is useful when we wish to implement a
CCCS with low input impedance and high output impedance. Impedance modification in the
above manner is another useful application of negative feedback.

If input is fed at the gate of a MOSFET with a resistance at the source (see
adjacent figure), it works as a source-degenerated common-source amplifier
with reduced gate transconductance and increased output impedance. The
voltage gain remains nearly the same, however. The advantage in this amplifier
is that the relative accuracy of the resulting current source is much higher since it
is possible to fabricate resistors more accurately in CMOS technologies. Current
mirrors are therefore usually designed with source-degenerated MOSFETs for
better matching and higher accuracy. The analysis for the effective
transconductance of the source-degenerated common-source amplifier (without
the body-effect) follows:

assuming that the load impedance is less than the degeneration impedance. Since can be
fabricated with better absolute accuracy as well as relative matching, the source-degenerated
MOSFET has a more accurate and better matched transconductance compared to a similar
MOSFET.

The output impedance of the source-degenerated current-source amplifier may be derived as

follows:
As may be seen, the output impedance increases by exactly the same amount as that by which the
transconductance degrades, hence preserving the voltage gain for small load impedances. But the
source-degenerated common-source amplifier is seldom used as a VCVS (voltage amplifier), and
more commonly used as a VCCS stand-alone, or as a CCCS (current mirror) in conjunction with
a diode-connected, source-degenerated MOSFET CCVS. Recall that when a circuit is used as a
current source, its load impedance is expected to be small.

When the source-degenerated MOSFET VCCS is driven by

a similar source-degenerated diode-connected MOSFET
CCVS (see adjacent figure), we obtain a source-degenerated
current mirror. The source-degenerated current mirror has
the following advantages:
1. It provides better accuracy and matching since it is
simpler to fabricate a matched resistor pair than a matched
MOSFET pair.
2. It provides higher output impedance than the bare
common-source amplifier, and can therefore drive currents
to higher load impedances.
It also has the following disadvantages:
1. The voltage drop across the degenerating resistor requires additional supply headroom /
dropout.
2. The area of the current mirror increases, especially for low currents and high values of
the resistance.
Remark: While the thermal noise of the source-degenerated current mirror is higher, its flicker
noise is much lower at the output, since the degenerating resistor itself has no flicker noise, while
the MOSFET’s flicker noise is attenuated by the factor .

When the source-degenerated current mirror is used as

the load of a differential input pair, we obtain superior
accuracy at the cost of additional dropout requirement.
The superior accuracy is on account of lower current
mismatch error and lower flicker noise.

The low frequency small-signal gain of the differential

gain stage with source-degenerated current mirror as
the load is derived next. If we denote the
transconductance of the source degenerated
p-MOSFET by , and the input and output
impedances of the source-degenerated current mirror
by and , then we must have:
where

Taking the difference of the top two equations, we obtain

The difference with respect to the basic differential stage is that the regular p-MOSFET output
impedance has been replaced by the source-degenerated p-MOSFET’s output impedance .
Thus the voltage gain is a minor improvement over that of the differential gain stage, but the
accuracy improves on account of the better matching in the current mirror.
Remark: The transconductance and output impedance of the source-degenerated MOSFET have
already been derived earlier in this section. As for the input impedance of a source-degenerated
MOSFET, it is simply the series equivalent of a resistance and a diode-connected MOSFET.
220303: Circuit simulation using spectre
The design and simulation of analog circuits at the schematic level using Cadence tools goes
through the following steps:
1. Plan the circuit according to desired functionality and performance metrics.
2. Start the Cadence drawing tool “virtuoso” from the command line and open the library
manager from the “Tools” menu.
3. Create a new schematic cell in an existing or new library.
4. Draw the first cut design by instantiating the devices, making the necessary connections,
adding input and output pins and checking and saving the design.
5. Start the Analog Design Environment (ADE) from the schematic “Launch” menu.
Optionally, edit the simulator, directory, host, temperature, include files, model libraries,
and analog options, setup the outputs from the simulation, define design variables and
select the analyses that are to be performed on the circuit. Generate the netlist from the
“Simulation” menu in the ADE.
6. Run the spectre simulator from the command line or directly from the ADE.
7. Use Cadence viva visualization and analysis tool to browse through the results and plot
the outputs of interest.
8. Modify the circuit as required and go back to step 4. Keep iterating steps 4 through 8
until the circuit performance specifications are acceptable.
230307: Cascode differential-input gain stage
In order to increase the gain of the differential input gain stage, it is usually modified by adding
a cascode transistor. The basic idea here is to increase the output impedance before driving a
MOSFET in a subsequent output gain stage. This especially makes sense in MOSFET circuits,
where the low-frequency input impedance of a MOSFET is high. With bipolar junction
transistors, the high output impedance can potentially be squandered by the finite input
impedance of the next stage. Such a problem does not arise with MOSFET circuits.

The cascode configuration is most easily understood in the simple case of the
common-source amplifier and extrapolated to more sophisticated gain-stages like
the differential input amplifier. It consists of a common-gate MOSFET operating as
a CCCS (current buffer) stacked at the drain of a common-source MOSFET
operating as a VCCS (transconductance). The low-frequency small-signal
transconductance and voltage gain of a cascoded common-source amplifier may be
derived from the current gain of a common-gate amplifier (refer to previous section
on common-gate amplifier). In the limiting case of very high load impedances, the
voltage gain of the cascode configuration is the square of the voltage gain of the
plain common-source amplifier. The limiting case is straightforward to implement
by using a cascoded complementary MOSFET as the load: in the case of a cascoded n-MOSFET
input transistor, the load could consist of a cascoded p-MOSFET.

The subscript in , , and indicates that the small-signal parameters are those
associated with the cascode transistor.

The effective transconductance and voltage gain with

a cascoded differential input, cascoded
complementary-MOSFET load, and differential output
is identical to the above result, as follows from a half
circuit analysis. With a single-ended output, the gain is
almost similar, if not identical. The differential input
single-ended output regular cascode amplifier is
shown in the adjacent figure. The gates of the
p-MOSFET and n-MOSFET cascode transistors are
driven by constant bias voltage sources. The cascode
bias voltages are generated so as to maximize the
output swing.
 One of the limitations of the above amplifier is the
limited output swing relative to the input. The
single-ended output cannot go lower than
below or the n-MOSFET cascode
transistor on the right arm would exit the active
region and enter the triode region. This limitation
on the output swing may be eliminated by using a
“folded” cascode structure (see adjacent figure).
The folded cascode structure has similar gain as
the regular cascode, but wider output swing,
almost from rail to rail if biased appropriately. The
quiescent power dissipation however doubles since both the input side as well as the folded side
need quiescent bias current.

The constant voltage bias at the gate of the cascode transistor may be generated using any of the
below bias-generation circuits (on the high-side, the n-MOSFETs are replaced by p-MOSFETs,
but the topology remains the same) in order of increasing complexity:

The circuit on the top left is the most simple in that there is no special effort to maximize output
swing or increase output impedance. The other three circuits maximize the output swing by
biasing the cascode transistor at to require a dropout of only from the
ground-rail. The circuit on the top right increases the output impedance by a factor of nearly
of the cascode transistor, while the two on the bottom increase the output impedance by
nearly . The circuit on the bottom left uses positive feedback to increase the output
impedance of the sink transistor by , while the one on the bottom right uses negative
feedback to increase the cascode transistor’s transconductance by .