IET Circuits, Devices & Systems

Research Article

FPGA-based system for heart rate monitoring ISSN 1751-858X

Received on 13th May 2018
Revised 5th March 2019
Accepted on 19th March 2019
E-First on 30th August 2019
doi: 10.1049/iet-cds.2018.5204
www.ietdl.org

Karim Meddah1,2 , Malika Kedir Talha1, Mohammed Bahoura2,3, Hadjer Zairi1

1Department of Electronics and Computer Science, University of Sciences and Technology Houari Boumediene, USTHB, BP32 El alia 16111

Bab Ezzouar, Algiers, Algeria

2Department of Engineering, Université du Québec à Rimouski, 300, allée des Ursulines, Rimouski, QC, Canada
3Department of Electronics, Saad Dahlab University of Blida 1, BP 270, Road of Soumaa, 09000 Blida, Algeria

E-mail: kmeddah@usthb.dz

Abstract: The continuous monitoring of cardiac patients requires an ambulatory system that can automatically detect heart
diseases. This study presents a new field programmable gate array (FPGA)-based hardware implementation of the QRS
complex detection. The proposed detection system is mainly based on the Pan and Tompkins algorithm, but applying a new,
simple, and efficient technique in the detection stage. The new method is based on the centred derivative and the intermediate
value theorem, to locate the QRS peaks. The proposed architecture has been implemented on FPGA using the Xilinx System
Generator for digital signal processor and the Nexys-4 FPGA evaluation kit. To evaluate the effectiveness of the proposed
system, a comparative study has been performed between the resulting performances and those obtained with existing QRS
detection systems, in terms of reliability, execution time, and FPGA resources estimation. The proposed architecture has been
validated using the 48 half-hours of records obtained from the Massachusetts Institute of Technology - Beth Israel Hospital (MIT-
BIH) arrhythmia database. It has also been validated in real time via the analogue discovery device.

1 Introduction software approach. On the basis of the same popular QRS detection
algorithm [3], an improved version has been implemented on
The real-time monitoring of heart failure patients, especially people FPGA [21]. It calculates the threshold value for the next peak
with cardiac arrhythmia, is a very important task [1]. Continuous detection cycle from the median of the eight previously detected
monitoring can help minimise the need for human supervision in peaks. Another algorithm based on the integer WT has been
hospitals [2], and ensure the medical monitoring of individuals at implemented on FPGA for QRS detection using very high speed
risk for cardiac seizures without requiring heavy and costly integrated circuit (VHSIC) VHSIC hardware description language
hospital management. Therefore, the development of an embedded (VHDL) [22]. A simple algorithm for real-time QRS detection
monitoring system is needed. By integrating the acquisition of the from ECG data using an FPGA-based architecture system has been
electrocardiogram (ECG) and its processing on the same embedded presented [23]. It detects a QRS complex based on the slope of the
hardware, it is possible to perform real-time monitoring of this kind 20th sample that follows it and the 20th sample that precedes the
of patient. position of the R-wave. This position is defined when its amplitude
Recently, various algorithms have been developed, in software, is greater than those of the three samples that follow the R position
to detect the QRS complex in the ECG signal. The diversity of and those of the three that precede it [23]. A hardware
approaches in these algorithms clearly reflects the great advances implementation of an improved QRS detector has been proposed,
in the signal processing field [2]. For example, algorithms based on where the decision step was made by comparing the R–R interval
the R-wave slope [3–5], wavelet transform (WT) [6–8], artificial with the calculated time range [24]. Another Advanced RISC
neural networks [9–11], and support vector machines [12–14] have Machines (ARM)-based system for arrhythmia detection was
been proposed for the detection of the QRS complex. However, performed, by exploiting the R-peck detection algorithm, the fast
there are many other approaches such as genetic algorithms [15], Fourier transform (FFT)-based WT and neural network [25]. An
quadratic filter [16] heuristic methods [17], the Hilbert transform FPGA-based real-time detection system of P- and T-wave peaks
(HT) [18], and empirical mode decomposition [19, 20]. from an ECG signal has been proposed [26]; it is based on the
Nowadays, intelligent systems play a large part in our daily life. slope information of the T and P waves, and the T–P interval of the
Therefore, developing new methods is not limited to the software ECG signal. Another FPGA-based system for ECG signal
approach, but can be extended to hardware implementation in order processing able to detect the QRS complex and classify it into
to reduce the power consumption, the size of the prototype, and the either normal or premature ventricular contractions (PVCs) has
computational burden. Hardware implementation using field been designed [27]; its detection step is based on the phase-space
programmable gate array (FPGA) chips has become one of the portrait of ECG described in [28]. The classification step has been
most used of the recent technologies. These chips can be explained in [29]. Inspired by this method [28], and the gridding
considered as a perfect tool for developing telemedicine partition methods [30, 31], a new real-time QRS complex detector,
applications, and are able to perform complex calculations. FPGAs named box-scoring calculation was proposed [32]. Considering the
are preferred to other programmable chips due to their specific fact that only addition and subtraction are needed for box-scoring
purpose components, their low cost, their reconfigurability, and calculation, the fast QRS detection method proposed can be
their highly parallel and interconnected architecture. In the last two implemented on the microcontroller-based wearable ECG system
decades, various hardware implementations for QRS detection in real time [32].
have been proposed. The Pan and Tompkins QRS detection An FPGA architecture for QRS complex detection, based on
algorithm [3] has been implemented on FPGA using Verilog integer Haar transform, has been designed. The performance of this
Hardware Description Language (HDL) [1], improving the design has been evaluated in terms of the total detection accuracy
calculation performance by a factor of about 2.5 compared with the (Acc) (98%) and the silicon consumption (only 8% silicon

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 This paper is organised as follows. After Section 1, Section 2
presents the embedded system, the theory, and the principles of the
method for detecting a QRS complex. Section 3 presents the
proposed architecture including the software and the hardware
implementations. The results are presented and compared with
those from previous detection methods in Section 4. Finally, some
conclusions and perspectives are presented in Section 5.

2 Materials and methods

2.1 Electrocardiography
The ECG represents the electrical activity of the heart. It is widely
used in the medical field due to its non-invasive nature. It is
composed of three main waves: P, T and the QRS, which are the
most essential characteristic of the ECG. Each wave corresponds to
an electrical phenomenon included in the heart area, where the
QRS complex reflects ventricular depolarisation [46]. The ECG
signal is mostly generated by detecting and amplifying tiny
potential charges on the skin. These charges are activated when the
electrical signal in the heart muscle changes and spreads during
each heartbeat. They appear as small rises and falls in the voltage
between two electrodes placed at either side of the heart. To design
and validate the system for the detection of the QRS complex, we
have used the MIT-BIH ECG arrhythmia database [45]. It is made
Fig. 1  Diagram of the proposed embedded system and the validation up of 48 half-hours selected from 24 h of the records of 48
testbed different patients, annotated manually by doctors for each beat. It is
divided into two groups. The first 23 recordings contain a routine
clinical recording, while the remaining records consist of different
arrhythmia diseases such as junctional, complex ventricular, and
supraventricular arrhythmias. These records were digitised at 360 
Hz and band-pass filtered at 0.1–100 Hz with a resolution of 11 
bits over a range of 10 mV [45, 47, 48].

2.2 Embedded system

To build and validate the proposed embedded system, several
electronic modules have been used (Fig. 1). The ECG signal was
acquired with three electrodes, forming a bipolar leads connection,
Fig. 2  Procedure of the proposed algorithm
and a conditioning circuit built on an instrumentation amplifier
AD8232 [49]. This electronic module was modified to enlarge its
resources of the target chip are occupied). This structure has been frequency band up to 120 Hz while adding a 50 Hz notch filter to
adopted later as a core unit to create an FPGA-based system to reject power-line interference. The resulting analogue signal from
recognise stress [33]. A method combining the HT and the the conditioning circuit is passed through an analogue-to-digital
Shannon energy has been proposed for detecting the QRS complex. converter (PmodAD1) to be processed next on the FPGA of a
The FPGA-based implementation was optimised, at the HT stage, Nexys-4 board. After applying the proposed detection method to
by using real-valued FFT (RFFT) and inverse RFFT techniques. Its the obtained ECG signal, the heart rate is sent to 3-digit 7-segment
performances were evaluated using the Massachusetts Institute of displays, provided by the Nexys-4 evaluation kit. The results of the
Technology - Beth Israel Hospital (MIT-BIH) arrhythmia database. detection stage and the original ECG signal are then sent back
It provided significant accuracy (Acc) and sensitivity (Se) of 99.86 through a digital-to-analogue converter (PmodDA2) to be
and 99.95%, respectively [34]. Other FPGA-based systems for displayed on a personal computer (PC) for validation, using the
QRS detection have been proposed in the literatures [1, 21–23, 26, analogue discovery device [50] and the WaveForms interface [51].
27, 35–37, 38, 39]. This optimisation has led us to develop a As shown in Fig. 1, the proposed system can be validated on the
reliable system-on-chip to build robust medical devices [40–42]. MIT-BIH database stored on the PC, using the analogue discovery
The basic idea of our work has been presented in [43, 44]. device.
However, the proposed monitoring system is an improved version
that has a better QRS detection performance, even when the
recordings contain artefacts. The derivative filter has been replaced 2.3 Proposed QRS detection algorithm
by another more suited to the detection of QRS. A non-linear The proposed QRS detection algorithm has two main stages. The
transformation is ensured by the square function, which increases first is a preprocessing stage, which is performed by five
the gap between the peaks and the background noise. Better consecutive filters, beginning with a band-pass filter and a
performing filters were used, where the detection stage is derivative filter, then passed through a squaring filter and an
completely improved by exploiting several amplitude and time integrator filter, ending with a low-pass filter to obtain a smooth
adaptive thresholds to minimise the detection errors. The proposed signal. The next main stage is the R-peak detection stage, which is
detection system is mainly based on the Pan and Tompkins itself composed of three parts: taking the centred derivative,
algorithm, but with the addition of a new, simple, and efficient detecting the maximum peak, and thresholding on the amplitude
technique in the detection stage. Also, it has been implemented on and time, as shown in Fig. 2. In the following sections, this will be
an FPGA chip, using the Xilinx System Generator (XSG) interface. described in detail.
Therefore, this paper presents four main contributions: (i)
development of a new technique for detecting a QRS complex; (ii) 2.3.1 ECG preprocessing: The first stage is mainly based on the
hardware implementation on an FPGA chip; (iii) validation of the Pan and Tompkins concept [3], with the addition of a low-pass
implemented system on the whole of the MIT-BIH arrhythmia filter to better smooth its output [52]. Therefore, the ECG signal is
records [45]; and (iv) real-time validation with the Nexys-4 FPGA first band-pass filtered in the range 5–15 Hz [53], using a fourth-
evaluation kit using the analogue discovery device. order recursive filter that is defined as follows:

772 IET Circuits Devices Syst., 2019, Vol. 13 Iss. 6, pp. 771-782
© The Institution of Engineering and Technology 2019
 (6.765 − 13.53z−2 + 6.765z−4)(10−3) added: amplitude thresholding to discard the maximum peaks of
H(z) = (1) small amplitudes caused by noise and time thresholding to
1 − 3.711z−1 + 5.209z−2 − 3.278z−3 + 0.7812z−4
eliminate the peaks which are too close to each other, which are
To extract the slope information of the QRS complex, a derivative probably caused by the T-waves. Adaptive thresholds are used
function is then calculated using the following transfer function: because the amplitude of the beats can vary significantly from one
recording to another or even in the same recording [52].
H(z) = 0.2002z−1 + 0.4004z−3 − 0.4004z−4 − 0.2002z−5 (2)
(c) Adaptive amplitude and time thresholding: The amplitude
Then, a non-linear transformation is performed by calculating the thresholding allows distinguishing R-wave peaks from T-wave
square of the derivative signal. This allows only positive values peaks, which are generally much smaller. The amplitude threshold
and increases the contrast between large and small amplitudes is defined as 25% of the average value of the last five detected R-
wave peaks. The next peak will be validated and considered as an
R-wave if it exceeds this threshold; otherwise, the algorithm
y(n) = [x(n)]2 (3)
continues the search for the next maximum
A moving window integrator is applied to the squared signal using sQRS(n) if (sMax Peak(n) > 0.25sMean Peak);
the following equation: sMax Peak(n) is (9)
sNoise(n) otherwise .
N
y(n) = ∑ x(n − k) (4) where sMean Peak is the mean amplitude of the last five detected R-
k=0
wave peaks.
where N is the size of the moving window [3], which is typically In several cases (change of position, ventricular extra systole,
chosen equal to double the QRS width (150 ms). For a sampling …), a sudden decrease in the amplitude of the R-waves can be
frequency of 360 Hz N = 0.150 s × 360 s−1 = 54. seen. This causes the non-detection of multiple R-wave peaks that
Finally, the output of the integrator is smoothed by a first-order are below the threshold value. Therefore, to overcome this
low-pass filter defined as follows: limitation, the probability of observing the QRS in a given interval
has been taken into account. So, if no new R-wave peak is detected
0.00865 + 0.00865z−1 using the amplitude threshold of 25% of the average value of the
H(z) = (5)
1 − 0.98269z−1 last five R-wave peaks validated within 166% of the average time
of the previous five RR intervals, the algorithm restarts the search
2.3.2 QRS complex detection: This second stage is the principal for R-wave peaks using a lowered threshold of 5% of the mean of
part of the proposed QRS detection algorithm. It operates in five the last five detected R-wave peaks [52]
steps: centred derivative, maximum peak detection, and adaptive
amplitude and time thresholding. RR < 1.66RRMean
SQRS(n) if
&SMax Peak(n) > 0.25SMean Peak
(a) Centred derivative: The derivative of the preprocessed ECG
SMax Peak(n) is RR > 1.66RRMean (10)
signal is taken in order to find the extreme values (peaks) of the SQRS(n) if
signal. For each time index n, the derivative of the preprocessed &SMax Peak(n) > 0.05SMean Peak
ECG signal s(n) is defined by SNoise(n) otherwise
s(n + 1) − s(n − 1) where sMean Peak is the mean amplitude of the last five detected R-
d(n) = (6)
2T
wave peaks and RRMean represents the mean, in samples, of the last
where T is the sampling period. five RR intervals.
However, in some pathological cases, the adjacent T-wave peak
(b) Maximum peak detection: To detect the peaks (maxima and
has a significant amplitude, and therefore can be confused with an
minima), the zero crossings of the derivative of the preprocessed
R-wave peak [2]. To avoid false detection errors, time validation is
ECG are calculated using the intermediate value theorem. When
introduced. The minimum time between two R peaks is 0.2 s. In
the product of two successive values of the derivative is negative, a
our case, it is necessary that the system waits for 72 samples to
peak in the preprocessed ECG signal will be detected
validate another R-wave peak. This value is calculated by
0.2 s × 360 Hz = 72, where 360 Hz is the sampling frequency.
sPeak(n) if d(n)d(n − 1) < 0;
s(n) is (7) Finally, the maximum peak detection is done using adaptive
sNot Peak(n) if d(n)d(n − 1) ≥ 0; amplitude and time thresholding, according to the following:

The peak detection block provides the locations of both the 72 < RR < 1.66RRMean
maxima and the minima, but in the QRS detection, only the SQRS(n) if
&SMax Peak(n) > 0.25SMean Peak
maxima have to be used. To discard the minimal peaks, the sign of
the slope of the derivative is then employed SMax Peak(n) is RR > 1.66RRMean (11)
SQRS(n) if
&SMax Peak(n) > 0.05SMean Peak
SNoise(n) otherwise
s(n) is
where sMean Peak is the mean amplitude of the previous five detected
sMax Peak(n) if (d(n)d(n − 1) < 0)&(d(n + 1) < d(n − 1)); (8)
R-wave peaks and RRMean represents the mean, in samples, of the
sMin Peak(n) if (d(n)d(n − 1) < 0)&(d(n + 1) > d(n − 1)); last five RR intervals. These two values are adaptively adjusted at
each new R-wave peak detection.
sNot Peak(n) if (d(n)d(n − 1) ≥ 0);
2.4 Heart rate calculation
This maximum peak detection step permits detecting the QRS
complexes in the ECG signal. It can also detect local maxima of After the R-wave peaks detection, the heart rate can be obtained by
smaller amplitudes that may correspond either to noise or T-waves. measuring the RR interval. It is defined as follows:
So, this step is not sufficient to identify only those peaks that
correspond to the R-waves. Therefore, two thresholding steps are

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Fig. 3  Top-level implementation diagram of the proposed architecture for QRS complex detection using XSG blockset

Fig. 4  Implementation of the preprocessing subsystem of Fig. 3

1 60 f s
Heart rate = beats/ min = beats/ min (12)
TR NR

where T R represents the time, in minutes, between two consecutive

R peaks, f s is the sampling frequency, and NR is the number of
samples between two successive R-wave peaks. In this case
f s = 360 Hz.
The heart rate is calculated after each detection of a QRS
complex, but the detection of arrhythmia (tachycardia or
bradycardia) is made when the average value of the last five values
of the heart rate exceeds 120 beats/min or when it is <50 beats/min.

3 Implementation methods
Two different implementations of the arrhythmia detection
algorithm have been carried out. The proposed method was first
implemented and validated in software using the MATLAB
environment and then implemented in hardware using a low-cost
FPGA chip. Fig. 5  Implementation of the band-pass filter of Fig. 4 using XSG blockset

3.1 Software implementation

The proposed QRS detection and heart rate calculation algorithm
was first implemented in MATLAB software. It is a high-level
programming tool with an interactive environment that facilitates
the development of a programme for a complex calculation task.
The MATLAB-based software implementation will serve as a
reference to evaluate the effectiveness and Acc of the hardware
implementation approach.

3.2 Hardware implementation

This section describes how the proposed architecture has been
implemented on an FPGA using the XSG blockset. It also shows
how the designed XSG-based model has been tested and validated
on an actual FPGA from MATLAB/Simulink (hardware co-
simulation). Finally, it presents how the proposed architecture can
be uploaded and executed in real time on FPGA, independently of
the MATLAB/Simulink environment.

3.2.1 XSG-based hardware design: After the successful

simulation of the MATLAB-based software implementation, the
proposed method has been implemented on an FPGA chip using Fig. 6  Implementation of the derivative filter of Fig. 4 using XSG blockset
XSG and the Nexys-4 evaluation board. The XSG tool has been
used to set up, test, and implement the proposed algorithm on the signal from the MATLAB workspace, a Scope block to plot the
evaluation board. This tool provides a modelling system and resulting signals, a Display block to show the calculated heart rate
automatic HDL code generation from the MATLAB/Simulink and its associated class, and an In/Out gateway that allows passing
environment. from Simulink double data type to XSG fixed-point type or vice
Fig. 3 presents the top-level diagram of the proposed system versa.
using the XSG blockset. It contains three main blocks: the As described in Section 2.3.1, the preprocessing stage
preprocessing subsystem, the peak detection subsystem, and the (subsystem) is divided into five main steps. Fig. 4 presents this
class decision. Moreover, there is a block to download the ECG stage implemented using the XSG blockset. The details of the

774 IET Circuits Devices Syst., 2019, Vol. 13 Iss. 6, pp. 771-782
© The Institution of Engineering and Technology 2019
Fig. 7  Implementation of the integrator filter of Fig. 4 using XSG blockset

Fig. 8  Implementation of the low-pass filter of Fig. 4 using XSG blockset

Fig. 9  Implementation of the QRS detection and the heartbeat calculation subsystem of Fig. 3 using XSG blockset

Fig. 10  Implementation of the class decision subsystem of Fig. 3 using

XSG blockset
Fig. 11  JTAG-based hardware co-simulation diagram of the proposed
XSG-based architecture of Fig. 3
implementation of the five preprocessing steps are shown in
Figs. 5–8. For example, Fig. 5 presents the band-pass filter
implemented with the XSG blockset. A direct-form II diagram has

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Fig. 12  XSG-based diagram for real-time implementation of the QRS detector and the heart rate calculation

been chosen for this filter in order to optimise the number of the real time. For a database stored on a PC, the analogue discovery
delay blocks. The XSG-based implementation of the derivative device is used to provide an analogue ECG signal that will be
filter is shown in Fig. 6. As can be seen in Fig. 4, the squaring acquired by the FPGA of the Nexys-4 board through an analogue-
operator is performed using a single multiplier block. Fig. 7 shows to-digital converter (PmodAD1). The resulting QRS complex
the implementation of the integrator, which consists of 54 cascaded detection signal provided by the FPGA through the digital-to-
delays, and Fig. 8 presents the implementation of the low-pass analogue converter (PmodDA2) can be displayed on the PC using
filter, using its direct-form II diagram. the analogue discovery device. The heart rate is displayed on 3-
The preprocessed signal is applied to the QRS detector and digit 7-segment displays, available on the Nexys-4 evaluation
heartbeat calculator, as described in Sections 2.3.2 and 2.4. Fig. 9 board, and an red, green, and blue (RGB) light-emitting diode
presents the XSG-based implementation of the whole stage; its (LED) to show the appropriate class. Fig. 12 presents the XSG-
different steps are surrounded by dashed lines. After the centred based diagram of the real-time hardware implementation of the
derivative step, the maximum peak is then detected. To be proposed QRS complex detection and heart rate calculation system.
considered as an R-wave peak, it must fulfil the amplitude and time Additional components have been added to configure: (a) the
constraints that are performed by the amplitude and the time PmodAD1 module to acquire the ECG signal, (b) the PmodDA2 to
validation steps, respectively. As can be seen in Fig. 9, the detected provide the resulting QRS complex detection signal (with the
maximum peak is validated as an R-wave peak only if its delayed ECG signal), and (c) the 7-segment displays to display the
amplitude is >25% of the mean of the last five validated maximum beat rate.
peaks and within a time that exceeds 200 ms (72 samples) from the Fig. 13 shows more details about the XSG-based module that
previous validated maximum peak. However, the amplitude controls the heart rate display. It is composed of three main blocks:
threshold will be reduced to 5% of the mean of the last validated the first block is a black box programmed in VHDL that converts
maximum peaks if no R-wave was detected within 166% of the the heart rate value from binary to binary-coded decimal (BCD). It
mean value of the previous five validated RR intervals. allows separating BCD heart rate values into hundreds, tens, and
The heart rate is calculated by dividing 60 f s = 21, 600 by the units. The second is based on the Slice blocks: it allows separating
number of samples between two consecutive validated peaks (the each digit on four bits, and the third block is the BCD-to-7-
RR interval). In fact, the mean of the last five interval values is segment decoder, which enables decoding the 4 bit information
used as an input to the decision class, according to (12). If this into a 7 bit control signal. A 2 bit counter drives two multiplexer
value exceeds 120 beats/min, the system will classify it as blocks that allow a sequential display over three 7-segment
tachycardia (class 2); if it is <50 beats/min, it will be classified as displays. The architectures were designed at first for the hardware
bradycardia (class 1). However, it will be classified as normal co-simulation implementation (Fig. 11) and then were tested and
(class 0) if the represented heart rate is between 50 and 120 beats/ validated on the real-time implementation (Fig. 12). The required
min, as shown in Fig. 10. The class decision subsystem has been resources for the proposed architecture are shown in Table 1. The
implemented using two relational components to obtain the 2 bit real-time architecture requires more resources than the hardware
class index. co-simulation due to the additional configuration blocks for the
Pmods and the 7-segment displays.
3.2.2 Hardware co-simulation: The XSG-based design can be The proposed real-time architecture consumes fewer resources
simulated in the MATLAB/Simulink environment to validate the [Slices, look-up tables (LUTs), and input/output block (IOB)],
proposed hardware implementation approach. However, it can be which make it more suitable for applications in real-time systems.
executed on an actual FPGA from MATLAB/Simulink using the
hardware co-simulation. The system generator will automatically 4 Results and discussion
generate the bitstream file and its associated Simulink block The proposed architecture for real-time QRS complex detection
(Fig. 11). This will later be uploaded and executed on the FPGA and heart rate calculation was first tested in the MATLAB/
board (Nexys-4) using the joint test action group (JTAG) Simulink environment using the hardware co-simulation approach
connection. The system generator reads the MIT-BIH signals from and then verified in a real-time implementation environment.
the MATLAB workspace and sends them to the board via the
JTAG connection. It then reads back the QRS complex detection
signal and the heart rate, from JTAG, to display them on Simulink 4.1 Co-simulation test
using the Scope and Display blocks, respectively. It should be Fig. 14 is divided into six subfigures. The first describes the
noted that the Nexys-4 board must be configured manually to original ECG input signal. The rest show the different results of the
achieve carrying out the hardware co-simulation. preprocessing stage, from the band-pass filter to the low-pass filter
(Figs. 14a–f). The results output from the QRS complex detection
3.2.3 Real-time test: The proposed XSG-based architecture can is displayed in Fig. 15, which is also divided into four successive
be uploaded and tested in real time on an actual FPGA, subfigures, Figs. 15a–d, providing the outputs of the derivative, the
independently of the MATLAB/Simulink environment. As shown maximum peak detection, the time validation, and the amplitude
in Fig. 1, additional electronic modules are required to operate in validation steps.

776 IET Circuits Devices Syst., 2019, Vol. 13 Iss. 6, pp. 771-782
© The Institution of Engineering and Technology 2019
Fig. 13  Implementation of the display control block of Fig. 12 using XSG blockset

Table 1 Estimated resources required by our proposed method on Nexys-4

Architecture Hardware co-simulation Real time
Resource utilisation
Slices (15,850) 2238 (14%) 2299 (14%)
LUTs (63,400) 6925 (10%) 7157 (11%)
Flip flops (126,800) 2226 (1%) 2542 (2%)
Bonded IOBs (210) 24 (11%) 26 (12%)
DSP48E1s (240) 4 (1%) 4 (1%)
maximum operating frequency 3.936 MHz 3.933 MHz
total estimated power 42 mW 42 mW

Fig. 14  Output of each preprocessing step using hardware co-simulation on Nexys-4
(a) Original ECG signal of record no. 107: 1234–1238 s, (b) Output of band-pass filter, (c) Output of the derivative filter, (d) Output of non-linear transformation, (e) Output of
integrator, (f) Output of low-pass filter

The preprocessed signal passes through the QRS detector stage, Figs. 18 and 19. Even though the amplitude of these artefacts is
starting with taking the centred derivative, followed by the significant, one can see that they are easily discarded.
maximum peak detector. Temporal and amplitude validation steps
will be applied to the detected maximum in order to validate it. 4.2 Performance evaluation
Fig. 16 presents the QRS detection results in segment 1102–1112 s
of MIT-BIH record no. 222. It should be noted that the frequency To evaluate the performance of the proposed QRS complex
range of the baseline drift, which is 0–2.5 Hz, is completely detection algorithm, the following statistical parameters have been
eliminated, and the QRS complex in the R-peak detection signal is used
correctly detected. Fig. 17 presents a case of a sharp abrupt change
in amplitude in the segment corresponding to the ECG segment TP
Se = (13)
172–182 s of record no. 101. The proposed method detects the TP + FN
peaks of the QRS complexes correctly, but with two false positive
(FP) peaks. ECG signals with sharp muscle artefacts are given in TP
PPV = (14)
TP + FP

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 FP + FN the proportion of misclassified cases [54]. The performance of the
DER = (15)
TP proposed R-wave peak detection method, for software (MATLAB)
and hardware (FPGA) implementations, using 48 ECG recordings
TP in the MIT-BIH arrhythmia database, is summarised in Table 2.
Acc = (16)
TP + FP + FN The MATLAB-based implementation detected a total of 109,012
true R peaks (TP) and 350 false R peaks (FP), while missing 458 R
where true positive (TP) represents the number of correctly peaks (FN). According to the results of this table, it can be seen
detected R-wave peaks, false negative (FN) is the number of that there were a great number of FNs in the case of two signals:
missed R-wave peaks, and FP is the number of noise artefacts nos. 114 and 228. This is due to high-amplitude peaks, which will
misdetected as R-wave peaks. The Se measures the proportion of cause a great amplitude threshold value. This error can be adjusted
patient (disease) cases that are correctly identified. The positive by limiting the R-wave peak values. Therefore, the resulting Se,
predictive value (PPV) presents the proportion of positive results. PPV, DER, and Acc are 99.58, 99.68, 0.74, and 99.26%,
The Acc is the ratio of correct results (TPs and true negatives) to respectively. The results obtained by the FPGA-based
the total number of cases tested. The detection error rate (DER) is implementation are very close to those obtained by the MATLAB-

Fig. 15  Output of each QRS detection step using hardware co-simulation on Nexys-4 for the same input signal as Fig. 14
(a) Output of derivative filter, (b) Output of maximum peak detection, (c) Output of time validation, (d) Output of amplitude validation

Fig. 16  ECG waveform and R-peak localisation plot for segment 1102–1112 s of MIT-BIH record no. 222, presenting a baseline shift

Fig. 17  ECG waveform and R-peak localisation plot for 172–182 s of MIT-BIH record no. 101, with a severe abrupt change in amplitude

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Fig. 18  ECG waveform and R-peak localisation plot for 1358–1368 s of MIT-BIH record no. 208, with muscle artefacts

Fig. 19  ECG waveform and R-peak localisation plot for 348–361 s of MIT-BIH record no. 200, with muscle artefacts

based implementation. The differences can be attributed to signal was provided by the analogue discovery device from the
quantisation errors. MIT-BIH database for Fig. 20a, using the WaveForms tool
installed on the PC, and from the three electrodes shown in
4.3 Performance comparison Fig. 20b. The analogue ECG signal was then acquired by the
FPGA through the PmodAD1 at a sampling frequency of 360 Hz.
The proposed R-wave peak detection method has been compared The resulting QRS detection signal with a delayed version of the
with existing methods, as evaluated on the entire MIT-BIH original ECG signal was simultaneously passed through the
database. The results from the MATLAB implementation are PmodDA2. These two signals were acquired by the analogue
compared with those of other software-based techniques. As shown discovery device using the WaveForms tool, as shown on the
in Table 3, the performance is comparable with the reference bottom of the screen of Figs. 20a and b. The original signal was
methods. The main error was caused in some recordings (such as delayed in order to synchronise its QRS complexes with the
nos. 105, 108, 114, 203, 207, and 228) leading to an error >3%. detection impulses. On the other hand, the heart rate was displayed
These recordings suffer from a change of signal quality, baseline using the three right 7-segment displays available on the Nexys-4
change, and high and sharp P waves [28]. These two properties board, the RGB LED lights up to describe the class decision cases:
allow the P waves to qualify as QRS complexes, and they will blue indicates the tachycardia, red indicates bradycardia, and green
produce a large number of FPs in several places in the recordings. indicates a normal beat.
The FN results were generally caused by PVCs. These PVCs have
low amplitude and occur between two normal high-amplitude
beats. So in this case, the beat will not exceed the lower detection
5 Conclusion
threshold level and will be not detected [28]. In this paper, a real-time cardiac arrhythmia detector has been
On the other hand, for the FPGA-based architecture, the results proposed. It was successfully implemented on an FPGA using the
are compared with those of other hardware-based systems XSG and the Nexys-4 evaluation kit. The proposed method was
(Table 4). The proposed architecture presents an improvement of first implemented in software (MATLAB) and also optimised in
the Pan and Tompkins method, with a new and efficient QRS order to maximise the detection of QRS complexes and minimise
detection method. Its hardware implementation on FPGA has the false detection caused by noise. Then, it was mapped to an
proven to be optimal for embedded systems. It can be noted that El FPGA-based hardware implementation. The proposed method has
Mimouni and Karim [35] and Chowdhury [57] did not test their been evaluated in real time, through the analogue discovery device,
systems on the entire MIT-BIH database, but chose some records using the standard MIT-BIH database. The performance and
that they considered the noisiest. effectiveness of our system have been evaluated in terms of Se,
specificity, and Acc rate. Both the software-based and hardware
4.4 Real-time evaluation architectures achieved the following results: average rates of the
Accs of 99.26 and 99.39%, Se rates of 99.58 and 99.83%, and
Fig. 20 shows the testbed used to validate the real-time positive predictivities 99.68 and 99.56%. Compared to the existing
implementation of the proposed system. The bitstream generated Pan and Tompkins hardware-based methods, our proposed FPGA-
from the XSG-based diagram, shown on the top of the screen in based system provides better results.
Figs. 20a and b, was uploaded to the FPGA Nexys-4 board through
the universal serial bus programming cable. The analogue ECG

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© The Institution of Engineering and Technology 2019
Table 2 Performance of the software (MATLAB) and software (XSG) implementations of the proposed R-peak detection
method using the MIT-BIH arrhythmia database
Record name, m Software (MATLAB) implementation Hardware (FPGA) implementation
TP FP FN Se, % PPV, % DER, % Acc, % TP FP FN Se, % PPV, % DER, % Acc, %
100 2273 0 0 100.00 100.00 0.00 100.00 2273 0 0 100.00 100.00 0.00 100.00
101 1865 1 0 100.00 99.95 0.05 99.95 1865 3 0 100.00 99.84 0.16 99.84
102 2187 0 0 100.00 100.00 0.00 100.00 2187 0 0 100.00 100.00 0.00 100.00
103 2082 0 2 99.90 100.00 0.10 99.90 2084 0 0 100.00 100.00 0.00 100.00
104 2218 10 11 99.51 99.55 0.95 99.06 2191 8 38 98.30 99.64 2.10 97.94
105 2569 25 3 99.88 99.04 1.09 98.92 2571 35 1 99.96 98.66 1.40 98.62
106 2026 0 0 100.00 100.00 0.00 100.00 2026 0 0 100.00 100.00 0.00 100.00
107 2135 0 1 99.95 100.00 0.05 99.95 2136 0 0 100.00 100.00 0.00 100.00
108 1761 39 2 99.89 97.83 2.33 97.72 1760 26 2 99.89 98.54 1.59 98.43
109 2530 0 2 99.92 100.00 0.08 99.92 2532 0 0 100.00 100.00 0.00 100.00
111 2124 0 0 100.00 100.00 0.00 100.00 2124 1 0 100.00 99.95 0.05 99.95
112 2539 0 0 100.00 100.00 0.00 100.00 2539 0 0 100.00 100.00 0.00 100.00
113 1794 0 0 100.00 100.00 0.00 100.00 1794 0 0 100.00 100.00 0.00 100.00
114 1747 8 131 93.02 99.54 7.96 92.63 1861 58 17 99.09 96.98 4.03 96.13
115 1952 0 0 100.00 100.00 0.00 100.00 1952 0 0 100.00 100.00 0.00 100.00
116 2394 0 6 99.75 100.00 0.25 99.75 2396 1 4 99.83 99.96 0.21 99.79
117 1535 0 0 100.00 100.00 0.00 100.00 1535 0 0 100.00 100.00 0.00 100.00
118 2278 0 0 100.00 100.00 0.00 100.00 2278 1 0 100.00 99.96 0.04 99.96
119 1987 0 0 100.00 100.00 0.00 100.00 1987 0 0 100.00 100.00 0.00 100.00
121 1863 0 0 100.00 100.00 0.00 100.00 1863 0 0 100.00 100.00 0.00 100.00
122 2475 0 0 100.00 100.00 0.00 100.00 2476 0 0 100.00 100.00 0.00 100.00
123 1518 0 0 100.00 100.00 0.00 100.00 1518 0 0 100.00 100.00 0.00 100.00
124 1619 8 0 100.00 99.51 0.49 99.51 1619 0 0 100.00 100.00 0.00 100.00
200 2599 0 2 99.92 100.00 0.08 99.92 2600 1 1 99.96 99.96 0.08 99.92
201 1936 0 26 98.67 100.00 1.34 98.67 1904 2 58 97.04 99.90 3.15 96.95
202 2130 1 6 99.72 99.95 0.33 99.67 2121 1 15 99.30 99.95 0.75 99.25
203 2924 2 56 98.12 99.93 1.98 98.05 2967 1 13 99.56 99.97 0.47 99.53
205 2656 0 0 100.00 100.00 0.00 100.00 2656 0 0 100.00 100.00 0.00 100.00
207 1856 239 4 99.78 88.59 13.09 88.42 1855 315 3 99.84 85.48 17.14 85.37
208 2939 0 15 99.49 100.00 0.51 99.49 2948 0 6 99.80 100.00 0.20 99.80
209 3005 1 0 100.00 99.97 0.03 99.97 3005 2 0 100.00 99.93 0.07 99.93
210 2614 1 36 98.64 99.96 1.42 98.60 2628 2 22 99.17 99.92 0.91 99.10
212 2748 0 0 100.00 100.00 0.00 100.00 2748 0 0 100.00 100.00 0.00 100.00
213 3251 0 0 100.00 100.00 0.00 100.00 3250 0 0 100.00 100.00 0.00 100.00
214 2262 0 0 100.00 100.00 0.00 100.00 2261 1 1 99.96 99.96 0.09 99.91
215 3362 0 0 100.00 100.00 0.00 100.00 3362 0 0 100.00 100.00 0.00 100.00
217 2207 0 0 100.00 100.00 0.00 100.00 2207 1 0 100.00 99.95 0.05 99.95
219 2154 0 0 100.00 100.00 0.00 100.00 2154 0 0 100.00 100.00 0.00 100.00
220 2048 0 0 100.00 100.00 0.00 100.00 2048 0 0 100.00 100.00 0.00 100.00
221 2425 0 1 99.96 100.00 0.04 99.96 2425 0 1 99.96 100.00 0.04 99.96
222 2480 0 2 99.92 100.00 0.08 99.92 2480 10 4 99.84 99.60 0.56 99.44
223 2603 0 1 99.96 100.00 0.04 99.96 2604 0 0 100.00 100.00 0.00 100.00
228 1904 11 148 92.79 99.43 8.35 92.29 2052 10 0 100.00 99.52 0.49 99.52
230 2256 0 0 100.00 100.00 0.00 100.00 2256 0 0 100.00 100.00 0.00 100.00
231 1571 0 0 100.00 100.00 0.00 100.00 1571 0 0 100.00 100.00 0.00 100.00
232 1780 4 0 100.00 99.78 0.22 99.78 1780 5 0 100.00 99.72 0.28 99.72
233 3078 0 3 99.90 100.00 0.10 99.90 3078 0 0 100.00 100.00 0.00 100.00
234 2753 0 0 100.00 100.00 0.00 100.00 2753 0 0 100.00 100.00 0.00 100.00
total 109,012 350 458 99.58 99.68 0.74 99.26 109,280 484 186 99.83 99.56 0.61 99.39

780 IET Circuits Devices Syst., 2019, Vol. 13 Iss. 6, pp. 771-782
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Table 3 Performance comparison of our QRS complex detection method with other existing software-based methods using the
MIT-BIH database
Method (FN + TP) FN FP Se, % PPV, % DER, % Acc, %
Pan and Tompkins [3] 116,137 507 277 99.56 99.76 0.68 99.33
Zidelmal et al. [7] 109,494 393 193 99.64 99.82 0.54 99.47
Panigrahy et al. [36] 109,474 58 116 99.95 99.89 0.16 99.84
Mak et al. [55] 109,134 753 330 99.31 99.70 1.00 99.01
Ravanshad et al. [56] 109,428 1216 651 98.89 99.40 1.73 99.30
our method 109,470 458 350 99.58 99.68 0.74 99.26

Table 4 Performance comparison of the proposed QRS 6 References

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