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10.2478/v10048-011-0024-z
MEASUREMENT SCIENCE REVIEW, Volume 11, No. 4, 2011

A FPGA system for QRS complex detection based on Integer

Wavelet Transform
R. Stojanović1, D. Karadaglić2, M. Mirković1 and D. Milošević3
1
Faculty of Electrical Engineering, University of Montenegro, Džordža Vašingtona bb, 81000, Podgorica, Montenegro,
stox@ac.me
2
University of Manchester, Oxford Road, M13 9PL, Manchester, United Kingdom, Dejan.Karadaglic@manchester.ac.uk
3
University of Kragujevac, Technical Faculty Čačak, Serbia, danijela.tfc@gmail.com

Due to complexity of their mathematical computation, many QRS detectors are implemented in software and cannot operate in
real time. The paper presents a real-time hardware based solution for this task. To filter ECG signal and to extract QRS complex
it employs the Integer Wavelet Transform. The system includes several components and is incorporated in a single FPGA chip
what makes it suitable for direct embedding in medical instruments or wearable health care devices. It has sufficient accuracy
(about 95%), showing remarkable noise immunity and low cost. Additionally, each system component is composed of several
identical blocks/cells what makes the design highly generic. The capacity of today existing FPGAs allows even dozens of detectors
to be placed in a single chip. After the theoretical introduction of wavelets and the review of their application in QRS detection, it
will be shown how some basic wavelets can be optimized for easy hardware implementation. For this purpose the migration to the
integer arithmetic and additional simplifications in calculations has to be done. Further, the system architecture will be presented
with the demonstrations in both, software simulation and real testing. At the end, the working performances and preliminary
results will be outlined and discussed. The same principle can be applied with other signals where the hardware implementation of
wavelet transform can be of benefit.

Keywords: QRS detection, FPGA, Wavelet Transform.

1. INTRODUCTION emphasised need to implement bulk of the software

algorithms for biomedical signal processing in this
T HE QRS COMPLEX is the most important segment in
electrocardiogram (ECG) signal and its shape, moment
of occurrence and frequency gives us indispensable
technology.
There are few articles about implementing QRS detection
information about heart condition. Many methods were in FPGA. References [2] and [3] implement Pan-Tompkins
attempted for QRS complex detection, and an extensive algorithm, while [4] uses the wavelets. They employ
review of the approaches proposed in the last decade can be complex filtering and mathematical calculations as well as
found in [1]. sophisticated state-machine blocks. It results in a complex
The results of studies of these approaches have design and huge requirements on silicon resources.
demonstrated that the Wavelet Transform (WT) in its In this paper a cost and performance effective design
discrete form - Discrete Wavelet Transform (DWT) - is the methodology will be proposed, which combines the positive
most reliable method among all of them to extract critical characteristics of Wavelets in QRS detecting and FPGAs in
points from the ECG signal. However, the majority of hardware-based signal processing. The final developed
published algorithms are heavily processor demanding, system works in real time, does not require memory and is
therefore do not allow real-time operation on a personal modular in principle. During the design and construction,
computer. the care has been taken to minimise total number of
In the recent years, significant research, academic and adjustable parameters.
industrial attention has been turned to the Telemedicine and In Section 2 the related theoretical background on WT
Wearable Health Care (WHC) systems. Such systems are with emphasis to its optimization in integer arithmetic will
based on autonomous ultra-low-power devices capable of be elaborated briefly. The principle of WT based detection
performing real-time sampling, signal processing and of QRS complexes will be explained in Section 3. Section 4
wireless transfer for what they employ general purpose will deal with proposed design approach from system and
microprocessors/microcontrollers and very often, in last component point of view with focus to software simulation
time, Programmable Logic Devices (PLDs) like Field and verification of proper work. The testing procedure and
Programmable Gate Arrays (FPGAs). preliminary results will be presented in Section 5.
A FPGA consists of reconfigurable logic, I/O and
interconnections blocks and differs from microcontrollers 2. THEORETICAL BACKGROUND
and DSP processors, which are Von Neumann type of
machines. In addition to the parallelism, other advantages A. Wavelet transform
include, but not limit to: higher throughput, low price, WT is a time-scale representation that has been used
flexibility of design, testing and rapid prototyping as well as successfully in a broad range of applications, and most
an ability to transform digital design directly to Application typically in signal compressions. Recently, the WT has
Specific Integrated Circuits (ASICs). Therefore, there is an been applied to several problems in electrocardiology,

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 MEASUREMENT SCIENCE REVIEW, Volume 11, No. 4, 2011

including data compression, denoising, analysis of CD1[n] = ∑k H [k ] X [2n + k ] (5)

ventricular late potentials and detection of ECG
characteristic points. It is a linear operation that decomposes
signal into a number of scales related to frequency where n and k denote discrete time coefficients and X stands
components and analyses each scale with a certain for the given signal. In the second decomposition level the
resolution. WT uses a short time interval for evaluating CA1[n] plays a role of x[n] and so on. CAi(n) and CDi(n) are
higher frequencies and a long time interval for lower usually called the approximations and the details,
frequencies. Because of this property, high frequency respectively.
components of short duration can be observed successfully The coefficients for L and H filters can vary from the
by WT. One of the advantages of the WT is ability to simplest, such as Haar, over Doubisch up to those such as
decompose signal at various resolutions, what allows an Quadratic Spline, having different vector lengths and,
accurate feature extraction from non-stationary signals like usually, floating point values. The L and H filters, within L-
ECG. H cell, Fig.1, can be easily implemented in hardware only in
Analytically, the WT in its continuous form, for signal f(t) the case of simplification their transfer functions. It means
is defined by: both; the reduction of vector length and escaping floating
point calculations. Thereby, the positive characteristics of
∞ the wavelets should be retained.
W ( a, b) = ∫
−∞
f (t )ψ a ,b (t )dt (1)

1 ∗ t −b
ψ a ,b (t ) = ψ ( ) (2)
a a

Where * denotes complex conjugation and ψ a ,b (t ) is

window function called the mother wavelet, a is a scale
factor and b is a translation factor. Here, ψ ∗ ( t − b ) is a
a
shifted and scaled version of a mother wavelet which is used
as a basis for wavelet decomposition. However, the
continuous wavelet transform provides certain amount of
redundant information.
DWT is sufficient for most practical applications
providing enough information and offering a significant
reduction in the computation time. For a discrete function
f(n) the DWT is given by:

W (a, b) = C ( j, k ) = ∑ n∈Z f (n)ψ j ,k (n) (3)

where ψ j ,k (n) presents a discrete wavelet defined as

j Fig.1. Wavelet decomposition scheme.
−
ψ j ,k (n) = 2 2ψ (2− j n − k ) . The parameters a, b are defined
B. Wavelet transform
as a = 2 j and b = 2 j k .
The Haar wavelet is considered to be the simplest one. In
discrete form it is related to the Haar transform, which
In practice, DWT is computed by passing the signal serves as a prototype for all wavelet transforms. The L and
through a Low-Pass (L) and a High-Pass (H) filters
H filters are of two elements wide, L = ⎡ 1 , 1 ⎤ ,
successively according to the Mallat’s decomposition ⎢ ⎥
⎣ 2 2⎦
scheme [5], as shown in Fig. 1. For each decomposition
level i, the L and H filters are followed by downsampling ⎡ 1 1 ⎤ . The CA1(n) and CD1(n) are given by:
H =⎢ ,− ⎥
operator ↓2 which can be expressed as (X↓2)[n]=X[2n]), ⎣ 2 2⎦
what is in fact the reduction of sampling rate by 2.
Therefore, the outputs CAi(n) and CDi(n) from one 1 1
CA1 [n] = X [ 2n ] + X [2n + 1] (6)
decomposition level, in our case the first one, i=1, are given 2 2
by:
1 1
CA1[n] = ∑k L[k ] X [2n + k ] (4) CD1 [n] = X [ 2 n] − X [2n + 1] (7)
2 2

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 MEASUREMENT SCIENCE REVIEW, Volume 11, No. 4, 2011

This transform has a number of advantages; it is (i)

conceptually simple, (ii) fast, (iii) memory efficient, since it
can be calculated in a place without a temporary array. Also,
it is reversible without the edge effect which can be a
problem with some other Wavelet transforms.
The Haar transform also has its limitations, which can be
of a problem in some applications, mainly in signal
compression and noise removal from audio or video signal.
But, in our case this is not an issue.

C. Integer Haar Transform

Although very simple in principle, the Haar transform in
above form is still complicated enough for hardware
implementation, because of the floating point nature.
However, like any other wavelet transform, it can be
generalized to an integer to integer version as shown in the
excellent reference [6]. Its integer form is known as S
transform [7]:

⎢1 1 ⎥
CA1[n] = ⎢ X [2n] + X [2n + 1]⎥ (8)
⎣2 2 ⎦
Fig.2. QRS detection using wavelet decomposition. Signal X[n]
CD1[n] = X [2n] − X [2n + 1] (9) sampled with frequency of 800 Hz.

Usually, the modulus maxima are found by thresholding

Where ⎣ ⎦ denotes rounding operator. techniques and the threshold values vary from one scale to
On the binary level the division with 2 and rounding are another. As an example, according to [9] the thresholds are
performed by right shifting for one position, >>1, which is proportional to the RMS value of the WT and can be
very helpful circumstance in the term of digital logic calculated as RMS(Di) for i=1,2 and 3 and 0.5RMS(Di) for
implementation. With this, equation (8) becomes: i=4.

CD1[n] = ( X [2n] + X [2n + 1]) >> 1 (10)

As seen, the CA1[n] is calculated by an adder and shifter

and the CD1[n] by a subtractor, excluding the necessity for
floating point multipliers. Now, the L-H cell from Fig.1
should be very easy implemented in digital logic. The
rounding to the nearest integer does not implicate the
significant error in signal reconstruction [6].

3. WAVELET DECOMPOSITION AND QRS DETECTION

WT is capable of distinguishing the QRS-complex within
ECG signal by using decomposition scheme from Fig.1,
[8], [9]. The CD coefficients across the scales show that the
peak of the QRS complex corresponds to the zero crossing
between two modulus maxima.
Fig.2 illustrates the decomposition of real ECG signal X(n)
up to the 4th level , (CD1, CD2, CD3 and CD4), using Haar
wavelet from (6) and (7). For each decomposition level, the Fig.3. Matching the S Transform and Haar Transform.
QRS complex produces two modulus maxima with opposite
signs, with a zero crossing (ZC) between. In the practical applications the challenge is the selection
This method for QRS detection is very robust and allows of the most suitable decomposition level/levels. Most of the
direct application over the raw ECG data because the energy for QRS complex lies between 3Hz and 40Hz.
frequency domain filtering is performed implicitly by Translated to WT it means somewhere between scales 23
computing the coefficients. Fig.2 shows the clear signal at and 24, with the largest at 24. The energy of motion artifacts
4th decomposition level. The built-in filtering is an important and baseline wander (i.e., noise) increases for scales greater
additional contribution of wavelet decomposition in QRS than 25. Article [9] states that most energies of a typical
detection. QRS-complex are at scales 23 and 24, and the energy at scale

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 MEASUREMENT SCIENCE REVIEW, Volume 11, No. 4, 2011

23 is the largest. According to [11], for QRS-complex with vector X[n], driven in by system clock clk, while the main
high frequency components, the energy at scale 22 is larger outputs are the true zero crossings (ZCi_OK), summing of
than that at scale 23. The authors recommend mainly the true zero crossings (SUM_ZC) and vector of time stamps
scales 23 to 24 for satisfactory detection. which corresponds to the position of R peak (RTIME) in
Another complication is the acquisition of certain time scale. SUM_ZC and RTIME are obtained by summation
thresholds for finding the modulus maxima. the values of of ZCi_OKs and multiplexing RTIMEi by address SL. R
thresholds differ usually from one level to another. The third presents the asynchronous reset which puts all outputs to
obstacle is the change of decision rules according to zero. The threshold parameters TR1 and TR2 as well as
circumstances and it is a very ambiguous and time- parameters Ti_1 and Ti_2 related to the QRS inclination
consuming task. Mentioned restrictions confine the method times are stored in configuration registers or internal Read
to off-line use and put heavy demand on the computing Only Memory (ROM). As seen, the architecture can be
resources. extended very easily to the desired decomposition level by
In the presented research, instead of classical Wavelet adding a new branch of L-H, ZC&MT and DR. Also, in the
Transform, additionally optimised Integer Wavelet case of reduction, unnecessary branches can be omitted.
Transform (S Transform) is used for the task of QRS
detection. Fig.3 shows that the absolute error is less than one B. Wavelet decomposition
count at 4th coefficient when using S transform given by (9) L-H cell from Fig.5 is the core unit in decomposition
and (10) instead of Haar transform given by (6) and (7). scheme from Fig.4. It presents digital expression of
equations (9) and (10). The delay line is implemented by
4. THE DESIGN APPROACH cascade of REG1 and REG2. The ((X(n)+X(n+1))>>1)) and
X(n)-X(n+1) computations are done for each sample. The
A. System Architecture signal clk_out=clk_in/2 is used for downsampling (↓2) and
Simplified diagram of the proposed methodology for QRS stores X(2n)-X(2n+1) and ((X(2n)+X(2n+1))>>1)) values in
complex detection is given in Fig.4. Wavelet decomposition adequate output registers REGs. Ca output from the
is realized with pipelined L-H cells. Each cell is followed by previous cell is the input X to the further cell and so on. The
branch consisting of two circuits/blocks: Zero Crossing and calculation time per Ca and Cd is 2clk. The signal clk_out
Modulus Thresholding (ZC&MT) and Decision Rules (DR). presents a clk_in for the next cell. The implementation of L-
The outputs from ZC&MT and DR are fed to the MUX and H cell in Fig.5 is a very fast way to calculate equations (9)
summing (OR) circuits. The input to the system is the ECG and (10) without multipliers.

Fig.4. Simplified architecture of FPGA based QRS detection

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 MEASUREMENT SCIENCE REVIEW, Volume 11, No. 4, 2011

are recalculated in integer values considering frequency of

system clock (clk). In developed system 30ms<T4_1<50ms,
90ms<T4_2<150ms, 15ms<T3_1<25ms and
45ms<T3_2<75ms are used for 4th and 3rd levels.

Fig.5. Architecture of L-H cell .

C. Zero crossing and modulus thresholding

In order to detect zero crossing (ZC_i) for the chosen
coefficients CDi, it is necessary to recognize the modulus
maxima pair, Fig.6 (up). Instead of using a classical way
based on the local max-min finding ZC&MT technique has
been employed in this paper.
Negative (min) and positive (max) peaks are isolated by
negative and positive thresholds TR1 and TR2, producing
the digital signals CRiTR1 and CRiTR2, with zero
crossing ZC_i between, Fig.6 (middle). Usually,
TR2=abs(TR1)=k*Max(X(n)), where k varies between
0.05<k<0.5. For the purpose of demonstration in Fig.6
TR2<abs(TR1) is selected. The signal ZC_i is found by
scanning successive samples such that CD(n-1)<0 and
CD(n)>0.

D. Decision making
For each decomposition level the Decision Rules (DR)
circuit receives the signals CRiTR1, CRiTR2 and ZC_i, from
ZC&MT, Fig.6(middle). The detection of true zero crossing
begins on the falling edge of signal CRiTR1 by starting the
counter driven by system clock CLK, Fig.6 (down). The
counter has been previously reset by rising edge of CRiTR1. Fig.6. Graphical illustration of the algorithm for finding modulus
The counter stops on the falling edge of CRiTR2 latching the maxima and zero crossing. Bottom is a decision making technique.
time t0. If Ti_1<t0<Ti_2 the detected ZC_i is declared to be
the true one. Only then the trigger ZCi_OK is generated. If Generally, the system can be implemented till highest
the rising edge of CRiTR2 is not detected within time Ti_2, level, in our case 4th. The signals ZC1_OK, ZC2_OK,
the detected ZC_i is considered to be false, the counter ZC3_OK and ZC4_OK with corresponding values RTIME1,
cleared, and trigger ZCi_OK remains zero. If ZC_i is RTIME2, RTIME3 and RTIME4 have to be considered. A
declared to be true it is necessary to store the time when it number of ZCi_OK within SUM_ZC and adequate RTIMEi
occurred (RTIMEi), because this time corresponds to the are sufficient information for decision. In practice two levels
position of R peak. It is ensured by double latch, Fig.6 (3rd and 4th) are enough for satisfactory detection rate, using
(down); first when ZC_i happened, whether it is true or not, the signals ZC1_OK, ZC2_OK, RTIME1 and RTIME2. In
and then when the ZC_i is declared as true, namely ZCi_OK this case the resources are less occupied, and thresholds are
generated. By multiplexor MUX, Fig.4, the RTIME will be easier to adjust.
taken from RTIMEi which corresponds to the better
accuracy. As an example, if R peak is detected at all four E. Simulation
levels the RTIME1 will be forwarded out. As an alternative The simulation is performed using real ECG samples
the mean value, mean(RTIMEi, RTIMEi, RTIMEi, RTIMEi), brought to the system input X[n]. For this purpose a
can be considered. separately circuit/block (simulation generator) is designed
Here, a possible complication may arise from selection of and embedded into same chip. It consists of an up-counter
parameters Ti_1 and Ti_2 which depend on the inclination which addresses the FPGA’s ROM in incremental order.
and duration times within the QRS complex. These values The counter is driven by clock whose frequency is identical

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 MEASUREMENT SCIENCE REVIEW, Volume 11, No. 4, 2011

to the ECG sampling frequency. The ROM is initialized

through memory initialization (*.mif) file, which is in fact
an array of test samples X[n], X[n+1].... Thus, the
simulation process is synchronized using the real samples.
After the simulation and verification, before chip
configuration, the simulation generator can be removed.
Fig.7 shows the timing diagrams in characteristic points
for 3rd decomposition level. The ECG segment with R peak
was isolated as a test sequence. The TR1 and TR2 were
adjusted at -30 and 30 and signals D3, CR3TR1, CR3TR2,
ZC_3, ZC3_OK and RTIME observed. As seen, ZC3_OK is
generated and RTIME=RTIME3 captured. This means the
successful detection of R peak.
In Fig.8 the scenario simulated was as all four
decomposition levels worked in parallel. Test signal of 1024
samples was acquired in sampling frequency of 400Hz
(2.5ms), in total duration of 2.5s. The thresholds TR1 and
TR2 were adjusted to -22 and 22. The R peak has been
detected at all decomposition levels. ZC1_OK, ZC2_OK,
ZC3_OK and ZC4_OK are summed in SUM_ZC. Because
of the accuracy reason the RTIME was captured from 1st
level, RTIME =RTIME1. Previously the same signal had
been passed through identical MATLAB detector,
measuring R-R intervals. As seen, the good matching is
obtained, 0.9915s against 0.9900s and 0.9330s against
0.9150s respectively.
Fig.7. Simulation of decomposition, ZC&MT and DR blocks for
ECG sequence with R peak. 400Hz sampling frequency.

Fig.8. Illustration of simulation results. 4 decomposition levels. 400Hz sampling frequency.

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 MEASUREMENT SCIENCE REVIEW, Volume 11, No. 4, 2011

F. Hardware occupancy monitor/logger MD100B (Med Choice) in three lead

To asses the design efficiency in the term of silicon configuration (LA-RA-LL). The noise was caused by main
consumption the system and its components were voltage (50Hz) and artifacts. The recorded signals were
considered till 4th decomposition level, Table 1. One L-H transferred to PC and stored in *.txt raw files as 8bits
cell occupied 32 LCs (Logic Cells), 4(L-H) cells 174 LCs, integers. There were totally 105,200 heart beats within 10
while overall system with 4(L-H) cells and 4(ZC&MT+DR) files/records assigned to each student. From each record the
blocks and one MUX occupied 651 LCs. The table also signal/array Xi[n] (i=1:10) was formed and fed to the FPGA
gives the other combinations. These are very good detector. The particular detection error rate DERi was
optimization results even for low-capacity FPGA chips. defined as:

Table 1. Occupation of silicon resources in function of system NFP + NFN

complexity. DERi [%] = 100(1 − ) (11)
TN
Number of LCs
where are: NFP- number of false positives in Xi[n] , NFN-
Configuration (Logic Cells) number of false negatives in Xi[n] and TN- total number of
out of 5980 complexes in Xi[n]. The averaged accuracy
L-H 32
1 i =10
2(L-H) 76
ADER[%] = ∑ DERi [%]
10 i =1
(12)

3(L-H) 120
was about 95.23% for using 3rd&4th levels in parallel, Table
4(L-H) 174 2. It had been assumed that R peak appeared if the signal
4(L-H)+ZC&MT+DR 301 ZCi_OK occurred at CD3 or CD4 or at both of them.

4(L-H)+2(ZC&MT+DR) 385 Table 2. Partial and average accuracy.

4(L-H)+3(ZC&MT+DR) 459 Records Beats in NFP+NFN DERi(%)
4(L-H)+4(ZC&MT+DR) 533 Xi(n) Xi(n)
1 9200 442 95,19565
4(L-H)+4(ZC&MT+DR)+MUX 651 2 10400 532 94,88462
3 8300 457 94,49398
4 11200 695 93,79464
5. TESTING AND RESULTS 5 12600 687 94,54762
The system was designed in Altera’s Quartus 9.1 6 11800 369 96,87288
development environment. As a target chip FPGA Cyclone 7 9600 526 94,52083
EP1C12Q240 was chosen. All components were 8 8700 276 96,82759
implemented in Very High Speed Integrated Circuit 9 12000 636 94,7
Hardware Description (VHDL) Language, compiled, 10 11400 409 96,41228
simulated, verified, converted to the symbols and then Sums/
integrated into system. The simulation results were ADER[%] 105200 5029 95,22501
discussed in Section 4.E. After simulation and verification,
the 4th level system is configured in a target chip. The In the terms of hardware performances the system was
characteristic signals were taken out from 3rd, 4th or both evaluated against two parameters: occupancy of silicon
levels (3rd&4th). resources (Section 4.E) and operation speed. The most
On-chip functionality was verified by specially designed demanding 4th level configuration occupies around 11%
tool set based on MC (microcontroller) board and personal resources of Cyclone EP1C12Q240 chip. It means that at
computer (PC). The board communicated with PC via serial least 8 systems for QRS detection can be implemented in
port. Microcontroller (ATMEL’s AVR ATMega32) was this device. For higher-capacity chips that number could be
receiving digital samples X[n] from PC, forwarding then much higher. Maximum operation frequency for system
them to the FPGA chip via I/O bus and simultaneously clock is 27.23MHz that is much more than the strongest
generating control and threshold signals (clk, SL, TR1, TR2, requirements regarding sampling frequency for ECG signal.
T1_3, T2_3, T1_4, T2_4,). The signal SUM_ZC from FPGA
chip caused the hardware interrupts on microcontroller. In
6. CONCLUSION
interrupt routine the contexts of registers RTIME3 and
RTIME4 were captured and sent back to PC. MATLAB Wavelet Transform is a reliable method for detection QRS
virtual interface managed the process between PC and MC complexes within ECG signal. Together with distinguishing
board and performed the signal processing and statistics. QRS complexes it performs signal filtering. Additionally it
In order to determine the detection accuracy, the student can be easily implemented in hardware, after certain
volunteers recorded their ECGs by portable handheld ECG optimizations in term of integer arithmetic. This paper

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 MEASUREMENT SCIENCE REVIEW, Volume 11, No. 4, 2011

presents the hardware system based on these principles. The [4] Shukla, A., Macchiarulo, L. (2008). Exploring and
QRS detector was implemented in a single chip from FPGA Prototyping Designs for Biomedical Applications.
family. It has accuracy of about 95% and boasts noise Xcell Journal, Third Quarter (65), 18-21.
immunity and low cost. Because of the design optimization [5] Mallat, S.G. (1989). A theory for multiresolution
and capacity of FPGA, dozens detectors can be placed in signal decomposition: The wavelet representation.
same chip and directly embedded in medical instruments or IEEE Trans. Pattern Analysis and Machine
wearable health care devices. After theoretically Intelligence, 11 (7), 674-693.
explanation, overall design methodology was presented [6] Calderbanka, A.R., Daubechiesb, I., Sweldensc, W.,
including description of the components and the system as a Yeod, B.L. (1998). Wavelet transforms that map
whole. Also the software simulation and the verification are integers to integers. Applied and Computational
performed. Further, the testing procedures and preliminary Harmonic Analysis, 5 (3), 332-369.
results were elaborated and discussed. The same principle
[7] Said, A., Pearlman, W.A. (1996). An image
could be applied with other signals where required hardware
multiresolution representation for lossless and lossy
implementation of wavelet transform.
compression. IEEE Trans. Image Processing, 5,
1303-1310.
ACKNOWLEDGMENT
[8] Walker, J.S. (1999). A Primer on Wavelets and
The work presented was funded mainly by the Scientific Applications. Boca Raton: CRC Press.
Montenegrin Ministry of Science. The authors are thankful
[9] Li, C., Zheng, C., Tai, C. (1995). Detection of ECG
for the support.
characteristic points using wavelet transform. IEEE
Trans. Biomedical Engineering, 42 (1), 21-28.
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