Towards Automation Of 180nm, 90nm And 45nm

Standard Cell Library Characterization

By Shraddha Maheshwari, Rajat Bansal and Rishi Sharma (Students)

shraddha.15bec2027@abes.ac.in, rajat.15bec2065@abes.ac.in & rishi.15bec2015@abes.ac.in
ABES-EC Department of Electronics and Communication Engineering
Affiliated to Dr. A.P.J. Abdul Kalam Technical University

Abstract – The focus of this paper is to study the SS, FS, SF), temperature and voltage corners will
parameters involved in the standard cell library be the part of the proposed work.
characterization taking into account the three
technologies nodes i.e., 180nm, 90nm & 45 nm. Cell Library Characterizarion is a process of
Commercial library cells are proprietary analyzing a circuit using static and dynamic
information of EDA companies. The companies methods to generate models suitable for chip
usually impose certain restrictions on the access of implementation. Standard Cell Library
these library cells. For example, Synopsys is Characterization is basically done to analyze the
offering Liberty NCX, Cadence has Virtuoso logic cells in terms of area, performance and
Foundation IP Characterization and power. Along with this, implementation and fixing
MentorGraphics & Z-circuit technology (acquired of the standard set of rules as per the specifications
by MentorGrapics) is offering Kronos for Standard provided by the foundry. The key factor for the
Cell Library Characterization. Producing designs rapid growth of the integrated system is the use of
based on sub-micron technologies at a competitive ASIC (Application Specific Integrated Circuit)
cost has always been a challenge for library for various system functions. It consists of
manufacturers. well designed and verified blocks that shortens
development time and manages complexity of the
Keywords : Standard cell, library, chip. The economic and efficient accomplishment
characterization, VLSI design, ASIC, down- of the ASIC designs depends on the choice of
scaling, technology nodes, area, timing, power, library. Therefore it is necessary to build the
PVT corners library that fulfills the design requirement.The
main focus is to minimize the area of each standard
I. INTRODUCTION cell. This will further cater the placement and
Standard cell library is a collection of routing of the logic blocks placed over integrated
combinational and sequential logic gates. It is an circuit in terms of reduction of the area of the
abstraction of specific logic gates, providing whole chip with minimum change in the
characteristics and description of these gates performance. So, the main focus is to design
including area, timing and power. Standard cell standard cells of Inverter, NOR, NAND, MUX, D-
methodology allows designer to focus on higher FlipFlop(Sequential Circuit) and Full Adder.
level circuit and system design without worrying
too much about the detailed implementation of a II. LITERATURE REVIEW
specific cell. Down scaling of the technology node may not have
impact on the functional and behavioral aspects of
The intent of the work is to create standard cell
the design but timing and performance are affected
libraries at 180nm, 90nm & 45nm technology significantly. Starting from this the first study
nodes along with the characterization results for which we will be discussing is “Characterizing
academic and research purposes. The study of the VLSI Standard Cell Library”. This study has
involved parameters at different process(TT, FF, described a system for characterizing standard cell
library, consisting of a stimuli database describing optimization of SC library namely Exhaustive
the characterizations requirements of each cell. transistor sizing and transistor placement with
Entire characterization system, called ch, using euler paths. In exhaustive transistor sizing, for a set
standard UNIX facilities like sh, awk, ed, sed, cpp of basic logic SCs, we obtain a set of most
etc. Geometrical circuit data is extracted from the balanced pull-up and pull-down networks.Euler
GDSII description using DRACULA layout path theory generates optimal source/drain sharing
parasitic extractor. for compact SC area.There may exist multiple
area-optimal Euler paths for a Standard cell
Moving towards the second study i.e. “Design of a library.The path with better pin accessibility and
Custom Standard-Cell Library in 28nm smaller pin capacitance is favoured. Further
CMOS”. This study compares the results of library-level optimizations are performed based on
different standard cells on varying the parameters final PPA metrics from entire synthesis flow.
such as transistor sizing, threshold voltage,
dimensions of power tracks, number of tracks in a
standard cell and PVT corners. The conclusions on
the basis of delay optimizations, leakage power
consumption and delay has been made. The
significance of clock tree synthesis over
performance of the design is also been explained
and verified with the results.The ultimate goal of
the project is to analyze the design to cater the
designing and fabrication of the 32-byte SPI .

The another study which is involved to lead to the

proposed work is, “Standard Cell Library Based
Layout Characterization and Power Analysis
for 10nm Gate-All-Around (GAA) Transistors”.
The superior gate electrostatic control of the
channel over FinFET, gate-all-around (GAA) Fig (i)
transistor technology is one of the most promising [Design Flow]
candidates for ultimately scaled FETs. The
parameters considered for analysis are ND, Ns, Nc, This is the synthesis flow of the study. This study
electrostatic-charge and threshold voltage. revolves around the optimizations that can be took
care of at 7nm technology node.
As moved towards FinFET and GAA, one of the
challenges is the discrete size of the fin and III. DIGITAL DESIGN FLOW
nanowire. Transistor width, which is one of the
main variables for tweaking transistor sizes, is no The project is concerned towards designing of
longer a continuum. The driving strength standard cells. Digital Design Flow is described
of GAA transistor depends on geometrical below.
parameters of nanowires. Thus, the GAA standard
The design flow starts from the specifications
cell sizing involves selecting the appropriate
number of nanowires for pull-up and pull-down gained by the user/clients. As per the specification
networks of each logic cell. Here, in this study, a like technology node, Chip density, Area, Power,
general sizing method is adopted that targets at Timing etc, process of designing the standard cells
balancing the rise and fall delays of a standard cell. started. The flow is then divided into 6 modules:

The next that we are referring to is, “Standard 1. Starting from schematic design, creating symbol
Cell Library Design and Optimization
of the schematic will end up to the pre-layout
Methodology for ASAP7 PDK”. This study
mainly suggests two techniques for design and simulations or schematic simulations.
 To design a Standard Cells Library
Characterization the following tools of Cadence
Design Tool will be used:
TOOL PURPOSE
Virtuoso Schematic Editor Schematic Design
Spectre Schematic Simulator
Virtuoso Layout Editor L Layout Design
Calibre Layout Verification
(DRC,LVS)
Layout XL Layout Simulation
Assura Run DRC, LVS
RedHat (OS) Environment
Table 1
[Tools Used]

Input Files : .lib, .db, .def, .lef

.LIB(Liberty Timing File) : .lib is basically a

timing model contains cell delays, transition, setup and
hold time requirements. The design needs to be
tested for PVT (Process Voltage and Temperature)
corners. But for every PVT corner, the timing of
the cells are different. Hence, there is .lib for every
PVT corner.

Fig (ii) .DB(Database file) : .db file is the technology

[VLSI Design Flow] library file. Like gdpk180nm, gdpk90nm etc.

2. Designing of the cell specific layout as per the .DEF(Design Exchange Format) : The DEF file
standard Design Rule Checks (DRC). Followed basically contains the placement information of
macros , standard cells, I/O pins and other physical
by SPICE netlist extraction of the layout.
entities. DEF generated by PnR are used by STAR
3. The next step will be to run Layout vs RC extraction.
Schematic (LVS) check to validate the design.
4. Then post layout simulation will take place . .LEF(Library Exchange Format) : The LEF file
5. Parasitic Extraction then will be performed to is the abstract view of cells. It only gives the idea
analyze the design parasitics and the effects of about PR boundary, pin position and metal layer
information of a cell.
the parasitics (resistance & capacitance) over
the performance of the design. IV. CHARACTERIZATION METHOD
6. After this, placement and route will come into
picture. The idea is to focus on the library characterization
Then we will follow all the above mentioned steps of the combinational circuits (Inverter, NAND,
at different PVT corners by model selection and NOR, MUX) and sequential circuits (D-FlipFlop,
specification. Lastly the verification of the design Adder) at three technology nodes i.e., 180nm,
90nm, 45nm. Library Characterization till date is
will take place at these PVT corners.
done at any one technology node, mainly focusing
on combinational circuits but the current work will
 be providing wide range of analysis of each cell 1ARM Inc., Austin, TX, USA, “Standard Cell
(combinational and sequential) at three technology Library Design and Optimization Methodology for
nodes at the same tool. It will cover analysis of all ASAP7 PDK”, IEEE, INSPEC Accession Number:
the cells on the basis of timing, power dissipation, 17430566, ISSN: 1558-2434, ISBN: 978-1-5386-
area, threshold voltage and leakage current from 3094-5, 14th December 2017
higher to lower technology nodes. Addition to that
analysis and results of PVT checks and TT corner [2] Jan Pliva, Rui Ma, Bastian Lindner, Laszlo
of the cells at three technology nodes will also be Szilagyi, Florian Protze, Ronny Henker and Frank
captured. Schematic Simulations performed will Ellinger Chair for Circuit Design and Network
mainly be transient in nature since the main focus Theory Technische Universitat Dresden, 01069
is digital logic standard cells. The main purpose is Dresden, Germany, “Design of a Custom Standard-
to build understanding of the library Cell Library for Mixed-Signal Applications in 28
characterization of the standard cells. This will also nm CMOS”, IEEE, INSPEC Accession Number:
make it easy to understand the logical and physical 16963905, ISBN: 978-1-5090-5582-1, 15th June
functioning of the combinational and sequential 2017
logic gate with respect to time, area, power
dissipation and leakage. All the cells will be [3] Luhao Wang, Tiansong Cui, Shahin Nazarian,
framed using CMOS (Complementary Metal Yanzhi Wang and Massoud Pedram Department of
Oxide Semiconductor) technology and pass Electrical Engineering University of Southern
transistor technology. California, Los Angeles, CA, “Standard Cell
Library Based Layout
V. CONCLUSION Characterization and Power Analysis for 10nm
Gate-All-Around (GAA) Transistors”, INSPEC
The study till now has been made on either any of Accession Number: 16836330, Electronic ISBN:
the cell or a technology node. The conclusion is to 978-1-5090-1367-8, Electronic ISSN: 2164-1706,
perform analysis on 12 cells i.e., Invereter, NAND, 24th April 2017
NOR, MUX, D-flipflop and full adder using
CMOS and pass transistor technology at the three [4] Mehmet A. Cirit Adaptec Inc. 691 South
technology nodes(180nm, 90nm & 45nm). Milpitas Blvd. Milpitas, C A 95035,
Addition to that the cells will be analyzed at 2 “Characterizing a VLSI Standard Cell Library”,
driving strengths (Nf=1,2). The standard cells then IEEE, INSPEC Accession Number: 4188640,
will be characterized on the basis of delay, leakage ISBN: 0-7803-0015-7, 6th August 2002
power and area at all design styles, driving
strengths and design technology nodes. This will [5]Yu Yuan, Cecilia Garcia Martin and Erdal
ultimately provide a large sum of data analysis Oruklu Electrical and Computer Engineering
points for academia and research purposes. Illinois Institute of Technology Chicago, IL,
60616, “Standard Cell Library Characterization for
VI. FUTURE SCOPE FinFET Transistors using BSIM-CMG Models”,
IEEE, INSPEC Accession Number: 15519747, 8th
The future scope could be automation of the October 2015
standard cell design using cadence language
SKILL in collaboration with TCL (Scripting [6] Srujan R, Vinay S, Sruja m & Vishal M S,
Language) in RedHat (Operating System) “Design, Implementation and Characterization of
environment on the basis of given specifications. 45nm standard cell library for industrial synthesis
Developing a script to facilitate automated flow”, International Journal for Scientific Research
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[1] Xiaoqing Xu, Nishi Shah, Andrew Evans,

Saurabh Sinha, Brian Cline1, and Greg Yeric