WHAT IS VHDL

VHDL stands for VHSIC HDL where VHSIC stands for Very High Speed Integrated Circuit and HDL stands for Hardware Description Language Initially designer used traditional method of paper pencil method to design system. Now design methodology is automated. Although the concept of HDLs is not new, their widespread use in digital system is no more than a decade old. Now we are available with CAD for digital system design.

HDL is being used to write model for a system. Initially it was used to describe digital system models. why actually we need system modeling?? Requirement specifications Documentation Testing using simulation Formal verification Synthesis Requirement specifications means, system specification. In HDL language, we can model the system as per the required specification and it can also be changed if required by just changing the HDL program of the model.

 Main advantage that HDL provides is testing. Before actual implementation, every design can be tested for its functionality. In a hardware design environment, a hardware description uses component models and definitions from a simulating library to form a simulatable hardware model. Now the hardware model and set of stimuli (test inputs) are used as inputs of a hardware simulation engine. The simulator produces simulation results that indicate the conduct of the hardware component for the given set of test data.

 Once design is verified, next step is to do synthesis which will realize the system using FPGA. A design aid that automatically transforms design descriptions from one form to another is called a synthesis. HDLs are useful media for input and output of hardware synthesizers. FPGA synthesis tool, available from FPGA vendor

Modeling Digital System

Do you think that design is a straight forward logical process?? Some times its seems that goal is straightforward, but path to the goal has a number of decision points. Some time, some specifications of the system to be designed is not clear or incomplete or it may happen that implementation forces us to redesign the system. Most of the designs are done twice, sometimes even thrice for satisfying system specifications. It is best described as hit & trail method. So we need a language that helps with the real (interactive) design process.

Also the time taken to complete the design, know as design time, can be divided into the following parts Architecture design time means the system architecture is to be decided (20%) Coding design time i.e. time taken for coding the decided architecture of the system.(20%) Debugging time i.e. the system should be verified for its functionality as well its timing requirement has to be verified. If specification is not being satisfied, then designer have to look into coding part or many even think for its architecture change (45%) Synthesis time: Once everything is verified, design moves on to synthesis tool for its implementation.(15%)

 The most crucial part is coding. If coding is simple and correct, then we are sure the system design will be successful. HDL (hardware description language) has some more salient feature. The first one is multiple level of abstraction i.e. we can design system either by using gates or we can design using some other system. Also we can describe functional blocks and then interconnections will give the desired system.

 Two major HDLs which are very popular nowadays are Verilog and VHDL. Both are programming languages base or text and easier to create a design. Difference between the HDL and the regular programming language is that the regular programming language is inherently sequential whereas HDLs have concurrency (parallel execution) and timing. Also HDLs have constructs to describe hardware

Main feature of VHDL requirements

General Features: VHDL should be a language for design and description of hardware. VHDL should be used for design, documentation, high-level design, simulation, synthesis, and testing of hardware. Design hierarchy: In VHDL, some times we need hierarchical specification of system that we want to design. A design consists of an interface description and a separate part for describing its operation. Several descriptions may exist for describing the operation of a design, all corresponding to the same interface.

What is Abstraction?
Abstraction means the level of detail contained within the system model i.e. the representation of the system. Currently we have the following abstraction mechanisms in hardware systems. A system can be modeled at system level algorithms or instruction set level register transfer level(RTL) Logic or gate level Circuit or schematic level A model of the system can be described by Behavioral method Structural method Physical method

Top to Down VHDL based design methodology

Whenever system is to be designed the first step is to obtain VHDL description of the system. After that the model is being verified for its functionality, and this is know as functional simulation. Once functionality is verified, synthesis is done to realize it. After synthesis, timing simulation is done to verify the timing constraints for the system. This is known as timing verification. After timing verification, the design is to be realized on FPGA or ASIC. This will be handled through floor plan, placement and routing algorithm

Flow Chart for the HDL based design

BASIC HDL CONCEPTS

VHDL is case insensitive Entity or Interface declaration Architectural declaration. Test bench generation Synthesis and Timing verification.

Interface declaration
This is known as entity declaration. This gives us information about the number of inputs to the system and the output that we are expecting from the system. Take example of 2X4 decoder. As we know 2X4 decoder has 2 input lines (say X and Y) and 4 output lines( say D0 , D1 , D2 , D3 ). So for designing any system, the input and output line in the system must be known.

 we can say entity declaration is simply the black box presentation of the system that designer wants to design. These input or output lines are also known as ports.

Four types of Port

Input mode Output mode In out mode Buffer mode

Entity declaration
The following format is used to declare entity. Entity entity name is Port (port names ); End entity name; all the bold statements are key words

 entity for three input OR gate. We have three inputs as a, b, c port and output is at o port.

 Here entity name can be any identifier. While declaring ports, mode must be given along with its type i.e. data type. This port type indicates the type of values that system port can take. The data type will be discussed next. Right now, we are assuming that each input is of single binary bit and this is being defined as Bit. Each line ended with semi column (;). Once all the port is being declared, close the port declaration by small bracket- ). Every entity declaration must be ended with end entity entity name. Some version of VHDL simulator supports end entity name.

Tips for entity declaration

It should not be any standard key word otherwise complier will give error message. Key words can easily be identified by VHDL simulator in blue color while writing program on source window. Also avoid giving same entity name to different design. Mode inout should only be used in the case of bi-directional signals. If the signal has to be reread, either mode buffer or an internal dummy signal should be used. If input is of more then one bit i.e. if design consists of vector type of input, then data type have to be defined like this: bit_vector (0 to 3), where 0 to 3 indicates that system port is having four bit. Take the design of 4X1 Mux, where we have four input line which will be acting as data lines and two inputs which will be acting as selector inputs. The entity for the same can be written as given below assuming selector signal is of 2 bit.

Entity mux4x1 is Port (I0, I1, I2, I3: in bit; S: in bit_vector (0 to 1); F: out bit); End entity mux4x1; In the above entity declaration, port S, will be taken as S(0),S(1) by the VHDL simulator. If we want to take S(1)S(0) presentation for S, then we have to declare S as bit_vector (1 downto 0). Tips regarding vector type of port: Use downto options since in digital system design we prefer to interpret vector input/ output from its MSB to LSB.

Architectural Declaration
In architectural declaration part, we have to define the functionality of the system that we are going to design. The architectural declaration takes place after entity declaration and its format is given below Architecture name of entity name is Where name is the name of architecture, which can be any valid name and entity name is the name of entity for which this architecture will work. For the previous example, Architecture beh of mux4x1 is

After architectural declaration, the architecture must be end with command as shown below Architecture beh of mux4x1 is End beh; Where .. indicates programming part, and beh is name of architecture.

Types of Architectural declaration

The functionality of any system can be defined by various means as discussed earlier. Go back to Y-chart, we can see any system can be modeled by the following method. Behavioral method Structural method Physical method

 Behavioral method: This method is used when the system output behavior is known in terms of inputs. The detail analysis will be done in Behavioral chapter. Structural method: This method is used when we know that system can be designed by using smaller components. This method of designing is also known as bottom to top approach. If smaller components can be connected to get the bigger design, then structural type of modeling is used. The detail analysis will be done later. Physical method: This is also known as dataflow type of modeling. This method is used when the system outputs are known in term of Boolean expression of inputs. The detail analysis will be done in dataflow modeling topic.

Data types, Objects and Class

Objects mean the name of ports or intermediate signals use for connection. An object contains a value of a specified type and a class. Type indicates what type of data the object contains. Class indicates what can be done with the object VHDL is strongly typed language. It means different data types cant be mixed i.e. data of different type cant be assigned to each other. If we want to assign two objects of different data type then first of all it should be converted to compatible form by using type conversion concept.

Example: signal a : std_logic; a is object, signal is class and std_logic is data type. There are three different classes namely Variable Signal Constant Variable and signal can change its value but constant does not change value and each of them can be of any data type Tips for declaring the different class: Variable is declared only inside process and subprogram part of vhdl and it can be used only in that process and subprogram where its declared. A signal is declared between architecture and begin but it can be used any where i.e in sequential as well as concurrent part of vhdl. Constant can be declared between architecture and begin and also in package, but it can be used any where i.e in sequential as well as concurrent part of vhdl. Package will be discussed later.

Data Types
Boolean type: The Boolean data type can only be true or false. A<= X<Y; then output A will be true when X<Y, otherwise A will be false. Integer type: This data type is used when integer value is to be taken. An integer value can vary between 2147483648 to 2147483647. Example: signal A: integer range 0 to 255 signal B: integer: = 30; Bit type: This is defined in the standard library. This can take only two values, 0 and 1. For example, Signal b: bit; mean signal b can take either 0 or 1 value.

If we want to assign any input as vector say 101, then the data type used for the same will be of bit_vector type. Only bit and bit_vector were initially defined in the VHDL standard. This leads to several restrictions in design as given below: 1. Its not possible to describe tri state logic i.e. we cant assign high impedance state to any signal 2. Its not possible to assign unknown to a signal 3. Its not possible to assign dont care to a signal

Std_Logic Data types

As bit can assume only the values 0 and 1, threestate and unknown, cant be described using bit or bit_vector. Also in case of tri state logic, where several signal are often driving one signal cannot be handled with bit or bit_vector data type. So we have to find some new data type for handling the same. VHDL suppliers have created their own data types but this created new problems as indicated below

1. The VHDL code becomes tool dependent 2. Design from two different tools were not compatible as these data types are only defined in their respective tools, and when VHDL code is moved from one simulator to other then compatibility problems comes into picture. This problem created confusion on the basic idea behind VHDL philosophy of platform and tool independency.

 To solve the above mentioned problem, IEEE defined new data types as std_logic and std_ulogic. These standards now have become industry standard for design. Both of the new data types can assume exactly the same value, provided std_logic is resolved subtype of std_ulogic.

 Std_ulogic type: This is declared in the IEEE package named: std_logic_1164. It can assume the following values as given below along with its meaning U -- for un initialized X -- for unknown values 0 -- for 0 values 1 -- for 1 value Z -- for high impedance W -- for weak unknown L -- for weak 0 H -- for weak 0 - -- dont care

Resolved Data Type

For Std_logic data type all the values of std_ulogic are same. Std_logic is resolved means that, if a signal is driven by several drivers, a predefined resolution function is called up, which then resolves the conflict and decides which value the signal will be given. If by mistake if we had written VHDL code such that there are two drivers for the same signal, then std_logic data type will not give error This feature of std_logic can be utilized for tristate buses in which several drivers drives the same signal on the bus as shown in next slide.

Dout <= din1 when en1=1 else z; Dout <= din2 when en2=1 else z; If a std_ulogic signal is driven by more than one driver, it will result in an error as VHDL does not permit an unresolved signal to be driven by more than one driver. This restriction on std_ulogic has led to data type std_logic preferred.

 Vectors: Lets define A, which is acting as input port for any design, and is of 4 bit. So it can be defined as A: in bit_vector (0 to 3) or A : in std_logic_vector (0 to 3). It is permissible to define vectors with both to and downto. If to be used, the vector gets value as (0 to 3). If downto is used, the vector gets value as (3 downto 0). As far as hardware designing is concerned, downto better suits as the first bit is generally MSB. Time: when any object is to handle timing information, then data type has to be defined as time. The format for the same is given: constant delay: time; Vector assignment: When any port or any signal, constant or variable is defined as vector type, then the following notation is used for assigning value to the same. A<=0000010;

 If logical operators like AND, OR, XOR are used on vectors, the result will be bit wise. Take the following example where A and B is signal of 4 bit each and C is AND of A and B. Signal A: std_logic_vector (0 to 3); Signal B: std_logic_vector (0 to 3); Begin C<= A and B; End; Note: It is to be noted that whenever logical operators are to be used, both the vector must be of same vector length and the assigning vector should also be of same length.

Slice of Array
Some time it may happen that you want to assign a value to a bit or a part of the vector. It can be done as given below: Signal a: std_logic_vector (0 to 4); Begin a(4)<= 0; a(3 downto 0)<=0111 It is to be noted that when a slice of array is assigned a value, the slice direction must be the same as in the declaration. It is also permissible to assign a vector a slice of another vector. Signal a:bit_vector(0 to 3); Signal b:bit_vector(3 downto 0); Begin b(2 downto 0)<= a(0 to 2); end ;

Concatenation
It can be very useful in vector assignments. Ampersand (&) symbol is used for concatenation. Signal a: std_logic_vector (0 to 2); Signal b: std_logic_vector (0 to 4); Signal c: std_logic_vector(0 to 7); Begin c<= a &b; end; It is not permissible to use concatenation on the left of the signal assignment symbol. See the following example

Signal a: std_logic_vector (0 to 2); Signal b: std_logic_vector (0 to 3); Begin 0 & a <= b; End; This program is erroneous as 0 & a is invalid on left side of <= symbol.

 Some time it may happen that we need to assign the same value to the entire vector. If the size of vector is very large then one option that can be done to assign the entire vector is shown below, for 8 bit number. B<=00000000; If the size of vector is very large then it can be handled by using aggregate technique in VHDL. B<= (others=>0); The assignment is independent of the vector length. b<= (1=>1,2=>0,others=>0); b<=(1=>1,2=>0,others=>a(2));

Aggregate

Operators
In VHDL, there are two important types of operators. First one is relational operator and the second one is arithmetic operators. Relational operator: In VHDL there are several types of relational operators as shown below along with symbol and its operand.

These operators produce a Boolean i.e. true or false type of result. Symbol = /= < > <= >= Operand equal not equal Less than Greater than less than or equal greater than or equal

 Arithmetic operator: There are predefined arithmetic operators in VHDL as shown below along with symbol and operator. Symbol + * / rem mod ** abs Operator Addition Subtraction Multiplication Division Remainder Modulus Exponentiation Absolute value

These operators are predefined for data types integers, real and time. If we want these operations on std_logic or std_logic_vector, then the following library have to be included in your VHDL code. Use ieee.std_logic_unsigned.all;

Initial value
All signals have an initial value when simulation begins. This value can either be user defined or will be default value. The simulator will assign these initial values to signals during the simulation. User can define the initial value by the following statements Signal a: std_logic:=1;

 For type bit, the initial value is 0and that for std_logic is U. As far as synthesis is concerned, there is no hardware interpretation of an initial value. It is not possible to initialize all signals in a circuit with a known value. Even though it is possible to do a power-on reset in some logic technology, it would not be desirable to do this for every wire in the circuit. So, synthesis must ignore initial values. This may cause circuit failure for a synthesis generated design. It may get permanent stuck in an unknown state. It is the designers responsibilities to provide a technique for putting the circuit into a known state, either in the form of a global reset input to the system or by designing circuit so that system can be put into a known state in some way.

Predefined Signal Attributes

Signal attributes are very useful when it comes to making VHDL models. An attribute is information which can be obtained on blocks, array, signal and types. The syntax for using the attribute is <name> attribute identifier The most commonly attributes are given below 1. <signal>event: means if a is signal then a event means the value of a has changed on transition have occurred on the clock. 2. <signal> last_value: means return the last value. 3. <signal> range: means return the signal range. If a is signal of std_logic_vector(0 to 3) then a range means 0 to 3.

DATA FLOW MODELING

Data flow type of modeling is used when output relationship is known with inputs as Boolean expressions. Consider design of 2X1 multiplexers F = I0.S + I1.S Entity mux is Port (I0,I1,S: in bit; F : out bit); End mux; Architecture t1 of mux is Begin F<= (I0 and (not S)) or ( I1 and S); End t1;

Problem: write dataflow model for Half adder

Half adder is having two inputs A,B each of single bit and two outputs, say, S and C, which represents Sum, carry after adding A and B. Entity HA is Port (A, B: in bit; S, C: out bit); End entity HA; Architecture t1 of HA is Begin S<= A Xor B; C<= A and B; End t1;

About Comment line

If we want to put comment for more readability of the code, we can do it by using -- syntax before the comment that we want to put. Comment makes the line non executable what ever written after --. In the above program if we want to add some comment for S, see the following method. S<= A Xor B; --S is representing Sum C<= A and B; -- C is representing Carry

Concurrent & Sequential Statements

The statements in VHDL is broadly classified in two parts 1. sequential statements 2. concurrent statements Sequential statements: most of the programming languages that we have gone through are sequential. Sequential means statements are compiled line by line. In another way we can say that in this type of statements, order of writing program will affect system behavior as program is executed line by line sequentially. In VHDL, sequential statements are written inside process command. The if-then-else command and case command are most commonly used sequential command in vhdl.

Concurrent statements: concurrent statements mean statements that will be compiled at a same time or executed parallely. In another way, order of statements in writing program will not affect system behavior. In VHDL, concurrent statements must be written outside process command. The with-select command and while command are most commonly used concurrent command in vhdl.

concurrent language
Signal assignments: Signals are concurrent objects. In hardware it usually feels natural to work concurrently using signal assignment statements. S<= A Xor B; The above example has no component delay. This is the normal method of description for VHDL code written for synthesis

 Alternatively, the code could have been written with a component delay 5 ns, using the after command in VHDL . It is possible to define several values in one signal assignment. X<= 1, 0 after 5 ns, B after 7 ns; Note: 1 is when X is of Bit or std_logic type, i.e. of single bit. If its of more than one bit, we have to use 000 i.e. double quotation.

Concurrency
Hardware is parallel by nature, and so is VHDL. This means that all concurrent language constructions in VHDL code can be executed concurrently, making the order in which the code is written irrelevant. Example: Begin a<= b; b<= c; end s1; This is same if we write as given below Begin b<= c; a<= b; end s1;

 Signal assignments assignment is event controlled means whenever the value of signal or expression changes on right hand side then the new value is assigned to the signal of left hand side of signal assignment operator. Lets take b<= c; The above statement is executed only when the value of c is changing.

There are three types of delay model in VHDL 1. Inertial Delay model 2. Transport Delay model 3. Delta Delay model

Delay Model in VHDL

Inertial delay model: This type of delay is used to model component or system delay. Specialty of inertial delay is that spikes can be handled effectively. This is used along with after command. Example: Q1<= a after 5 ns; If a spike of 2 ns occurs at the input side and if the system delay is 5 ns; then this will not be able to affect the system output. if spike is of certain specified duration, use reject command to handle the same Q1<= reject 2 ns inertial a after 10 ns;

 Transport delay: This type of delay modeling is used to model propagation or interconnection delay from one point to other point. Q1<= a transport after 5 ns; The above statement indicates that Q1 will be getting the value of a after 5ns irrespective of spikes.

 Delta delay: Delta delay is used in VHDL for queuing up sequential events. The time between two sequential events is called a delta delay. In a signal assignment, the value is not assigned to the signal directly, but after a delta delay at the earliest b<= c; In the above statement the signal b get the value of c after delta delay The synthesis tools do not support any of these delay models. They are used when making VHDL model for simulation.

Examples
Signal A is in the input mode and signal B1, B2 and B3 are in the output mode. Lets we have the following transitions on signal A.

Now find the output waveform for the following statements B1<= inertial a after 10 ns; B2<= transport a after 10 ns; B3<= reject 4 ns inertial a after 10 ns;

Solution

CONCURRENT COMMANDS
When-else statements: This command executes operations depending on the value of expression. Syntax : target signal <= expression when condition else Entity ex is Port (A: in bit_vector (0 to 1); F: out bit); End ex; Architecture t1 of ex is Begin F<=1 when A=11 else 0 when A=00 else 0 when A=10 else 0; End t1;

 It is permissible to use several conditional expressions in when-else command. F<=A when enable =1 else B when input =00 else C when clock =1 else 0; Note that the conditions are checked in the order in which they are written. The conditions are evaluated line by line until a condition is true If enable=1, input=00 and clock=1.This will give output F as A since while going through each statement line by line, first condition got satisfied so next condition will not be checked It is only between concurrent commands that order is not important. Inside a concurrent command, e.g. in when else, order is important.

 With statements: Syntax With expression select Example: With S select F<= I0 when 0, I1 when 1; End t1; In case S is std_logic type, which have 9 possible values, all the possible condition of input signal has to be specified otherwise there will be simulation error. Other way to handle this situation is to use When Others command, as shown below. With S select F<= I0 when 0, I1 when 1, Z when others;

Sequential statements
In the sequential statements all statements are executed sequential i.e. one by one. In VHDL, sequential statements are written only inside process command. Process command will be covered later. If- then- else command : Format If (conditional expression) then Statements ; Else Statements; End if;

For 2x1 Mux, If (Sel=0) then f<= I0; else f<=I1; End if; Similarly we can write the VHDL model for 4X1 Mux, If (Sel=00) then f<= I0; elsif (Sel=01) then f<=I1; elsif (Sel=10) then f<=I2; else f<=I3; End if; Since we have four condition on Sel, so we have to use elsif command.

Case command
This command is same as that of switch case used in C language. The basic format for using case command is given below Case expression is When condition1 => statements; When condition2 => statements; ---------------------------end case;

Case Sel is When 00 => f<= I0; When 01 => f<= I1; When 10 => f<= I2; When 11 => f<= I3; End case; Every case command must have its end All the choices must be listed or must have when others=> command at the end.

 Its also permissible to define ranges in the choice list. This can be done by using to or downto. If a in input of type integer and q is output of type integer then Case a is When 0 => q<=3; When 1 to 100 => q<= 4; When 200 downto 101 => q<=5; When others => q<=0; End case;

 If you want to include several vectors in a choice list in the case statements, it is not possible to use concatenation command (&) to combine the vectors as one choice. This is because the case expression must be static. Case a&b is The solution is to use a variable or Signal to which the value a & b is assigned. For example Variable temp: std_logic_vector (5 downto 0) ; Begin temp:= a & b; case temp is

 Null statements: In VHDL there is a statement which means do noting. This command can be used when we dont want any signal assignments or any output value to change. In the case of when others command used in case statements, case temp is When 000000 => q<= 100; When 010010 => q<=101; When others => null ; End case;

Signal and variable assignments

Variables are used for sequential execution whereas signals are used for concurrent execution. The main comparison between them are shown below 1. Variable assignment symbol:= and signal assignment <= 2. Variable can only be declared and used in the sequential part of VHDL means it can only be declared and used inside process command, whereas signal is declared between architecture and begin and can be used in sequential as well as concurrent part of VHDL 3. The big difference between them is that the signal is only assigned its value after a delta delay, while variable gets its value immediately.

 The difference between the executions of signal and variable:

Process (a,b) Begin b<= a; c<= b; end process;
Time: 0 ns, a=0 and b=0. Time: T ns, a=1 i.e. a changed to 1 and b is kept same. This means the first statement will execute only as its event dependent and a is only changing. Time: T + , b will get 1, c will get old value of b i.e. 0. Time: T+ 2., b will not change its value as a is not changing but since b has just changed, so the second statement will execute and c will get 1. Now neither b nor a are changing so both the statement will not be executing any more and system will be having value on a as 1, b as 1 and c as 1 finally.

Process (a) Variable b,c:std_logic; Begin b: = a; c: = b; end process; The variable assignment takes place immediately. Lets analyze the following event. Time: 0 ns, a=0 and b=0. Time: T ns, a=1 i.e. a changed to 1 and b is kept same. Time: T + , b will get 1, since b gets its new value immediately so c will get this new value of b immediately i.e. c will become 1.

WHEN TO USE SIGNAL AND VARIABLE

Determine the suitable conditions to use signal/variable????? Ask yourself will I be using this assigned value in this same simulation tick If yes, obviously you need to use variable, otherwise use signal.

Process( ) Begin .. Var : = 5; .. .. If( Var=5) then .. . End process;

Assignment used in the same simulation tick in the sequential statements

 It is also for the reader to remember that usage of variable is local only to a process. If an assigned value is to be shared among different process, a signal is more appropriate. P1: Process( ) Begin .. Var < = 5; .. end process p1; P2: Process( ) Begin If( Var=5) then .. . End process p2;

Process statement
The process statement contains only sequential statements. The process command is declared after architecture-begin. The general format for declaring process command is as given below Architecture name is entity name is Begin Process (sensitivity list) Variables declaration Begin Sequential statements --------------------------------End process;

 Sensitivity list is the name of signal on which the execution of process depends. There are basically two types of process statements. (a) Combinational process (b) sequential process
Combinational process: whenever combinational system is to be designed, put the entire signal that are in the in mode, in the sensitivity list. process(I0, I1,Sel) begin Case Sel is When 0 => f<=I0; When others => f<=I1; End case; End process; End t1;

 Sequential process: Whenever sequential system is to be designed, we have to use sequential process. This is basically clocked process means process depends on the clock transitions. Clocked processes are synchronous and several such processes can be joined with the same clock. It means that no process can start unless clock transitions occur. Process (clock) Begin A<= din; End process;

 This process will start whenever clock changes from 0 to 1 or from 1 to 0. At each transition din value will be assigned to output A. If clock is not changing then output will retain its previous value. This clocked process will be used during flip flop realization.

 If a signal is not assigned a value in a clocked process, the signal will retain the previous value. The synthesis result from such a description will result in feedback of the signal from the output signal to the flip flop via multiplexers to itself. This type of situation arises when if-then-else command is used without giving else condition and if is directly ended with end if.

Different clock descriptions

Method 1: process (clock) Begin If ( clock event and clock=0 ) then Qout<=din; End if; End process;

 Method 2: process (clock) Begin If (clock=1) then Qout<= din; End if; Method 3: process Begin Wait until clock=1; Qout<= din; End process; Method 4: process (clock) Begin If ( clock event and clock=0and clock last_value=1) then Qout<=din; End if; End process;

Handling synchronous and asynchronous system modeling

There are two different ways of resetting a flip flop. They are synchronous reset and asynchronous reset. Asynchronous reset: With asynchronous reset, the flip flop will be reset as soon as the reset is activated, irrespective of clock event. This means reset signal must be included in the sensitivity list along with the clock.

 A general method of description which is supported by the majority of synthesis tools. Alt1. Process (clock, reset) Begin If (reset=1) then output<=0; Elsif ( clock event and clock=0) then Output<= input; End if; End process;

 Synchronous reset: With synchronous reset the flip flop can only be reset at an active clock edge. This means that if a sensitivity list is used in a clocked process which has to have a synchronous reset, only the clock should be included on the sensitivity list. A general method of description which is supported by the majority is shown below Alt2: Process (clock) Begin If ( clock event and clock=0) then If (reset=1) then output<=0; else Output<= input; End if; End if; End process;

 Latches: As we know latch is level triggered and output of the latch keep on responding according the changes in input. Process (enable, input) Begin If (enable=1) then Output<= input; End if; End process;

Wait statements
There are four different ways of describing wait statements in a process: 1. Process (x, y) 2. Wait until a=1; 3. Wait on x, y ; 4. Wait for 10 ns; The first and the third are identical if wait on x, y is placed at the end of the process.

The following two processes are therefore identical

P1: Process(x, y) Begin If (x>y) then Q<=1; Else Q<=0; End if; End process; p2: process begin if (x>y) then q<=1; else q<=0; end if; wait on x, y; End process;

 Wait until a=1; means that, for the wait condition to be satisfied and execution of the code to continue, it is necessary for signal a to have an event, i.e. change value and the new value to be 1, i.e. a rising edge for signal a. Wait on x, y; is satisfied when either signal a or b has an event (changes value) Wait for 10 ns: means that the simulator will wait for 10 ns before continuing execution of the process. Synthesis tools do not support use of wait for 10 ns type of wait command

Loop statements: There are two kinds of loop statements in sequential VHDL. (a) For loop (b) While loop. For Loop: This is used inside process command as its sequential command. The format for using the same is given below. Label: for <identifier> in <range> loop F1: For i in 0 to 3 loop If (a (i) =1) then Q (i) <= b (i); Else Q (i) <= c(i); End if; End loop F1; Each for loop command must have end loop

 While loop: This loop command is used inside process command. The logic for while loop is explained below with example. While (q<12) loop Statements.. q<= q + 1; End loop;

Structural Modeling
What is the purpose of structural modeling?

Structural VHDL is simply the interconnection of the number of components constraint with structural modeling is that block diagram for the complete system must be known. The following steps are involved for structural modeling. 1. Component declaration 2. Component specification 3. Interconnection between components

Component Declaration
The component that we want to use for bigger design must to available. For structural modeling of Half adder, the model for XOR and basic AND gate must be available to you. While writing structural program for Half adder, the components must be declared between architecture and begin as shown in next slide.

Architecture t1 of halfadder is component xor1 Port (a, b: in std_logic; c: out std_logic); end component; component and1 Port (x, y: in std_logic; z: out std_logic); end component; begin

 Its to be noted that port name can be same in different components. In the above example we can have the same name for ports x, y, z as used below. Architecture t1 of halfadder is component xor1 Port (a, b: in std_logic; c: out std_logic); end component; component and1 Port (a, b: in std_logic; c: out std_logic); end component; begin

 Its to be noted that the order of the signal in the port command must be same as that in the entity declaration otherwise it will give syntax error. If XOR1 entity declaration is like as given below and its to be used for half adder as shown above then the component declared below will give syntax error. Entity xor1 Port (a, b: in std_logic; c: out std_logic); end xor1; and during component declaration its written as component xor1 Port ( b, a : in std_logic; c: out std_logic); end component; -- error as in the entity a is declared before b.

Component Specification
If the VHDL simulator is to find the declared component, the component must be specified. This is done with the use of the following command. Syntax:
for: <component_name>use entity library. <entity name> (architecture name)

For u1: xor1 use entity work.xor1 (t1);

Interconnection between components

After component declaration, the main job is to interconnect the different component to get the complete system. This is known as component instantiation and different component are linked to other components using port map command. The port map command does the job of connection. The format for the same is being shown below. Label: entity name Port map (port association list) Label is indicating only the component label.

Half Adder Designing using XOR and basic AND gate

Before doing interconnection between different components and the original design, first find which signal from the outside world is to be connected with which port of the component used. In the above example its clear that a, b and c ports of XOR gate is to be connected with X,Y and S ,respectively, of the main block. This connection between the main block and the ports of the component used is known as association list as indicated on the port map format.

Entity half is Port (X, Y: in std_logic; S, C: out std_logic); End half; Architecture t1 of half is component xor1 Port (a, b: in std_logic; c: out std_logic); end component; component and1 Port (a, b: in std_logic; c: out std_logic); end component; begin U1: xor1 port map (X, Y, S); U2: and1 port map (X, Y, C); End t1;

Port Association: U1: xor1 port map (a=>X, b=> Y, c=> S);

Important tips about port map: 1. Unconnected inputs: Some times it may happen that some input ports of the component used may not utilized by the main block during interconnection. Then how to handle it? As no silicon supplier will accept an input to a hierarchical block which is floating or unconnected. If an input on a component is not in use, the signal should be connected to Vcc or Gnd such that overall functionality should not change.

 Suppose we have taken three input AND gate as a component and only two of its inputs are required for some application Component and1 Port (a, b, c: in std_logic; -- 3 input AND gate. F : out std_logic); End component; Signal high : std_logic ; -- this is representing logic high Begin High<= 1; U1: and1 port map ( x ,y ,high ,z );

 Unconnected outputs: Some time it may happen that some output ports of the component declared may not be utilized by the main block during interconnection. Then how to handle it? This can be done by using the VHDL command open. u1: Ha port map (A, B, F, open); If the last port declared in the component is to be kept open, then we need not to write open since by default it will be connected to open.

Generic command
Generic can be used to introduce information into a model. This information can be timing information, vector length etc. the generic must be declared in the entity before the port declaration command. A generic can have any data type i.e. it can have data type like time, real, integer. The following example illustrate the used of generic command. Example: entity generic1 is Generic ( N : integer:=3); Port (a : in std_logic_vector(0 to N); C: out std_logic_vector (0 to N)); End generic1;

 Similarly we can introduce generic delay information in any vhdl model. Lets see the program given below. Example: entity generic2 is Generic (delay: time: =3 ns); Port (a, b: in std_logic; C: out std_logic); End generic2; Architecture t1 of generic2 is Begin C<= a and b after delay; End t1;

Generic Map
If generic component have been specified in the component to be instanced, there generic parameter can be changed during instantiation using generic map. Lets write generic program for N input OR gate.

Entity or1 is Generic (n: integer: =5); Port ( a : in std_logic_vector( 0 to N); f : out std_logic); end or1; architecture t1 of or1 is begin process (a) variable temp : std_logic; begin temp:= 0; for i in 0 to N loop if (a (i)=1) then temp:= 1; end if; end loop; f<= temp; end process; end t1;

 We want to use the above component in other design using structural modeling. component or1 Generic (n: integer: =5); Port ( a : in std_logic_vector( 0 to N); f : out std_logic); end component ; begin u1: or1 generic map (n=>1) port map( a(0)=> X1, a(1)=>X2, f=>f1); u2: or1 generic map (n=>2) port map( a(0)=> X3, a(1)=>X4, a(2)=> X5, f=>f1); end t1;

Generate command
Sometimes, during structural modeling, it may happen that the same component is to be used more then once. Simple method is to use port map command for each component. But if the number of components is very large then this method will be very lengthy. If the same component has to be instanced several times in the architecture, it may be effective to include port map command in a loop. This can be done by using generate command. The format for using the same is being given below.

Label: for < loop index> range generate Label: entity name port map (port association list); End generate <label>;

Suppose we want to instanced a component, Entity test is Port (a: in bit; f : out bit); end test; 10 times in other entity whose entity is as shown below Entity t1 is Port ( x: in bit_vector (9 downto 0 ); q: out bit_vector( 9 downto 0)); end t1;

Entity t1 is Port ( x: in bit_vector (9 downto 0 ); q: out bit_vector( 9 downto 0)); end t1; architecture behave of t1 is component test Port (a: in bit; f : out bit); end component ; begin l1: for i in 0 to 9 generate u1: test port map( x (i) , q (i)); end generate l1; end behave;

TEST BENCH
After the design part is over, the design must be verified for its functionality. The general method is to apply input stimuli signal during simulation and then check the outputs from the system. Another method of verification is to write the test bench, where all the possible combinations for which the system is to be tested are written. This means that you design a test bench which provides input signals and test the output signal from the design. The recommendation is to use test bench for checking functionality. The advantage of test bench is that its fast and platform independent. The disadvantage is that the VHDL test bench can contain the same logical error as the design, i.e. the designer thinks the test is correct when it is in fact incorrect.

 The test bench is made up of two parts. One part generates the input signals for the model to be tested, while the other part checks the output signals from the model.