Networks on Chip (NoC)

Network-on-Chip (NoC) is used as the communication network in many applications that use multiple cores or Processing Elements (PEs). Routers play a crucial role as connectors since a faulty router can degrade the NoC's performance and cause miscommunication between the network's components. Thus a faulty router may cause the system to fail. To avoid failure in routers in NoCs, a novel self-healing technique is proposed. Self-healing serves to recover hardware faults, and it is defined as the ability of a system to recover from its faults without any external intervention. The proposed self-healing method is to heal faulty routers and their port buffers of faults as they occur. The proposed method uses the neighboring routers of a faulty router for computation. The data packet includes three bits for routing. A neighbor's active router updates these bits according to the destination of the packet. A self-healing block is added inside each router. The proposed method also covers faulty buffers, and it uses active buffers to store the packet of a faulty one. It has been implemented and tested using VHDL and Altera Arria 10 GX FPGA. It has been found to attain improved reliability and Mean Time to Failure (MTTF) at an area overhead of 27%. It has been tested for complex NoC structure, and the results show it is practical, scalable, stable, and robust. INDEX TERMS NoC, self-healing, hardware faults, fault tolerance, neural network, FPGA architecture.

Network on chip (NoC) is emerging as a new trend for a System on chip (SoC) design. The key advantages of NoC are high performance and scalability. Despite those improvements over the conventional shared-bus based systems, NoC are not shown as the ideal solution for the future SoC. Recently, with the three dimension (3D) technology. The 3D NoC has been designed to overcome the high power consumption, high- cost communication and low throughput. This paper present a 3D router design which can support seven requests simultaneously. The traditional Turn Model technique used in 2D NoC has been extended in the case of 3D NoC in order to avoid deadlock conflicts. Experimental results in terms of area, power and clock frequency, relatively to 2D NoC and others famous 3D routers has been discussed.

—this paper presents AMBA AXI-4, supports 16 masters and 16 slaves interfacing, with single master single slave talking to each other at a time. The AMBA AXI-4 system consists of master, slave and bus (arbiters and decoders). The operating frequency is set to 100MHz. Each master and slave has their own ID tags. Each slave is having 100 addressable locations. During each transaction the address/data to be read/written is initiated by the master, the slave responds accordingly. Arbiter avoids the collision, when two masters initiate the transaction at a same time. Decoder decodes the addresses received by master and goes to particular location of slave. The AMBA AXI-4 Master is designed in this project, which is modeled in Verilog and simulation results for read/write operation for data/address are shown in VCS tool.

Self-healing is increasingly becoming a promising approach to designing reliable digital systems, and it refers to the ability of a system to detect faults or failures and fix them through healing or repairing. Digital systems with architecture for self-healing are expected to compensate faults. However, there are a few research challenges that need to be overcome before self-healing becomes a mainstream approach. For example, current self-healing techniques face challenges such as scalability, reliability, area overhead, and mapping. This paper explains the self-healing concept and investigates the self-healing approaches related to digital design in the literature. It gives a general overview of the topic and explains levels of abstraction at which self-healing can be used: hardware level, application level, and system level. The paper presents multiple related works at each level of abstraction. In the faulted phase, different types of faults and fault detection methods are described. For the evaluation of a self-healing technique, this paper presents the parameters which can be used to evaluate a self-healing method. These parameters are redundancy rate, the maximum ratio of repair, self-healing time consumption, reliability, and area overhead. The paper also presents a comparison between previous works of self-healing in terms of evaluation techniques. Implementations using VHDL and ISE Xilinx Vertex-5 for self-healing on Embryonic Hardware (EmHW) and Network-on-Chip (NoC) are also presented. The simulation results show the contribution of self-healing to improve system reliability and mean time to failure.

Network-on-chip (NoC) architecture provides the communication infrastructure for system-on-chip (SoC) design. The architecture, size, and algorithm dominate the performance of NoC and influence on the design of arbiters in the switch. FIFO buffers are essential components of network switches-buffers have been estimated to be the single largest power consumer for a typical switch in an on-chip network. The presented work has design a 128-bit FIFO to store 128-bit flits in the NoC. The proposed architecture of FIFO is implemented in RTL model using verilog language. The FIFO has achieved a maximum operation frequency 675 MHz on Xilinx Vertex-6 6VLX75TFF484 device.

Network-on-Chip (NoC) is known as a scalable and high performance interconnect in Systems-on-Chip (SoCs) with multiple processing elements (PEs). Recently, the design paradigm of SoCs has shifted from static to dynamic run-time reconfigurable system. In these systems, the PEs can be loaded/unloaded on demand. Therefore, the NoC should be able to adapt as quickly as possible to the changes to maintain the performance of the systems. In this work, we present a non-intrusive runtime reconfigurable time-division-multiplexed circuit-switched NoC, XNoC, which offers the following benefits (1) it switches between different routes within a predictable latency that is strictly determined by the length of the route and the number of time slots; (2) the configuration process can be masked effectively by overlapping with communication and (3) the multi-cast service is supported with aggregate feedback from sink nodes. We propose an XSwitch which requires 3.5X less resource than the conventional switch with similar features. The overall resource cost of XNoC is also smaller than the most known NoC and the clock timing is up to 50% better. We also propose a novel distributed control plane to accelerate the reconfiguration process and to improve the scalability of NoC. The achieved reconfiguration speedup compared to the centralized control unit is up to 7.6X in certain conditions. On average, it takes only 74 clock cycles to activate a 12-hop connection.

Neural networks are increasingly being used in many applications because of their ability to solve complex problems. In order to increase the processing speed of neu-ral networks, hardware-based techniques are being actively researched in the literature. However, implementing a neural network using conventional hardware design methods is a complex and challenging task for hardware designers as there are many hyperparameters and trade-offs that need to be examined in depth. This paper presents a novel Neural-Network-on-Chip (N2OC) to provide a hardware implementation of a neural network based on network-on-chip. The proposed approach provides reconfigurability when the number of nodes per layer varies depending on the desired performance and application. The proposed method provides a flexible hardware implementation of a neural network where the number and order of nodes can be controlled. Two datasets have been used for testing the proposed method, and the proposed method has a comparable result with the state-of-the-art. The hardware design is implemented using VHDL and Altera Arria 10 GX FPGA 10AX115N2F45E1SG. Throughput and average delay of the network are studied, and the simulation result shows the design has stable performance. On a problem studied (in handwritten digits classification), the proposed method has an accuracy of 99.24% while the state-of-the-art has an accuracy of 98.17%.

Network on chip architecture provides a way to design complex integrated circuits with an objective to reduce connection issues, design productivity, and energy utilization. Network performance of a network is calculated by various factors but throughput is the most dominant characteristic for measuring network performance. So, this work includes investigation of various NoC topologies and analysis is done on basis of average throughput and average latency for ensuring network performance.

Sistemas intra-chip (SoCs – Systems-on-Chip) são o atual paradigma utilizado na implementação de sistemas embarcados. O poder computacional destas plataformas possibilita a execução simultânea de diversas aplicações com diferentes requisitos. Neste cenário, o emprego de redes intra-chip (NoCs – Networks-on-chip) como infraestrutura de comunicação é uma realidade em pesquisas acadêmicas e projetos industriais. NoCs normalmente são vistas como alternativas à comunicação via barramento, oferecendo como principais vantagens a escalabilidade e suporte a comunicações paralelas.
Muitos trabalhos têm sido conduzidos na última década na área de NoCs, tratando da capacidade e potencial que esta infraestrutura de comunicação pode garantir aos SoCs. Devido à recente introdução do paradigma de circuitos integrados 3D e 2.5D, diversas pesquisas apontam a topologia tridimensional das NoCs como uma grande solução para SoCs que necessitam de centenas de núcleos de processamento. Motivados pela escassez de NoCs de código aberto que possuem nativamente a topologia de malha tridimensional e que sejam de fácil acesso a estudantes e desenvolvedores, o projeto da NoC Arke busca oferecer uma NoC estável, que dá suporte às topologias malha bidimensional e malha tridimensional, com diversos aspectos parametrizáveis, de fácil entendimento e independente de frameworks para geração automatizada de diferentes instâncias.
A NoC Hermes foi o principal objeto de estudos em relação ao funcionamento de uma NoC e ponto de partida para a implementação da NoC Arke. Ambas NoCs possuem muitas características em comum. Durante a criação da Arke buscou-se superar o modelo no qual ela havia sido moldada. Aspectos relacionados a facilidade de utilização, legibilidade do código, independência de framework, área ocupada pelo circuito, potência dissipada e tempo de roteamento foram pontos onde a Arke mostrou-se mais eficiente.

The significant decline in the cost of genome sequencing has dramatically changed the typical bioinformatics pipeline for analysing sequencing data. Where traditionally, the computational challenge of sequencing is now secondary to genomic data analysis. Short read alignment (SRA) is a ubiquitous process within every modern bioinformatics pipeline in the field of genomics and is often regarded as the principal computational bottleneck. Many hardware and software approaches have been provided to solve the challenge of acceleration. However, previous attempts to increase throughput using many-core processing strategies have enjoyed limited success, mainly due to a dependence on global memory for each computational block. The limited scalability and high energy costs of many-core SRA implementations pose a significant constraint in maintaining acceleration. The Networks-On-Chip (NoC) hardware interconnect mechanism has advanced the scalability of many-core computing systems and, more recently, has demonstrated potential in SRA implementations by integrating multiple computational blocks such as pre-alignment filtering and sequence alignment efficiently, while minimizing memory latency and global memory access. This article provides a state of the art review on current hardware acceleration strategies for genomic data analysis, and it establishes the challenges and opportunities of utilizing NoCs as a critical building block in nextgeneration sequencing (NGS) technologies for advancing the speed of analysis.

Three-Dimensional (3-D) ICs are able to obtain significant performance benefits over two-dimensional (2-D) ICs based on the electrical
and mechanical properties resulting from the new geometrical arrangement. The arrangement of 3-D ICs also offers opportunities for new
circuit architecture based on the geometric capacity. The emerging 3-D VLSI integration and process technologies allow the new design
opportunities in 3-D Network-on-Chip (NoC). The 3-D NoC can reduce significant amount of wire length for local and global
interconnects. In this paper, we have proposed an efficient 3-D Asymmetric Torus routing algorithm for NoC. The 3-D torus has constant
node degree, recursive structure, simple communication algorithms, and good scalability. A Quadrant-XYZ dimension order routing
algorithm is proposed to build 3-D Asymmetric Torus NoC router. The algorithm partitions the geometrical space into quadrants and
selects the nearest wrap-around edge to connect the destination node. Thus, the presented algorithm guarantees minimal paths to each
destination based on routing regulations. The complexity of the algorithm is O (n). The proposed routing algorithm has been compared with
the traditional XYZ algorithm and the comparison results show that the Quadrant-XYZ router has shorter path length. This paper presents a
Register Transfer Logic (RTL) simulation model of Quadrant-XYZ dimension order routing algorithm for 3-D asymmetric torus NoC
written in Verilog. The model represents the functional behavior of the routing chip down to the flit (byte) level. The 3-D asymmetric torus
NoC has achieved a maximum operating frequency 750 MHz on Xilinx Vertex-6 programmable device.

Efficiency of Network-on-Chip (NoC) based multi-processor systems largely depends on optimal placement of tasks onto processing elements (PEs). Although number of task mapping heuristics have been proposed in literature, selecting best technique for a given environment remains a challenging problem. Keeping in view the fact that comparisons in original study of each heuristic may have been conducted using different assumptions, environment, and models. In this study, we have conducted a detailed quantitative analysis of selected dynamic task mapping heuristics under same set of assumptions, similar environment, and system models. Comparisons are conducted with varying network load, number of tasks, and network size for constantly running applications. Moreover, we propose an extension to communication-aware packing based nearest neighbor (CPNN) algorithm that attempts to reduce communication overhead among the interdependent tasks. Furthermore, we have conducted formal verification and modeling of proposed technique using high level Petri nets. The experimental results indicate that proposed mapping algorithm reduces communication cost, average hop count, and end-to-end latency as compared to CPNN especially for large mesh NoCs. Moreover, proposed scheme achieves up to 6% energy savings for smaller mesh NoCs. Further, results of formal modeling indicate that proposed model is workable and operates according to specifications.

We propose to partition links in a network-on-chip into multiple segments and use spare wires at the level of each segment to address permanent errors due to manufacturing or wear out defects. Because different segments of the spare wires address different errors from different segments, the proposed reconfigurable link structure can tolerate a larger number of errors with a reduced number of spare wires. The proposed self-repairing segmented link structure is implemented and simulated in Verilog and verified on a Virtex 5 FPGA. Experimental results on area, power consumption, delay, and reliability show that the optimal link is achieved when the link is partitioned into two segments.

In this paper, we propose a new fault-tolerant and congestion-aware adaptive routing algorithm for Networks-on-Chip (NoCs). The proposed algorithm is based on the ball and-string model and employs a distributed approach based on partitioning of the regular NoC architecture into regions controlled by local monitoring units. Each local monitoring unit runs a shortest path computation procedure to identify the best routing path so that highly congested routers and faulty links are avoided while latency is improved. To dynamically react to continuously changing traffic conditions, the shortest path computation procedure is invoked periodically. Because this procedure is based on the ball-and-string model, the hardware overhead and computational times are minimal. Experimental results based on an actual Verilog implementation demonstrate that the proposed adaptive routing algorithm improves significantly the network throughput compared to traditional XY routing and DyXY adaptive algorithms.

—In multiprocessor system-on-chip (MPSoC), a CPU can access physical resources, such as on-chip memory or I/O devices. Along with normal requests, malevolent ones, generated by malicious processes running in one or more CPUs, could occur. A protection mechanism is therefore required to prevent injection of malicious instructions or data across the system. We propose a self-contained Network-on-Chip (NoC) firewall at the network interface (NI) layer which, by checking the physical address against a set of rules, rejects untrusted CPU requests to the on-chip memory, thus protecting all legitimate processes running in a multicore SoC. To sustain high performance, we implement the firewall in hardware, with rule-checking performed at segment-level based on deny rules. Furthermore, to evaluate its impact, we develop a novel framework on top of gem5 simulation environment , coupling ARM technology and an instance of a commercial point-to-point interconnect from STMicroelectronics (STNoC). Simulation tests include scenarios in which legitimate and malicious processes, running in different CPUs, request access to shared memory. Our results indicate that a firewall implementation at the NI can have a positive effect on network performance by reducing both end-to-end network delay and power consumption. We also show that our coarse-grain firewall can prevent saturation of the on-chip network and performs better than fine-grain alternatives that perform rule checking at page-level. Simulation results are accompanied with field measurements performed on a Zedboard platform running Linux, whereas the NoC Firewall is implemented as a reconfigurable, memory-mapped device on top of AMBA AXI4 interconnect fabric.

Hierarchical  topologies  are  frequently  proposed  for  large  NetworksonChip  (NoCs). Hierarchical architectures utilize, at the upper levels, long links of the order of the die size. RC  delays of long links might reach dozens of clock cycles in advanced technology nodes, if delay reduction techniques (e.g. wire sizing and repeater insertion) are not applied. Some proposals assume  that  long  links  can  be  adjusted  to  satisfy  timing  requirements,  but  lack  a  deep evaluation  of  the  tradeoffs  and  costs.  Other  proposals  assume  that  long links  must  be pipelined, but do not provide a comprehensive justification.
In this paper we evaluate the efficiency and the system costs of wire sizing and repeater insertion  as  methods  to  reduce  link  delays  in  hierarchical  NoCs.  We  present  a  unified  interconnect cost function that accounts for power and wiring overheads of these methods. Then, we quantify the costs of modifying long links in typical hierarchical NoCs for different
target clock frequencies and technology nodes. Although long links might undergo aggressive adjustments, we find these overall costs to be low at the system level for typical cases, taking into  account  that  there  are  only  a  few  long  links  in  most  proposed  hierarchical  NoC architectures.

We formulate the problem of energy consumption and reliability oriented application mapping on regular Network-on-Chip topologies. We propose a novel branch-and-bound based algorithm to solve this problem. Reliability is estimated by an efficient Monte Carlo algorithm based on the destruction spectrum of the network. Simulation results demonstrate that reliability can be improved without sacrificing much of energy consumption.

Network-on-Chip (NoC) is a paradigm proposed to satisfy the communication demands of future Systems-on-Chip (SoC). The main components of an NoC are the network adapters, routing nodes, and network interconnect links. Reducing area and power consumption has higher priority in the case of on-chip networks compared to conventional off-chip networks. This paper presents an area efficient design for the routing node component of an NoC. T he area efficiency is obtained by applying the concept of a pipelined design as well as the use of custom IP (intellectual property) cores.

Network on chip (NoC) is an emerging communication
paradigm for integrating a large number of Intellectual Property (IP) cores on a single silicon chip. The results could benefit from adoption of NoCs is constraint by the performance limitation imposed by the communication channel. The conventional two dimensional (2-D) integrated circuit (IC) has limited scope for floor planning and therefore limits the performance improvements resulting from the NoC paradigm. Three Dimensional (3-D) ICs are able to obtain significant performance benefits over 2-D ICs based on the electrical and mechanical properties resulting from the new geometrical arrangement (topology). The arrangement of 3-D also offers opportunities for new circuit architecture based on the geometric capacity that provide greater numbers of interconnections among multi-layer active circuits. In this paper, we present the survey on performance evaluation of 3-D NoC topologies in terms of latency, throughput, wiring area overhead compared to 2-D topologies.

This paper proposes a 4-Bit full adder using FinFET at 45nm technology. The CMOS has been used widely in current technology. But scaling the CMOS will cause the short  channel  effects  such  as  DIBL, GIDL, Sub threshold  swing, channel length modulation, mobility degradation etc. To  replace  nano-scale  CMOS,  a  multi gate  device  called  FinFET  is proposed.  FinFET  has  its own  advantages  over  the  CMOS  such  as  reduction  in  leakage  power,  operating  power, leakage  current  and  transistor gate delay, reduced  threshold  level and  steeper  subthreshold  swing. The  target  of  this  paper  is  to  reduce and calculate  leakage  power  of  4-Bit  full  adder  using  FinFET.

A lot many routing algorithms have been proposed for MPSoC networks. But most of them focus only on 2D-network topologies [2].But as the demand for faster processors having high processing power over area ratio is increasing we have to now extend these algorithms for 3D-network topologies. Most recently, chips with 64 or more processors have already been developed in 2D- networks [7], [9]. To route packets among these processing elements we need a fast and efficient router. In this paper we propose a router implementing Balanced Dimension Ordered Routing (BDOR) algorithm for 3D-Mesh and 3D-Torus topologies.

A Network-on-Chips (NoCs) is rapid promising for an on-chip alternative designed in support of many-core System-on-Chips (SoCs). In spite of this, developing an increased overall performance low latency Network on chip using low area overhead has always been a new challenge. Network on Chips (NoCs) by using mesh and torus interconnection topologies have become widely used because of the easy construction. A torus structure is nearly the same as the mesh structure, however, has very slighter diameter. In this regard, we propose effective router design for Decoupled Resource sharing in a torus topology based on clustering algorithms Based Hierarchical Routing (CABHR) to get better the efficiency of NoC. We show that our approach is provides improved latency and energy consumption, overall performance developments compared to the most distinguished existing routing technique.

As the number of modules grows, performance scalability of planar topology Networks-on-Chip (NoCs) becomes limited due to increasing hop-distances, since long paths involve more routers. The growing hop-distance affects both end-to-end network latency and overall network saturation. Hierarchical topologies provide routes with shorter hop-distances and therefore are more adequate for large systems. The introduction of hierarchical NoCs poses new challenges as they should provide the shortest hop-distance for as many as possible source–destination pairs with minimal interference among packets, at the lowest hardware and system costs.

In this paper, a framework for design and dynamic management of hierarchical NoCs is introduced. The design space of hierarchical NoCs is explored under cost and performance constraints. A dynamic management scheme termed DTrD (Dynamic Traffic Distribution) is proposed. DTrD enables to dynamically adapt the routing policy in hierarchical NoCs to varying traffic conditions. Finally, a set of guidelines is formulated for proper design and dynamic control of hierarchical NoCs.

The design of more complex systems becomes an increasingly difficult task because of different issues related to latency, design reuse, throughput and cost that has to be considered while designing. In Real-time applications there are different communication needs among the cores. When NoCs (Networks on chip) are the means to interconnect the cores, use of some techniques to optimize the communication are indispensable. From the performance point of view, large buffer sizes ensure performance during different applications execution. But unfortunately, these same buffers are the main responsible for the router total power dissipation. Another aspect is that by sizing buffers for the worst case latency incurs in extra dissipation for the mean case, which is much more frequent. Reconfigurable router architecture for NOC is designed for processing elements communicate over a second communication level using direct-links between another node elements. Several possibilities to use the router as additional resources to enhance complexity of modules are presented. The reconfigurable router is evaluated in terms of area, speed and latencies. The proposed router was described in VHDL and used the ModelSim tool to simulate the code. Analyses the average power consumption, area, and frequency results to a standard cell library using the Design Compiler tool. With the reconfigurable router it was possible to reduce the congestion in the network, while at the same time reducing power dissipation and improving energy.

Traditional System-on-Chip (SoC) design employed shared buses for data transfer among various subsystems. As SoCs become more complex involving a larger number of subsystems, traditional bus-based architecture is giving way to a new paradigm for on-chip communication. This paradigm is called Network-on-Chip (NoC). A communication network of point-to-point links and routing switches is used to facilitate communication between subsystems. The routing switch proposed in this paper consists of four components, namely the input ports, output ports, switching fabric, and scheduler. The scheduler design is described in this paper. The function of the scheduler is to arbitrate between requests by data packets for use of the switching fabric. The scheduler uses an improved round robin based arbitration algorithm. Due to the symmetric structure of the scheduler, an area-efficient design is proposed by folding the scheduler onto itself, thereby reducing its area roughly by 50%.

This study proposes a new router architecture to improve the performance of dynamic allocation of virtual
channels. The proposed router is designed to reduce the hardware complexity and to improve power and
area consumption, simultaneously. In the new structure of the proposed router, all of the controlling
components have been implemented sequentially inside the allocator router modules. This optimizes
communications between the controlling components and eliminates the most of hardware overloads of
modular communications. Eliminating additional communications also reduces the hardware complexity.
In order to show the validity of the proposed design in real hardware resources, the proposed router has
been implemented onto a Field-Programmable Gate Array (FPGA). Since the implementation of a
Network-on-Chip (NoC) requires certain amount of area on the chip, the suggested approach is also able
to reduce the demand of hardware resources. In this method, the internal memory of the FPGA is used for
implementing control units. This memory is faster and can be used with specific patterns. The use of the
FPGA memory saves the hardware resources and allows the implementation of NoC based FPGA.

As the number of applications and programmable units in CMPs and MPSoCs increases, the Network-on-Chip (NoC) encounters diverse and time dependent traffic loads. This trend motivates the introduction of NoC load-balanced, adaptive routing mechanisms that achieve higher throughput as compared with traditional oblivious routing schemes that are perceived better suited for hardware implementations. However, an efficient adaptive routing scheme should base its decisions on the global state of the system rather than on local or regional congestion signals as is common in current adaptive routing schemes. In this paper we introduce a novel paradigm of NoC centralized adaptive routing, and a specific design for mesh topology. Our scheme continuously monitors the global traffic load in the network and modifies the routing of packets to improve load balancing accordingly. In our specific mesh-based design, XY or YX routes are adaptively selected for each source-destination pair. We show that while our implementation is scalable and lightweight in hardware costs, it outperforms distributed adaptive routing schemes in terms of load balancing and throughput.

We propose a novel cost-effective long-range NoC interconnect design based on current-mode signaling. The proposed CMOS based long-range link reduces the communication delay of long wires significantly without using traditional pipelined repeaters, making it a cost efficient alternative to wireless and optical interconnects. Spice simulations are performed to verify the performance of the proposed current-mode transceiver. The performance of the proposed interconnect is analyzed and compared with wireless, optical and existing CMOS based interconnects. Also a modified NoC simulator is utilized to demonstrate the benefit of current-mode long-range links.