Hardware Acceleration

Modern radio telescopes like the Square Kilometer Array (SKA) will need to process in real-time exabytes of radio-astronomical signals to construct a high-resolution map of the sky. Near-Memory Computing (NMC) could alleviate the performance bottlenecks due to frequent memory accesses in a state-of-the-art radio-astronomy imaging algorithm. In this paper, we show that a sub-module performing a two-dimensional fast Fourier transform (2D FFT) is memory bound using CPI breakdown analysis on IBM Power9. Then, we present an NMC approach on FPGA for 2D FFT that outperforms a CPU by up to a factor of 120x and performs comparably to a high-end GPU, while using less bandwidth and memory.

Abstract-Simulating spatiotemporal neurons is fundamental to understanding motion detection mechanisms in the primary visual cortex and cloning these mechanisms in digital systems. We present a hardware accelerator that leverages the parallelism of a modern Field Programmable Gate Array (FPGA) to increase the speed of spatiotemporal computations by 1∼2 orders of magnitude for video framebuffer sizes up to 128×128×25 pixels. The accelerator is primarily intended for running simulations of large spatiotemporal neuron populations but can also be used in computer vision applications that require high-speed spatiotemporal processing such as realtime motion detection.

This thesis was prepared at DTU Compute in fulfilment of the requirements for acquiring an M.Sc. in Engineering.

The goal of the thesis is the implementation of a hardware accelerator on FPGA technology for a specific financial application, targeted at the Series 7 Xilinx devices.

By employing FPGA-based hardware acceleration, specific compute-intensive tasks that normally run on the CPU are offloaded to the accelerator, which implements the same algorithm and would obtain the same results, while utilizing a fraction of the time and power required for this processing on general purpose CPUs.

In implementing the aforementioned acceleration, the setup is based around a CPU-FPGA communication via a PCIe bus, thus seamlessly integrating this technology with existing applications, while making the necessary changes to the software side of the algorithm. We will extend on previous work in the field by targeting the implementation on newer generation devices and we will compare the results.

The thesis work was carried out in collaboration with DTU (Technical University of Denmark), under the supervision of Alberto Nannarelli.

A new approach to analyze injection locking mode of oscillators under small external excitation is proposed. The proposed approach exploits existence conditions of the solution of HB linear system with degenerate matrix. The method allows one to obtain the locking range for an arbitrary oscillator circuit with an arbitrary periodic injection waveform. The approach can be easily implemented into a circuit simulator. Examples are given to confirm the correctness of the new approach.

This paper proposes a parallel hardware architecture for real-time image classification based on Scale Invariant Feature Transform (SIFT), Bag of Features (BoF) and Support Vector Machine (SVM) algorithms. The proposed architecture exploits different forms of parallelism in these algorithms in order to accelerate their execution to achieve real-time performance. Different techniques have been used to parallelize the execution and reduce the hardware resource utilization of the computationally intensive steps in these algorithms. The architecture takes a 640×480 pixel image as an input and classifies it based on its content within 33ms. A prototype of the proposed architecture is implemented on an FPGA platform and evaluated using two benchmark datasets, namely; Caltech-256 and the Belgium Traffic Sign datasets. The architecture is able to detect up to 1270 SIFT features per frame with an increment of 380 extra features from the best recent implementation. We were able to speed up the feature extraction algorithm when compared to an equivalent software implementation by ×54 and for classification algorithm by ×6, while maintaining the difference in classification accuracy within 3%. The hardware resources utilized by our architecture were also less than those used by other existing solutions.

Modern radio telescopes like the Square Kilometer Array (SKA) will need to process in real-time exabytes of radio-astronomical signals to construct a high-resolution map of the sky. Near-Memory Computing (NMC) could alleviate the performance bottlenecks due to frequent memory accesses in a state-of-the-art radio-astronomy imaging algorithm. In this paper, we show that a sub-module performing a two-dimensional fast Fourier transform (2D FFT) is memory bound using CPI breakdown analysis on IBM Power9. Then, we present an NMC approach on FPGA for 2D FFT that outperforms a CPU by up to a factor of 120x and performs comparably to a high-end GPU, while using less bandwidth and memory.

In India nearly thousands of people die every year due to pesticide poisoning. Toxic pesticides like chlorpyrifos, ethion, acetamiprid are used without knowing the side effects. Detection of the pesticides using image processing can bring a solution. In order to detect the pesticide residue, three Convolutional Neural Network (CNN) is developed by training the crop leaf image dataset. The Convolutional Neural Network are Basic Convolutional Neural Network, Frozen Convolutional Neural Network and Fine Tuned Convolutional Neural Network. To make this analysis possible, Graphical processing Unit (GPU) is used to run the image processing algorithm. Three Graphical Processing Units are used to understand the accuracy, time taken and to compare their benchmarks.

The significant decline in the cost of genome sequencing has dramatically changed the typical bioinformatics pipeline for analysing sequencing data. Where traditionally, the computational challenge of sequencing is now secondary to genomic data analysis. Short read alignment (SRA) is a ubiquitous process within every modern bioinformatics pipeline in the field of genomics and is often regarded as the principal computational bottleneck. Many hardware and software approaches have been provided to solve the challenge of acceleration. However, previous attempts to increase throughput using many-core processing strategies have enjoyed limited success, mainly due to a dependence on global memory for each computational block. The limited scalability and high energy costs of many-core SRA implementations pose a significant constraint in maintaining acceleration. The Networks-On-Chip (NoC) hardware interconnect mechanism has advanced the scalability of many-core computing systems and, more recently, has demonstrated potential in SRA implementations by integrating multiple computational blocks such as pre-alignment filtering and sequence alignment efficiently, while minimizing memory latency and global memory access. This article provides a state of the art review on current hardware acceleration strategies for genomic data analysis, and it establishes the challenges and opportunities of utilizing NoCs as a critical building block in nextgeneration sequencing (NGS) technologies for advancing the speed of analysis.

Coarse-grained reconfigurable array (CGRA) is a promising solution that can accelerate even non-parallel loops. Acceleration achieved through CGRAs critically depends on the goodness of mapping (of loop operations onto the PEs of CGRA), and in particular, the com-piler's ability to route the dependencies among operations. Previous works have explored several mechanisms to route data dependencies , including, routing through other PEs, registers, memory, and even re-computation. All these routing options change the graph to be mapped onto PEs (often by adding new operations), and without rescheduling , it may be impossible to map the new graph. However , existing techniques explore these routing options inside the Place and Route (P&R) phase of the compilation process, which is performed after the scheduling step. As a result, they either may not achieve the mapping or obtain poor results. Our method RAMP, explicitly and intelligently explores the various routing options, before the scheduling step, and makes improve the mapping-ability and mapping quality. Evaluating top performance-critical loops of MiBench benchmarks over 12 architectural configurations, we find that RAMP is able to accelerate loops by 23× over sequential execution , achieving a geomean speedup of 2.13× over state-of-the-art.

Do formal verification tools and methodologies require a drastic overhaul to move beyond equivalence checking? Equivalence checking catches errors in synthesis and local hand-modifications to designs. However, powerful formal verification technologies are emerging to combat" behavioral" errors, which represent today's biggest verification problems. Nonetheless, formal verification experts are split on how formal tools should adapt to this challenge. Some of our panelists feel that designers can sufficiently benefit from ...

The most pervasive compute operation carried out in almost all bioinformatics applications is pairwise sequence homology detection (or sequence alignment). Due to exponentially growing sequence databases, computing this operation at a large-scale is becoming expensive. An effective approach to speed up this operation is to integrate a very high number of processing elements in a single chip so that the massive scales of fine-grain parallelism inherent in several bioinformatics applications can be exploited efficiently. Network-on-chip (NoC) is a very efficient method to achieve such large-scale integration. In this work, we propose to bridge the gap between data generation and processing in bioinformatics applications by designing NoC architectures for the sequence alignment operation. Specifically, we 1) propose optimized NoC architectures for different sequence alignment algorithms that were originally designed for distributed memory parallel computers and 2) provide a thorough comparative evaluation of their respective performance and energy dissipation. While accelerators using other hardware architectures such as FPGA, general purpose graphics processing unit (GPU), and the cell broadband engine (CBE) have been previously designed for sequence alignment, the NoC paradigm enables integration of a much larger number of processing elements on a single chip and also offers a higher degree of flexibility in placing them along the die to suit the underlying algorithm. The results show that our NoC-based implementations can provide above 102-103-fold speedup over other hardware accelerators and above 104-fold speedup over traditional CPU architectures. This is significant because it will drastically reduce the time required to perform the millions of alignment operations that are typical in large-scale bioinformatics projects. To the best of our knowledge, this work embodies the first attempt to accelerate a bioinformatics application - using NoC.

Do formal verification tools and methodologies require a drastic overhaul to move beyond equivalence checking? Equivalence checking catches errors in synthesis and local hand-modifications to designs. However, powerful formal verification technologies are emerging to combat" behavioral" errors, which represent today's biggest verification problems. Nonetheless, formal verification experts are split on how formal tools should adapt to this challenge. Some of our panelists feel that designers can sufficiently benefit from ...

Several Elliptic Curve Processors (ECP) have been proposed in the literature associated with various architectures using different and sometimes confusing terminologies. This paper is a short review study of ECP architectures, considering the hardware platforms used for their implementations. The main design parameters of the ECP architectures, including the field choice and scalar multiplication algorithms were identified. Based on these parameters, a statistical study is conducted on a large collection of the published work. From the analysis of the collected data, several conclusions were deduced, such as the notion that binary field is easier to be implemented in hardware than prime field as well as the polynomial basis is dominant over other bases representation. Another significant conclusion is that Montgomery scalar multiplier has been used more than Lopez-Dahab, Binary, and NAF methods, particularly with the dominance of Lopez-dahab Projective coordinate.

— This paper gives an overview of low-power techniques proposed in the literature for mobile multimedia and Internet appli-cations. Exploitable aspects are discussed in the behavior of differ-ent video compression tools. These power-efficient solutions are then classified ...

Assisted by recent advances in programmable graphics hardware, fast rasterization-based techniques have made significant progress in photorealistic rendering, but still only render a subset of the effects possible with ray tracing. We are closing this gap ...

Matrix Algebra and Deep Neural Networks represent foundational classes of computational algorithms across multiple emerging applications like Augmented Reality(AR) or Virtual Reality(VR), autonomous navigation (cars, drones, robots), data science, and various artificial intelligence-driven solutions. An accelerator-based architecture can provide performance and energy efficiency supporting fixed functions through customized data paths. However, constrained Edge systems requiring multiple applications and diverse matrix operations to be efficiently supported, cannot afford numerous custom accelerators. In this paper, we present MxCore, a unified architecture that comprises tightly coupled vector and programmable cores sharing data through highly optimized interconnects along with a configurable hardware scheduler managing the co-execution. We submit MxCore as the generalized approach to facilitate the flexible acceleration of multiple Matrix Algebra and Deep-learning applications acr...

In this paper we present a novel real-time cartoon-style rendering approach, which targets very large meshes. Cartoon drawing usually uses a limited number of colors for shading and emphasizes special effects, such as sharp curvature and silhouettes. It also paints the remaining large regions with uniform solid colors. Our approach quantizes light intensity to generate different shadow colors and utilizes multiresolution mesh hierarchy to maintain appropriate levels of detail across various regions of the mesh. To comply with visual requirements, our algorithm exploits graphics hardware programmability to draw smooth silhouette and color boundaries within the vertex and fragment processors. We have adopted a simplification scheme that executes simplification operators without incurring extra simplification operations as a precondition. The real-time refinement of the mesh, which is performed by the graphics processing unit (GPU), dramatically improves image quality and reduces CPU load.

Norm Optimal Iterative Learning Control (NOILC) is state of the art control strategy that  is  being  used  in  Gantry robot  and  rehabilitation  robotics.  However  due  to  the  memory requirement for storing trial data and matrix manipulations, the fore mentioned applications use
desktop  PC which  is not  an  efficient  solution  in  terms  of  area,  power,  cost  and  mobility. This  thesis  concerns  the  use  of  FPGA as  an  implementation  platform  for  NOILC.  In  this  regard floating  point  norm  optimal  iterative  learning  controller for  Gantry robot  is developed
and  synthesized  on  Vertex  5  Xc5vlx110T  FPGA  chip.  The comparison  with  general  purpose  processor  based  implementation
shows  that  the  proposed  FPGA  implementation  reduces  the
execution time from 830ms to 1.47ms.

Coarse-grained reconfigurable array (CGRA) is a promising solution to accelerate loops featuring loop-carried dependencies or low trip-counts. One challenge in compiling for CGRAs is to efficiently manage both recurring (repeatedly written and read) and nonrecurring (read-only) variables of loops. Although prior works manage recurring variables in rotating register file (RF), they access the nonrecurring variables through the on-chip memory. It increases memory accesses and degrades the performance. Alternatively, both the variables can be managed in separate rotating and nonrotating RFs. But, it increases code size and effective utilization of the registers becomes challenging. Instead, this paper proposes URECA, a compiler solution to manage the variables in a single nonrotating RF. During mapping loop operations on CGRA, the compiler allocates necessary registers and splits RF in rotating and nonrotating parts. It also pre-loads read-only values in the unified RF, which are then directly accessed at run-time. Evaluating compute-intensive benchmarks from MiBench show that URECA provides a geomean speedup of 11.41x over sequential loop execution. It improves the loop acceleration through CGRAs by 1.74x at 32% reduced energy consumption over state-of-the-art.

Several many-cores tackle scalability issues by leveraging tightly-coupled clusters as building blocks, where low-latency, high-bandwidth interconnection between a small or medium number of processors and L1 memory achieves high performance/watt. Tight coupling of hardware accelerators into these multicore clusters constitutes a promising approach to further improve performance/area/watt. However, accelerators are often clocked at a lower frequency than processors clusters for energy efficiency reasons. In this paper, we pro- pose a technique to integrate shared-memory accelerators within the tightly-coupled clusters of the STMicroelectronics STHORM architecture. Our methodology permits to significantly relax timing constraints for tightly-coupled accelerators, while at the same optimizing data bandwidth. In addition, our technique allows to operate the accelerator at an integer submultiple of the cluster frequency. Experimental results show that the proposed approach allows to recover up to ~84% of the slow-down implied by reduced accelerator speed.

Overlay architectures implemented on FPGA devices have been proposed as a means to increase FPGA adoption in general-purpose computing. They provide the benefits of software such as flexibility and programmability, thus making it easier to build dedicated compilers. However, existing overlays are generic, resource and power hungry with performance usually an order of magnitude lower than bare metal implementations. As a result, FPGA overlays have been confined to research and some niche applications. In this paper, we introduce Application-Specific FPGA Overlays (AS-Overlays), which can provide bare-metal performance to FPGA overlays, thus opening doors for broader adoption. Our approach is based on the automatic extraction of hardware kernels from data flow applications. Extracted kernels are then leveraged for application-specific generation of hardware accelerators. Reconfiguration of the overlay is done with RapidWright which allows to bypass the HDL design flow. Through prototy...

Do formal verification tools and methodologies require a drastic overhaul to move beyond equivalence checking? Equivalence checking catches errors in synthesis and local hand-modifications to designs. However, powerful formal verification technologies are emerging to combat" behavioral" errors, which represent today's biggest verification problems. Nonetheless, formal verification experts are split on how formal tools should adapt to this challenge. Some of our panelists feel that designers can sufficiently benefit from ...

In this paper we present a novel real-time cartoon-style rendering approach, which targets very large meshes. Cartoon drawing usually uses a limited number of colors for shading and emphasizes special effects, such as sharp curvature and silhouettes. It also paints the remaining large regions with uniform solid colors. Our approach quantizes light intensity to generate different shadow colors and utilizes multiresolution mesh hierarchy to maintain appropriate levels of detail across various regions of the mesh. To comply with visual requirements, our algorithm exploits graphics hardware programmability to draw smooth silhouette and color boundaries within the vertex and fragment processors. We have adopted a simplification scheme that executes simplification operators without incurring extra simplification operations as a precondition. The real-time refinement of the mesh, which is performed by the graphics processing unit (GPU), dramatically improves image quality and reduces CPU load.