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This paper proposes a 4-Bit full adder using FinFET at 45nm technology. The CMOS has been used widely in current technology. But scaling the CMOS will cause the short channel effects such as DIBL, GIDL, Sub threshold swing, channel length modulation, mobility degradation etc. To replace nano-scale CMOS, a multi gate device called FinFET is proposed. FinFET has its own advantages over the CMOS such as reduction in leakage power, operating power, leakage current and transistor gate delay, reduced threshold level and steeper subthreshold swing. The target of this paper is to reduce and calculate leakage power of 4-Bit full adder using FinFET.
Indian Journal of Science and Technology, 2018
Objectives: To reduce the leakage power dissipation and minimize the propagation delay, a Fin FET based 8-bit adder architecture is constructed. The performance metrics of these structures are calculated over a range of temperatures and are compared with the MOSFET based 8-bit adder architecture. Various logic styles are utilized for constructing the adder. Method/Analysis: A Ripple carry adder structure is employed. The existing adder architecture is constructed using 90nm MOSFET technology. The proposed adder architecture is constructed using 32nm FINFET technology. The various logic styles employed are Complementary Metal-Oxide Semiconductor logic (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission Gate logic (TG) and Gate Diffusion Input logic (GDI). Cadence Virtuoso is used for designing purpose and simulation is performed using Spectre. Findings: Key performance metrics like static power, dynamic power, leakage power, delay and power delay product are calculated. The dynamic power of MOSFET architecture ranges from 7.42μW to 882.6μW. The dynamic power of FINFET architecture ranges from 0.407nW to 156.2nW. The static power (inputs at high logic level) of MOSFET architecture ranges from 0.001μW to 945.76μW. The static power (inputs at high logic level) of Fin FET architecture ranges from 0.725pW to 170.4nW. The static power (inputs at low logic level) of MOSFET architecture ranges from 0.94nW to 1.68mW. The static power (inputs at low logic level) of Fin FET architecture ranges from 0.127pW to 305.3nW. The leakage power (inputs at high logic level) of MOSFET architecture ranges from 1.27nW to 134.7μW. The leakage power (inputs at high logic level) of Fin FET architecture ranges from 0.36pW to 24.77nW. The leakage power (inputs at low logic level) of MOSFET architecture ranges from 0.54nW to 139.9μW. The leakage power (inputs at low logic level) of Fin FET architecture ranges from 0.15nW to 227.6nW. The delay of MOSFET architecture ranges from 0.344μs to 0.46μs. The delay of Fin FET architecture ranges from 0.19μs to 0.28μs. The power delay product of MOSFET architecture ranges from 2.66 to 405.99. The power delay product of Fin FET architecture ranges from 0.83 to 29.67. Novelty/Improvements: The FINFET adder architecture proved to be effective in reducing the propagation delay and leakage power dissipation. This may find usage in high performance devices like microchips and supercomputers.
This paper proposes a 4-Bit Arithmetic logic unit (ALU) using FinFET at 32nm technology. The CMOS has been used widely in current technology. But scaling the CMOS will cause the short channel effects such as DIBL, GIDL, Sub threshold swing, channel length modulation, mobility degradation etc. To change nanoscale CMOS, a multi gate device called FinFET is suggested. FinFET has its own advantages over the CMOS such as reduction in leakage power, operating power, leakage current and transistor gate delay, reduced threshold level and steeper subthreshold swing. The target of this paper is to reduce and calculate leakage power of 4-Bit ALU using FinFET.
Paper discussed the comparative analysis ofdifferent full adder cells with two logic styles.The logic styles used for implementation of FinFET based 1-bit full adder are Complementary MOS (CMOS) and Transmission Gate (TG). The simulations of full adders have being done at 10nm, 20nm and 32nm technology node. PTM models for multi-gate transistors (PTM-MG) low power are used for simulations. This model is based on BSIM-CMG, a dedicated model for multi-gate devices. Investigation of performance and energy efficiency ofall types of full adder cell designs has been done. The performance metrics that were measured, analyzed and compared are average power, leakage power, delay, and energy. It is observed that less power is consumed in Transmission Gate (TG) based full adderthan the Convention full adder in 10nm technology node.
Electronic System Design …, 2010
This paper investigates a robust 1-bit static full adder using FinFET at near-threshold region (NTR), a design space where the supply voltage is approximately equal to the threshold voltage of the transistors. This region provides minimum-energy point for the different frequency of operation with more favorable performance and variability characteristics. The proposed design features higher computing speed (by 4.49.×) and lower energy (by 3.90.× ) at the expense of 1.13.× higher power dissipation. The proposed design also offers 1.38× improvements in power variability, 2.19× improvements in delay variability and 2.41× improvement in power delay product (PDP) variability against process, voltage, and temperature (PVT) variations. The power, speed and energy evaluation has been carried out using extensive simulation on HSPICE circuit simulator. The simulation results are based on 32nm Berkeley Predictive Technology Model (BPTM).
IEEE International Conference SESC 2013 organized by MNNIT Allahabad, INDIA, 2013
An overview of performance analysis and compression between various parameters of a low power high speed conventional 1-bit full adder has been presented here. The work elucidated here gives a quantitative comparison of the adder cell performance. This paper shows the advancement over active power, leakage current and delay. The comparative study based on a new logic approach, which reduces power consumption. With power supply of 0.7V, we have achieved reduction in active power consumption of 98.28nW and propagation delay of 0.737ns, which makes this circuit highly energy efficient. In this circuit we have reduced leakage current of 135.9nA. The designs have been carried out by virtuoso tool of cadence at 45nm technology.
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