CoProcessors

Simulation of quantum computers using classical computers is a hard problem with high memory and computational requirements. Parallelization can alleviate this problem, allowing the simulation of more qubits at the same time or the same number of qubits to be simulated in less time. A promising approach is to exploit the high performance computing capabilities provided by the latest graphical processing units. In this paper we present a parallel implementation of the QC-lib quantum computer simulator on the GPU using the CUDA programming model. The proposed scheme for partitioning the terms that describe the state of a quantum register takes advantage of the specific characteristics of the CUDA memory spaces and allows for an efficient parallelization of the general singe qubit operator. Experimental results indicate that very good speed-ups can be obtained in contrast with the sequential implementation.

This paper presents the design of a FPGA-based hardware co-processor, based on the SPHINX 3 speech recognition engine from CMU; capable of performing Acoustic Modeling (AM) for medium sized vocabularies in real-time. By creating an input-driven pipeline for performing the ...

This paper presents a 3D graphics engine which is specifically designed to minimize the hardware cost while providing sufficient computing capability for consumer electronics with small to medium screen sizes (up to 800times600) such as digital television. The presented 3D engine consists of a fixed full 3D graphics pipeline for both geometry and rendering operation. This engine provides a standard AHB interface that makes it easily to be integrated into an AMBA-based SoC. The development of the 3D engine has gone through a rigorous design process: starting from system modeling (using System-C), RTL implementation, hardware/software co-simulation and FPGA verification to test chip fabrication. This 3D engine provides 3.3 M vertices/s and 278 Mpixels/s in maximum performance at 139 MHz using 0.18 silicon technology with 987 K gates that is sufficient for most applications for digital television. At the same time, a complete OpenGL-ES 1.1 API, windowing system, Linux operating system, device driver and a 3D performance monitoring tool have been developed for our 3D engine. This performance monitoring tool provides run-time performance information include frame rate, triangle rate, pixel rate, involved OpenGL function list, function counts, memory utilization and etc. Moreover, a built-in real-time AHB bus tracer is also provided to monitor the bus activities of the 3D engine and other components on the system bus. The bus tracer captures on-chip bus signals at ether cycle accurate or transaction levels and applies real-time compression to both levels of signals. With the performance monitoring tool and the bus tracer, the 3D application developer can easily analyze the communication of the components and fine tune the 3D application to optimize the entire SoC system performance and to satisfy performance/cost constrains on consumer electronics. Both of the hardware and software have been carefully verified and demonstrated on FPGA using ARM versatile SoC develop board- .

Abstract—Spiking neural network (NN) architecture that uses Hebbian learning and reinforcement-learning schemes for adapting the synaptic weights is implemented in silicon and performs dynamic optimization according to hemodynamic sensor for a cardiac resynchronization therapy (CRT) device. The spiking NN architecture dynamically changes the atrioventricular (AV) delay and interventricular (VV) interval parameters according to the information provided by the intracardiac electrograms (IEGMs) and hemodynamic sensors. The spiking NN coprocessor performs the adaptive part and is controlled by a deterministic algorithm master controller. The simulated cardiac output obtained with the adaptive CRT device is 30 % higher than with a nonadaptive CRT device and is likely to provide improvement in the quality of life for patients with congestive heart failure. The spiking NN architecture shows synaptic plasticity acquired during the learning process. The synaptic plasticity is manifested by a...

Random numbers are used in a wide variety of applications from simulation and encryption to gambling and clinical trials. A good quality random number generator is an asset for applications like encryption, randomized designs and network and information security. Various mathematical models have been developed in the past to improve the quality of random numbers. It can be construed that in general to obtain random numbers of excellent quality, a complex mathematical model has to be used which can be a performance bottleneck. In this work, we propose a novel technique to implement a True Random Number Generator (TRNG) using sources of uncertainty found within Graphics Processing Units (GPUs) together with histogram equalization to obtain maximum entropy. We evaluate the random numbers generated by our approach using four tests. First, we measure the correlation values between two sequences of random numbers, second, we measure the entropy values, third, we use watermarking, an application used in network security and finally we use Monte Carlo analysis for pi-value calculation. Based on these quality measurements, our method has achieved better results than popular random number generators compared in this work. Furthermore, this approach is a massively scalable solution ideal for high performance computing implementations.

Although some interesting routing algorithms based on HNN were already proposed, they are slower when compared to other routing algorithms. Since HNN are inherently parallel, they are suitable for parallel implementations, such as Graphic Processing Units (GPU). In this paper we propose a fast routing algorithm based on Hopfield Neural Networks (HNN) for GPU, considering some implementation issues. We analyzed the memory bottlenecks, the complexity of the HNN and how the kernel functions should be implemented. We performed simulations for five different variations of the routing algorithm for two communication network topologies. We achieved speed-ups up to 55 when compared to the simplest version implemented in GPU and up to 40 when compared to the CPU version. These new results suggest that it is possible to use the HNN for routing in real networks.