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WO2024183408A1 - 桥接芯片、芯片封装结构及制作方法、电子设备 - Google Patents

桥接芯片、芯片封装结构及制作方法、电子设备 Download PDF

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Publication number
WO2024183408A1
WO2024183408A1 PCT/CN2023/140243 CN2023140243W WO2024183408A1 WO 2024183408 A1 WO2024183408 A1 WO 2024183408A1 CN 2023140243 W CN2023140243 W CN 2023140243W WO 2024183408 A1 WO2024183408 A1 WO 2024183408A1
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WO
WIPO (PCT)
Prior art keywords
chip
substrate
metal wiring
bridge
wiring layer
Prior art date
Application number
PCT/CN2023/140243
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English (en)
French (fr)
Inventor
张童龙
刘思言
吴声豪
李珩
罗威
Original Assignee
华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2024183408A1 publication Critical patent/WO2024183408A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to a bridge chip, a chip packaging structure and a manufacturing method, and an electronic device.
  • 2.5D/3D packaging technology uses multi-chip (chiplets) to package multiple chips (die) together, which has the advantages of small package size, low power consumption, and fewer pins.
  • a bridge chip BRG (bridge die; also called bridge grain) needs to be used as an interconnection structure between different chips to meet the interconnection communication between chips.
  • the existing bridge chip BRG is made of silicon (Si) base. Since the thermal expansion coefficient (CTE) of silicon itself is small, and the thermal expansion coefficient of the packaging structure around the bridge chip BRG is large, it will cause the bridge chip BRG and the chip to generate a large stress due to thermal mismatch, which will cause the interconnection structure between the bridge chip BRG and the chip to crack.
  • the present application provides a bridge chip, a chip packaging structure and a manufacturing method, and an electronic device, which can improve the overall thermal expansion coefficient of the bridge chip.
  • the present application provides a bridge chip, the bridge chip includes a first mold layer, a metal wiring layer, and at least two chip connection areas.
  • a plurality of TMVs are arranged in the first mold layer, the metal wiring layer is arranged on the first mold layer, and the metal wiring layer is electrically connected to the plurality of TMVs.
  • At least two chip connection areas are located on a side of the metal wiring layer away from the first mold layer, each chip connection area is provided with a plurality of first metal connection structures, and the plurality of first metal connection structures are electrically connected to the metal wiring layer.
  • an organic composite structure is formed by setting a molding layer (first molding layer) at the bottom.
  • the thermal expansion coefficient of the molding material used in the molding layer is larger, thereby increasing the overall thermal expansion coefficient of the bridge chip.
  • the first molding layer includes at least one of resin and polyimide.
  • the bridge chip further includes a substrate, which is located between the metal wiring layer and the first molding layer.
  • a second metal connection structure is disposed in the substrate, and the metal wiring layer is electrically connected to the molding through-hole through the second metal connection structure.
  • the bridge chip of the prior art needs to use a thick substrate to meet the support requirements, such as thick silicon of more than 60 ⁇ m, so it is necessary to set a deep through silicon via (TSV) on the thick silicon to meet the connection requirements.
  • TSV deep through silicon via
  • the first molding layer set in the bridge chip of the present application can play a supporting role, so that a thin substrate (such as thin silicon of about 20 ⁇ m) can meet the requirements; in this way, a TSV with a smaller depth combined with a TMV can meet the connection requirements. It is understandable that the production cost of TSV and TMV with a smaller depth is much lower than that of TSV with a larger depth, thereby reducing the cost of the bridge chip.
  • the substrate includes one or more of silicon, glass, silicon nitride, and ceramics.
  • a deep trench capacitor is disposed on a surface of the substrate near the metal wiring layer, and the deep trench capacitor is electrically connected to the metal wiring layer.
  • the deep trench capacitor can rectify the transmission signal, thereby improving the stability of the transmission signal.
  • the present application also provides a chip packaging structure, which includes a substrate, a first chip, a second chip, and a bridge chip provided in any of the above possible implementation methods.
  • the bridge chip is electrically connected to the substrate through a plurality of TMVs.
  • the first chip and the second chip are located on a side of the bridge chip away from the substrate, and the first chip and the second chip are electrically connected to the first metal connection structure in the two chip connection areas, respectively.
  • the present application also provides a method for manufacturing a bridge chip, the method comprising: providing a substrate; wherein the substrate comprises a metal connection structure; manufacturing a metal wiring layer on a first surface of the substrate; wherein the metal wiring layer is electrically connected to the metal connection structure; manufacturing a first molding layer on a second surface of the substrate, forming a plurality of molding through holes TMV in the first molding layer, and the plurality of TMVs are connected to the metal wiring layer through the metal connection structure; The line layer is electrically connected.
  • the present application also provides a method for manufacturing a bridge chip, the method comprising: manufacturing a metal wiring layer, manufacturing a first molding layer on the metal wiring layer, forming a plurality of molding through holes TMV in the first molding layer, and the plurality of TMV are electrically connected to the metal wiring layer.
  • the present application also provides a method for manufacturing a chip packaging structure, the manufacturing method comprising: providing a carrier, a first chip, and a second chip, and placing the first chip and the second chip on the carrier with their active surfaces facing upward.
  • the present application also provides an electronic device, which includes a circuit board and the chip packaging structure as described above; the chip packaging structure is electrically connected to the circuit board.
  • FIG1 is a schematic diagram of a packaging structure provided in the prior art
  • FIG2 is a schematic diagram of the structure of a bridge chip provided in an embodiment of the present application.
  • FIG3 is a flow chart of a method for manufacturing a bridge chip provided in an embodiment of the present application.
  • FIG4 is a schematic diagram of a manufacturing process of a bridge chip provided in an embodiment of the present application.
  • FIG5 is a schematic diagram of the structure of a bridge chip provided in an embodiment of the present application.
  • FIG6 is a flow chart of a method for manufacturing a bridge chip provided in an embodiment of the present application.
  • FIG7 is a schematic diagram of a manufacturing process of a bridge chip provided in an embodiment of the present application.
  • FIG8 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application.
  • FIG9 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application.
  • FIG10 is a flow chart of a method for manufacturing a chip packaging structure provided in an embodiment of the present application.
  • FIG. 11 is a schematic diagram of a manufacturing process of a chip packaging structure provided in an embodiment of the present application.
  • the embodiment of the present application provides an electronic device, which includes a printed circuit board (PCB; also called a printed circuit board) and a chip packaging structure arranged on the circuit board.
  • the chip packaging structure adopts a new bridge chip (bridge die) and at least two chips (die), and two different chips (die) are electrically connected through the new bridge chip, that is, the two different chips are interconnected and communicated through the new bridge chip.
  • the new bridge chip adopts a composite structure of a high-density interconnection layer and an organic layer, which can improve the overall thermal expansion coefficient (CTE) of the bridge chip and reduce the stress caused by thermal mismatch between the bridge chip and the surrounding packaging structure, thereby reducing the probability of cracking of the interconnection structure between the bridge chip and the interconnection chip, thereby improving the reliability of the chip packaging structure.
  • CTE thermal expansion coefficient
  • the electronic device may be a mobile phone, a tablet computer, a notebook, a car computer, a smart watch, a smart bracelet, a server, or other electronic products or components.
  • the first embodiment provides a bridge chip BRG, which includes a substrate 10, a metal wiring layer 20, and a first mold layer 30.
  • the metal wiring layer 20 and the first mold layer 30 are respectively arranged on two opposite surfaces of the substrate 10. Schematically, the metal wiring layer 20 can be arranged on the upper surface of the substrate 10, and the first mold layer 30 is arranged on the lower surface of the substrate 10.
  • a plurality of through molding vias TMV are provided in the first molding layer 30 , that is, a plurality of through holes are opened in the first molding layer 30 , and the through holes are filled with metal material, thereby forming the molding through holes TMV.
  • the material forming the first mold layer 30 may include a thermosetting material, such as epoxy, polyimide (PI), etc., but is not limited thereto.
  • a thermosetting material such as epoxy, polyimide (PI), etc., but is not limited thereto.
  • the filling material in the molded through hole TMV may include one or more metal materials such as copper, aluminum, gold, silver, etc., and the present application does not impose any limitation on this. In practice, suitable materials may be selected as needed.
  • the substrate 10 is provided with a metal connection structure (also referred to as a second metal connection structure, not shown in FIG. 2 ), and the molded through hole TMV is electrically connected to the metal wiring layer 20 through the metal connection structure in the substrate 10.
  • the metal connection structure in the substrate 10 may include a metal connection line, a metal via (such as a through silicon via), etc., and the present application does not limit this, and it can be set as needed in practice.
  • the present application does not limit the material used for the substrate 10.
  • the material of the substrate 10 can be one or more of silicon, glass, silicon nitride, ceramics, and the like.
  • the substrate 10 may be a silicon substrate, and the metal connection structure provided on the silicon substrate may be a through silicon via (TSV).
  • TSV through silicon via
  • the through molded via TMV provided in the first mold layer 30 is electrically connected to the metal wiring layer 20 through the through silicon via (TSV) on the silicon substrate.
  • the metal wiring layer 20 may be a redistribution layer (RDL) manufactured by a back end of line (BEOL) process in a semiconductor manufacturing process.
  • RDL redistribution layer
  • BEOL back end of line
  • the main body material of the bridge chip is silicon, and the thermal expansion coefficient of silicon (2.6 ppm/° C.) is relatively small, so that a large stress is generated between the bridge chip and the surrounding packaging structure due to thermal mismatch.
  • the bridge chip BRG provided in the first embodiment has a first molding layer 30 at the bottom.
  • the first molding layer 30 uses a molding material, and the molding material includes an organic dielectric material, such as a resin (epoxy), polyimide (PI), etc.
  • the molding material has a larger thermal expansion coefficient (CTE), thereby increasing the thermal expansion coefficient of the bridge chip as a whole.
  • the bridge chip provided in the present embodiment increases the thermal expansion coefficient of the bridge chip as a whole by forming an organic composite structure by setting the first molding layer 30, thereby reducing the stress caused by thermal mismatch between the bridge chip and the surrounding packaging structure, thereby reducing the probability of cracking of the interconnection structure between the bridge chip and the interconnection chip.
  • the bridge chip of the prior art needs to use a thick substrate to meet the support requirements, such as thick silicon of more than 60 ⁇ m.
  • a deep through silicon via (TSV) needs to be set on the thick silicon to meet the connection requirements.
  • the bridge chip provided in the first embodiment of the present invention is provided with a first mold layer 30, which can play a supporting role, so that thin silicon (such as about 20 ⁇ m) can be used to meet the requirements; in this way, a through silicon via (TSV) with a smaller depth combined with a molded through hole TMV can meet the connection requirements.
  • TSV through silicon via
  • the bridge chip BRG in order to meet the interconnection requirements of the bridge chip BRG, as shown in Figure 2, in the bridge chip BRG, at least two chip connection areas A can be set on the surface of the metal wiring layer 20 away from the first mold layer 30, and a metal connection structure a (also referred to as a first metal connection structure) is set in each chip connection area A, and the metal connection structure a is electrically connected to the metal wiring layer 20.
  • a metal connection structure a also referred to as a first metal connection structure
  • the metal connection structure a is electrically connected to the metal wiring layer 20.
  • the metal connection structure a provided in the chip connection region A may be a pad, but is not limited thereto.
  • a deep trench capacitor can be set on the upper surface of the substrate 10 (that is, the surface close to the metal wiring layer 20).
  • the deep trench capacitor is electrically connected to the metal wiring layer 20, so that the transmission signal can be rectified through the deep trench capacitor, thereby improving the stability of the transmission signal.
  • the first embodiment further provides a method for manufacturing a bridge chip BRG as shown in FIG. 2 .
  • the manufacturing method may include:
  • Step 101 Referring to FIG. 4 (a), a substrate 10 is provided; wherein the substrate 10 includes a metal connection structure.
  • the above step 101 may include: providing a silicon substrate, and manufacturing metal connection structures such as through silicon vias on the silicon substrate.
  • a deep trench capacitor can also be manufactured on the surface of the substrate 10 .
  • Step 102 Referring to FIG. 4 ( b ), a metal wiring layer 20 is fabricated on the first surface of the substrate 10 ; wherein the metal wiring layer 20 is electrically connected to the metal connection structure in the substrate 10 .
  • the above step 102 may include: using a back-end-of-line (BEOL) process to form a redistribution line layer (RDL) on a silicon substrate with through silicon vias, and the redistribution line layer (RDL) is electrically connected to the through silicon vias (TSV) on the silicon substrate.
  • BEOL back-end-of-line
  • TSV through silicon vias
  • Step 103 Referring to (c) and (d) in FIG. 4 , a first mold layer 30 is formed on the second surface (another surface opposite to the first surface) of the substrate 10 , and a plurality of molded through holes TMV are formed on the first mold layer 30 , and the molded through holes TMV are electrically connected to the metal wiring layer 20 through the metal connection structure in the substrate 10 .
  • a first molding layer 30 is formed by using a molding material (such as PI); then, a plurality of through holes 31 are formed on the first molding layer 30 by a photolithography process; next, referring to FIG. 4 (d), a filling process can be used to fill metal copper in the plurality of through holes 31 to form a molding through hole TMV, and the molding through hole TMV is electrically connected to the metal wiring layer 20 through a metal connection structure in the substrate 10.
  • a molding material such as PI
  • a plurality of metal connection structures a may be produced in a plurality of chip connection regions A on the surface of the redistribution line layer (RDL) according to actual process requirements.
  • the second embodiment provides another bridge chip BRG, which is different from the bridge chip BRG provided in the first embodiment mainly in that the substrate 10 can be omitted.
  • the metal wiring layer 20 is disposed on the first mold layer 30, and the molded through hole TMV in the first mold layer 30 is directly electrically connected to the metal wiring layer 20.
  • the bridge chip BRG of the second embodiment omits the substrate 10 , which can further reduce the cost of the bridge chip BRG.
  • the bridge chip BRG of the second embodiment compared with the bridge chip BRG of the first embodiment, the bridge chip BRG of the second embodiment, on the one hand, eliminates the setting of the silicon substrate; on the other hand, the corresponding production of through silicon vias (TSV) in the silicon substrate is omitted, and the connection requirements can be met only by molded through vias TMV.
  • TSV through silicon vias
  • the production cost of molded through vias TMV is much lower, thereby reducing the cost of the bridge chip BRG.
  • the second embodiment further provides a method for manufacturing a bridge chip BRG as shown in FIG5 .
  • the manufacturing method may include:
  • Step 201 Referring to FIG. 7 (a), a metal wiring layer 20 is fabricated.
  • a metal wiring layer 20 such as a redistribution line layer (RDL) may be fabricated on a carrier through step 201 .
  • RDL redistribution line layer
  • Step 202 Referring to FIG. 7 ( b ), a first mold layer 30 is formed on the metal wiring layer 20 , and a plurality of molded through holes TMV are formed on the first mold layer 30 , and the molded through holes TMV are electrically connected to the metal wiring layer 20 .
  • a first mold layer 30 may be formed on the metal wiring layer 20 using a molding material (such as PI); then, a plurality of molded through holes TMV electrically connected to the metal wiring layer 20 are formed in the first mold layer 30 through a photolithography process and a filling process. Finally, referring to FIG. 7 (c), the carrier board may be removed to complete the fabrication of the bridge chip BRG.
  • a molding material such as PI
  • a plurality of metal connection structures a may be produced in a plurality of chip connection regions A on the surface of the redistribution line layer (RDL) according to actual process requirements.
  • the chip packaging structure includes a substrate 100, a first chip D1, a second chip D2 and a bridge chip BRG.
  • the first chip D1, the second chip D2 and the bridge chip BRG are integrally encapsulated in a plastic encapsulation material.
  • the bridge chip BRG is embedded in the substrate 100, and the lower surface of the bridge chip BRG is electrically connected to the substrate 100 through the molded through-via TMV.
  • the first chip D1 and the second chip D2 are located on the side of the bridge chip BRG away from the substrate 100, and the first chip D1 and the second chip D2 are electrically connected to the metal connection structures a in different chip connection areas A, respectively (see FIG. 5 ).
  • the first chip D1 and the second chip D2 are arranged on the substrate 100.
  • part of the area is connected to the metal wiring layer 20 of the bridge chip BRG, and part of the area is connected to the upper surface of the substrate 100.
  • part of the area is connected to the metal wiring layer 20 of the bridge chip BRG, and part of the area is connected to the upper surface of the substrate 100.
  • the first chip D1 and the second chip D2 can achieve interconnection and communication through the metal wiring layer 20 in the bridge chip BRG.
  • the bridge chip BRG is embedded in the substrate 100, and the upper surface of the bridge chip BRG can be flush with the upper surface of the substrate 100, and the first chip D1 and the second chip D2 are directly connected to the substrate 100 and the bridge chip BRG located in the same plane.
  • connection method between the first chip D1, the second chip D2, the bridge chip BRG, and the substrate 100 can be set according to needs, such as solder ball connection, copper column connection, etc., and this application does not impose any restrictions on this.
  • the chip packaging structure includes a substrate 100, a first chip D1, a second chip D2 and a bridge chip BRG.
  • the first chip D1, the second chip D2 and the bridge chip BRG are integrally encapsulated in a plastic encapsulation material.
  • the bridge chip BRG is arranged on the surface of the substrate 100, and the side of the bridge chip BRG where the molded through-hole TMV is arranged faces the substrate 100, and the bridge chip BRG is electrically connected to the substrate 100 through the molded through-hole TMV.
  • the first chip D1 and the second chip D2 are located on the side of the bridge chip BRG away from the substrate 100, and the first chip D1 and the second chip D2 are electrically connected to the metal connection structures a in different chip connection areas A, respectively (see FIG. 5 ).
  • the first chip D1 and the second chip D2 can achieve interconnection communication through the metal wiring layer 20 in the bridge chip BRG.
  • the present application does not limit the connection method between the first chip D1 and the substrate 100 and the bridge chip BRG.
  • the first chip D1 can be connected to the surface of the substrate 100 through a longer connection structure (such as a long metal column) and connected to the metal wiring layer 20 of the bridge chip BRG through a shorter connection structure (such as a short metal column).
  • the second chip D2 can be connected to the surface of the substrate 100 through a longer connection structure (such as a long copper column) and connected to the metal wiring layer 20 of the bridge chip BRG through a shorter connection structure (such as a short copper column).
  • a longer connection structure such as a long copper column
  • a shorter connection structure such as a short copper column
  • chip packaging structures illustrated in the above Figures 8 and 9 are illustrated using the bridge chip BRG in Example 2 as an example, but the present application is not limited to this; any bridge chip provided in the embodiments of the present application can be applied to the above two packaging methods.
  • the chip packaging structure can be a system on a chip (SOC).
  • the first chip D1 and the second chip D2 can be any two chips in the chip packaging structure.
  • the embodiment of the present application further provides a method for manufacturing a chip packaging structure as shown in FIG. 9 .
  • the manufacturing method may include:
  • Step 11 Referring to FIG. 11( a ), a carrier 200 , a first chip D1 , and a second chip D2 are provided, and the first chip D1 and the second chip D2 are disposed on the carrier 200 with their active surfaces facing upward.
  • the above step 11 may include: referring to FIG. 11 (a), providing a wafer, glass, etc. as a carrier 200, and using die attach film (DAF) or pyrolytic adhesive film to adhere the back sides of the first chip D1 and the second chip D2 to the surface of the carrier 200, that is, the active side (front side) of the chip (D1, D2) faces upward.
  • DAF die attach film
  • pyrolytic adhesive film to adhere the back sides of the first chip D1 and the second chip D2 to the surface of the carrier 200, that is, the active side (front side) of the chip (D1, D2) faces upward.
  • connection structures (such as copper pillars) are arranged in the active surfaces of the first chip D1 and the second chip D2.
  • a shorter connection structure can be arranged in the adjacent areas of the two chips for subsequent connection with the bridge chip BRG, and a longer connection structure can be arranged in other areas for subsequent connection with the substrate 100.
  • Step 12 Referring to FIG. 11( b ), a bridge chip BRG as in the above embodiment is provided, and the first chip D1 and the second chip D2 are electrically connected to the metal connection structures a in different chip connection regions A.
  • the above step 12 may include: referring to FIG. 11 (b), providing a new bridge chip BRG according to an embodiment of the present application, and welding the bridge chip BRG to the first chip D1 and the second chip D2 by flip chip (FC) combined with mass reflow (MR) or thermal compression bonding (TCB), so as to connect the metal connection structure a in the connection area A of the two chips to the shorter connection structures provided on the surface of the first chip D1 and the second chip D2, respectively, so as to realize the interconnection between the first chip D1 and the second chip D2 through the bridge chip BRG.
  • FC flip chip
  • MR mass reflow
  • TAB thermal compression bonding
  • Step 13 Referring to FIG. 11( c ), the first chip D1 , the second chip D2 , and the bridge chip BRG are plastic-encapsulated, and the connection structure on the active surface of the first chip D1 and the second chip D2 and the molded through-hole TMV on the surface of the bridge chip BRG are exposed by grinding.
  • the above step 13 may include: referring to FIG11(c), using a mold compound of a filler size to perform molded underfill (MUF), and plastic-sealing the first chip D1, the second chip D2, and the bridge chip BRG as a whole to achieve physical isolation and chemical protection.
  • MAF molded underfill
  • the above step 13 can be used to use underfill (UF) to fill the area between the bridge chip BRG and the chips (D1, D2) and between the first chip D1 and the second chip D2, and then use molding material (mold compound) to plastic-encapsulate the first chip D1, the second chip D2, and the bridge chip BRG as a whole.
  • underfill UF
  • molding material molding material
  • the carrier 200 when the chips (D1, D2) and the carrier 200 are bonded by a chip bonding adhesive (DAF), the carrier 200 can be removed by mechanical grinding; when the chips (D1, D2) and the carrier 200 are bonded by a pyrolytic adhesive film, the carrier 200 can be removed by mechanical thermal stripping. Finally, the molded through hole TMV on the surface of the bridge chip BRG and the connection structure on the surface of the first chip D1 and the second chip D2 can be exposed by mechanical grinding.
  • DAF chip bonding adhesive
  • step 13 the above-mentioned plastic-encapsulated structure can be connected to the substrate 100 according to actual needs.
  • the specific connection method can be set as needed, and the present application does not impose any restrictions on this.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

本申请提供一种桥接芯片、芯片封装结构及制作方法、电子设备，涉及半导体技术领域，能够提高桥接芯片整体的热膨胀系数。该桥接芯片包括第一模塑层、金属布线层、至少两个芯片连接区。其中，第一模塑层中设置有多个模塑通孔TMV(through molding vias)，金属布线层设置在第一模塑层上，且金属布线层与多个TMV电连接。至少两个芯片连接区位于金属布线层远离第一模塑层的一侧，每一芯片连接区均设置有多个第一金属连接结构，且多个第一金属连接结构与金属布线层电连接。本申请通过在桥接芯片中设置第一模塑层来增加桥接芯片整体的热膨胀系数，进而能够降低桥接芯片与周围的封装结构之间因热失配产生的应力。

Description

桥接芯片、芯片封装结构及制作方法、电子设备
本申请要求在2023年03月06日提交中国专利局、申请号为202310254321.3、发明名称为“桥接芯片、芯片封装结构及制作方法、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种桥接芯片、芯片封装结构及制作方法、电子设备。
背景技术
随着人们对芯片性能要求的不断提升，近年来2.5D/3D封装技术成为半导体行业的热门议题。2.5D/3D封装技术中采用多芯片(chiplets)形式，将多颗芯片(die)封装在一起，具有封装体积小、功耗低、引脚少等优势。
示意的，如图1所示，在一些2.5D封装结构中，根据实际的需求，需要在不同的芯片之间采用桥接芯片BRG(bridge die；也可以称为桥接晶粒)作为互连结构，来满足芯片之间的互联通信。但是，现有的桥接芯片BRG是采用硅(Si)基制作的，由于硅本身的热膨胀系数(coefficient of thermal expansion，CTE)较小，而桥接芯片BRG四周的封装结构的热膨胀系数较大，从而会导致桥接芯片BRG与芯片之间因热失配产生较大的应力，进而会造成桥接芯片BRG与芯片之间的互连结构出现断裂(crack)。
发明内容
本申请提供一种桥接芯片、芯片封装结构及制作方法、电子设备，能够提高桥接芯片整体的热膨胀系数。
本申请提供一种桥接芯片，桥接芯片包括第一模塑层、金属布线层、至少两个芯片连接区。其中，第一模塑层中设置有多个TMV，金属布线层设置在第一模塑层上，且金属布线层与多个TMV电连接。至少两个芯片连接区位于金属布线层远离第一模塑层的一侧，每一芯片连接区均设置有多个第一金属连接结构，且多个第一金属连接结构与金属布线层电连接。
本申请提供的桥接芯片中，通过底部设置模塑层(第一模塑层)形成有机复合结构，相比硅，模塑层采用的模塑材料的热膨胀系数更大，从而能够增加桥接芯片整体的热膨胀系数，在该桥接芯片应用至封装结构中时，能够降低桥接芯片与周围封装结构之间因热失配产生的应力，进而降低了桥接芯片与互联芯片之间的互连结构出现断裂(crack)的几率。
在一些可能实现的方式中，第一模塑层包括树脂、聚酰亚胺中的至少一种。
在一些可能实现的方式中，桥接芯片还包括衬底，衬底位于金属布线层与第一模塑层之间。衬底中设置有第二金属连接结构，金属布线层通过第二金属连接结构与模塑通孔电连接。
现有技术的桥接芯片需要采用厚衬底来满足支撑需求，如60μm以上的厚硅，从而需要在厚硅上设置深度较大的硅通孔(through silicon via，TSV)来满足连接需求。相比之下，本申请的桥接芯片中设置的第一模塑层可起到支撑作用，从而采用薄衬底(如20μm左右的薄硅)即可满足需求；这样一来，采用深度较小的TSV结合TMV的方式即可满足连接需求。可以理解的是，相比深度较大的TSV，深度较小的TSV和TMV的制作成本要低很多，从而也就降低了桥接芯片的成本。
在一些可能实现的方式中，衬底包括硅、玻璃、氮化硅、陶瓷中的一种或多种。
在一些可能实现的方式中，衬底在靠近金属布线层的一侧表面设置有深槽电容，且深槽电容与金属布线层电连接。通过该深槽电容能够实现对传输信号的整流作用，进而提高传输信号的稳定性。
本申请还提供一种芯片封装结构，该芯片封装结构包括基板、第一芯片、第二芯片、如前述任一种可能实现的方式中提供的桥接芯片。桥接芯片通过多个TMV与基板电连接。第一芯片和第二芯片位于桥接芯片远离基板的一侧，且第一芯片和第二芯片分别与两个芯片连接区中的第一金属连接结构电连接。
本申请还提供一种桥接芯片的制作方法，该制作方法包括：提供衬底；其中，衬底中包括金属连接结构。在衬底的第一表面制作金属布线层；其中，金属布线层与金属连接结构电连接。在衬底的第二表面制作第一模塑层，在第一模塑层中形成多个模塑通孔TMV，且多个TMV通过金属连接结构与金属布 线层电连接。
本申请还提供一种桥接芯片的制作方法，该制作方法包括：制作金属布线层。在金属布线层上制作第一模塑层，在第一模塑层中形成多个模塑通孔TMV，且多个TMV与金属布线层电连接。
本申请还提供一种芯片封装结构的制作方法，该制作方法包括：提供载板、第一芯片、第二芯片，并将所述第一芯片和所述第二芯片的有源面朝上设置在载板上。提供如前述任一种可能实现的方式的桥接芯片，并将第一芯片、第二芯片与桥接芯片中两个芯片连接区分别进行电连接。对第一芯片、第二芯片、桥接芯片进行塑封，并通过研磨露出第一芯片和第二芯片的有源面上的连接结构以及多个TMV。
本申请还提供一种电子设备，该电子设备包括电路板以及如前述的芯片封装结构；芯片封装结构与电路板电连接。
附图说明
图1为现有技术中提供的一种封装结构的示意图；
图2为本申请实施例提供的一种桥接芯片的结构示意图；
图3为本申请实施例提供的一种桥接芯片的制作方法流程图；
图4为本申请实施例提供的一种桥接芯片的制作过程示意图；
图5为本申请实施例提供的一种桥接芯片的结构示意图；
图6为本申请实施例提供的一种桥接芯片的制作方法流程图；
图7为本申请实施例提供的一种桥接芯片的制作过程示意图；
图8为本申请实施例提供的一种芯片封装结构的示意图；
图9为本申请实施例提供的一种芯片封装结构的示意图；
图10为本申请实施例提供的一种芯片封装结构的制作方法流程图；
图11为本申请实施例提供的一种芯片封装结构的制作过程示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请中的附图，对本申请中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书实施例和权利要求书及附图中的术语“第一”、“第二”等仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。“和/或”，用于描述关联对象的关联关系，表示可以存在三种关系，例如，“A和/或B”可以表示：只存在A，只存在B以及同时存在A和B三种情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“至少一个(项)”是指一个或者多个，“多个”是指两个或两个以上。“安装”、“连接”、“相连”等应做广义理解，例如可以是电连接，也可以是机械连接；可以是固定连接，也可以是可拆卸连接，或者一体地连接；可以是直接连接，也可以是通过中间媒介间接，也可以是两个元件内部的连通。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元。方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。“上”、“下”、“左”、“右”等仅用于相对于附图中的部件的方位而言的，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中的部件所放置的方位的变化而相应地发生变化。
本申请实施例提供一种电子设备，该电子设备包括电路板(printed circuit board，PCB；也可以称为印刷线路板)以及设置在电路板上的芯片封装结构。该芯片封装结构中采用一种新型桥接芯片(bridge die)以及至少两个芯片(die)，并且通过该新型桥接芯片对两个不同的芯片(die)进行电连接，也即两个不同的芯片通过该新型桥接芯片进行互联通信。
在本申请实施例提供的芯片封装结构中，新型桥接芯片采用高密度互联层与有机层组合的复合结构，能够提高桥接芯片整体的热膨胀系数(CTE)，降低了桥接芯片与周围封装结构之间因热失配产生的应力，从而能够降低桥接芯片与互联芯片之间的互连结构出现断裂(crack)的几率，进而提升了芯片封装结构的可靠性。
本申请对于上述电子设备的设置形式不做限制。示意的，该电子设备可以为手机、平板电脑、笔记本、车载电脑、智能手表、智能手环、服务器等电子产品或部件。
以下结合本申请实施例提供的新型桥接芯片，对芯片封装结构进行具体的说明。
首先，通过具体实施例对本申请提供的新型桥接芯片的结构进行说明。
实施例一
如图2所示，本实施例一提供一种桥接芯片BRG，该桥接芯片BRG包括衬底10、金属布线层20、第一模塑层30。其中，金属布线层20和第一模塑层30分别设置在衬底10的两个相对的表面。示意的，金属布线层20可以设置在衬底10的上表面，第一模塑层30设置在衬底10的下表面。
在此基础上，如图2所示，第一模塑层30中设置有多个模塑通孔TMV(through molding vias)，也即在第一模塑层30中开设有多个通孔，且通孔中填充有金属材料，从而形成模塑通孔TMV。
示意的，形成第一模塑层30的材料可以包括热固性材料，如树脂(epoxy)、聚酰亚胺(polyimide，PI)等，但并不限制于此。
示意的，模塑通孔TMV中的填充材料可以包括铜、铝、金、银等金属材料中的一种或多种，本申请对此不做限制，实际中可以根据需要选用合适的材料即可。
上述衬底10中设置有金属连接结构(也可以称为第二金属连接结构，图2中未示出)，模塑通孔TMV通过衬底10中的金属连接结构与金属布线层20电连接。示意的，衬底10中的金属连接结构可以包括金属连接线、金属过孔(如硅通孔)等，本申请对此不做限制，实际中可以根据需要进行设置即可。
本申请对于衬底10采用的材料不做限制。例如，在一些可能实现的方式中，衬底10的材料可以为硅、玻璃、氮化硅、陶瓷等材料中的一种或多种。
示意的，在一些可能实现的方式中，衬底10可以采用硅衬底，该硅衬底上设置的金属连接结构可以是硅通孔(through silicon via，TSV)。在此情况下，第一模塑层30中设置的模塑通孔TMV通过硅衬底上的硅通孔(TSV)与金属布线层20电连接。
示意的，在一些可能实现的方式中，金属布线层20可以是采用半导体制作工艺中的后道工序(back end of line，BEOL)制作的再分布线层(redistribution layer，RDL)。
现有技术中的桥接芯片主体材料采用硅，而硅的热膨胀系数(2.6ppm/℃)较小，从而会在桥接芯片与周围的封装结构之间因热失配产生较大的应力。
在本实施例一提供的桥接芯片BRG在底部设置第一模塑层30，第一模塑层30采用模塑材料，模塑材料中包含有机介质材料，如树脂(epoxy)、聚酰亚胺(polyimide，PI)等；相比硅，模塑材料具有较大的热膨胀系数(CTE)更大，从而能够增加桥接芯片整体的热膨胀系数。也就是说，本实施例提供的桥接芯片中通过设置第一模塑层30形成有机复合结构，来增加桥接芯片整体的热膨胀系数，从而能够降低桥接芯片与周围封装结构之间因热失配产生的应力，进而降低了桥接芯片与互联芯片之间的互连结构出现断裂(crack)的几率。
另外，现有技术的桥接芯片需要采用厚衬底来满足支撑需求，如60μm以上的厚硅，在此情况下，需要在厚硅上设置深度较大的硅通孔(TSV)来满足连接需求。相比之下，本实施例一提供的桥接芯片中设置第一模塑层30，该第一模塑层30可起到支撑作用，从而采用薄硅(如20μm左右)即可满足需求；这样一来，采用深度较小的硅通孔(TSV)结合模塑通孔TMV的方式即可满足连接需求。可以理解的是，相比深度较大的TSV，深度较小的TSV和模塑通孔TMV的制作成本要低很多，从而也就降低了桥接芯片BRG的成本。
当然，为了满足桥接芯片BRG的互连需求，如图2所示，可以在桥接芯片BRG中，位于金属布线层20远离第一模塑层30一侧的表面设置有至少两个芯片连接区A，在每一芯片连接区A中设置有金属连接结构a(也可以称为第一金属连接结构)，并且金属连接结构a与金属布线层20电连接，这样一来，多个芯片与不同的芯片连接区A中的金属连接结构a电连接，进而通过金属布线层20实现多芯片之间的互连通信。
示意的，上述芯片连接区A中设置的金属连接结构a可以是焊盘(pad)，但并不限制于此。
另外，为了满足桥接芯片BRG在进行互联通信过程中的信号稳定性，在一些可能实现的方式中，可以在衬底10的上表面(也即靠近金属布线层20一侧的表面)设置深槽电容(deep trench capacitor，DTC)，该深槽电容与金属布线层20电连接，从而通过该深槽电容能够实现对传输信号的整流作用，进而提高传输信号的稳定性。
示意的，本实施例一还提供一种如图2中示意的桥接芯片BRG的制作方法，如图3所示，该制作方法可以包括：
步骤101：参考图4中(a)所示，提供衬底10；其中，衬底10中包括金属连接结构。
示意的，在一些可能实现的方式中，上述步骤101可以包括：提供硅衬底，并在硅衬底上制作硅通孔等金属连接结构。
当然，根据桥接芯片BRG的实际需求，还可以在衬底10的表面制作深槽电容(DTC)。
步骤102：参考图4中(b)所示，在衬底10的第一表面制作金属布线层20；其中，金属布线层20与衬底10中的金属连接结构电连接。
示意的，在一些可能实现的方式中，上述步骤102可以包括：采用后道工序(BEOL)在制作有硅通孔的硅衬底上制作再分布线层(RDL)，并且再分布线层(RDL)与硅衬底上的硅通孔(TSV)电连接。
步骤103：参考图4中(c)、(d)所示，在衬底10的第二表面(与第一表面相对的另一个表面)制作第一模塑层30，并在第一模塑层30上形成多个模塑通孔TMV，且模塑通孔TMV通过衬底10中金属连接结构与金属布线层20电连接。
示意的，在一些可能实现的方式中，参考图4中(c)所示，在衬底10上未设置金属布线层20的另一个表面，采用模塑材料(如PI)形成第一模塑层30；然后，通过光刻工艺在第一模塑层30上形成多个通孔31；接下来，参考图4中(d)所示，可以采用填充工艺在多个通孔31中填充金属铜形成模塑通孔TMV，并且该模塑通孔TMV通过衬底10中金属连接结构与金属布线层20电连接。
当然，参考图2所示，可以在完成再分布线层(RDL)的制作后，根据实际的工艺要求，在再分布线层(RDL)表面的多个芯片连接区A，制作多个金属连接结构a。
实施例二
本实施例二提供另一种桥接芯片BRG，该桥接芯片BRG与实施例一提供的桥接芯片BRG的区别主要在于：可以省去衬底10的设置。
如图5所示，在本实施例二提供的桥接芯片BRG中，金属布线层20设置在第一模塑层30上，并且第一模塑层30中的模塑通孔TMV与金属布线层20直接电连接。在该桥接芯片BRG中通过设置第一模塑层30形成有机复合结构，能够增加桥接芯片整体的热膨胀系数，从而降低了桥接芯片与周围结构之间因热失配产生的应力，进而降低了桥接芯片与互联芯片之间的互连结构出现断裂(crack)的几率。
另外，相比于实施例一的桥接芯片BRG，本实施例二的桥接芯片BRG中省去了衬底10的设置，能够进一步降低桥接芯片BRG的成本。
示意的，在一些可能实现的方式中，相比于实施例一的桥接芯片BRG，本实施例二的桥接芯片BRG，一方面省去硅衬底的设置；另一方面，对应的也就省去了硅衬底中硅通孔(TSV)的制作，仅通过模塑通孔TMV即可满足连接需求，相比TSV，模塑通孔TMV的制作成本要低很多，从而也就降低了桥接芯片BRG的成本。
本实施例二提供的桥接芯片BRG中的其他结构部分，可以参考实施例一中对应的部分的说明，此处不在赘述。
示意的，本实施例二还提供一种如图5中示意的桥接芯片BRG的制作方法，如图6所示，该制作方法可以包括：
步骤201：参考图7中(a)所示，制作金属布线层20。
示意的，在一些可能实现的方式中，参考图7中(a)所示，通过步骤201可以在载板上制作金属布线层20，如再分布线层(RDL)。
步骤202：参考图7中(b)所示，在金属布线层20上形成第一模塑层30，并在第一模塑层30上形成多个模塑通孔TMV，并且模塑通孔TMV与金属布线层20电连接。
示意的，在一些可能实现的方式中，参考图7中(b)所示，可以采用模塑材料(如PI)在金属布线层20上形成第一模塑层30；然后，通过光刻工艺和填充工艺在第一模塑层30中形成与金属布线层20电连接的多个模塑通孔TMV。最后，参考图7中(c)所示，可以去除载板，以完成桥接芯片BRG的制作。
当然，参考图5所示，可以在完成再分布线层(RDL)的制作后，根据实际的工艺要求，在再分布线层(RDL)表面的多个芯片连接区A制作多个金属连接结构a。
以下对采用上述实施例提供的桥接芯片BRG的芯片封装结构进行说明。
封装方式一
如图8所示，在一些可能实现的方式中，芯片封装结构中包括基板100、第一芯片D1、第二芯片D2以及桥接芯片BRG。第一芯片D1、第二芯片D2以及桥接芯片BRG整体塑封在塑封材料中。
桥接芯片BRG嵌入在基板100内部，并且桥接芯片BRG的下表面通过模塑通孔TMV与基板100电连接。第一芯片D1和第二芯片D2位于桥接芯片BRG远离基板100的一侧，并且第一芯片D1和第二芯片D2分别与不同的芯片连接区A中的金属连接结构a电连接(可参考图5)。
第一芯片D1和第二芯片D2设置在基板100上。第一芯片D1的有源面中，部分区域与桥接芯片BRG的金属布线层20连接，部分区域与基板100的上表面连接。类似的，第二芯片D2的有源面中，部分区域与桥接芯片BRG的金属布线层20连接，部分区域与基板100的上表面连接。在此情况下，第一芯片D1和第二芯片D2能够通过桥接芯片BRG中的金属布线层20实现互联通信。
示意的，在该封装方式一中，桥接芯片BRG嵌入在基板100中，并且桥接芯片BRG的上表面可以与基板100的上表面平齐，第一芯片D1和第二芯片D2直接与位于同一平面内的基板100和桥接芯片BRG进行连接。
实际中可以根据需求来设置第一芯片D1、第二芯片D2与桥接芯片BRG、基板100之间的连接方式，如焊球连接、铜柱连接等，本申请对此不做限制。
封装方式二
如图9所示，在一些可能实现的方式中，芯片封装结构中包括基板100、第一芯片D1、第二芯片D2以及桥接芯片BRG。第一芯片D1、第二芯片D2以及桥接芯片BRG整体塑封在塑封材料中。
桥接芯片BRG设置在基板100表面，桥接芯片BRG设置模塑通孔TMV的一侧朝向基板100，并且桥接芯片BRG通过模塑通孔TMV与基板100电连接。第一芯片D1和第二芯片D2位于桥接芯片BRG远离基板100的一侧，并且第一芯片D1和第二芯片D2分别与不同的芯片连接区A中的金属连接结构a电连接(可参考图5)。
第一芯片D1的有源面中，部分区域与桥接芯片BRG的芯片连接区A电连接，部分区域与基板100电连接。类似的，第二芯片D2的有源面中，部分区域与桥接芯片BRG的芯片连接区A电连接，部分区域与基板100电连接。在此情况下，第一芯片D1和第二芯片D2能够通过桥接芯片BRG中的金属布线层20实现互联通信。
本申请对于第一芯片D1与基板100、桥接芯片BRG的连接方式不做限制。例如，第一芯片D1可以通过较长的连接结构(如长金属柱)与基板100的表面连接，通过较短的连接结构(如短金属柱)与桥接芯片BRG的金属布线层20连接。
类似的，如第二芯片D2的设置。第二芯片D2可以通过较长的连接结构(如长铜柱)与基板100的表面连接，通过较短的连接结构(如短铜柱)与桥接芯片BRG的金属布线层20连接。
需要说明的是，上述图8和图9示意的芯片封装结构中均是以实施例二中的桥接芯片BRG为例进行示意的，但本申请并不限制于此；本申请实施例提供的任意桥接芯片均可适用于前述的两种封装方式。
本申请对于上述芯片封装结构的设置形式不做限制。示意的，该芯片封装结构可以是系统级芯片(system on a chip，SOC)。
本申请上述芯片封装结构中的芯片数量不做限制，可以是2个、3个、4个等，上述第一芯片D1和第二芯片D2可以是芯片封装结构中的任意两个芯片。
示意的，本申请实施例还提供一种如图9中示意的芯片封装结构的制作方法，如图10所示，该制作方法可以包括：
步骤11：参考图11中(a)所示，提供载板200、第一芯片D1、第二芯片D2，并将第一芯片D1和第二芯片D2的有源面朝上设置在载板200上。
示意的，在一些可能实现的方式中，上述步骤11可以包括：参考图11中(a)所示，提供如晶圆(wafer)、玻璃等作为载板200，并采用芯片粘结胶(die attach film，DAF)或热解胶膜，将第一芯片D1和第二芯片D2的背面粘贴至载板200表面，也即芯片(D1、D2)的有源面(正面)朝上。
另外，第一芯片D1和第二芯片D2的有源面中设置有连接结构(如铜柱)，在两个芯片的相邻区域可以设置较短的连接结构，用于后续与桥接芯片BRG进行连接，在其他区域可以设置较长的连接结构，用于后续与基板100进行连接。
步骤12：参考图11中(b)所示，提供如前述实施例中的桥接芯片BRG，并将第一芯片D1、第二芯片D2与不同的芯片连接区A中的金属连接结构a进行电连接。
示意的，在一些可能实现的方式中，上述步骤12可以包括：参考图11中(b)所示，提供本申请实施例的新型桥接芯片BRG，并可以采用倒装芯片(flip chip，FC)结合热风重熔(mass reflow，MR)或者热压键合(thermal compression bonding，TCB)的方式，将桥接芯片BRG焊接到第一芯片D1、第二芯片D2上，以将两个芯片连接区A中的金属连接结构a分别与第一芯片D1、第二芯片D2表面设置的较短的连接结构连接，从而实现第一芯片D1、第二芯片D2之间通过桥接芯片BRG的互联。
步骤13：参考图11中(c)所示，对第一芯片D1、第二芯片D2、桥接芯片BRG进行塑封，并通过研磨露出第一芯片D1和第二芯片D2的有源面上的连接结构以及桥接芯片BRG表面的模塑通孔TMV。
示意的，在一些可能实现的方式中，上述步骤13可以包括：参考图11中(c)所示，采用填料尺寸(filler size)的模塑材料(mold compound)对进行模塑底部填充(molded underfill，MUF)，对第一芯片D1、第二芯片D2、桥接芯片BRG整体进行塑封，以起到物理隔离和化学保护的目的。
当然，作为另一种可能实现的方式，可以通过上述步骤13采用底部填充(underfill，UF)对桥接芯片BRG与芯片(D1、D2)之间以及第一芯片D1与第二芯片D2之间的区域进行填充，然后再采用模塑材料(mold compound)对第一芯片D1、第二芯片D2、桥接芯片BRG整体进行塑封。
接下来，参考图11中(d)所示，在芯片(D1、D2)与载板200之间通过芯片粘结胶(DAF)粘结的情况下，可以通过机械研磨的方式去掉载板200；在芯片(D1、D2)与载板200之间通过热解胶膜粘结的情况下，可以采用机械热剥离的方式去除载板200。最后，可以通过机械研磨露出桥接芯片BRG表面的模塑通孔TMV，以及第一芯片D1与第二芯片D2表面的连接结构。
当然，在步骤13之后，参考图9所示，可以根据实际的需求，将上述塑封后的结构与基板100进行连接，具体连接方式可以根据需要进行设置，本申请对此不做限制。
应理解，在本申请的各制作方法中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其具体作用和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
另外，对于上述制作方法中其他的相关内容，可以对应的参考前述对应结构实施例中的部分，此处不再赘述；对于前述结构实施例中的其他设置结构，可以参考对应的制作方法以及相关制作方法进行调整，此处不再一一赘述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (10)

  1. 一种桥接芯片，其特征在于，包括：
    第一模塑层，所述第一模塑层中设置有多个模塑通孔TMV；
    金属布线层，所述金属布线层设置在所述第一模塑层上，且所述金属布线层与所述多个TMV电连接；
    至少两个芯片连接区，所述至少两个芯片连接区位于所述金属布线层远离所述第一模塑层的一侧，每一所述芯片连接区均设置有多个第一金属连接结构，且所述多个第一金属连接结构与所述金属布线层电连接。
  2. 根据权利要求1所述的桥接芯片，其特征在于，
    所述第一模塑层包括树脂、聚酰亚胺中的至少一种。
  3. 根据权利要求1或2所述的桥接芯片，其特征在于，
    所述桥接芯片还包括衬底，所述衬底位于所述金属布线层与所述第一模塑层之间；
    所述衬底中设置有第二金属连接结构，所述金属布线层通过所述第二金属连接结构与所述TMV电连接。
  4. 根据权利要求3所述的桥接芯片，其特征在于，
    所述衬底包括硅、玻璃、氮化硅、陶瓷中的一种或多种。
  5. 根据权利要求3或4所述的桥接芯片，其特征在于，
    所述衬底在靠近所述金属布线层的一侧表面设置有深槽电容，且所述深槽电容与所述金属布线层电连接。
  6. 一种芯片封装结构，其特征在于，包括基板、第一芯片、第二芯片、如权利要求1-5任一项所述的桥接芯片；
    所述桥接芯片通过所述多个TMV与所述基板电连接；
    所述第一芯片和所述第二芯片位于所述桥接芯片远离所述基板的一侧，且所述第一芯片和所述第二芯片与不同的所述芯片连接区中的所述第一金属连接结构电连接。
  7. 一种桥接芯片的制作方法，其特征在于，包括：
    提供衬底；其中，所述衬底中包括金属连接结构；
    在所述衬底的第一表面制作金属布线层；其中，所述金属布线层与所述金属连接结构电连接；
    在所述衬底的第二表面制作第一模塑层，在所述第一模塑层上形成多个模塑通孔TMV，且所述多个TMV通过所述金属连接结构与所述金属布线层电连接。
  8. 一种桥接芯片的制作方法，其特征在于，包括：
    制作金属布线层；
    在所述金属布线层上制作第一模塑层，在所述第一模塑层上形成多个模塑通孔TMV，且所述多个TMV与所述金属布线层电连接。
  9. 一种芯片封装结构的制作方法，其特征在于，包括：
    提供载板、第一芯片、第二芯片，并将所述第一芯片和所述第二芯片的有源面朝上设置在所述载板上；
    提供如权利要求1-5任一项所述的桥接芯片，并将所述第一芯片、所述第二芯片与所述桥接芯片的两个所述芯片连接区分别进行电连接；
    对所述第一芯片、所述第二芯片、所述桥接芯片进行塑封，并通过研磨露出所述第一芯片和所述第二芯片的有源面上的连接结构以及所述多个TMV。
  10. 一种电子设备，其特征在于，包括电路板以及权利要求6所述的芯片封装结构；所述芯片封装结构与所述电路板电连接。
PCT/CN2023/140243 2023-03-06 2023-12-20 桥接芯片、芯片封装结构及制作方法、电子设备 WO2024183408A1 (zh)

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JP2011082361A (ja) * 2009-10-07 2011-04-21 Fujitsu Ltd 回路基板及びその製造方法
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CN114050145A (zh) * 2021-10-25 2022-02-15 日月光半导体制造股份有限公司 半导体封装结构及其制造方法
CN114267661A (zh) * 2021-11-09 2022-04-01 华为技术有限公司 电子设备、芯片封装结构及其制作方法
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JP2011082361A (ja) * 2009-10-07 2011-04-21 Fujitsu Ltd 回路基板及びその製造方法
CN103635993A (zh) * 2011-04-21 2014-03-12 泰塞拉公司 具有模塑成型的低热膨胀系数电介质的插入体
CN114050145A (zh) * 2021-10-25 2022-02-15 日月光半导体制造股份有限公司 半导体封装结构及其制造方法
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