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WO2024065425A9 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2024065425A9
WO2024065425A9 PCT/CN2022/122729 CN2022122729W WO2024065425A9 WO 2024065425 A9 WO2024065425 A9 WO 2024065425A9 CN 2022122729 W CN2022122729 W CN 2022122729W WO 2024065425 A9 WO2024065425 A9 WO 2024065425A9
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WO
WIPO (PCT)
Prior art keywords
light
electrically connected
pixel circuit
emitting elements
anode
Prior art date
Application number
PCT/CN2022/122729
Other languages
English (en)
French (fr)
Other versions
WO2024065425A1 (zh
Inventor
方飞
刘珂
郭丹
景阳钟
彭博
韩婷
石领
曾佳元
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280003426.5A priority Critical patent/CN118120003A/zh
Priority to EP22960062.2A priority patent/EP4421788A4/en
Priority to PCT/CN2022/122729 priority patent/WO2024065425A1/zh
Publication of WO2024065425A1 publication Critical patent/WO2024065425A1/zh
Publication of WO2024065425A9 publication Critical patent/WO2024065425A9/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes

Definitions

  • the present disclosure relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device.
  • OLED Organic light emitting diodes
  • QLED quantum dot light emitting diodes
  • the present disclosure provides a display substrate, a display substrate comprising: a display area and a peripheral area at least partially surrounding the display area, the display area comprising a light-transmitting display area and a conventional display area located at least on one side of the light-transmitting display area, the light transmittance of the light-transmitting display area being greater than the light transmittance of the conventional display area;
  • the display substrate comprises: a substrate and a plurality of light-emitting elements and a plurality of pixel circuits located on one side of the substrate, the plurality of light-emitting elements comprising a plurality of first-type light-emitting elements located in the light-transmitting display area, the plurality of pixel circuits comprising a plurality of first-type pixel circuits located in the light-transmitting display area, at least one first-type pixel circuit of the plurality of first-type pixel circuits being electrically connected to at least two first-type light-emitting elements emitting light of the same color, and the first-type pixel circuit being configured to drive the at least two first-type light-emitting elements to emit light;
  • the orthographic projection of the at least one first-type pixel circuit on the substrate overlaps with the orthographic projection of the at least one first-type light-emitting element on the substrate.
  • an orthographic projection of the at least one first-type pixel circuit on the substrate overlaps with an orthographic projection of at least some of the at least two first-type light-emitting elements electrically connected to the at least one first-type pixel circuit on the substrate.
  • the plurality of first signal lines include at least one of the following: a scan signal line, a reset signal line, an initial signal line, and a light emitting signal line.
  • the plurality of first signal lines include a plurality of sub-signal lines; adjacent sub-signal lines of the first signal lines are electrically connected through electrically connected first-type pixel circuits.
  • the multiple second signal lines include at least one of the following: a data signal line and a first power line, and the multiple data signal lines and the multiple first power lines extend along a first direction; the data signal line and the first power line electrically connected to the first type pixel circuit are located between adjacent sub-signal lines of the first signal line, and the orthographic projection of the data signal line and the first power line electrically connected to the first type pixel circuit on the substrate overlaps with the orthographic projection of the first type pixel circuit on the substrate.
  • At least one of the scan signal line, the reset signal line, the initial signal line, the light emitting signal line, the data signal line and the first power line partially overlaps the orthographic projection of the first type light emitting element on the substrate.
  • the plurality of first type light emitting elements include at least: a plurality of first light emitting elements emitting a first color light, a plurality of second light emitting elements emitting a second color light, and a plurality of third light emitting elements emitting a third color light;
  • the anode area of at least one of the plurality of first light-emitting elements is larger than the anode area of at least one of the plurality of third light-emitting elements
  • the anode area of at least one of the plurality of second light-emitting elements is larger than the anode area of the at least one third light-emitting element
  • the anode area of at least one of the plurality of second light-emitting elements is larger than the anode area of at least one of the plurality of first light-emitting elements
  • the first color light is red light
  • the second color light is blue light
  • the third color light is green light
  • the first type pixel circuit includes: a plurality of transistors and at least one capacitor; in a direction perpendicular to the display substrate, the light-transmitting display area includes at least: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a transparent conductive layer, a first planar layer, a fourth conductive layer, and a second planar layer disposed on the substrate;
  • the semiconductor layer includes at least: an active layer of a plurality of transistors of the first type pixel circuit;
  • the first conductive layer at least includes: control electrodes of a plurality of transistors of the first type pixel circuit and a first electrode plate of a capacitor;
  • the second conductive layer at least includes: a second plate of a capacitor of the first type pixel circuit;
  • the third conductive layer at least includes: first electrodes and second electrodes of a plurality of transistors of the first type pixel circuit and a plurality of connecting electrodes;
  • the transparent conductive layer at least includes: a plurality of first signal lines, a plurality of second signal lines and a plurality of anode connection lines, at least one anode connection line of the plurality of anode connection lines is electrically connected to at least one first type pixel circuit and anodes of at least two first type light emitting elements emitting light of the same color; the at least one first type pixel circuit is electrically connected to at least one first signal line and at least one second signal line;
  • the fourth conductive layer at least includes: a plurality of signal connection lines.
  • the plurality of first type light emitting elements are arranged as follows:
  • the plurality of third light-emitting elements are arranged at certain intervals in the i-th row, the second light-emitting element and the first light-emitting element are alternately arranged in adjacent rows of the i-th row, the first light-emitting element and the second light-emitting element are alternately arranged in the j-th column, the plurality of third light-emitting elements are arranged at certain intervals in adjacent columns of the j-th column, the first light-emitting element and the third light-emitting element are alternately arranged along a third direction, the second light-emitting element and the third light-emitting element are alternately arranged along a fourth direction, the third direction and the fourth direction intersect with the first direction and the second direction respectively, the first direction is a column direction, and the second direction is a row direction.
  • the multiple first-type pixel circuits include: at least one first pixel circuit, at least one second pixel circuit, at least one third pixel circuit and at least one fourth pixel circuit; the first pixel circuit is electrically connected to two of the first light-emitting elements, the second pixel circuit is electrically connected to two of the second light-emitting elements, the third pixel circuit is electrically connected to two of the third light-emitting elements, the fourth pixel circuit is electrically connected to two of the third light-emitting elements, and the third pixel circuit and the fourth pixel circuit are electrically connected to different third light-emitting elements.
  • the two first light-emitting elements electrically connected to the first pixel circuit are located in the same row
  • the two second light-emitting elements electrically connected to the second pixel circuit are located in the same row
  • the two third light-emitting elements electrically connected to the third pixel circuit are located in the same row
  • the two third light-emitting elements electrically connected to the fourth pixel circuit are located in the same row.
  • the orthographic projection of the first pixel circuit on the substrate partially overlaps with the orthographic projection of one of the electrically connected first light emitting elements on the substrate;
  • the orthographic projection of the second pixel circuit on the substrate partially overlaps with the orthographic projection of the first light-emitting element located between two electrically connected second light-emitting elements on the substrate;
  • the orthographic projection of the third pixel circuit on the substrate partially overlaps with the orthographic projection of the second light-emitting element on the substrate, and the second light-emitting element overlapping with the third pixel circuit is located in an adjacent row to the row where two third light-emitting elements electrically connected to the third pixel circuit are located, and is located in a middle column where two third light-emitting elements electrically connected to the third pixel circuit are located;
  • the orthographic projection of the fourth pixel circuit on the substrate partially overlaps with the orthographic projection of the second light-emitting element on the substrate, the second light-emitting element overlapping with the fourth pixel circuit is located in an adjacent row to the row where the two third light-emitting elements electrically connected to the fourth pixel circuit are located, and is located in a middle column to the column where the two third light-emitting elements electrically connected to the fourth pixel circuit are located, and the second light-emitting element overlapping with the third pixel circuit and the second light-emitting element overlapping with the fourth pixel circuit are different light-emitting elements.
  • the first signal line extends along a second direction
  • the anode connection wires include: a first anode connection wire, a second anode connection wire, a third anode connection wire and a fourth anode connection wire;
  • the first anode connecting line is electrically connected to the first pixel circuit and the first light-emitting element, respectively, and at least a portion of the first anode connecting line extends along the second direction;
  • the second anode connecting line is electrically connected to the second pixel circuit and the second light-emitting element, respectively, and at least a portion of the second anode connecting line extends along the second direction;
  • the third anode connecting line is electrically connected to the third pixel circuit and the third light-emitting element, respectively, and at least a portion of the third anode connecting line extends along the second direction, and the third anode connecting line is located between the data signal line electrically connected to the third pixel circuit and the first power line;
  • the fourth anode connecting line is electrically connected to the fourth pixel circuit and the third light-emitting element, respectively, and at least a portion of the fourth anode connecting line extends along the second direction, and the fourth anode connecting line is located between the data signal line electrically connected
  • the first power lines electrically connected to at least two adjacent first-type pixel circuits in the same column are arranged at intervals, and the first power lines arranged at intervals in the same column are electrically connected through at least one signal connection line located in the fourth conductive layer;
  • the data signal lines electrically connected to at least two adjacent first-type pixel circuits in the same column are arranged at intervals, and the data signal lines arranged at intervals in the same column are electrically connected through at least one signal connection line located in the fourth conductive layer.
  • the two first light-emitting elements electrically connected to the first pixel circuit are arranged along a third direction
  • the two second light-emitting elements electrically connected to the second pixel circuit are arranged along a fourth direction
  • the two third light-emitting elements electrically connected to the third pixel circuit are located in the same column
  • the two third light-emitting elements electrically connected to the fourth pixel circuit are located in the same column.
  • the orthographic projection of the first pixel circuit on the substrate overlaps with the orthographic projection of one of the electrically connected first light-emitting elements on the substrate;
  • the orthographic projection of the second pixel circuit on the substrate overlaps with the orthographic projection of one of the electrically connected second light emitting elements on the substrate;
  • the orthographic projection of the third pixel circuit on the substrate overlaps with the orthographic projection of one of the electrically connected third light emitting elements on the substrate;
  • the orthographic projection of the fourth pixel circuit on the substrate overlaps with the orthographic projection of one of the electrically connected third light-emitting elements on the substrate, and the third light-emitting element overlapping with the third pixel circuit and the third light-emitting element overlapping with the fourth pixel circuit are different light-emitting elements.
  • the anode connection wire includes: a first anode connection wire, a second anode connection wire, a third anode connection wire, and a fourth anode connection wire;
  • the first anode connecting line is electrically connected to the first pixel circuit and the first light-emitting element, respectively, and at least a portion of the first anode connecting line extends along the first direction;
  • the second anode connecting line is electrically connected to the second pixel circuit and the second light-emitting element, respectively, and at least a portion of the second anode connecting line extends along the first direction;
  • the third anode connecting line is electrically connected to the third pixel circuit and the third light-emitting element, respectively, and at least a portion of the third anode connecting line extends along the first direction, and the third anode connecting line is located on a side of the first power line electrically connected to the third pixel circuit away from the data signal line;
  • the fourth anode connecting line is electrically connected to the fourth pixel circuit and the third light-emitting element, respectively, and at least a portion of the fourth anode connecting line extends along the first direction, and the fourth anode connecting line is located on a
  • the data signal lines electrically connected to the first type pixel circuits located in the same column are the same signal line
  • the first power lines electrically connected to at least two adjacent first type pixel circuits located in the same column are spaced apart
  • the spaced apart first power lines located in the same column are electrically connected through at least one signal connection line located in the fourth conductive layer.
  • the transparent conductive layer further includes: a power connection line, at least a portion of which extends along the second direction;
  • the power connection line is electrically connected to first power lines electrically connected to two adjacent first-type pixel circuits in the same row, and the first power line and the power connection line are electrically connected via a connection electrode located in the third conductive layer.
  • the first power line includes: a power main body portion extending along the first direction and a power connection portion extending along the second direction, the power connection portion being located on a side of the power main body portion away from the data signal line;
  • the power connection line is electrically connected to a power connection portion of one of the first type pixel circuits and a power main portion of another first type pixel circuit in adjacent first type pixel circuits located in the same row.
  • the plurality of first type light emitting elements are arranged as follows:
  • the multiple second light-emitting elements are arranged in the jth column, the first light-emitting element and the third light-emitting element are alternately arranged in adjacent columns of the jth column, the multiple second light-emitting elements are arranged in the i-th row, and the first light-emitting element and the third light-emitting element are arranged between adjacent second light-emitting elements in the same row.
  • the multiple first-type pixel circuits include: at least one first pixel circuit, at least one second pixel circuit and at least one third pixel circuit; the first pixel circuit is electrically connected to two of the first light-emitting elements, the second pixel circuit is electrically connected to two of the second light-emitting elements and the third pixel circuit is electrically connected to two of the third light-emitting elements.
  • two first light emitting elements electrically connected to the first pixel circuit are located in the same row
  • two second light emitting elements electrically connected to the second pixel circuit are located in the same row
  • two third light emitting elements electrically connected to the third pixel circuit are located in the same row.
  • the orthographic projection of the first pixel circuit on the substrate partially overlaps with the orthographic projection of one of the electrically connected first light emitting elements on the substrate;
  • the orthographic projection of the second pixel circuit on the substrate partially overlaps with the orthographic projection of one of the electrically connected second light-emitting elements on the substrate;
  • the orthographic projection of the third pixel circuit on the substrate partially overlaps with the orthographic projection of one of the electrically connected third light-emitting elements on the substrate.
  • At least two of the first light emitting element overlapped by the first pixel circuit, the second light emitting element overlapped by the second pixel circuit, and the third light emitting element overlapped by the third pixel circuit are adjacent.
  • the orthographic projection of the first pixel circuit on the substrate partially overlaps with the orthographic projection of one of the electrically connected first light emitting elements on the substrate;
  • the orthographic projection of the second pixel circuit on the substrate partially overlaps with the orthographic projection of one of the electrically connected second light-emitting elements on the substrate;
  • An orthographic projection of the third pixel circuit on the substrate partially overlaps with an orthographic projection of the second light emitting element located between two third light emitting elements electrically connected to the third pixel circuit on the substrate.
  • the orthographic projection of the first pixel circuit on the substrate partially overlaps with the orthographic projection of a second light emitting element located between the two first light emitting elements electrically connected to the first pixel circuit on the substrate;
  • the orthographic projection of the second pixel circuit on the substrate partially overlaps with the orthographic projection of one of the electrically connected second light-emitting elements on the substrate;
  • the orthographic projection of the third pixel circuit on the substrate partially overlaps with the orthographic projection of one of the electrically connected third light-emitting elements on the substrate.
  • the anode connection wire includes: a first anode connection wire, a second anode connection wire, and a third anode connection wire;
  • the first anode connecting line is electrically connected to the first pixel circuit and the first light-emitting element, respectively, and at least a portion of the first anode connecting line extends along the second direction;
  • the second anode connecting line is electrically connected to the second pixel circuit and the second light-emitting element, respectively, and at least a portion of the second anode connecting line extends along the second direction;
  • the third anode connecting line is electrically connected to the third pixel circuit and the third light-emitting element, respectively, and at least a portion of the third anode connecting line extends along the second direction.
  • the data signal lines electrically connected to the first type pixel circuits located in the same column are the same signal line
  • the first power lines electrically connected to at least two adjacent first type pixel circuits located in the same column are spaced apart
  • the spaced apart first power lines located in the same column are electrically connected through at least one signal connection line located in the fourth conductive layer.
  • the plurality of light emitting elements further include a plurality of second-type light emitting elements located in the regular display area
  • the plurality of pixel circuits further include a plurality of second-type pixel circuits located in the regular display area
  • At least one of the multiple second-type light-emitting elements is electrically connected to at least one of the multiple second-type pixel circuits, and the orthographic projection of the second-type light-emitting element on the substrate and the orthographic projection of the electrically connected second-type pixel circuit on the substrate overlap.
  • the present disclosure further provides a display device, comprising the above-mentioned display substrate.
  • FIG1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of the arrangement of the first type of light emitting elements in the light-transmitting display area according to at least one embodiment of the present disclosure
  • FIG3 is a second schematic diagram of the arrangement of the first type of light emitting elements in the light-transmitting display area of at least one embodiment of the present disclosure
  • FIG4 is a schematic diagram of the arrangement relationship between the first type pixel circuit and the first type light emitting element in the light-transmitting display area provided by an exemplary embodiment
  • FIG5 is a second schematic diagram of the arrangement relationship between the first type pixel circuit and the first type light emitting element in the light-transmitting display area provided by an exemplary embodiment
  • FIG6 is a third schematic diagram of the arrangement relationship between the first type pixel circuit and the first type light emitting element in the light-transmitting display area provided by an exemplary embodiment
  • FIG. 7 is a fourth schematic diagram of the arrangement relationship between the first type pixel circuit and the first type light emitting element in the light-transmitting display area provided by an exemplary embodiment
  • FIG8 is a fifth schematic diagram of the arrangement relationship between the first type pixel circuit and the first type light emitting element in the light-transmitting display area provided by an exemplary embodiment
  • FIG9 is a sixth schematic diagram of the arrangement relationship between the first type pixel circuit and the first type light emitting element in the light-transmitting display area provided by an exemplary embodiment
  • FIG10 is an equivalent circuit diagram of a first type pixel circuit
  • FIG11 is a working timing diagram of the first type pixel circuit provided in FIG10 ;
  • FIG. 12 is a partial top view of a light-transmitting display area provided by an exemplary embodiment
  • FIG13 is a second partial top view of a light-transmitting display area provided by an exemplary embodiment
  • FIG. 14 is a third partial top view of a light-transmitting display area provided by an exemplary embodiment
  • FIG15A is a schematic diagram of a light-transmitting display area provided in FIG12 after a semiconductor pattern is formed;
  • FIG15B is a schematic diagram of a pattern of a first conductive layer in a light-transmitting display area provided in FIG12 ;
  • FIG15C is a schematic diagram of the light-transmitting display area provided in FIG12 after the first conductive layer pattern is formed;
  • FIG15D is a schematic diagram of a second conductive layer pattern in the light-transmitting display area provided in FIG12 ;
  • FIG15E is a schematic diagram of a light-transmitting display area provided in FIG12 after a second conductive layer pattern is formed;
  • FIG15F is a schematic diagram of a light-transmitting display area provided in FIG12 after a third insulating layer pattern is formed;
  • FIG15G is a schematic diagram of a third conductive layer pattern in the light-transmitting display area provided in FIG12 ;
  • FIG15H is a schematic diagram of a light-transmitting display area provided in FIG12 after a third conductive layer pattern is formed;
  • FIG15I is a schematic diagram of a light-transmitting display area provided in FIG12 after a fourth insulating layer pattern is formed;
  • FIG15J is a schematic diagram of a transparent conductive layer pattern in a light-transmitting display area provided in FIG12 ;
  • FIG15K is a schematic diagram of a transparent conductive layer pattern formed in the light-transmitting display area provided in FIG12 ;
  • FIG15L is a schematic diagram of the light-transmitting display area shown in FIG12 after a first flat layer is formed;
  • FIG15M is a schematic diagram of a fourth conductive layer pattern in the light-transmitting display area provided in FIG12 ;
  • FIG15N is a schematic diagram of a light-transmitting display area provided in FIG12 after a fourth conductive layer pattern is formed;
  • FIG15O is a schematic diagram of the light-transmitting display area provided in FIG12 after a second flat layer pattern is formed;
  • FIG15P is a schematic diagram of the pattern of the anode conductive layer in the light-transmitting display area provided in FIG12 ;
  • FIG15Q is a schematic diagram of the light-transmitting display area provided in FIG12 after an anode conductive layer pattern is formed;
  • FIG16A is a schematic diagram of a light-transmitting display area provided in FIG13 after a semiconductor pattern is formed;
  • FIG16B is a schematic diagram of a pattern of a first conductive layer in a light-transmitting display area provided in FIG13 ;
  • FIG16C is a schematic diagram of the light-transmitting display area provided in FIG13 after the first conductive layer pattern is formed;
  • FIG16D is a schematic diagram of a second conductive layer pattern in the light-transmitting display area provided in FIG13 ;
  • FIG16E is a schematic diagram of a light-transmitting display area provided in FIG13 after a second conductive layer pattern is formed;
  • FIG16F is a schematic diagram of a light-transmitting display area provided in FIG13 after a third insulating layer pattern is formed;
  • FIG16G is a schematic diagram of a third conductive layer pattern in the light-transmitting display area provided in FIG13 ;
  • FIG16H is a schematic diagram of the light-transmitting display area of FIG13 after a third conductive layer pattern is formed;
  • FIG16I is a schematic diagram of a light-transmitting display area provided in FIG13 after a fourth insulating layer pattern is formed;
  • FIG16J is a schematic diagram of a transparent conductive layer pattern in a light-transmitting display area provided in FIG13 ;
  • FIG16K is a schematic diagram of a transparent conductive layer pattern formed in the light-transmitting display area provided in FIG13 ;
  • FIG16L is a schematic diagram of a light-transmitting display area provided in FIG13 after a first flat layer is formed;
  • FIG16M is a schematic diagram of a fourth conductive layer pattern in the light-transmitting display area provided in FIG13 ;
  • FIG16N is a schematic diagram of a light-transmitting display area provided in FIG13 after a fourth conductive layer pattern is formed;
  • FIG16O is a schematic diagram of the light-transmitting display area provided in FIG13 after a second planar layer pattern is formed;
  • FIG16P is a schematic diagram of the pattern of the anode conductive layer in the light-transmitting display area provided in FIG13 ;
  • FIG16Q is a schematic diagram of the light-transmitting display area provided in FIG13 after an anode conductive layer pattern is formed;
  • FIG17A is a schematic diagram of a light-transmitting display area provided in FIG14 after a semiconductor pattern is formed;
  • FIG17B is a schematic diagram of the pattern of the first conductive layer in the light-transmitting display area provided in FIG14 ;
  • FIG17C is a schematic diagram of the light-transmitting display area provided in FIG14 after the first conductive layer pattern is formed;
  • FIG17D is a schematic diagram of a second conductive layer pattern in the light-transmitting display area provided in FIG14 ;
  • FIG17E is a schematic diagram of the light-transmitting display area provided in FIG14 after a second conductive layer pattern is formed;
  • FIG17F is a schematic diagram of a light-transmitting display area provided in FIG14 after a third insulating layer pattern is formed;
  • FIG17G is a schematic diagram of a third conductive layer pattern in the light-transmitting display area provided in FIG14 ;
  • FIG17H is a schematic diagram of a light-transmitting display area provided in FIG14 after a third conductive layer pattern is formed;
  • FIG17I is a schematic diagram of a light-transmitting display area provided in FIG14 after a fourth insulating layer pattern is formed;
  • FIG17J is a schematic diagram of a transparent conductive layer pattern in a light-transmitting display area provided in FIG14 ;
  • FIG17K is a schematic diagram of a transparent conductive layer pattern formed in the light-transmitting display area provided in FIG14 ;
  • FIG17L is a schematic diagram of the light-transmitting display area shown in FIG14 after a first flat layer is formed;
  • FIG17M is a schematic diagram of a fourth conductive layer pattern in the light-transmitting display area provided in FIG14 ;
  • FIG17N is a schematic diagram of a light-transmitting display area provided in FIG14 after a fourth conductive layer pattern is formed;
  • FIG17O is a schematic diagram of the light-transmitting display area provided in FIG14 after a second planar layer pattern is formed;
  • FIG17P is a schematic diagram of the pattern of the anode conductive layer in the light-transmitting display area provided in FIG14 ;
  • FIG17Q is a schematic diagram of the light-transmitting display area provided in FIG14 after an anode conductive layer pattern is formed;
  • FIG18 is a schematic diagram of the structure of a display device provided in an embodiment of the present disclosure.
  • Fig. 19 is a cross-sectional view of Fig. 18 along the A-A line.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • electrically connected includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the "element having some electrical function” as long as it can transmit electrical signals between connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having multiple functions.
  • a transistor refers to an element including at least three terminals: a gate, a drain, and a source.
  • a transistor has a channel region between a drain (drain electrode terminal, a drain region, or a drain electrode) and a source (source electrode terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source.
  • a channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the "source electrode” and the “drain electrode” may be interchanged.
  • the gate electrode may also be called a control electrode.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • the "light transmittance" in the present disclosure refers to the ability of light to pass through a medium, which is the percentage of the luminous flux passing through a transparent or translucent body to its incident luminous flux.
  • At least one embodiment of the present disclosure provides a display substrate, comprising: a display area and a peripheral area at least partially surrounding the display area, the display area comprising a light-transmitting display area and a conventional display area located at least on one side of the light-transmitting display area, the light transmittance of the light-transmitting display area being greater than the light transmittance of the conventional display area;
  • the display substrate comprises: a substrate and a plurality of light-emitting elements and a plurality of pixel circuits located on one side of the substrate, the plurality of light-emitting elements comprising a plurality of first-type light-emitting elements located in the light-transmitting display area, the plurality of pixel circuits comprising a plurality of first-type pixel circuits located in the light-transmitting display area, at least one of the plurality of first-type pixel circuits being electrically connected to at least two first-type light-emitting elements emitting light of the same color, the first-type pixel
  • the display substrate provided in the embodiment of the present disclosure reduces the number of first-type pixel circuits in the light-transmitting display area and uses one first-type pixel circuit to drive at least two first-type light-emitting elements that emit light of the same color, thereby ensuring that the resolution (PPI) of the display area of the display substrate is consistent, improving the light transmittance of the light-transmitting display area, and reducing the diffraction of the light-transmitting display area when taking pictures.
  • the display substrate provided in this embodiment can be applied to QHD (Quarter High Definition) display devices. However, this embodiment is not limited to this.
  • an orthographic projection of at least one first type pixel circuit on the substrate overlaps with an orthographic projection of at least some of at least two first type light emitting elements electrically connected to the at least one first type pixel circuit on the substrate.
  • the display substrate may further include: a plurality of first signal lines, at least one of which is electrically connected to at least one first type pixel circuit, wherein the plurality of first signal lines include at least one of the following: a scan signal line, a reset signal line, an initial signal line, and a light emitting signal line.
  • the plurality of first signal lines include a plurality of sub-signal lines; adjacent sub-signal lines of the first signal lines are electrically connected through electrically connected first-type pixel circuits.
  • the display substrate may further include: a plurality of second signal lines, at least one first type pixel circuit being electrically connected to at least one second signal line; the plurality of second signal lines including at least one of the following: a data signal line and a first power line, the plurality of data signal lines and the plurality of first power lines extending along the first direction.
  • the data signal line and the first power line electrically connected to the first type pixel circuit are located between adjacent sub-signal lines of the first signal line, and the orthographic projection of the data signal line and the first power line electrically connected to the first type pixel circuit on the substrate overlaps with the orthographic projection of the first type pixel circuit on the substrate.
  • an orthographic projection of at least one of the scan signal line, the reset signal line, the initial signal line, the light emitting signal line, the data signal line and the first power supply line on the substrate partially overlaps an orthographic projection of the first type light emitting element on the substrate.
  • the plurality of first-type light-emitting elements at least include: a plurality of first light-emitting elements emitting a first color light, a plurality of second light-emitting elements emitting a second color light, and a plurality of third light-emitting elements emitting a third color light.
  • the anode area of at least one of the plurality of first light-emitting elements is greater than the anode area of at least one of the plurality of third light-emitting elements
  • the anode area of at least one of the plurality of second light-emitting elements is greater than the anode area of at least one of the third light-emitting elements.
  • the first color light may be red light
  • the second color light may be blue light
  • the third color light may be green light.
  • FIG. 1 is a schematic diagram of a display substrate of at least one embodiment of the present disclosure.
  • the display substrate may include: a display area AA and a peripheral area BB surrounding the periphery of the display area AA.
  • the display area AA of the display substrate may include: a light-transmitting display area A1 and a conventional display area A2 located on at least one side of the light-transmitting display area A1.
  • the light-transmitting display area A1 is the aforementioned light-transmitting display area, and the light-transmitting display area A1 may also be referred to as an under-display camera (UDC, Under Display Camera) area.
  • UDC Under Display Camera
  • the conventional display area A2 may also be referred to as a normal display area.
  • the orthographic projection of hardware such as a photosensitive sensor (such as a camera, an infrared sensor) on the display substrate may be located within the light-transmitting display area A1 of the display substrate.
  • the light-transmitting display area A1 may be circular, and the size of the orthographic projection of the photosensitive sensor on the display substrate may be less than or equal to the size of the light-transmitting display area A1.
  • this embodiment is not limited to this.
  • the light-transmitting display area may be rectangular, and the size of the orthographic projection of the light-sensitive sensor on the display substrate may be smaller than or equal to the size of the inscribed circle of the light-transmitting display area.
  • the light-transmitting display area A1 may be located at the top center of the display area AA.
  • the conventional display area A2 may surround the light-transmitting display area A1.
  • this embodiment is not limited to this.
  • the light-transmitting display area A1 may be located at other positions such as the upper left corner or the upper right corner of the display area AA.
  • the display area AA may be a rectangle, such as a rounded rectangle.
  • the light-transmitting display area A1 may be a circle or an ellipse. However, this embodiment is not limited thereto.
  • the light-transmitting display area may be a rectangle, a pentagon, a hexagon, or other shapes.
  • the display area AA includes at least a plurality of pixel units arranged regularly, a plurality of gate lines extending along a first direction Y (for example, including: a scanning signal line, a reset signal line, and a light emitting signal line), a plurality of data signal lines extending along a second direction X, and a first power line.
  • the first direction Y and the second direction X are located in the same plane, and the first direction Y intersects with the second direction X, for example, the first direction Y is perpendicular to the second direction X.
  • one pixel unit of the display area AA may include three sub-pixels, and the three sub-pixels may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively.
  • this embodiment is not limited to this.
  • one pixel unit may include four sub-pixels, and the four sub-pixels may be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, respectively.
  • the shape of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the three sub-pixels may be arranged in parallel horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the four sub-pixels may be arranged in parallel horizontally, vertically, or in a square pattern.
  • this embodiment is not limited to this.
  • At least one sub-pixel includes a pixel circuit and a light-emitting element.
  • the pixel circuit is configured to drive an electrically connected light-emitting element.
  • the pixel circuit is configured to provide a driving current to drive the light-emitting element to emit light.
  • the pixel circuit may include a plurality of transistors and at least one capacitor, for example, the pixel circuit may be a 3T1C (3 transistors and 1 capacitor) structure, an 8T1C (8 transistors and 1 capacitor) structure, a 7T1C (7 transistors and 1 capacitor) structure, or a 5T1C (5 transistors and 1 capacitor) structure.
  • the light-emitting element may be an organic light-emitting diode (OLED), which emits red light, green light, blue light, or white light, etc., driven by its corresponding pixel circuit.
  • OLED organic light-emitting diode
  • the light-emitting color of the light-emitting element may be determined as required.
  • the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode.
  • the anode of the light-emitting element may be electrically connected to the corresponding pixel circuit.
  • this embodiment is not limited to this.
  • the display substrate includes: a substrate and a plurality of light-emitting elements and a plurality of pixel circuits located on one side of the substrate.
  • the plurality of light-emitting elements may include a plurality of first-type light-emitting elements L1 located in the light-transmitting display area A1 and a second-type light-emitting element L2 located in the conventional display area A2
  • the plurality of pixel circuits may include a plurality of first-type pixel circuits P1 located in the light-transmitting display area A1 and a second-type pixel circuit P2 located in the conventional display area A2.
  • the light-transmitting display area A1 is provided with a plurality of first-type light-emitting elements and a plurality of first-type pixel circuits. At least one first-type pixel circuit is electrically connected to at least two first-type light-emitting elements emitting light of the same color. That is, at least two sub-pixels of the same color in the light-transmitting display area A1 share a first-type pixel circuit.
  • the conventional display area A2 is provided with a plurality of second-type light-emitting elements and a plurality of second-type pixel circuits. A plurality of second-type light-emitting elements and a plurality of second-type pixel circuits are electrically connected one-to-one.
  • the display substrate of this exemplary embodiment adopts a design in which a first-type pixel circuit drives at least two first-type light-emitting elements in the light-transmitting display area A1, which can ensure that the resolution of the display area of the display substrate is consistent, and improve the light transmittance of the light-transmitting display area, and reduce diffraction when taking pictures.
  • this embodiment is not limited to this.
  • FIG. 2 is a schematic diagram of the arrangement of the first type of light-emitting elements in the light-transmitting display area of at least one embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of the arrangement of the first type of light-emitting elements in the light-transmitting display area of at least one embodiment of the present disclosure.
  • the plurality of first type light-emitting elements in the light-transmitting display area A1 may include: a plurality of first light-emitting elements 11 emitting a first color light, a plurality of second light-emitting elements 12 emitting a second color light, and a plurality of third light-emitting elements 13 emitting a third color light.
  • the first color light may be red light
  • the second color light may be blue light
  • the third color light may be green light. That is, the first light-emitting element 11 may be a red light-emitting element, the second light-emitting element 12 may be a blue light-emitting element, and the third light-emitting element 13 may be a green light-emitting element.
  • this embodiment is not limited to this.
  • a plurality of first-type light-emitting elements of the light-transmitting display area A1 may be arranged in a Pentile structure, wherein a plurality of third light-emitting elements 13 are arranged at certain intervals in the i-th row, the second light-emitting element 12 and the first light-emitting element 11 are alternately arranged in adjacent rows of the i-th row, the first light-emitting element 11 and the second light-emitting element 12 are alternately arranged in the j-th column, a plurality of third light-emitting elements 13 are arranged at certain intervals in adjacent columns of the j-th column, the first light-emitting element 11 and the third light-emitting element 13 are alternately arranged along a third direction F1, the second light-emitting element 12 and the third light-emitting element 13 are alternately arranged along a fourth direction F2, the third direction F1 and the fourth direction F4 intersect with the first direction
  • a plurality of third light-emitting elements 13 are arranged at certain intervals in the i-th row, and the second light-emitting elements 12 and the first light-emitting elements 11 are alternately arranged in the adjacent rows of the i-th row, which means that a plurality of third light-emitting elements 13 are arranged at certain intervals in the i-th row, the second light-emitting elements 12 and the first light-emitting elements 11 are alternately arranged in the i+1th row adjacent to the i-th row, a plurality of third light-emitting elements 13 are arranged at certain intervals in the i+2th row adjacent to the i+1th row, and the first light-emitting elements 11 and the second light-emitting elements 12 are alternately arranged in the i+3th row adjacent to the i+2th row.
  • first-type light-emitting elements can be repeatedly arranged according to the above rule.
  • the first light-emitting element 11 and the second light-emitting element 12 are alternately arranged in the jth column, and the plurality of third light-emitting elements 13 are arranged at a certain interval in the adjacent column of the jth column.
  • first light-emitting element 11 and the second light-emitting element 12 are alternately arranged in the jth column
  • the plurality of third light-emitting elements 13 are arranged at a certain interval in the j+1th column adjacent to the jth column
  • the first light-emitting element 11 and the second light-emitting element 12 are alternately arranged in the j+2th column adjacent to the j+1th column
  • the plurality of third light-emitting elements 13 are arranged at a certain interval in the j+3th column.
  • Multiple columns of first-type light-emitting elements can be repeatedly arranged according to the above rules.
  • the sizes of the first light-emitting element 11 and the second light-emitting element 12 can both be larger than the size of the third light-emitting element 13.
  • i and j are both integers.
  • the light emitting region 110 of the first light emitting element 11, the light emitting region 120 of the second light emitting element 12, and the light emitting region 130 of the third light emitting element 13 may all be circular or elliptical.
  • the light emitting region 110 of the first light emitting element 11 may be larger than the light emitting region 130 of the third light emitting element 13, and the light emitting region 120 of the second light emitting element 12 may be larger than the light emitting region 130 of the third light emitting element 13.
  • the light emitting region of the light emitting element may be a portion of the light emitting element located at a pixel opening of the pixel definition layer.
  • the light-emitting area of the first type of light-emitting element in the light-transmitting display area A1 may be smaller than the light-emitting area of the second type of light-emitting element emitting light of the same color in the conventional display area A2.
  • the area of the light-emitting area of the first type of light-emitting element may be 40% to 60% of the area of the light-emitting area of the second type of light-emitting element emitting light of the same color, for example, may be about 50%.
  • the light-transmitting area of the light-transmitting display area A1 may be increased, thereby improving the light transmittance of the light-transmitting display area A1.
  • the plurality of first-type light-emitting elements of the light-transmitting display area A1 may be arranged in a triangle.
  • the plurality of second light-emitting elements 12 are arranged in the jth column, the first light-emitting element 11 and the third light-emitting element 13 are alternately arranged in the adjacent columns of the jth column, the plurality of second light-emitting elements 12 are arranged in the i-th row, and the first light-emitting element 11 and the third light-emitting element 13 are arranged between the adjacent second light-emitting elements 12 in the same row.
  • the plurality of second light-emitting elements 12 are arranged in the jth column, the first light-emitting element 11 and the third light-emitting element 13 are alternately arranged in the adjacent columns of the jth column, and the plurality of second light-emitting elements 12 are arranged in the jth column at a certain interval, the first light-emitting element 11 and the third light-emitting element 13 are alternately arranged in the j+1th column adjacent to the jth column, the plurality of second light-emitting elements 12 are arranged in the j+2th column adjacent to the j+1th column at a certain interval, and the first light-emitting element 11 and the second light-emitting element 12 are alternately arranged in the j+3th column adjacent to the j+2th column. According to the above rules, multiple columns of first type light emitting elements can be repeatedly arranged.
  • FIG. 4 is a schematic diagram of the arrangement relationship between the first type pixel circuit and the first type light emitting element in the light-transmitting display area provided by an exemplary embodiment
  • FIG. 5 is a schematic diagram of the arrangement relationship between the first type pixel circuit and the first type light emitting element in the light-transmitting display area provided by an exemplary embodiment
  • FIG. 6 is a schematic diagram of the arrangement relationship between the first type pixel circuit and the first type light emitting element in the light-transmitting display area provided by an exemplary embodiment
  • FIG. 7 is a schematic diagram of the arrangement relationship between the first type pixel circuit and the first type light emitting element in the light-transmitting display area provided by an exemplary embodiment
  • FIG. 4 is a schematic diagram of the arrangement relationship between the first type pixel circuit and the first type light emitting element in the light-transmitting display area provided by an exemplary embodiment
  • FIG. 5 is a schematic diagram of the arrangement relationship between the first type pixel circuit and the first type light emitting element in the light-transmitting
  • FIG. 8 is a schematic diagram of the arrangement relationship between the first type pixel circuit and the first type light emitting element in the light-transmitting display area provided by an exemplary embodiment
  • FIG. 9 is a schematic diagram of the arrangement relationship between the first type pixel circuit and the first type light emitting element in the light-transmitting display area provided by an exemplary embodiment.
  • the position of the first type pixel circuit is indicated by a rectangular frame.
  • FIG. 4 and FIG. 5 are illustrated by taking the multiple first type light emitting elements in the light-transmitting display area A1 as an example that can be arranged in a Pentile structure, and FIG. 6 to FIG.
  • FIG. 9 are illustrated by taking the multiple first type light emitting elements in the light-transmitting display area A1 as an example that can be arranged in a shape of a triangle.
  • FIG. 4 to FIG. 9 are all described by taking a first-type pixel circuit connecting two first-type light-emitting elements as an example.
  • the area of the anode 111 of the first light-emitting element (e.g., the first light-emitting elements 11a and 11b) is larger than the area of the anode 131 of the third light-emitting element (e.g., the third light-emitting elements 13a and 13b), and the area of the anode 121 of the second light-emitting element (e.g., the second light-emitting elements 12a and 12b) is larger than the area of the anode 131 of the third light-emitting element (e.g., the third light-emitting elements 13a and 13b).
  • the plurality of first-type pixel circuits include: at least one first pixel circuit, at least one second pixel circuit, at least one third pixel circuit, and at least one fourth pixel circuit; the first pixel circuit is electrically connected to two first light-emitting elements, the second pixel circuit is electrically connected to two second light-emitting elements, the third pixel circuit is electrically connected to two third light-emitting elements, the fourth pixel circuit is electrically connected to two third light-emitting elements, and the third pixel circuit and the fourth pixel circuit are electrically connected to different third light-emitting elements.
  • the plurality of first-type pixel circuits of the light-transmitting display area may include at least: a first pixel circuit 15a, a second pixel circuit 15b, a third pixel circuit 15c, and a fourth pixel circuit 15d.
  • the first pixel circuit 15a is electrically connected to the two first light-emitting elements 11a and 11b that emit the first color light, and is configured to drive the two first light-emitting elements 11a and 11b to emit light.
  • the orthographic projection of the first pixel circuit 15a on the substrate overlaps with the orthographic projection of the anode 111 of the first light-emitting element 11a on the substrate, and does not overlap with the orthographic projection of the anode of the first light-emitting element 11b on the substrate.
  • the second pixel circuit 15b is electrically connected to the two second light-emitting elements 12a and 12b that emit the second color light, and is configured to drive the two second light-emitting elements 12a and 12b to emit light.
  • the orthographic projection of the second pixel circuit 15b on the substrate does not overlap with the orthographic projection of the anode of the second light-emitting element 12a and the second light-emitting element 12b on the substrate, and overlaps with the orthographic projection of the first light-emitting element 11b located between the second light-emitting element 12a and the second light-emitting element 12b on the substrate.
  • the third pixel circuit 15c is electrically connected to the two third light-emitting elements 13a and 13b that emit the third color light, and is configured to drive the two third light-emitting elements 13a and 13b to emit light.
  • the orthographic projection of the third pixel circuit 15c on the substrate overlaps with the orthographic projection of the anode of the second light-emitting element 12a on the substrate, and does not overlap with the orthographic projection of the anode of the two third light-emitting elements 13a and 13b on the substrate.
  • the second light-emitting element 12a overlapping with the third pixel circuit 15c is located in the upper row of the row where the two third light-emitting elements 13a and 13b are located, and is located in the middle column of the column where the two third light-emitting elements 13a and 13b are located.
  • the fourth pixel circuit 15d is electrically connected to the two third light-emitting elements 13c and 13d that emit the third color light, and is configured to drive the two third light-emitting elements 13c and 13d to emit light.
  • the orthographic projection of the fourth pixel circuit 15d on the substrate overlaps with the orthographic projection of the anode of the second light-emitting element 12b on the substrate, and does not overlap with the orthographic projection of the anode of the two third light-emitting elements 13c and 13d on the substrate.
  • the second light-emitting element 12b overlapping with the fourth pixel circuit 15d is located in the upper row of the row where the two third light-emitting elements 13c and 13d are located, and is located in the middle column of the column where the third light-emitting elements 13c and 13d are located.
  • the first type pixel circuit is located under the anode of the first light emitting element or the second light emitting element having a larger anode area, and does not overlap with the anode of the third light emitting element having a smaller anode area.
  • the first type pixel circuit is disposed under the first type light emitting element having a larger anode area, and the first type pixel circuit is not disposed under the first type light emitting element having a smaller anode area, so that the light transmittance of the light-transmitting display area can be improved.
  • the two first light-emitting elements 11a and 11b electrically connected to the first pixel circuit 15a are in the second direction X (i.e., the two first light-emitting elements 11a and 11b are located in the same row), the two second light-emitting elements 12a and 12b electrically connected to the second pixel circuit 15b are in the second direction X (i.e., the two second light-emitting elements 12a and 12b are located in the same row), and the two third light-emitting elements 13a and 13b electrically connected to the third pixel circuit 15c are in the second direction X (i.e., the two third light-emitting elements 13a and 13b are located in the same row).
  • the two third light-emitting elements 13c and 13d electrically connected to the fourth pixel circuit 15d are in the second direction X (i.e., the two third light-emitting elements 13c and 13d are located in the same row).
  • the plurality of first-type pixel circuits in the light-transmitting display area may include at least: a first pixel circuit 15a, a second pixel circuit 15b, a third pixel circuit 15c, and a fourth pixel circuit 15d.
  • the first pixel circuit 15a is electrically connected to the two first light-emitting elements 11a and 11b that emit the first color light, and is configured to drive the two first light-emitting elements 11a and 11b to emit light.
  • the orthographic projection of the first pixel circuit 15a on the substrate overlaps with the orthographic projection of the anode 111 of the first light-emitting element 11a on the substrate, and does not overlap with the orthographic projection of the anode of the first light-emitting element 11b on the substrate.
  • the second pixel circuit 15b is electrically connected to the two second light-emitting elements 12a and 12b that emit the second color light, and is configured to drive the two second light-emitting elements 12a and 12b to emit light.
  • the orthographic projection of the second pixel circuit 15b on the substrate overlaps with the orthographic projection of the anode of the second light-emitting element 12a on the substrate, and does not overlap with the orthographic projection of the anode of the second light-emitting element 12b on the substrate.
  • the third pixel circuit 15c is electrically connected to the two third light-emitting elements 13a and 13b that emit the third color light, and is configured to drive the two third light-emitting elements 13a and 13b to emit light.
  • the orthographic projection of the third pixel circuit 15c on the substrate overlaps with the orthographic projection of the anode of the third light-emitting element 13a on the substrate, and does not overlap with the orthographic projection of the anode of the third light-emitting element 13b on the substrate.
  • the fourth pixel circuit 15d is electrically connected to the two third light-emitting elements 13c and 13d that emit the third color light, and is configured to drive the two third light-emitting elements 13c and 13d to emit light.
  • the orthographic projection of the fourth pixel circuit 15d on the substrate overlaps with the orthographic projection of the anode of the third light-emitting element 13c on the substrate, and does not overlap with the orthographic projection of the anode of the third light-emitting element 13d on the substrate.
  • the two first light emitting elements 11a and 11b electrically connected to the first pixel circuit 15a are in the third direction F1.
  • the two second light emitting elements 12a and 12b electrically connected to the second pixel circuit 15b are in the third direction F1.
  • the two third light emitting elements 13a and 13b electrically connected to the third pixel circuit 15c are in the first direction Y (i.e., the two third light emitting elements 13a and 13b are located in the same column).
  • the two third light emitting elements 13c and 13d electrically connected to the fourth pixel circuit 15d are in the first direction Y (i.e., the two third light emitting elements 13c and 13d are located in the same column).
  • the plurality of first type pixel circuits may include: at least one first pixel circuit, at least one second pixel circuit and at least one third pixel circuit; the first pixel circuit is electrically connected to two first light-emitting elements, the second pixel circuit is electrically connected to two second light-emitting elements and the third pixel circuit is electrically connected to two third light-emitting elements.
  • the plurality of first-type pixel circuits in the light-transmitting display area may include at least: a first pixel circuit 15a, a second pixel circuit 15b, and a third pixel circuit 15c.
  • the first pixel circuit 15a is electrically connected to the two first light-emitting elements 11a and 11b that emit the first color light, and is configured to drive the two first light-emitting elements 11a and 11b to emit light.
  • the orthographic projection of the first pixel circuit 15a on the substrate overlaps with the orthographic projection of the anode 111 of the first light-emitting element 11a on the substrate, and does not overlap with the orthographic projection of the anode of the first light-emitting element 11b on the substrate.
  • the second pixel circuit 15b is electrically connected to the two second light-emitting elements 12a and 12b that emit the second color light, and is configured to drive the two second light-emitting elements 12a and 12b to emit light.
  • the orthographic projection of the second pixel circuit 15b on the substrate overlaps with the orthographic projection of the anode of the second light-emitting element 12a on the substrate, and does not overlap with the orthographic projection of the second light-emitting element 12b on the substrate.
  • the third pixel circuit 15c is electrically connected to the two third light-emitting elements 13a and 13b that emit the third color light, and is configured to drive the two third light-emitting elements 13a and 13b to emit light.
  • the orthographic projection of the third pixel circuit 15c on the substrate overlaps with the orthographic projection of the anode of the third light-emitting element 13a on the substrate, and does not overlap with the orthographic projection of the anode of the third light-emitting element 13b on the substrate.
  • the plurality of first-type pixel circuits in the light-transmitting display area may include at least: a first pixel circuit 15a, a second pixel circuit 15b, and a third pixel circuit 15c.
  • the first pixel circuit 15a is electrically connected to the two first light-emitting elements 11a and 11b that emit the first color light, and is configured to drive the two first light-emitting elements 11a and 11b to emit light.
  • the orthographic projection of the first pixel circuit 15a on the substrate overlaps with the orthographic projection of the anode 111 of the first light-emitting element 11b on the substrate, and does not overlap with the orthographic projection of the anode of the first light-emitting element 11a on the substrate.
  • the second pixel circuit 15b is electrically connected to the two second light-emitting elements 12a and 12b that emit the second color light, and is configured to drive the two second light-emitting elements 12a and 12b to emit light.
  • the orthographic projection of the second pixel circuit 15b on the substrate overlaps with the orthographic projection of the anode of the second light-emitting element 12a on the substrate, and does not overlap with the orthographic projection of the second light-emitting element 12b on the substrate.
  • the third pixel circuit 15c is electrically connected to the two third light-emitting elements 13a and 13b that emit the third color light, and is configured to drive the two third light-emitting elements 13a and 13b to emit light.
  • the orthographic projection of the third pixel circuit 15c on the substrate overlaps with the orthographic projection of the anode of the third light-emitting element 13a on the substrate, and does not overlap with the orthographic projection of the anode of the third light-emitting element 13b on the substrate.
  • the plurality of first-type pixel circuits in the light-transmitting display area may include at least: a first pixel circuit 15a, a second pixel circuit 15b, and a third pixel circuit 15c.
  • the first pixel circuit 15a is electrically connected to the two first light-emitting elements 11a and 11b that emit the first color light, and is configured to drive the two first light-emitting elements 11a and 11b to emit light.
  • the orthographic projection of the first pixel circuit 15a on the substrate overlaps with the orthographic projection of the anode 111 of the first light-emitting element 11a on the substrate, and does not overlap with the orthographic projection of the anode of the first light-emitting element 11b on the substrate.
  • the second pixel circuit 15b is electrically connected to the two second light-emitting elements 12a and 12b that emit the second color light, and is configured to drive the two second light-emitting elements 12a and 12b to emit light.
  • the orthographic projection of the second pixel circuit 15b on the substrate overlaps with the orthographic projection of the anode of the second light-emitting element 12a on the substrate, and does not overlap with the orthographic projection of the second light-emitting element 12b on the substrate.
  • the third pixel circuit 15c is electrically connected to the two third light-emitting elements 13a and 13b that emit the third color light, and is configured to drive the two third light-emitting elements 13a and 13b to emit light.
  • the orthographic projection of the third pixel circuit 15c on the substrate does not overlap with the orthographic projection of the anodes of the two third light-emitting elements 13a and 13b on the substrate, but overlaps with the orthographic projection of the anode of the second light-emitting element 12b located between the two third light-emitting elements 13a and 13b on the substrate.
  • the plurality of first-type pixel circuits in the light-transmitting display area may include at least: a first pixel circuit 15a, a second pixel circuit 15b, and a third pixel circuit 15c.
  • the first pixel circuit 15a is electrically connected to the two first light-emitting elements 11a and 11b that emit the first color light, and is configured to drive the two first light-emitting elements 11a and 11b to emit light.
  • the orthographic projection of the first pixel circuit 15a on the substrate does not overlap with the orthographic projection of the anode 111 of the first light-emitting elements 11a and 11b on the substrate, and overlaps with the orthographic projection of the anode of the second light-emitting element 12b located between the first light-emitting elements 11a and 11b on the substrate.
  • the second pixel circuit 15b is electrically connected to the two second light-emitting elements 12a and 12b that emit the second color light, and is configured to drive the two second light-emitting elements 12a and 12b to emit light.
  • the orthographic projection of the second pixel circuit 15b on the substrate overlaps with the orthographic projection of the anode of the second light-emitting element 12a on the substrate, and does not overlap with the orthographic projection of the second light-emitting element 12b on the substrate.
  • the third pixel circuit 15c is electrically connected to the two third light-emitting elements 13a and 13b that emit the third color light, and is configured to drive the two third light-emitting elements 13a and 13b to emit light.
  • the orthographic projection of the third pixel circuit 15c on the substrate overlaps with the orthographic projection of the anode of the third light-emitting element 13a on the substrate, and does not overlap with the orthographic projection of the anode of the third light-emitting element 13b on the substrate.
  • the two first light-emitting elements 11a and 11b electrically connected to the first pixel circuit 15a are in the second direction X (i.e., the two first light-emitting elements 11a and 11b are located in the same row)
  • the two second light-emitting elements 12a and 12b electrically connected to the second pixel circuit 15b are in the second direction X (i.e., the two second light-emitting elements 12a and 12b are located in the same row)
  • the two third light-emitting elements 13a and 13b electrically connected to the third pixel circuit 15c are in the second direction X (i.e., the two third light-emitting elements 13a and 13b are located in the same row).
  • FIG7 is described by taking the first light-emitting element overlapping the first pixel circuit, the second light-emitting element overlapping the second pixel circuit, and the third light-emitting element overlapping the third pixel circuit as an example in which the first light-emitting element overlapping the first pixel circuit, the second light-emitting element overlapping the second pixel circuit, and the third light-emitting element overlapping the third pixel circuit are located in the same light-emitting unit
  • FIG6, FIG8 and FIG9 are described by taking the first light-emitting element overlapping the first pixel circuit, the second light-emitting element overlapping the second pixel circuit, and the third light-emitting element overlapping the third pixel circuit as an example in which the first light-emitting element overlapping
  • a first-type pixel circuit in a light-transmitting display area, is used to drive at least two first-type light-emitting elements that emit light of the same color, and the first-type pixel circuit is arranged under an anode having a first light-emitting element, a second light-emitting element, and a third light-emitting element. This can improve light transmittance while ensuring the resolution of the display substrate.
  • FIG10 is an equivalent circuit diagram of a first type pixel circuit.
  • the first type pixel circuit of this exemplary embodiment may be an 8T1C structure, that is, including a first transistor T1 to a seventh transistor T7 and a capacitor C.
  • the first type light emitting elements EL1 and EL2 may emit light of the same color, and may each include an anode, a cathode, and an organic light emitting layer located between the anode and the cathode.
  • the third transistor T3 is a driving transistor.
  • the first type pixel circuit is electrically connected to a scan signal line Gate, a reset signal line RST, an initial signal line INIT, a light emitting signal line EM, a data signal line Data, a first power line VDD, and a second power line VSS.
  • the first power line VDD is configured to provide a constant first voltage signal to the first type pixel circuit
  • the second power line VSS is configured to provide a constant second voltage signal to the first type pixel circuit
  • the voltage value of the first voltage signal is greater than the voltage value of the second voltage signal.
  • the scan signal line Gate is configured to provide a scan signal to the first type pixel circuit
  • the data signal line Data is configured to provide a data signal to the first type pixel circuit
  • the light emitting signal line EM is configured to provide a light emitting control signal to the first type pixel circuit
  • the reset signal line RST is configured to provide a reset control signal to the first type pixel circuit.
  • the reset signal line RST can be connected to the scan signal line Gate of the first type pixel circuit of the n-1th row. In this way, the signal lines of the display substrate can be reduced to achieve a narrow frame of the display substrate.
  • a control electrode of the first transistor T1 is electrically connected to a reset signal line RST, a first electrode of the first transistor T1 is electrically connected to an initial signal line INIT, and a second electrode of the first transistor T1 is electrically connected to a first node N1.
  • a control electrode of the second transistor T2 is electrically connected to a scan signal line Gate, a first electrode of the second transistor T2 is electrically connected to a first node N1, and a second electrode of the second transistor T2 is electrically connected to a third node N3.
  • a control electrode of the third transistor T3 is electrically connected to the first node N1, a first electrode of the third transistor T3 is electrically connected to a second node N2, and a second electrode of the third transistor T3 is electrically connected to a third node N3.
  • a control electrode of the fourth transistor T4 is electrically connected to a scan signal line Gate, a first electrode of the fourth transistor T4 is electrically connected to a data signal line Data, and a second electrode of the fourth transistor T4 is electrically connected to a second node N2.
  • a control electrode of the fifth transistor T5 is electrically connected to a light emitting signal line EM, a first electrode of the fifth transistor T5 is electrically connected to a first power supply line VDD, and a second electrode of the fifth transistor T5 is electrically connected to a second node N2.
  • the control electrode of the sixth transistor T6 is electrically connected to the light emitting signal line EM, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4.
  • the control electrode of the seventh transistor T7 is electrically connected to the scanning signal line Gate, the first electrode of the seventh transistor T7 is electrically connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4.
  • the first plate of the capacitor C is electrically connected to the first node N1, and the second plate of the capacitor C is electrically connected to the first power supply line VDD.
  • the first node N1 is the connection point of the capacitor C
  • the first transistor T1 and the third transistor T3 is the connection point of the fifth transistor T5, the fourth transistor T4 and the third transistor T3
  • the third node N3 is the connection point of the third transistor T3, the second transistor T2 and the sixth transistor T6, and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the two first type light-emitting elements EL1 and EL2.
  • the first to seventh transistors T1 to T7 of the first type pixel circuit may all be P-type transistors, or may all be N-type transistors.
  • the first type transistor of the first type pixel circuit may be a low temperature polysilicon thin film transistor or an oxide thin film transistor.
  • the active layer of the low temperature polysilicon thin film transistor is low temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide).
  • LTPS low temperature polysilicon
  • Oxide oxide semiconductor
  • Low temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current. Integrating low temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate to form a low temperature polycrystalline oxide (LTPO) display substrate can take advantage of the advantages of both, realize low frequency driving, reduce power consumption, and improve display quality.
  • this embodiment is not limited to this.
  • multiple transistors of the first type pixel circuit may all be low temperature polysilicon thin film transistors, or oxide thin film transistors.
  • Fig. 11 is a working timing diagram of the first type pixel circuit provided in Fig. 10. The working process of the first type pixel circuit shown in Fig. 10 is described below with reference to Fig. 11.
  • the first transistor T1 to the seventh transistor T7 of the first type pixel circuit are P-type transistors.
  • the operation process of the first type pixel circuit may include: a first stage S1 , a second stage S2 , and a third stage S3 .
  • the first stage S1 is called the reset stage.
  • the signal provided by the reset signal line RST is a low-level signal, which turns on the first transistor T1.
  • the initial signal provided by the initial signal line INIT is provided to the first node N1, initializes the first node N1, and clears the original data voltage in the capacitor C.
  • the signal provided by the scanning signal line Gate is a high-level signal
  • the light-emitting control signal EM provided by the light-emitting signal line EM is a high-level signal, which turns off the fourth transistor T4, the second transistor T2, the seventh transistor T7, the fifth transistor T5, and the sixth transistor T6.
  • the first type light-emitting elements EL1 and EL2 do not emit light.
  • the second stage S2 is called the data writing stage or the threshold compensation stage.
  • the signal provided by the scanning signal line Gate is a low-level signal, and the data signal line Data outputs data.
  • the third transistor T3 is turned on.
  • the signal provided by the scanning signal line Gate turns on the second transistor T2, the fourth transistor T4 and the seventh transistor T7, and the second transistor T2 and the fourth transistor T4 are turned on, so that the data voltage Vdata output by the data signal line Data is provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage Vdata output by the data signal line Data and the threshold voltage of the third transistor T3 is charged into the capacitor C, and the voltage of the first electrode of the capacitor C (i.e., the first node N1) is Vdata-
  • the seventh transistor T7 is turned on, so that the initial signal Vinit provided by the initial signal line INIT is provided to the fourth node N4, the anodes of the two first-type light-emitting elements EL1 and EL2 are initialized (reset), the pre-stored voltage inside them is cleared, and the initialization is completed to ensure that the first-type light-emitting elements EL1 and EL2 do not emit light.
  • the signal provided by the reset signal line RST is a high-level signal, which turns off the first transistor T1.
  • the signal provided by the light-emitting signal line EM is a high-level signal, which turns off the fifth transistor T5 and the sixth transistor T6.
  • the third stage S3 is called the light-emitting stage.
  • the signal provided by the light-emitting signal line EM is a low-level signal, which turns on the fifth transistor T5 and the sixth transistor T6.
  • the signals provided by the scanning signal line Gate and the reset signal line RST are high-level signals, which turns off the second transistor T2, the fourth transistor T4, the seventh transistor T7 and the first transistor T1.
  • the first voltage signal output by the first power line VDD provides a driving voltage to the anodes of the first-type light-emitting elements EL1 and EL2 through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the two first-type light-emitting elements EL1 and EL2 to emit light.
  • the driving current flowing through the third transistor T3 is determined by the voltage difference between its control electrode and the first electrode. Since the voltage of the first node N1 is Vdata-
  • )-Vth] 2 K ⁇ [VDD-Vdata] 2 ;
  • I is the driving current flowing through the third transistor T3, that is, the driving current driving the first type light-emitting element
  • K is a constant
  • Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3
  • Vth is the threshold voltage of the third transistor T3
  • Vdata is the data voltage output by the data signal line Data
  • VDD is the first voltage signal output by the first power line PL1.
  • the first type pixel circuit of this embodiment can better compensate for the threshold voltage of the third transistor T3.
  • Fig. 12 is a partial top view 1 of a light-transmitting display area provided by an exemplary embodiment
  • Fig. 13 is a partial top view 2 of a light-transmitting display area provided by an exemplary embodiment
  • Fig. 14 is a partial top view 3 of a light-transmitting display area provided by an exemplary embodiment.
  • Fig. 12 is illustrated by taking the light-transmitting display area provided by Fig. 4 as an example
  • Fig. 13 is illustrated by taking the light-transmitting display area provided by Fig. 5 as an example
  • Fig. 14 is illustrated by taking the light-transmitting display area provided by Fig. 6 as an example.
  • the first type pixel circuit includes: a plurality of transistors and at least one capacitor; in a direction perpendicular to the display substrate, the light-transmitting display area includes at least: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a transparent conductive layer, a first flat layer, a fourth conductive layer and a second flat layer arranged on a substrate.
  • the semiconductor layer includes at least: an active layer of a plurality of transistors of a first type pixel circuit;
  • the first conductive layer at least includes: control electrodes of a plurality of transistors of the first type pixel circuit and a first electrode plate of the capacitor;
  • the second conductive layer at least includes: a second plate of a capacitor of the first type pixel circuit;
  • the third conductive layer at least includes: first electrodes and second electrodes of a plurality of transistors of the first type pixel circuit and a plurality of connection electrodes;
  • the transparent conductive layer at least includes: a plurality of first signal lines, a plurality of second signal lines and a plurality of anode connection lines, at least one anode connection line of the plurality of anode connection lines is electrically connected to at least one first type pixel circuit and anodes of at least two first type light emitting elements emitting light of the same color; at least one first type pixel circuit is electrically connected to at least one first signal line and at least one second signal line;
  • the fourth conductive layer at least includes: a plurality of signal connection lines.
  • At least one first signal line includes a plurality of sub-signal lines; adjacent sub-signal lines of the first signal line are electrically connected via a first type pixel circuit.
  • the plurality of first signal lines include at least one of the following: a scan signal line, a reset signal line, an initial signal line, and a light-emitting signal line.
  • the scan signal line includes two sub-signal lines Gate_1 and Gate_2, the reset signal line includes two sub-signal lines RST_1 and RST_2, the initial signal line includes two sub-signal lines INIT_1 and INIT_2, and the light-emitting signal line includes two sub-signal lines EM_1 and EM_2.
  • the plurality of second signal lines include: a plurality of data signal lines Data and a plurality of first power lines VDD, and at least portions of the data signal lines Data and the first power lines VDD extend along a first direction Y.
  • the data signal lines Data and the first power lines VDD electrically connected to the first type pixel circuit are located between adjacent sub-signal lines of the first signal line, and their orthographic projections on the substrate overlap with the orthographic projections of the first type pixel circuit on the substrate.
  • the sub-signal line of the first signal line is in a zigzag shape, and at least a portion of the sub-signal line of the first signal line extends along the second direction X.
  • the anode connection line may include: a first anode connection line AL1, a second anode connection line AL2, a third anode connection line AL3, and a fourth anode connection line AL4.
  • the first anode connection line AL1, the second anode connection line AL2, the third anode connection line AL3, and the fourth anode connection line AL4 may be in a zigzag shape.
  • the first anode connection line AL1 is electrically connected to the first pixel circuit and the first light emitting element, respectively, and at least a portion of the first anode connection line AL1 may extend along the second direction X.
  • the second anode connection line AL2 is electrically connected to the second pixel circuit and the second light emitting element, respectively, and at least a portion of the second anode connection line AL2 extends along the second direction X.
  • the third anode connection line AL3 is electrically connected to the third pixel circuit and the third light emitting element, respectively, and at least a portion of the third anode connection line AL3 extends along the second direction X, and the third anode connection line AL3 is located between the data signal line Data electrically connected to the third pixel circuit and the first power line VDD.
  • the fourth anode connection line AL4 is electrically connected to the fourth pixel circuit and the third light emitting element respectively, and at least a portion of the fourth anode connection line AL4 extends along the second direction X.
  • the fourth anode connection line AL4 is located between the data signal line Data electrically connected to the fourth pixel circuit and the first power line VDD.
  • first power lines electrically connected to at least two adjacent first-type pixel circuits in the same column are spaced apart, and the spaced apart first power lines in the same column are electrically connected via at least one signal connection line located in the fourth conductive layer.
  • data signal lines Data electrically connected to at least two adjacent first-type pixel circuits in the same column are arranged at intervals, and the spaced data signal lines Data in the same column are electrically connected through at least one signal connection line located in the fourth conductive layer.
  • the sub-signal line of the first signal line is a zigzag line type, and at least a portion of the sub-signal line of the first signal line extends along the first direction Y.
  • the anode connection line includes: a first anode connection line AL1, a second anode connection line AL2, a third anode connection line AL3, and a fourth anode connection line AL4.
  • the first anode connection line AL1, the second anode connection line AL2, the third anode connection line AL3, and the fourth anode connection line AL4 may be in a zigzag shape.
  • the first anode connection line AL1 is electrically connected to the first pixel circuit and the first light-emitting element, respectively, and at least a portion of the first anode connection line AL1 extends along the first direction Y.
  • the second anode connection line AL2 is electrically connected to the second pixel circuit and the second light-emitting element, respectively, and at least a portion of the second anode connection line AL2 extends along the first direction Y.
  • the third anode connection line AL3 is electrically connected to the third pixel circuit and the third light-emitting element, and at least a portion of the third anode connection line AL3 extends along the first direction Y, and the third anode connection line AL3 is located on the side of the first power line VDD electrically connected to the third pixel circuit away from the data signal line Data.
  • the fourth anode connection line AL4 is electrically connected to the fourth pixel circuit and the third light emitting element respectively, and at least part of the fourth anode connection line AL4 extends along the first direction Y.
  • the fourth anode connection line AL4 is located on the side of the first power line VDD electrically connected to the fourth pixel circuit away from the data signal line Data.
  • the data signal line Data electrically connected to the first-type pixel circuits located in the same column is the same signal line.
  • the first power lines VDD electrically connected to at least two adjacent first-type pixel circuits in the same column are spaced apart, and the spaced apart first power lines VDD in the same column are electrically connected through at least one signal connection line located in the fourth conductive layer.
  • the transparent conductive layer may further include: a power connection line VCL, at least a portion of which extends along the second direction X.
  • the power connection line VCL is electrically connected to first power lines VDD electrically connected to two adjacent pixel circuits located in the same row, respectively, and the first power line VDD and the power connection line VCL are electrically connected via a connection electrode located in the third conductive layer.
  • the first power line VDD may include: a power main body portion VDDM extending along the first direction Y and a power connection portion VDDS extending at least partially along the second direction X, the power connection portion VDDS being located on a side of the power main body portion VDDM away from the data signal line.
  • the power connection line VDDS is electrically connected to the power connection portion of one of the first-type pixel circuits and the power main body portion of another first-type pixel circuit in adjacent first-type pixel circuits located in the same row, respectively.
  • the sub-signal lines of the first signal line may be of a zigzag type, and at least a portion of the sub-signal lines of the first signal line may extend along the second direction X.
  • the anode connection line may include: a first anode connection line AL1, a second anode connection line AL2, and a third anode connection line AL3; the first anode connection line AL1, the second anode connection line AL2, and the third anode connection line AL3 may be in a zigzag shape.
  • the first anode connection line AL1 is electrically connected to the first pixel circuit and the first light emitting element, respectively, and at least a portion of the first anode connection line AL1 extends along the second direction X;
  • the second anode connection line AL2 is electrically connected to the second pixel circuit and the second light emitting element, respectively, and at least a portion of the second anode connection line AL2 extends along the second direction X;
  • the third anode connection line AL3 is electrically connected to the third pixel circuit and the third light emitting element, respectively, and at least a portion of the third anode connection line AL3 extends along the second direction X.
  • the data signal line Data electrically connected to the pixel circuits in the same column is the same signal line.
  • the first power lines VDD electrically connected to at least two adjacent first-type pixel circuits in the same column are spaced apart, and the spaced apart first power lines VDD in the same column are electrically connected through at least one signal connection line located in the fourth conductive layer.
  • the structure of the display substrate is explained below by an example of the preparation process of the display substrate.
  • the "patterning process" mentioned in the embodiment of the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials.
  • Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition
  • coating can be any one or more of spraying, spin coating and inkjet printing
  • etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure.
  • Thin film refers to a layer of thin film made by deposition, coating or other processes on a substrate of a certain material. If the “thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the preparation process of the light-transmitting display area provided in FIG. 12 may include the following operations.
  • Forming a semiconductor layer pattern may include: sequentially depositing a semiconductor thin film on a substrate, patterning the semiconductor thin film through a patterning process, and forming a semiconductor layer pattern, as shown in FIG. 15A , which is a schematic diagram of the light-transmitting display area provided in FIG. 12 after a semiconductor pattern is formed.
  • the semiconductor layer pattern includes: an active layer T11 of a first transistor to an active layer T71 of a seventh transistor.
  • the active layers T11 of the first transistor to the active layer T71 of the seventh transistor are an integral structure connected to each other.
  • the active layer T21 of the second transistor, the active layer T61 of the sixth transistor, and the active layer T71 of the seventh transistor may be located on the same side of the active layer T31 of the third transistor in the present subpixel
  • the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor may be located on the same side of the active layer T31 of the third transistor in the present subpixel
  • the active layer T21 of the second transistor and the active layer T41 of the fourth transistor may be located on different sides of the active layer T31 of the third transistor in the present subpixel.
  • the active layer T11 of the first transistor, the active layer T21 of the second transistor, the active layer T41 of the fourth transistor, and the active layer T71 of the seventh transistor may be located on the same side of the active layer T31 of the third transistor in the present subpixel, and the active layer T51 of the fifth transistor and the active layer T61 of the sixth transistor may be located on the other side of the active layer T31 of the third transistor in the present subpixel.
  • the active layer T11 of the first transistor may have an “n” shape
  • the active layer T21 of the second transistor may have an “L” shape
  • the active layer T31 of the third transistor may have an “ ⁇ ” shape
  • the active layer T41 of the fourth transistor the active layer T51 of the fifth transistor, the active layer T61 of the sixth transistor
  • the active layer T71 of the seventh transistor may have an “I” shape.
  • forming the first conductive layer pattern may include: depositing a first insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film by a patterning process, forming a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern located on the first insulating layer, as shown in FIG. 15B and FIG. 15C, wherein FIG. 15B is a schematic diagram of the first conductive layer pattern of the light-transmitting display area provided in FIG. 12, and FIG. 15C is a schematic diagram of the light-transmitting display area provided in FIG. 12 after the first conductive layer pattern is formed.
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern may include control electrodes T12 of the first transistor to T72 of the seventh transistor and a first plate C1 of the capacitor.
  • the shape of the first electrode plate C1 of the capacitor may be rectangular, and the corners of the rectangle may be chamfered, and the orthographic projection of the first electrode plate C1 of the capacitor on the substrate at least partially overlaps the orthographic projection of the active layer of the third transistor T3 on the substrate.
  • the first electrode plate C1 of the capacitor may also serve as the control electrode T32 of the third transistor.
  • the shape of the control electrode T12 of the first transistor may be a line shape extending in the second direction X. As shown in FIGS. 15B and 15C , the shape of the control electrode T12 of the first transistor may be a line shape extending in the second direction X. As shown in FIGS. 15B and 15C , the shape of the control electrode T12 of the first transistor may be a line shape extending in the second direction X. As shown in FIGS.
  • control electrode T22 of the second transistor, the control electrode T42 of the fourth transistor, and the control electrode T72 of the seventh transistor may be an integrally formed structure, and may be in the shape of a line extending along the second direction X.
  • control electrode T52 of the fifth transistor and the control electrode T62 of the sixth transistor may be an integrally formed structure, and may be in the shape of a line extending along the second direction X. As shown in FIG.
  • the semiconductor layer can be conductorized using the first conductive layer as a shield, and the semiconductor layer in the area shielded by the first conductive layer forms the channel area of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of the active layer of the first transistor to the seventh transistor are both conductorized, and the first area of the active layer of the third transistor after conductorization (also the second area of the active layer of the fourth transistor and the second area of the active layer of the fifth transistor) can simultaneously serve as the first electrode T33 of the third transistor, the second electrode T44 of the fourth transistor, and the second electrode T54 of the fifth transistor, and the second area of the active layer of the third transistor after conductorization (also the second area of the active layer of the second transistor and the first area of the active layer of the sixth transistor) also simultaneously serves as the second electrode T24
  • forming the second conductive layer pattern may include: depositing a second insulating layer film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process, and forming a second conductive layer pattern on the second insulating layer.
  • Figure 15D is a schematic diagram of the second conductive layer pattern of the light-transmitting display area provided in Figure 12
  • Figure 15E is a schematic diagram of the light-transmitting display area provided in Figure 12 after the second conductive layer pattern is formed.
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the second conductive layer pattern may include a first connection electrode VL1 and a second plate C2 of a capacitor.
  • At least a portion of the first connection electrode VL1 may extend in the second direction X. As shown in FIGS. 15D and 15E , at least a portion of the first connection electrode VL1 may extend in the second direction X. As shown in FIGS. 15D and 15E , at least a portion of the first connection electrode VL1 may extend in the second direction X. As shown in FIGS. 15D and 15E , at least a portion of the first connection electrode VL1 may extend in the second direction X. As shown in FIGS.
  • the contour shape of the second electrode plate C2 may be "L" shaped, and the orthographic projection of the second electrode plate C2 on the substrate overlaps with the orthographic projection of the first electrode plate C1 on the substrate, and the second electrode plate C2 serves as another electrode plate of the capacitor.
  • the first electrode plate C1 and the second electrode plate C2 constitute the capacitor of the pixel circuit.
  • forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer covering the second conductive layer, wherein a plurality of vias are provided on the third insulating layer, as shown in FIG. 15F , wherein FIG. 15F is a schematic diagram of the light-transmitting display area provided in FIG. 12 after the third insulating layer pattern is formed.
  • the multiple vias may each include: first vias V1 to sixth vias V6 arranged in the first insulating layer to the third insulating layer, seventh vias V7 to thirteenth vias V13 arranged in the second insulating layer and the third insulating layer, and fourteenth vias V14 to sixteenth vias V16 arranged on the third insulating layer.
  • the first via hole V1 exposes the connecting portion of the active layer of the first transistor and the active layer of the second transistor
  • the second via hole V2 exposes the connecting portion of the active layer of the first transistor and the active layer of the seventh transistor
  • the third via hole V3 exposes the active layer of the fourth transistor
  • the fourth via hole V4 exposes the active layer of the fifth transistor
  • the fifth via hole V5 exposes the active layer of the sixth transistor
  • the sixth via hole V6 exposes the active layer of the seventh transistor
  • the seventh via hole V7 and the eighth via hole V8 respectively expose the two ends of the control electrode of the first transistor
  • the ninth via hole V10 and the tenth via hole V11 respectively expose the two ends of the integrated structure of the control electrode of the second transistor
  • the eleventh via hole V11 and the twelfth via hole V12 respectively expose the two ends of the integrated structure of the control electrode of the fifth transistor and the control electrode of the sixth transistor
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the third insulating layer, as shown in FIGS. 15G and 15H , where FIG. 15G is a schematic diagram of the third conductive layer pattern of the light-transmitting display area provided in FIG. 12 , and FIG. 15H is a schematic diagram of the light-transmitting display area provided in FIG. 12 after the third conductive layer pattern is formed.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the third conductive layer pattern may include: a first electrode T13 and a second electrode T14 of the first transistor, a first electrode T23 of the second transistor, a first electrode T43 of the fourth transistor, a first electrode T53 of the fifth transistor, a second electrode T64 of the sixth transistor, a first electrode T73 and a second electrode T74 of the seventh transistor, second to eleventh connection electrodes VL2 to VL11, and a shielding electrode SL.
  • the first electrode T13 of the first transistor can be used as the first electrode T73 of the seventh transistor at the same time
  • the second electrode T14 of the first transistor can be used as the first electrode T23 of the second transistor at the same time
  • the second electrode T64 of the sixth transistor can be used as the second electrode T74 of the seventh transistor at the same time
  • the first electrode T43 of the fourth transistor and the first electrode T53 of the fifth transistor can be provided separately.
  • the first electrode T13 of the first transistor and the second electrode T14 of the first transistor can be L-shaped, the first electrode T43 of the fourth transistor is a block structure, the first electrode T53 of the fifth transistor is a horizontally flipped "L" shape, and the second electrode of the sixth transistor can be a zigzag shape extending along the first direction Y.
  • the second to eighth connection electrodes VL2 to VL8 are block structures, and the ninth to eleventh connection electrodes VL9 to VL11 are line shapes extending in the first direction Y or zigzag shapes.
  • the shielding electrode SL is a block-shaped structure, and an orthographic projection on the substrate partially overlaps an orthographic projection of the control electrode of the first transistor on the substrate.
  • the first electrode T13 of the first transistor is electrically connected to the connection point of the active layer of the first transistor and the active layer of the seventh transistor through the second via hole, and is electrically connected to the first connection electrode through the sixteenth via hole
  • the second electrode T14 of the first transistor is electrically connected to the connection point of the active layer of the first transistor and the active layer of the second transistor through the first via hole, and is electrically connected to the first plate of the capacitor through the thirteenth via hole
  • the first electrode T43 of the fourth transistor is electrically connected to the active layer of the fourth transistor through the third via hole
  • the first electrode T53 of the fifth transistor is electrically connected to the active layer of the fifth transistor through the fourth via hole, and is electrically connected to the second plate of the capacitor through the fourteenth via hole
  • the second electrode T64 of the sixth transistor is electrically connected to the active layer of the sixth transistor through the fifth via hole, and is electrically connected to the active layer of the seventh transistor through the sixth via hole.
  • the second connection electrode VL2 is electrically connected to the control electrode of the first transistor through the seventh via hole.
  • the third connection electrode VL3 is electrically connected to the control electrode of the first transistor through the eighth via hole.
  • the fourth connection electrode VL4 is electrically connected to the control electrode of the fourth transistor through the ninth via
  • the fifth connection electrode VL5 is electrically connected to the control electrode of the fourth transistor through the tenth via
  • the sixth connection electrode VL6 is electrically connected to the control electrode of the fifth transistor through the eleventh via
  • the seventh connection electrode VL7 is electrically connected to the control electrode of the fifth transistor through the twelfth via
  • the eighth connection electrode VL8 is electrically connected to the first connection electrode through the fifteenth via.
  • forming a fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the third conductive layer, wherein a plurality of vias are provided on the fourth insulating layer, as shown in FIG15I.
  • FIG15I is a schematic diagram of the light-transmitting display area provided in FIG12 after the fourth insulating layer pattern is formed.
  • the plurality of vias of the fourth insulating layer pattern may each include: a seventeenth via V17 to a thirty-first via V31.
  • the seventeenth via V17 exposes the first electrode of the first transistor
  • the eighteenth via V18 exposes the first electrode of the fourth transistor
  • the nineteenth via V19 exposes the first electrode of the fifth transistor
  • the twentieth via V20 exposes the second electrode of the sixth transistor
  • the twenty-first via V21 exposes the second connection electrode
  • the twenty-second via V22 exposes the third connection electrode
  • the twenty-third via V23 exposes the fourth connection electrode
  • the twenty-fourth via V24 exposes the fifth connection electrode
  • the twenty-fifth via V25 exposes the sixth connection electrode
  • the twenty-sixth via V26 exposes the seventh connection electrode
  • the twenty-seventh via V27 exposes the eighth connection electrode
  • the twenty-eighth via V28 exposes the shielding electrode
  • the twenty-ninth via V29 exposes the ninth connection electrode
  • the number of the twenty-ninth via holes V29 may be two, and the two twenty-ninth via holes may be arranged along the first direction Y and respectively located at two ends of the ninth connection electrode.
  • the number of the thirtieth via holes V30 may be two, and the two thirtieth via holes V30 may be arranged along the first direction Y and respectively located at both ends of the tenth connection electrode.
  • the number of the thirty-first via holes V31 may be two, and the two thirty-first via holes V31 may be arranged along the first direction Y and respectively located at both ends of the eleventh connection electrode.
  • Forming a transparent conductive layer pattern may include: depositing a transparent conductive film on the substrate on which the aforementioned pattern is formed, patterning the transparent conductive film using a patterning process, and forming a transparent conductive layer disposed on the fourth insulating layer, as shown in FIGS. 15J and 15K , wherein FIG. 15J is a schematic diagram of a transparent conductive layer pattern in the light-transmitting display area provided in FIG. 12 , and FIG. 15K is a schematic diagram of a transparent conductive layer pattern after the transparent conductive layer pattern is formed in the light-transmitting display area provided in FIG. 12 .
  • the transparent conductive layer pattern may include: a data signal line Data, a first power line VDD, a first anode connecting line AL1, a second anode connecting line AL2, a third anode connecting line AL3, a fourth anode connecting line AL4, two sub-signal lines INIT_1 and INIT_2 of an initial signal line, two sub-signal lines RST_1 and RST_2 of a reset signal line, two sub-signal lines Gate_1 and Gate_2 of a scan signal line, two sub-signal lines EM_1 and EM_2 of a light emitting signal line, a twelfth connecting electrode VL12, and a thirteenth connecting electrode VL13.
  • the data signal line Data and the first power line VDD can be located between two sub-signal lines of a plurality of first signal lines electrically connected to a first type pixel circuit electrically connected to the data signal line Data and the first power line VDD, and their orthographic projections on the substrate overlap with the orthographic projections of the first type pixel circuit on the substrate.
  • the data signal line Data may be a zigzag line, at least a portion of the data signal line Data may extend along the first direction Y, and the data signal line Data electrically connected to adjacent first-type pixel circuits in the same column may be the same signal line, or may be arranged at intervals.
  • the data signal lines Data electrically connected to two adjacent first-type pixel circuits in the same column arranged at intervals may be electrically connected to the ninth connection electrode through the twenty-ninth via hole, respectively, and the data signal lines Data electrically connected to the first-type pixel circuits arranged at intervals in the same column may be electrically connected through the ninth connection electrode.
  • the data signal line is electrically connected to the first electrode of the fourth transistor of the electrically connected first-type pixel circuit through the eighteenth via hole.
  • the first power line VDD may be a zigzag line, at least a portion of the first power line VDD may extend along the first direction Y, and the first power lines VDD electrically connected to adjacent first-type pixel circuits in the same column may be arranged at intervals.
  • the first power line is electrically connected to the first electrode of the fifth transistor of the electrically connected first-type pixel circuit through the nineteenth via, and is electrically connected to the shielding electrode through the twenty-eighth via.
  • the first power lines VDD electrically connected to two adjacent first-type pixel circuits in the same column arranged at intervals may be directly electrically connected through a tenth connection electrode, or may be electrically connected through the tenth connection electrode, the twelfth connection electrode, and the tenth connection electrode, respectively.
  • the first power line VDD electrically connected to the first-type pixel circuit and the twelfth connection electrode may be electrically connected to the tenth connection electrode through the thirtieth via.
  • the first to fourth anode connection lines AL1 to AL4 may have a zigzag line shape.
  • the first anode connection line AL1 is located between the first power lines arranged at intervals, and at least a portion of the first anode connection line AL1 extends along the second direction X, and the first anode connection line AL1 is electrically connected to the second electrode of the sixth transistor of the electrically connected first type pixel circuit through the twentieth via hole.
  • the second anode connection line AL2 is located between the first power lines arranged at intervals, and at least a portion of the second anode connection line AL2 extends along the second direction X, and the second anode connection line AL2 is electrically connected to the second electrode of the sixth transistor of the electrically connected first type pixel circuit through the twentieth via hole, and is electrically connected to the eleventh connection electrode through the thirty-first via hole.
  • the third anode connection line AL3 is located between the data signal line Data electrically connected to the electrically connected first type pixel circuit and the first power line VDD, and at least a portion of the third anode connection line AL3 extends along the second direction X, and the third anode connection line AL3 is electrically connected to the second electrode of the sixth transistor of the electrically connected first type pixel circuit through the twentieth via hole.
  • the fourth anode connection line AL4 is located between the data signal line Data electrically connected to the electrically connected first type pixel circuit and the first power line VDD, and at least a portion of the fourth anode connection line AL4 extends along the second direction X, and the fourth anode connection line AL4 is electrically connected to the second electrode of the sixth transistor of the electrically connected first type pixel circuit through the twentieth via hole.
  • connection electrode VL13 extends along the second direction X and is electrically connected to the eleventh connection electrode through the thirty-first via hole.
  • the second anode connection line AL1 is electrically connected to the electrically connected first type pixel circuit, the eleventh connection electrode, and the thirteenth connection electrode, respectively.
  • the two sub-signal lines INIT_1 and INIT_2 of the initial signal line may be of a zigzag type, at least portions of the two sub-signal lines INIT_1 and INIT_2 of the initial signal line may extend along the second direction X, the sub-signal line INIT_1 of the initial signal line is electrically connected to the eighth connection electrode through the twenty-seventh via hole, and the sub-signal line INIT_2 of the initial signal line is electrically connected to the first electrode of the first transistor through the seventeenth via hole.
  • the sub-signal line INIT_1 of the initial signal line is electrically connected to the first connection electrode through the eighth connection electrode.
  • the sub-signal line INIT_2 of the initial signal line is electrically connected to the first connection electrode through the first electrode of the first transistor.
  • the two sub-signal lines RST_1 and RST_2 of the reset signal line may be in a zigzag shape, at least portions of the two sub-signal lines RST_1 and RST_2 of the reset signal line may extend along the second direction X, the sub-signal line RST_1 of the reset signal line is electrically connected to the second connection electrode through a twenty-first via hole, and the sub-signal line RST_2 of the reset signal line is electrically connected to the third connection electrode through a twenty-second via hole.
  • the sub-signal line RST_1 of the reset signal line is electrically connected to the control electrode of the first transistor through the second connection electrode
  • the sub-signal line RST_2 of the reset signal line is electrically connected to the control electrode of the first transistor through the third connection electrode.
  • the two sub-signal lines Gate_1 and Gate_2 of the scan signal line may be in a zigzag line shape, at least portions of the two sub-signal lines Gate_1 and Gate_2 of the scan signal line may extend along the second direction X, the sub-signal line Gate_1 of the scan signal line is electrically connected to the fourth connection electrode through the twenty-third via hole, and the sub-signal line Gate_2 of the scan signal line is electrically connected to the fifth connection electrode through the twenty-fourth via hole.
  • the sub-signal line Gate_1 of the scan signal line is electrically connected to the control electrode of the fourth transistor through the fourth connection electrode
  • the sub-signal line Gate_2 of the scan signal line is electrically connected to the control electrode of the fourth transistor through the fifth connection electrode.
  • the two sub-signal lines EM_1 and EM_2 of the light emitting signal line may be in a zigzag shape, at least portions of the two sub-signal lines EM_1 and EM_2 of the light emitting signal line may extend along the second direction X, the sub-signal line EM_1 of the light emitting signal line is electrically connected to the sixth connection electrode through the twenty-fifth via hole, and the sub-signal line EM_1 of the light emitting signal line is electrically connected to the seventh connection electrode through the twenty-sixth via hole.
  • the sub-signal line EM_1 of the light emitting signal line is electrically connected to the control electrode of the fifth transistor through the sixth connection electrode, and the sub-signal line EM_2 of the light emitting signal line is electrically connected to the control electrode of the fifth transistor through the seventh connection electrode.
  • Forming a first planar layer pattern may include: depositing a first planar film on the substrate on which the aforementioned pattern is formed, forming a first planar layer pattern disposed on the transparent conductive layer, wherein the first planar layer pattern includes a plurality of vias, as shown in FIG. 15L , which is a schematic diagram of the light-transmitting display area provided in FIG. 12 after the first planar layer is formed.
  • the first planar layer pattern may include a thirty-second via hole V32 and a thirty-eighth via hole V38.
  • the thirty-second via hole V32 exposes the first anode connection line
  • the thirty-third via hole V33 exposes the second anode connection line
  • the thirty-fourth via hole V34 exposes the third anode connection line
  • the thirty-fifth via hole V35 exposes the fourth anode connection line
  • the thirty-sixth via hole V36 exposes the thirteenth connection electrode
  • the thirty-seventh via hole V37 exposes the first power line VDD
  • the thirty-eighth via hole V38 exposes the twelfth connection electrode.
  • the number of the thirty-second via holes V32 may be two, and they are respectively located at both ends of the first anode connection line.
  • the number of the thirty-third via holes V33 may be two, and they are respectively located at both ends of the second anode connection line.
  • the number of the thirty-fourth via holes V34 may be two, and they are respectively located at both ends of the third anode connection line.
  • the number of the thirty-fifth via holes V35 may be two, and they are respectively located at both ends of the fourth anode connection line.
  • forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the first flat layer, as shown in FIG. 15M and FIG. 15N, FIG. 15M is a schematic diagram of the fourth conductive layer pattern of the light-transmitting display area provided in FIG. 12, and FIG. 15N is a schematic diagram of the light-transmitting display area provided in FIG. 12 after the fourth conductive layer pattern is formed.
  • the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the fourth conductive layer pattern may include fourteenth to twenty-first connection electrodes VL14 to VL21 , first to second signal connection lines VDL1 and VDL2 .
  • the fourteenth to twenty-first connection electrodes VL14 to VL21 are block structures.
  • the first and second signal connection lines VDL1 and VDL2 may be zigzag lines, and at least portions of the first and second signal connection lines VDL1 and VDL2 extend along the first direction Y.
  • the fourteenth connection electrode VL14 and the fifteenth connection electrode VL15 are electrically connected to the first anode connection line through the thirty-second via hole
  • the sixteenth connection electrode VL1 is electrically connected to the second anode connection line through the thirty-third via hole
  • the seventeenth connection electrode VL17 is electrically connected to the thirteenth connection electrode through the thirty-sixth via hole
  • the eighteenth connection electrode VL18 and the nineteenth connection electrode VL19 are electrically connected to the third anode connection line through the thirty-fourth via hole
  • the twentieth via hole V20 and the twenty-first via hole V21 are electrically connected to the fourth anode connection line through the thirty-fifth via hole.
  • the first signal connection line VDL1 is electrically connected to the first power supply line VDD electrically connected to the first type pixel circuit through the thirty-seventh via hole
  • the second signal connection line VDL2 is electrically connected to the twelfth connection electrode through the thirty-eighth via hole, and is electrically connected to the first power supply line through the thirty-seventh via hole.
  • the first power line electrically connected to the first type pixel circuits in the same column is communicated through the first power connection line, the tenth connection electrode and the second power connection line.
  • the data signal line electrically connected to the first type pixel circuits in the same column is communicated through the ninth connection electrode.
  • the fourteenth connection electrode VL14 is electrically connected to the fifteenth connection electrode VL15 through the first anode connection line
  • the sixteenth connection electrode VL16 is electrically connected to the seventeenth connection electrode VL17 through the second anode connection line
  • the eighteenth connection electrode VL18 is electrically connected to the nineteenth connection electrode VL19 through the third anode connection line
  • the twentieth connection electrode VL20 is electrically connected to the twenty-first connection electrode VL21 through the fourth anode connection line.
  • the plurality of connection electrodes play a role of connection, which can avoid the unreliability of connection caused by opening deeper via holes, thereby improving the reliability of the display panel.
  • forming the second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the second planar film using a patterning process to form a second planar layer covering the fourth conductive layer, wherein a plurality of vias are disposed on the second planar layer, as shown in FIG. 15O , wherein FIG. 15O is a schematic diagram of the light-transmitting display area provided in FIG. 12 after the second planar layer pattern is formed.
  • the plurality of via holes of the second planar layer pattern may each include: a thirty-ninth via hole V39 to a forty-sixth via hole V46.
  • the thirty-ninth via hole V39 exposes the fourteenth connection electrode
  • the fortieth via hole V40 exposes the fifteenth connection electrode
  • the forty-first via hole V41 exposes the sixteenth connection electrode
  • the forty-second via hole V42 exposes the seventeenth connection electrode
  • the forty-third via hole V43 exposes the eighteenth connection electrode
  • the forty-fourth via hole V44 exposes the nineteenth connection electrode
  • the forty-fifth via hole V45 exposes the twentieth connection electrode
  • the forty-sixth via hole V46 exposes the twenty-first connection electrode.
  • the drive circuit layer is prepared on the substrate.
  • the drive circuit layer may include a plurality of first-type pixel circuits, a scan signal line, a reset signal line, a light-emitting signal line, a data signal line, an initial signal line, and a first anode connection line to a fourth anode connection line.
  • the drive circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a transparent conductive layer, a first flat layer, a fourth conductive layer, and a second flat layer stacked sequentially on the substrate.
  • the substrate may be a flexible substrate or a rigid substrate.
  • the rigid substrate may be, but is not limited to, one or more of glass and quartz
  • the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together.
  • the materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer may be amorphous silicon (a-si).
  • the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the transparent conductive layer may be made of, for example, indium tin oxide ITO or indium zinc oxide IZO, or may be made of a multi-layer composite structure, such as ITO/Ag/ITO.
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.
  • the first insulating layer may be referred to as a buffer layer
  • the second insulating layer may be referred to as a gate insulation (GI) layer
  • the third insulating layer may be referred to as an interlayer insulation (ILD) layer
  • the fourth insulating layer may be referred to as a passivation (PVX) layer.
  • the first flat layer and the second flat layer may be made of organic materials such as resins.
  • the semiconductor layer may be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene, and the like, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.
  • a light emitting structure layer is prepared on the driving circuit layer.
  • the preparation process of the light emitting structure layer may include the following operations.
  • Forming an anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the aforementioned pattern is formed, patterning the anode conductive film using a patterning process, and forming an anode conductive layer pattern disposed on the second flat layer, as shown in FIGS. 15P and 15Q, where FIG. 15P is a schematic diagram of the anode conductive layer pattern of the light-transmitting display area provided in FIG. 12, and FIG. 15Q is a schematic diagram of the light-transmitting display area provided in FIG. 12 after the anode conductive layer pattern is formed.
  • the anode conductive layer has a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO/Ag/ITO.
  • the anode conductive layer pattern may include an anode 110 of the first light emitting elements 11 a and 11 b , an anode 120 of the second light emitting element, and an anode 130 of the third light emitting elements 13 a to 13 d .
  • the anode of the first light-emitting element 11a is electrically connected to the fourteenth connecting electrode through the thirty-ninth via hole
  • the anode of the first light-emitting element 11b is electrically connected to the fifteenth connecting electrode through the fortieth via hole
  • the anode of the second light-emitting element 12b is electrically connected to the sixteenth connecting electrode through the forty-first via hole
  • the anode of the second light-emitting element 12a is electrically connected to the seventeenth connecting electrode through the forty-second via hole
  • the anode of the third light-emitting element 13a is electrically connected to the eighteenth connecting electrode through the forty-third via hole
  • the anode of the third light-emitting element 13b is electrically connected to the nineteenth connecting electrode through the forty-fourth via hole
  • the anode of the third light-emitting element 13c is electrically connected to the twentieth connecting electrode through the forty-fifth via hole
  • the anode of the first light-emitting element 11a is electrically connected to the anode of the first light-emitting element 11b through the fourteenth connecting electrode, the first anode connecting wire, and the fifteenth connecting electrode.
  • the anode of the second light-emitting element 12a is electrically connected to the anode of the second light-emitting element 12b through the sixteenth connecting electrode, the eleventh connecting electrode, the thirteenth connecting electrode, and the seventeenth connecting electrode.
  • the anode of the third light-emitting element 13a is electrically connected to the anode of the third light-emitting element 13b through the eighteenth connecting electrode, the third anode connecting wire, and the nineteenth connecting electrode.
  • the anode of the third light-emitting element 13c is electrically connected to the anode of the third light-emitting element 13d through the twentieth connecting electrode, the fourth anode connecting wire, and the twenty-first connecting electrode.
  • At least one of the anode 110 of the first light-emitting elements 11a and 11b, the anode 120 of the second light-emitting element, and the anode 130 of the third light-emitting elements 13a to 13d may include a main body portion and a connecting portion that are connected to each other, the main body portion may be rectangular in shape, the corners of the rectangle may be chamfered in an arc shape, and the connecting portion may be in the shape of a strip extending in a direction away from the main body portion.
  • the subsequent preparation process may include: first forming a pixel definition layer pattern, then forming an organic light-emitting layer by evaporation or inkjet printing, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer
  • the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer
  • the first encapsulation layer and the third encapsulation layer may be made of inorganic materials
  • the second encapsulation layer may be made of organic materials
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.
  • the preparation process of the light-transmitting display area provided in FIG. 13 may include the following operations.
  • Forming a semiconductor layer pattern may include: sequentially depositing a semiconductor thin film on a substrate, patterning the semiconductor thin film through a patterning process, and forming a semiconductor layer pattern, as shown in FIG. 16A , which is a schematic diagram of the light-transmitting display area provided in FIG. 13 after a semiconductor pattern is formed.
  • the semiconductor layer pattern provided in FIG. 16A is the same as the semiconductor layer pattern provided in FIG. 15A , and will not be described again herein.
  • forming the first conductive layer pattern may include: depositing a first insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film by a patterning process, forming a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern located on the first insulating layer, as shown in FIG. 16B and FIG. 16C, wherein FIG. 16B is a schematic diagram of the first conductive layer pattern of the light-transmitting display area provided in FIG. 13, and FIG. 16C is a schematic diagram of the light-transmitting display area provided in FIG. 13 after the first conductive layer pattern is formed.
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern provided in FIGS. 16B and 16C is the same as the pattern of the first conductive layer provided in FIGS. 15B and 15C , and will not be described again herein.
  • forming the second conductive layer pattern may include: depositing a second insulating layer film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process, and forming a second conductive layer pattern on the second insulating layer.
  • Figure 16D is a schematic diagram of the second conductive layer pattern of the light-transmitting display area provided in Figure 13
  • Figure 16E is a schematic diagram of the light-transmitting display area provided in Figure 13 after the second conductive layer pattern is formed.
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the pattern of the second conductive layer provided in FIGS. 16D and 16E is the same as the pattern of the second conductive layer provided in FIGS. 15D and 15E , and will not be described again herein.
  • forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer covering the second conductive layer, wherein a plurality of vias are provided on the third insulating layer, as shown in FIG16F , wherein FIG16F is a schematic diagram of the light-transmitting display area provided in FIG13 after the third insulating layer pattern is formed.
  • the third insulating layer pattern provided in FIG. 16F is the same as the third insulating layer pattern provided in FIG. 15F , and will not be described again herein.
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the third insulating layer, as shown in FIGS. 16G to 16H, wherein FIG. 16G is a schematic diagram of a third conductive layer pattern in the light-transmitting display area provided in FIG. 13, and FIG. 16H is a schematic diagram of a light-transmitting display area provided in FIG. 13 after the third conductive layer pattern is formed.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the third conductive layer pattern may include: a first electrode T13 and a second electrode T14 of the first transistor, a first electrode T23 of the second transistor, a first electrode T43 of the fourth transistor, a first electrode T53 of the fifth transistor, a second electrode T64 of the sixth transistor, a first electrode T73 and a second electrode T74 of the seventh transistor, the second connection electrode VL2 to the tenth connection electrode VL10, a shielding electrode SL and a power connection line VCL.
  • the first electrode T13 and the second electrode T14 of the first transistor, the first electrode T23 of the second transistor, the first electrode T43 of the fourth transistor, the first electrode T53 of the fifth transistor, the second electrode T64 of the sixth transistor, the first electrode T73 and the second electrode T74 of the seventh transistor, the second connection electrodes VL2 to the eighth connection electrodes VL8 and the shielding electrode provided in Figures 16G and 16H are the same as the patterns of the first electrode T13 and the second electrode T14 of the first transistor, the first electrode T23 of the second transistor, the first electrode T43 of the fourth transistor, the first electrode T53 of the fifth transistor, the second electrode T64 of the sixth transistor, the first electrode T73 and the second electrode T74 of the seventh transistor, the second connection electrodes VL2 to the eighth connection electrodes VL8 and the shielding electrode SL in Figures 15G and 15H, and are not repeated here.
  • At least portions of the ninth and tenth connection electrodes VL9 and VL10 extend in the second direction X.
  • the power connection line VCL extends.
  • forming a fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the third conductive layer, wherein a plurality of vias are provided on the fourth insulating layer, as shown in FIG16I.
  • FIG16I is a schematic diagram of the light-transmitting display area provided in FIG13 after the fourth insulating layer pattern is formed.
  • the plurality of via holes of the fourth insulating layer pattern may each include: a seventeenth via hole V17 to a thirty-first via hole V31.
  • the seventeenth via hole V17 to the twenty-eighth via hole V28 in FIG16I are the same as the seventeenth via hole V17 to the twenty-eighth via hole V28 in FIG15I, except that the twenty-ninth via hole V29 exposes the ninth connection electrode, the thirtieth via hole V30 exposes the tenth connection electrode, and the thirty-first via hole V31 exposes the power connection line VCL.
  • the number of the twenty-ninth via holes V29 may be two, and the two twenty-ninth via holes may be arranged along the second direction X and respectively located at two ends of the ninth connection electrode.
  • the number of the thirtieth via holes V30 may be two, and the two thirtieth via holes V30 may be arranged along the second direction X and respectively located at two ends of the tenth connection electrode.
  • the number of the thirty-first via holes V31 may be two, and the two thirty-first via holes V31 may be arranged along the second direction X and respectively located at two ends of the electrode connection line.
  • Forming a transparent conductive layer pattern may include: depositing a transparent conductive film on the substrate on which the aforementioned pattern is formed, patterning the transparent conductive film using a patterning process, and forming a transparent conductive layer disposed on the fourth insulating layer, as shown in FIG. 16J and FIG. 16K , FIG. 16J is a schematic diagram of a transparent conductive layer pattern in the light-transmitting display area provided in FIG. 13 , and FIG. 16K is a schematic diagram of a transparent conductive layer pattern after the transparent conductive layer pattern is formed in the light-transmitting display area provided in FIG. 13 .
  • the transparent conductive layer patterns may include: a data signal line Data, a first power line VDD, a first anode connecting line AL1, a second anode connecting line AL2, a third anode connecting line AL3, a fourth anode connecting line AL4, two sub-signal lines INIT_1 and INIT_2 of the initial signal line, two sub-signal lines RST_1 and RST_2 of the reset signal line, two sub-signal lines Gate_1 and Gate_2 of the scan signal line, two sub-signal lines EM_1 and EM_2 of the light emitting signal line, an eleventh connecting electrode VL11 and a twelfth connecting electrode VL12.
  • the data signal line Data and the first power line VDD can be located between two sub-signal lines of a plurality of first signal lines electrically connected to a first type pixel circuit electrically connected to the data signal line Data and the first power line VDD, and their orthographic projections on the substrate overlap with the orthographic projections of the first type pixel circuit on the substrate.
  • the data signal line Data is a zigzag line, at least a portion of the data signal line Data extends along the first direction Y, and the data signal line Data electrically connected to adjacent first-type pixel circuits in the same column may be the same signal line.
  • the data signal line is electrically connected to the first electrode of the fourth transistor of the electrically connected first-type pixel circuit through the eighteenth via hole.
  • the first power line VDD is a zigzag line, at least a portion of the first power line VDD extends along the first direction Y, and the first power lines VDD electrically connected to adjacent first-type pixel circuits in the same column may be arranged at intervals.
  • the first power line is electrically connected to the first electrode of the fifth transistor of the electrically connected first-type pixel circuit through the nineteenth via hole, and is electrically connected to the shielding electrode through the twenty-eighth via hole.
  • the first power line VDD includes a power main body portion VDDM extending in the first direction Y and a power connection portion VDDS extending at least partially in the second direction X. As shown in FIGS. 16J and 16K , the first power line VDD includes a power main body portion VDDM extending in the first direction Y and a power connection portion VDDS extending at least partially in the second direction X. As shown in FIGS. 16J and 16K , the first power line VDD includes a power main body portion VDDM extending in the first direction Y and a power connection portion VDDS extending at least partially in the second direction X. As shown in FIGS.
  • At least a portion of the power connection line VCL extends along the second direction X and is electrically connected to the first power line VDD electrically connected to the adjacent first-type pixel circuits in the same row.
  • the power connection portion of the first power line electrically connected to one of the adjacent first-type pixel circuits in the same row is electrically connected to the power connection line VCL through the thirty-first via hole, and the power main body of the first power line electrically connected to another of the adjacent first-type pixel circuits in the same row is connected to the power connection line VCL through the thirty-first via hole.
  • the setting of the power connection line VCL can cooperate with the first power line to form a mesh structure to achieve display uniformity of the display substrate.
  • the first to fourth anode connection lines AL1 to AL4 may be in a zigzag line shape.
  • the first anode connection line AL1 is located between the first power line VDD electrically connected to the electrically connected first type pixel circuit and the data signal line Data of the adjacent column first type pixel circuit, and at least a portion of the first anode connection line AL1 extends along the second direction X, and the first anode connection line AL1 is electrically connected to the second electrode of the sixth transistor of the electrically connected first type pixel circuit through the twentieth via hole, and is electrically connected to the ninth connection electrode through the twenty-ninth via hole.
  • the second anode connection line AL2 is located between the first power line VDD electrically connected to the electrically connected first type pixel circuit and the data signal line Data of the adjacent column first type pixel circuit, and at least a portion of the second anode connection line AL2 extends along the second direction X, and the second anode connection line AL2 is electrically connected to the second electrode of the sixth transistor of the electrically connected first type pixel circuit through the twentieth via hole, and is electrically connected to the tenth connection electrode through the thirtieth via hole.
  • the third anode connection line AL3 is located between the first power line VDD electrically connected to the electrically connected first type pixel circuit and the data signal line Data electrically connected to the adjacent first type pixel circuit located in the same row. At least a portion of the third anode connection line AL3 extends along the first direction Y, and the third anode connection line AL3 is electrically connected to the second electrode of the sixth transistor of the electrically connected first type pixel circuit through the twentieth via hole.
  • the fourth anode connection line AL4 is located between the first power line VDD electrically connected to the electrically connected first type pixel circuit and the data signal line Data electrically connected to the adjacent first type pixel circuit located in the same row. At least a portion of the fourth anode connection line AL4 may extend along the first direction Y, and the fourth anode connection line AL4 is electrically connected to the second electrode of the sixth transistor of the electrically connected first type pixel circuit through the twentieth via hole.
  • the two sub-signal lines INIT_1 and INIT_2 of the initial signal line may be in a zigzag shape, at least portions of the two sub-signal lines INIT_1 and INIT_2 of the initial signal line may extend along the first direction Y, the sub-signal line INIT_1 of the initial signal line is electrically connected to the eighth connection electrode through the twenty-seventh via hole, and the sub-signal line INIT_2 of the initial signal line is electrically connected to the first electrode of the first transistor through the seventeenth via hole.
  • the sub-signal line INIT_1 of the initial signal line is electrically connected to the first connection electrode through the eighth connection electrode.
  • the sub-signal line INIT_2 of the initial signal line is electrically connected to the first connection electrode through the first electrode of the first transistor.
  • the two sub-signal lines RST_1 and RST_2 of the reset signal line may be in a zigzag shape, at least portions of the two sub-signal lines RST_1 and RST_2 of the reset signal line may extend along the second direction Y, the sub-signal line RST_1 of the reset signal line is electrically connected to the second connection electrode through the twenty-first via hole, and the sub-signal line RST_2 of the reset signal line is electrically connected to the third connection electrode through the twenty-second via hole.
  • the sub-signal line RST_1 of the reset signal line is electrically connected to the control electrode of the first transistor through the second connection electrode
  • the sub-signal line RST_2 of the reset signal line is electrically connected to the control electrode of the first transistor through the third connection electrode.
  • the two sub-signal lines Gate_1 and Gate_2 of the scan signal line may be in a zigzag shape, at least portions of the two sub-signal lines Gate_1 and Gate_2 of the scan signal line may extend along the second direction Y, the sub-signal line Gate_1 of the scan signal line is electrically connected to the fourth connection electrode through the twenty-third via hole, and the sub-signal line Gate_2 of the scan signal line is electrically connected to the fifth connection electrode through the twenty-fourth via hole.
  • the sub-signal line Gate_1 of the scan signal line is electrically connected to the control electrode of the fourth transistor through the fourth connection electrode
  • the sub-signal line Gate_2 of the scan signal line is electrically connected to the control electrode of the fourth transistor through the fifth connection electrode.
  • the two sub-signal lines EM_1 and EM_2 of the light emitting signal line may be in a zigzag shape, at least portions of the two sub-signal lines EM_1 and EM_2 of the light emitting signal line may extend along the second direction Y, the sub-signal line EM_1 of the light emitting signal line is electrically connected to the sixth connection electrode through the twenty-fifth via hole, and the sub-signal line EM_1 of the light emitting signal line is electrically connected to the seventh connection electrode through the twenty-sixth via hole.
  • the sub-signal line EM_1 of the light emitting signal line is electrically connected to the control electrode of the fifth transistor through the sixth connection electrode, and the sub-signal line EM_2 of the light emitting signal line is electrically connected to the control electrode of the fifth transistor through the seventh connection electrode.
  • Forming a first planar layer pattern may include: depositing a first planar film on the substrate on which the aforementioned pattern is formed, to form a first planar layer pattern disposed on the transparent conductive layer, wherein the first planar layer pattern includes a plurality of vias, as shown in FIG16L , which is a schematic diagram of the light-transmitting display area provided in FIG13 after the first planar layer is formed.
  • the first planar layer pattern may include a thirty-second via hole V32 and a thirty-eighth via hole V38, wherein the thirty-second via hole exposes the first power line, the thirty-third via hole V33 exposes the first anode connection line, the thirty-fourth via hole V34 exposes the second anode connection line, the thirty-fifth via hole V35 exposes the third anode connection line, the thirty-sixth via hole V36 exposes the fourth anode connection line, the thirty-seventh via hole V37 exposes the eleventh connection electrode, and the thirty-eighth via hole V38 exposes the twelfth connection electrode.
  • the number of the thirty-third via hole V33 may be two, and they are respectively located at both ends of the first anode connection line.
  • the number of the thirty-fourth via hole V34 may be two, and they are respectively located at both ends of the second anode connection line.
  • the number of the thirty-fifth via hole V35 may be two, and they are respectively located at both ends of the third anode connection line.
  • the number of the thirty-sixth via hole V36 may be two, and they are respectively located at both ends of the fourth anode connection line.
  • forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the first flat layer, as shown in FIG. 16M and FIG. 16N, FIG. 16M is a schematic diagram of the fourth conductive layer pattern of the light-transmitting display area provided in FIG. 13, and FIG. 16N is a schematic diagram of the light-transmitting display area provided in FIG. 13 after the fourth conductive layer pattern is formed.
  • the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the fourth conductive layer pattern may include thirteenth to twentieth link electrodes VL13 to VL20 and a signal link line VDL.
  • the thirteenth to twentieth connection electrodes VL13 to VL20 are block structures.
  • the signal connection line VDL may be in a zigzag shape, and at least a portion of the signal connection line VDL may extend along the first direction Y.
  • the thirteenth connection electrode VL13 is electrically connected to the first anode connection line through the thirty-third via hole
  • the fourteenth connection electrode VL14 is electrically connected to the second anode connection line through the thirty-fourth via hole
  • the fifteenth connection electrode VL15 and the sixteenth connection electrode VL16 are electrically connected to the third anode connection line through the thirty-fifth via hole
  • the seventeenth connection electrode VL17 and the eighteenth connection electrode VL18 are electrically connected to the fourth anode connection line through the thirty-sixth via hole
  • the nineteenth connection electrode VL19 is electrically connected to the eleventh connection electrode through the thirty-seventh via hole
  • the twentieth connection electrode VL20 is electrically connected to the twelfth connection electrode through the thirty-eighth via hole.
  • the signal connection line VDL is electrically connected to the first power supply line electrically connected to the first type pixel circuit through the thirty-second via hole.
  • the first power supply lines electrically connected to the first type pixel circuits located in the same column are electrically connected through a signal connection line.
  • the thirteenth connection electrode VL13 is electrically connected to the nineteenth connection electrode VL19 through the first anode connection line
  • the ninth connection electrode and the eleventh connection electrode is electrically connected to the twentieth connection electrode VL20 through the second anode connection line
  • the tenth connection electrode and the twelfth connection electrode is electrically connected to the fifteenth connection electrode VL15 is electrically connected to the sixteenth connection electrode VL16 through the third anode connection line
  • the seventeenth connection electrode VL17 is electrically connected to the eighteenth connection electrode VL18 through the fourth anode connection line.
  • the plurality of connection electrodes play a role of connection, which can avoid the unreliability of connection caused by opening deeper via holes, thereby improving the reliability of the display panel.
  • forming the second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the second planar film using a patterning process to form a second planar layer covering the fourth conductive layer, wherein a plurality of vias are disposed on the second planar layer, as shown in FIG. 16O , wherein FIG. 16O is a schematic diagram of the light-transmitting display area provided in FIG. 13 after the second planar layer pattern is formed.
  • the plurality of via holes of the second planar layer pattern may each include: a thirty-ninth via hole V39 to a forty-sixth via hole V46.
  • the thirty-ninth via hole V39 exposes the thirteenth connection electrode
  • the fortieth via hole V40 exposes the fourteenth connection electrode
  • the forty-first via hole V41 exposes the fifteenth connection electrode
  • the forty-second via hole V42 exposes the sixteenth connection electrode
  • the forty-third via hole V43 exposes the seventeenth connection electrode
  • the forty-fourth via hole V44 exposes the eighteenth connection electrode
  • the forty-fifth via hole V45 exposes the nineteenth connection electrode
  • the forty-sixth via hole V46 exposes the twentieth connection electrode.
  • the drive circuit layer is prepared on the substrate.
  • the drive circuit layer may include a plurality of first-type pixel circuits, a scan signal line, a reset signal line, a light-emitting signal line, a data signal line, an initial signal line, and a first anode connection line to a fourth anode connection line.
  • the drive circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a transparent conductive layer, a first flat layer, a fourth conductive layer, and a second flat layer stacked sequentially on the substrate.
  • the substrate may be a flexible substrate or a rigid substrate.
  • the rigid substrate may be, but is not limited to, one or more of glass and quartz
  • the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together.
  • the materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer may be amorphous silicon (a-si).
  • the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the transparent conductive layer may be made of, for example, indium tin oxide ITO or indium zinc oxide IZO, or may be made of a multi-layer composite structure, such as ITO/Ag/ITO.
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.
  • the first insulating layer may be referred to as a buffer layer
  • the second insulating layer may be referred to as a gate insulating (GI) layer
  • the third insulating layer may be referred to as an interlayer insulating (ILD) layer
  • the fourth insulating layer may be referred to as a passivation (PVX) layer.
  • the first flat layer and the second flat layer may be made of organic materials such as resins.
  • the semiconductor layer may be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene, and the like, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.
  • a light emitting structure layer is prepared on the driving circuit layer.
  • the preparation process of the light emitting structure layer may include the following operations.
  • Forming an anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the aforementioned pattern is formed, patterning the anode conductive film using a patterning process, and forming an anode conductive layer pattern disposed on the second flat layer, as shown in FIGS. 16P and 16Q, where FIG. 16P is a schematic diagram of the anode conductive layer pattern of the light-transmitting display area provided in FIG. 13, and FIG. 16Q is a schematic diagram of the light-transmitting display area provided in FIG. 13 after the anode conductive layer pattern is formed.
  • the anode conductive layer has a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO/Ag/ITO.
  • the anode conductive layer pattern provided in FIG. 16P is the same as the anode conductive layer pattern provided in FIG. 15P , and will not be described again herein.
  • the anode of the first light-emitting element 11a is electrically connected to the thirteenth connecting electrode through the thirty-ninth via hole
  • the anode of the first light-emitting element 11b is electrically connected to the nineteenth connecting electrode through the forty-fifth via hole
  • the anode of the second light-emitting element 12a is electrically connected to the fourteenth connecting electrode through the forty-first via hole
  • the anode of the second light-emitting element 12b is electrically connected to the twentieth connecting electrode through the forty-sixth via hole
  • the anode of the third light-emitting element 13a is electrically connected to the fifteenth connecting electrode through the forty-first via hole
  • the anode of the third light-emitting element 13b is electrically connected to the sixteenth connecting electrode through the forty-second via hole
  • the anode of the third light-emitting element 13c is electrically connected to the seventeenth connecting electrode through the forty-third via hole
  • the anode of the first light-emitting element 11a is electrically connected to the anode of the first light-emitting element 11b through the thirteenth connecting electrode, the first anode connecting wire, the ninth connecting electrode, the eleventh connecting electrode, and the nineteenth connecting electrode.
  • the anode of the second light-emitting element 12a is electrically connected to the anode of the second light-emitting element 12b through the fourteenth connecting electrode, the second anode connecting wire, the tenth connecting electrode, the twelfth connecting electrode, and the twentieth connecting electrode.
  • the anode of the third light-emitting element 13a is electrically connected to the anode of the third light-emitting element 13b through the fifteenth connecting electrode, the third anode connecting wire, and the sixteenth connecting electrode.
  • the anode of the third light-emitting element 13c is electrically connected to the anode of the third light-emitting element 13d through the seventeenth connecting electrode, the fourth anode connecting wire, and the eighteenth connecting electrode.
  • the subsequent preparation process may include: first forming a pixel definition layer pattern, then forming an organic light-emitting layer by evaporation or inkjet printing process, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer
  • the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer
  • the first encapsulation layer and the third encapsulation layer may be made of inorganic materials
  • the second encapsulation layer may be made of organic materials
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.
  • the preparation process of the light-transmitting display area provided in FIG. 14 may include the following operations.
  • Forming a semiconductor layer pattern may include: sequentially depositing a semiconductor thin film on a substrate, patterning the semiconductor thin film through a patterning process, and forming a semiconductor layer pattern, as shown in FIG. 17A , which is a schematic diagram of the light-transmitting display area provided in FIG. 14 after a semiconductor pattern is formed.
  • the semiconductor layer pattern provided in FIG. 17A is the same as the semiconductor layer pattern provided in FIG. 15A , and will not be described again herein.
  • forming the first conductive layer pattern may include: depositing a first insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film by a patterning process, forming a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern located on the first insulating layer, as shown in FIG. 17B and FIG. 17C, wherein FIG. 17B is a schematic diagram of the first conductive layer pattern of the light-transmitting display area provided in FIG. 14, and FIG. 17C is a schematic diagram of the light-transmitting display area provided in FIG. 14 after the first conductive layer pattern is formed.
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern provided in FIGS. 17B and 17C is the same as the pattern of the first conductive layer provided in FIGS. 15B and 15C , and will not be described again herein.
  • forming the second conductive layer pattern may include: depositing a second insulating layer film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process, and forming a second conductive layer pattern on the second insulating layer.
  • Figure 17D is a schematic diagram of the second conductive layer pattern of the light-transmitting display area provided in Figure 14
  • Figure 17E is a schematic diagram of the light-transmitting display area provided in Figure 14 after the second conductive layer pattern is formed.
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the pattern of the second conductive layer provided in FIGS. 17D and 17E is the same as the pattern of the second conductive layer provided in FIGS. 15D and 15E , and will not be described again herein.
  • forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer covering the second conductive layer, wherein a plurality of vias are provided on the third insulating layer, as shown in FIG17F , wherein FIG17F is a schematic diagram of the light-transmitting display area provided in FIG14 after the third insulating layer pattern is formed.
  • the third insulating layer pattern provided in FIG. 17F is the same as the pattern of the third insulating layer provided in FIG. 15F , and will not be described again herein.
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the third insulating layer, as shown in FIGS. 17G to 17H, wherein FIG. 17G is a schematic diagram of the third conductive layer pattern of the light-transmitting display area provided in FIG. 14, and FIG. 17H is a schematic diagram of the light-transmitting display area provided in FIG. 14 after the third conductive layer pattern is formed.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the third conductive layer pattern may include: a first electrode T13 and a second electrode T14 of a first transistor, a first electrode T23 of a second transistor, a first electrode T43 of a fourth transistor, a first electrode T53 of a fifth transistor, a second electrode T64 of a sixth transistor, a first electrode T73 and a second electrode T74 of a seventh transistor, second to twelfth connection electrodes VL2 to VL12, and a shielding electrode SL.
  • the first electrode T13 and the second electrode T14 of the first transistor, the first electrode T23 of the second transistor, the first electrode T43 of the fourth transistor, the first electrode T53 of the fifth transistor, the second electrode T64 of the sixth transistor, the first electrode T73 and the second electrode T74 of the seventh transistor, the second connection electrode VL2 to the eighth connection electrode VL8 and the shielding electrode provided in Figures 17G and 17H are the same as the patterns of the first electrode T13 and the second electrode T14 of the first transistor, the first electrode T23 of the second transistor, the first electrode T43 of the fourth transistor, the first electrode T53 of the fifth transistor, the second electrode T64 of the sixth transistor, the first electrode T73 and the second electrode T74 of the seventh transistor, the second connection electrode VL2 to the eighth connection electrode VL8 and the shielding electrode SL in Figures 15G and 15H, and are not repeated here.
  • the ninth and twelfth connection electrodes VL9 and VL12 extend in the second direction X, and at least portions of the tenth and eleventh connection electrodes VL10 and VL11 extend in the second direction X.
  • forming a fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the third conductive layer, wherein a plurality of vias are provided on the fourth insulating layer, as shown in FIG17I.
  • FIG17I is a schematic diagram of the light-transmitting display area provided in FIG14 after the fourth insulating layer pattern is formed.
  • the plurality of via holes of the fourth insulating layer pattern may each include: a seventeenth via hole V17 to a thirty-second via hole V32.
  • the seventeenth via hole V17 to the twenty-eighth via hole V28 in FIG17I are the same as the seventeenth via hole V17 to the twenty-eighth via hole V28 in FIG15I, except that the twenty-ninth via hole V29 exposes the ninth connection electrode, the thirtieth via hole V30 exposes the tenth connection electrode, the thirty-first via hole V31 exposes the eleventh connection electrode, and the thirty-second via hole V32 exposes the twelfth connection electrode.
  • the number of the twenty-ninth via holes V29 may be two, and the two twenty-ninth via holes may be arranged along the second direction X and respectively located at two ends of the ninth connection electrode.
  • the number of the thirtieth via holes V30 may be two, and the two thirtieth via holes V30 may be arranged along the second direction X and respectively located at two ends of the tenth connection electrode.
  • the number of the thirty-first via holes V31 may be two, and the two thirty-first via holes V31 may be arranged along the second direction X and respectively located at two ends of the eleventh connection electrode.
  • the number of the thirty-second via holes V32 may be two, and the two thirty-second via holes V32 may be arranged along the second direction X and respectively located at two ends of the twelfth connection electrode.
  • Forming a transparent conductive layer pattern may include: depositing a transparent conductive film on the substrate on which the aforementioned pattern is formed, patterning the transparent conductive film using a patterning process, and forming a transparent conductive layer disposed on the fourth insulating layer, as shown in FIGS. 17J and 17K , wherein FIG. 17J is a schematic diagram of a transparent conductive layer pattern in the light-transmitting display area provided in FIG. 14 , and FIG. 17K is a schematic diagram of a transparent conductive layer pattern after the transparent conductive layer pattern is formed in the light-transmitting display area provided in FIG. 14 .
  • the transparent conductive layer patterns may include: a data signal line Data, a first power line VDD, a first anode connecting line AL1, a second anode connecting line AL2, a third anode connecting line AL3, two sub-signal lines INIT_1 and INIT_2 of the initial signal line, two sub-signal lines RST_1 and RST_2 of the reset signal line, two sub-signal lines Gate_1 and Gate_2 of the scan signal line, two sub-signal lines EM_1 and EM_2 of the light emitting signal line, and a thirteenth connecting electrode VL13 to a seventeenth connecting electrode VL17.
  • the data signal line Data and the first power line VDD can be located between two sub-signal lines of a plurality of first signal lines electrically connected to a first type pixel circuit electrically connected to the data signal line Data and the first power line VDD, and their orthographic projections on the substrate overlap with the orthographic projections of the first type pixel circuit on the substrate.
  • the data signal line Data can be linear, at least a portion of the data signal line Data can extend along the first direction Y, and the data signal lines Data electrically connected to adjacent first-type pixel circuits in the same column can be the same signal line, and the data signal line is electrically connected to the first electrode of the fourth transistor of the electrically connected first-type pixel circuit through an eighteenth via.
  • the first power line VDD can be linear, at least a portion of the first power line VDD can extend along the first direction Y, and the first power lines VDD electrically connected to adjacent first-type pixel circuits in the same column can be arranged at intervals, and the first power line is electrically connected to the first electrode of the fifth transistor of the electrically connected first-type pixel circuit through a nineteenth via, and is electrically connected to the shielding electrode through a twenty-eighth via.
  • the first to fourth anode connection lines AL1 to AL4 are in a zigzag line shape.
  • the first anode connection line AL1 is located between the first power line VDD electrically connected to the electrically connected first type pixel circuit and the data signal line Data of the first type pixel circuit in an adjacent column, and at least a portion of the first anode connection line AL1 can extend along the second direction X, and the first anode connection line AL1 is electrically connected to the second electrode of the sixth transistor of the electrically connected first type pixel circuit through the twentieth via hole, and is electrically connected to the tenth connection electrode through the thirtieth via hole.
  • the second anode connection line AL2 is located between the first power line VDD electrically connected to the electrically connected first type pixel circuit and the data signal line Data of the adjacent column first type pixel circuit, and at least a portion of the second anode connection line AL2 can extend along the second direction X, and the second anode connection line AL2 is electrically connected to the second electrode of the sixth transistor of the electrically connected first type pixel circuit through the twentieth via hole, and is electrically connected to the ninth connection electrode through the twenty-ninth via hole.
  • the third anode connection line AL3 is located between the first power line VDD electrically connected to the electrically connected first type pixel circuit and the data signal line Data electrically connected to the adjacent first type pixel circuit located in the same row, and at least a portion of the third anode connection line AL3 can extend along the first direction Y, and the third anode connection line AL3 is electrically connected to the twelfth connection electrode through the thirty-second via.
  • the two sub-signal lines INIT_1 and INIT_2 of the initial signal line may be in a zigzag shape, at least portions of the two sub-signal lines INIT_1 and INIT_2 of the initial signal line may extend along the first direction Y, the sub-signal line INIT_1 of the initial signal line is electrically connected to the eighth connection electrode through the twenty-seventh via hole, and the sub-signal line INIT_2 of the initial signal line is electrically connected to the first electrode of the first transistor through the seventeenth via hole.
  • the sub-signal line INIT_1 of the initial signal line is electrically connected to the first connection electrode through the eighth connection electrode.
  • the sub-signal line INIT_2 of the initial signal line is electrically connected to the first connection electrode through the first electrode of the first transistor.
  • the two sub-signal lines RST_1 and RST_2 of the reset signal line may be in a zigzag shape, at least portions of the two sub-signal lines RST_1 and RST_2 of the reset signal line may extend along the second direction Y, the sub-signal line RST_1 of the reset signal line is electrically connected to the second connection electrode through the twenty-first via hole, and the sub-signal line RST_2 of the reset signal line is electrically connected to the third connection electrode through the twenty-second via hole.
  • the sub-signal line RST_1 of the reset signal line is electrically connected to the control electrode of the first transistor through the second connection electrode
  • the sub-signal line RST_2 of the reset signal line is electrically connected to the control electrode of the first transistor through the third connection electrode.
  • the two sub-signal lines Gate_1 and Gate_2 of the scan signal line may be in a zigzag shape, at least portions of the two sub-signal lines Gate_1 and Gate_2 of the scan signal line may extend along the second direction Y, the sub-signal line Gate_1 of the scan signal line is electrically connected to the fourth connection electrode through the twenty-third via hole, and the sub-signal line Gate_2 of the scan signal line is electrically connected to the fifth connection electrode through the twenty-fourth via hole.
  • the sub-signal line Gate_1 of the scan signal line is electrically connected to the control electrode of the fourth transistor through the fourth connection electrode
  • the sub-signal line Gate_2 of the scan signal line is electrically connected to the control electrode of the fourth transistor through the fifth connection electrode.
  • the two sub-signal lines EM_1 and EM_2 of the light emitting signal line may be in a zigzag shape, at least portions of the two sub-signal lines EM_1 and EM_2 of the light emitting signal line may extend along the second direction Y, the sub-signal line EM_1 of the light emitting signal line is electrically connected to the sixth connection electrode through the twenty-fifth via hole, and the sub-signal line EM_1 of the light emitting signal line is electrically connected to the seventh connection electrode through the twenty-sixth via hole.
  • the sub-signal line EM_1 of the light emitting signal line is electrically connected to the control electrode of the fifth transistor through the sixth connection electrode, and the sub-signal line EM_2 of the light emitting signal line is electrically connected to the control electrode of the fifth transistor through the seventh connection electrode.
  • the thirteenth connection electrode VL13 is electrically connected to the tenth connection electrode through the thirtieth via hole, and is electrically connected to the eleventh connection electrode through the thirty-first via hole.
  • the fourteenth connection electrode VL14 is electrically connected to the eleventh connection electrode through the thirty-first via hole.
  • the thirteenth connection electrode is electrically connected to the fourteenth connection electrode through the first anode connection line, the tenth connection electrode, the thirteenth connection electrode and the eleventh connection electrode.
  • the fifteenth link electrode VL15 is electrically connected to the second electrode of the sixth transistor of the electrically connected first type pixel circuit through the twentieth via hole.
  • the sixteenth connection electrode VL16 is electrically connected to the ninth connection electrode through the twenty-ninth via hole.
  • the sixteenth connection electrode is electrically connected to the second anode connection line AL2 through the ninth connection electrode.
  • the seventeenth connection electrode VL17 is electrically connected to the twelfth connection electrode through the thirty-second via hole.
  • the seventeenth connection electrode VL17 is electrically connected to the third anode connection line AL3 through the twelfth connection electrode.
  • Forming a first planar layer pattern may include: depositing a first planar film on the substrate on which the aforementioned pattern is formed, forming a first planar layer pattern disposed on the transparent conductive layer, wherein the first planar layer pattern includes a plurality of vias, as shown in FIG. 17L , which is a schematic diagram of the light-transmitting display area provided in FIG. 14 after the first planar layer is formed.
  • the first planar layer pattern may include a thirty-third via hole V33 and a fortieth via hole V40.
  • the thirty-third via hole V33 exposes the first power line
  • the thirty-fourth via hole V34 exposes the first anode connection line
  • the thirty-fifth via hole V35 exposes the fourteenth connection electrode
  • the thirty-sixth via hole V36 exposes the sixteenth connection electrode
  • the thirty-seventh via hole V37 exposes the second anode connection line
  • the thirty-eighth via hole V38 exposes the fifteenth connection electrode
  • the thirty-ninth via hole V39 exposes the third anode connection line
  • the fortieth via hole V40 exposes the seventeenth connection electrode.
  • forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the first flat layer, as shown in FIG. 17M and FIG. 17N, FIG. 17M is a schematic diagram of the fourth conductive layer pattern of the light-transmitting display area provided in FIG. 14, and FIG. 17N is a schematic diagram of the light-transmitting display area provided in FIG. 14 after the fourth conductive layer pattern is formed.
  • the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the fourth conductive layer pattern may include eighteenth to twenty-third connection electrodes VL18 to VL23 and a signal connection line VDL.
  • the eighteenth to twenty-first connection electrodes VL18 to VL21 and the twenty-third connection electrode VL23 are block structures.
  • the twenty-second connection electrode VL22 is a horizontally flipped "7" shape, the signal connection line VDL can be a folded line, and at least a portion of the signal connection line VDL can extend along the first direction Y.
  • the signal connection line VDL is electrically connected to the first power line through the thirty-third via hole.
  • the eighteenth connection electrode VL18 is electrically connected to the fourteenth connection electrode through the thirty-fifth via
  • the nineteenth connection electrode VL19 is electrically connected to the first anode connection line through the thirty-fourth via
  • the twentieth connection electrode VL20 is electrically connected to the sixteenth connection electrode through the thirty-sixth via
  • the twenty-first connection electrode VL21 is electrically connected to the second anode connection line through the thirty-seventh via
  • the twenty-second connection electrode VL22 is electrically connected to the fifteenth connection electrode through the thirty-eighth via and is electrically connected to the third anode connection line through the thirty-ninth via
  • the twenty-third connection electrode VL23 is electrically connected to the seventeenth connection electrode through the fortieth via.
  • the first power lines electrically connected to the first type pixel circuits located in the same column are electrically connected through the signal connection line VDL.
  • the eighteenth connecting electrode VL18 is electrically connected to the nineteenth connecting electrode VL19 through the fourteenth connecting electrode, the eleventh connecting electrode, the thirteenth connecting electrode, the tenth connecting electrode and the first anode connecting line
  • the twentieth connecting electrode VL20 is electrically connected to the twenty-first connecting electrode VL21 through the sixteenth connecting electrode
  • the twenty-second connecting electrode VL22 is electrically connected to the twenty-third connecting electrode VL23 through the third anode connecting line, the twelfth connecting electrode and the seventeenth connecting electrode.
  • the plurality of connection electrodes play a role of connection, which can avoid the unreliability of connection caused by opening deeper via holes, thereby improving the reliability of the display panel.
  • forming the second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the second planar film using a patterning process to form a second planar layer covering the fourth conductive layer, wherein a plurality of vias are disposed on the second planar layer, as shown in FIG. 17O , wherein FIG. 17O is a schematic diagram of the light-transmitting display area provided in FIG. 14 after the second planar layer pattern is formed.
  • the plurality of via holes of the second planar layer pattern may each include: a 41st via hole V41 to a 46th via hole V46.
  • the 41st via hole V41 exposes the 18th connection electrode
  • the 42nd via hole V42 exposes the 19th connection electrode
  • the 43rd via hole V43 exposes the 20th connection electrode
  • the 44th via hole V44 exposes the 21st connection electrode
  • the 45th via hole V45 exposes the 22nd connection electrode
  • the 46th via hole V46 exposes the 23rd connection electrode.
  • the drive circuit layer is prepared on the substrate.
  • the drive circuit layer may include a plurality of first-type pixel circuits, a scan signal line, a reset signal line, a light-emitting signal line, a data signal line, an initial signal line, and a first anode connection line to a fourth anode connection line.
  • the drive circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a transparent conductive layer, a first flat layer, a fourth conductive layer, and a second flat layer stacked sequentially on the substrate.
  • the substrate may be a flexible substrate or a rigid substrate.
  • the rigid substrate may be, but is not limited to, one or more of glass and quartz
  • the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked, and the materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, and the material of the semiconductor layer may be amorphous silicon (a-Si).
  • PI polyimide
  • PET polyethylene terephthalate
  • SiOx silicon oxide
  • the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the transparent conductive layer may be made of, for example, indium tin oxide ITO or indium zinc oxide IZO, or may be made of a multi-layer composite structure, such as ITO/Ag/ITO.
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.
  • the first insulating layer may be referred to as a buffer layer
  • the second insulating layer may be referred to as a gate insulating (GI) layer
  • the third insulating layer may be referred to as an interlayer insulating (ILD) layer
  • the fourth insulating layer may be referred to as a passivation (PVX) layer.
  • the first flat layer and the second flat layer may be made of organic materials such as resins.
  • the semiconductor layer may be made of materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.
  • a light emitting structure layer is prepared on the driving circuit layer.
  • the preparation process of the light emitting structure layer may include the following operations.
  • Forming an anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the aforementioned pattern is formed, patterning the anode conductive film using a patterning process, and forming an anode conductive layer pattern disposed on the second flat layer, as shown in FIGS. 17P and 16Q, where FIG. 17P is a schematic diagram of the anode conductive layer pattern of the light-transmitting display area provided in FIG. 14, and FIG. 17Q is a schematic diagram of the light-transmitting display area provided in FIG. 14 after the anode conductive layer pattern is formed.
  • the anode conductive layer has a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO/Ag/ITO.
  • the anode of the first light-emitting element 11b is electrically connected to the eighteenth connecting electrode through the forty-first via hole
  • the anode of the first light-emitting element 11a is electrically connected to the nineteenth connecting electrode through the forty-second via hole
  • the anode of the second light-emitting element 12b is electrically connected to the twentieth connecting electrode through the forty-third via hole
  • the anode of the second light-emitting element 12a is electrically connected to the twenty-first connecting electrode through the forty-fourth via hole
  • the anode of the third light-emitting element 13a is electrically connected to the twenty-second connecting electrode through the forty-fifth via hole
  • the anode of the third light-emitting element 13b is electrically connected to the twenty-third connecting electrode through the forty-sixth via hole.
  • the anode of the first light-emitting element 11a is electrically connected to the anode of the first light-emitting element 11b through the eighteenth connection electrode, the fourteenth connection electrode, the eleventh connection electrode, the thirteenth connection electrode, the tenth connection electrode, the first anode connection line, and the nineteenth connection electrode.
  • the anode of the second light-emitting element 12a is electrically connected to the anode of the second light-emitting element 12b through the twentieth connection electrode, the sixteenth connection electrode, the ninth connection electrode, the first anode connection line, and the twenty-first connection electrode.
  • the anode of the third light-emitting element 13a is electrically connected to the anode of the third light-emitting element 13b through the twenty-second connection electrode VL22, the third anode connection line, the twelfth connection electrode, the seventeenth connection electrode, and the twenty-third connection electrode VL23.
  • the subsequent preparation process may include: first forming a pixel definition layer pattern, then forming an organic light-emitting layer by evaporation or inkjet printing, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer
  • the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer
  • the first encapsulation layer and the third encapsulation layer may be made of inorganic materials
  • the second encapsulation layer may be made of organic materials
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.
  • the structure and preparation process shown above in the present disclosure are merely exemplary.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.
  • the display panel of the present disclosure can be applied to a display device having a pixel circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display (QDLED), etc., which is not limited in the present disclosure.
  • a display device having a pixel circuit such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display (QDLED), etc., which is not limited in the present disclosure.
  • FIG18 is a schematic diagram of the structure of a display device provided by an embodiment of the present disclosure
  • FIG19 is a cross-sectional view along the A-A direction of FIG18.
  • an embodiment of the present disclosure further provides a display device, the display device comprising a display substrate 1 and a photosensitive sensor 2 provided by any of the aforementioned embodiments, the photosensitive sensor being located in a light-transmitting display area A1 of the display substrate 1 and being located on a side away from the light-emitting side of the display substrate 1.
  • the display substrate may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate.
  • the display device may be: an OLED display, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function, but the embodiments of the present disclosure are not limited thereto.
  • the orthographic projection area of the photosensor 2 on the substrate is less than or equal to the area of the inscribed circle of the light-transmitting display area A1.
  • the photosensitive sensor 2 may include at least one of a camera module (e.g., a front camera module), a 3D structured light module (e.g., a 3D structured light sensor), a time-of-flight 3D imaging module (e.g., a time-of-flight sensor), an infrared sensing module (e.g., an infrared sensing sensor), etc.
  • a camera module e.g., a front camera module
  • a 3D structured light module e.g., a 3D structured light sensor
  • a time-of-flight 3D imaging module e.g., a time-of-flight sensor
  • an infrared sensing module e.g., an infrared sensing sensor
  • the front camera module is usually enabled when the user takes a selfie or makes a video call, and the display area of the display device displays the image obtained by the selfie for the user to watch.
  • the front camera module includes, for example, a lens, an image sensor, an image processing chip, etc.
  • the optical image of the scene generated by the lens is projected onto the surface of the image sensor (the image sensor includes CCD and CMOS) and converted into an electrical signal, which is converted into a digital image signal through analog-to-digital conversion by the image processing chip, and then sent to the processor for processing, and the image of the scene is output on the display screen.
  • a 3D structured light sensor and a time of flight (ToF) sensor may be used for face recognition to unlock the display device.
  • ToF time of flight
  • the display device provided by the embodiment of the present disclosure can display images in the light-transmitting display area to maintain the display integrity of the entire display device.
  • the thickness and size of the layer or microstructure are exaggerated. It is understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, the element may be “directly” “on” or “under” the other element, or there may be intermediate elements.

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Abstract

一种显示基板和显示装置，其中，显示基板包括：显示区域(AA)，显示区域(AA)包括透光显示区(A1)；显示基板包括：多个发光元件和多个像素电路，多个发光元件包括位于透光显示区(A1)的多个第一类型发光元件(L1)，多个像素电路包括位于透光显示区(A1)的多个第一类型像素电路(P1)，多个第一类型像素电路(P1)中的至少一个第一类型像素电路(P1)与出射相同颜色光的至少两个第一类型发光元件(L1)电连接，第一类型像素电路(P1)被配置为驱动至少两个第一类型发光元件(L1)发光；至少一个第一类型像素电路(P1)在基底的正投影与至少一个第一类型发光元件(L1)在基底的正投影存在交叠。

Description

显示基板和显示装置 技术领域
本公开涉及但不限于显示技术领域，尤指一种显示基板和显示装置。
背景技术
有机发光二极管(OLED，Organic Light Emitting Diode)和量子点发光二极管(QLED，Quantum-dot Light Emitting Diode)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。屏下摄像头技术是为了提高显示装置的屏占比所提出的一种全新的技术。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种显示基板，一种显示基板，包括：显示区域和至少部分围绕所述显示区域的周边区域，所述显示区域包括透光显示区和位于所述透光显示区至少一侧的常规显示区，所述透光显示区的光透过率大于所述常规显示区的光透过率；
所述显示基板包括：基底和位于所述基底一侧的多个发光元件和多个像素电路，所述多个发光元件包括位于所述透光显示区的多个第一类型发光元件，所述多个像素电路包括位于所述透光显示区的多个第一类型像素电路，所述多个第一类型像素电路中的至少一个第一类型像素电路与出射相同颜色光的至少两个第一类型发光元件电连接，所述第一类型像素电路被配置为驱动所述至少两个第一类型发光元件发光；
所述至少一个第一类型像素电路在所述基底的正投影与所述至少一个第一类型发光元件在所述基底的正投影存在交叠。
在示例性实施方式中，所述至少一个第一类型像素电路在所述基底的正 投影和与所述至少一个第一类型像素电路电连接的至少两个第一类型发光元件中的至少部分第一类型发光元件在所述基底的正投影存在交叠。
在示例性实施方式中，还包括：多条第一信号线，所述至少一个第一类型像素电路与至少一条第一信号线电连接；
所述多条第一信号线包括以下至少之一：扫描信号线、复位信号线、初始信号线、发光信号线。
在示例性实施方式中，所述多条第一信号线包括多条子信号线；所述第一信号线的相邻子信号线通过电连接的所述第一类型像素电路电连接。
在示例性实施方式中，还包括：多条第二信号线，所述至少一个第一类型像素电路与至少一条第二信号线电连接；
所述多条第二信号线包括以下至少之一：数据信号线和第一电源线，所述多条数据信号线和所述多条第一电源线沿第一方向延伸；所述第一类型像素电路电连接的数据信号线和第一电源线位于所述第一信号线的相邻子信号线之间，且所述第一类型像素电路电连接的数据信号线和第一电源线在所述基底上的正投影与所述第一类型像素电路在所述基底上的正投影交叠。
在示例性实施方式中，所述扫描信号线、所述复位信号线、所述初始信号线、所述发光信号线、所述数据信号线和所述第一电源线中的至少一种在所述基底的正投影与所述第一类型发光元件在所述基底的正投影部分交叠。
在示例性实施方式中，所述多个第一类型发光元件至少包括：出射第一颜色光的多个第一发光元件、出射第二颜色光的多个第二发光元件以及出射第三颜色光的多个第三发光元件；
所述多个第一发光元件中的至少一个第一发光元件的阳极面积大于所述多个第三发光元件中的至少一个第三发光元件的阳极面积，所述多个第二发光元件中的至少一个第二发光元件的阳极面积大于所述至少一个第三发光元件的阳极面积，所述多个第二发光元件中的至少一个第二发光元件的阳极面积大于所述多个第一发光元件中的至少一个第一发光元件的阳极面积；
所述第一颜色光为红光，所述第二颜色光为蓝光，所述第三颜色光为绿光。
在示例性实施方式中，所述第一类型像素电路包括：多个晶体管和至少一个电容；在垂直于所述显示基板的方向上，所述透光显示区至少包括：设置在所述基底上的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层、透明导电层、第一平坦层、第四导电层和第二平坦层；
所述半导体层至少包括：所述第一类型像素电路的多个晶体管的有源层；
所述第一导电层至少包括：所述第一类型像素电路的多个晶体管的控制极以及电容的第一极板；
所述第二导电层至少包括：所述第一类型像素电路的电容的第二极板；
所述第三导电层至少包括：所述第一类型像素电路的多个晶体管的第一极和第二极以及多个连接电极；
所述透明导电层至少包括：多条第一信号线、多条第二信号线和多条阳极连接线，所述多条阳极连接线中的至少一条阳极连接线与至少一个第一类型像素电路和出射相同颜色光的至少两个第一类型发光元件的阳极电连接；所述至少一个第一类型像素电路与至少一条第一信号线和至少一条第二信号线电连接；
所述第四导电层至少包括：多个信号连接线。
在示例性实施方式中，所述多个第一类型发光元件按照如下方式排布：
所述多个第三发光元件以一定间隔排布在第i行中，所述第二发光元件和所述第一发光元件交替地排布在第i行的相邻行中，所述第一发光元件和所述第二发光元件交替地排布在第j列中，所述多个第三发光元件以一定间隔排布在第j列的相邻列中，所述第一发光元件和所述第三发光元件沿第三方向交替地排布，所述第二发光元件和所述第三发光元件沿第四方向交替地排布，所述第三方向和所述第四方向分别与所述第一方向和第二方向相交，所述第一方向为列方向，所述第二方向为行方向。
在示例性实施方式中，所述多个第一类型像素电路包括：至少一个第一像素电路、至少一个第二像素电路、至少一个第三像素电路和至少一个第四像素电路；所述第一像素电路与两个所述第一发光元件电连接，所述第二像 素电路与两个所述第二发光元件电连接，所述第三像素电路与两个所述第三发光元件电连接，所述第四像素电路与两个所述第三发光元件电连接，所述第三像素电路和所述第四像素电路电连接的第三发光元件不同。
在示例性实施方式中，所述第一像素电路电连接的两个所述第一发光元件位于同一行，所述第二像素电路电连接的两个所述第二发光元件位于同一行，所述第三像素电路电连接的两个所述第三发光元件位于同一行，所述第四像素电路电连接的两个所述第三发光元件位于同一行。
在示例性实施方式中，所述第一像素电路在所述基底的正投影与电连接的一个所述第一发光元件在所述基底的正投影部分交叠；
所述第二像素电路在所述基底上的正投影与位于电连接的两个所述第二发光元件之间的所述第一发光元件在所述基底上的正投影部分交叠；
所述第三像素电路在所述基底上的正投影与所述第二发光元件在所述基底上的正投影部分交叠，与所述第三像素电路交叠的所述第二发光元件位于所述第三像素电路电连接的两个所述第三发光元件所在行的相邻行，且位于所述第三像素电路电连接的两个所述第三发光元件所在列的中间列；
所述第四像素电路在所述基底上的正投影与所述第二发光元件在所述基底上的正投影部分交叠，与所述第四像素电路交叠的所述第二发光元件位于所述第四像素电路电连接的两个所述第三发光元件所在行的相邻行，且位于所述第四像素电路电连接的两个所述第三发光元件所在列的中间列，与所述第三像素电路交叠的所述第二发光元件和与所述第四像素电路交叠的所述第二发光元件为不同发光元件。
在示例性实施方式中，所述第一信号线沿第二方向延伸；
所述阳极连接线包括：第一阳极连接线、第二阳极连接线、第三阳极连接线和第四阳极连接线；
所述第一阳极连接线分别与所述第一像素电路和所述第一发光元件电连接，且所述第一阳极连接线的至少部分沿所述第二方向延伸；所述第二阳极连接线分别与所述第二像素电路和所述第二发光元件电连接，且所述第二阳极连接线的至少部分沿所述第二方向延伸；所述第三阳极连接线分别与所述 第三像素电路和所述第三发光元件电连接，且所述第三阳极连接线的至少部分沿所述第二方向延伸，所述第三阳极连接线位于所述第三像素电路电连接的数据信号线和第一电源线之间；所述第四阳极连接线分别与所述第四像素电路和所述第三发光元件电连接，且所述第四阳极连接线的至少部分沿所述第二方向延伸，所述第四阳极连接线位于所述第四像素电路电连接的数据信号线和第一电源线之间。
在示例性实施方式中，位于同一列的至少两个相邻第一类型像素电路电连接的第一电源线间隔设置，且位于同一列的间隔设置的第一电源线通过位于所述第四导电层的至少一个信号连接线电连接；
位于同一列的至少两个相邻第一类型像素电路电连接的数据信号线间隔设置，且位于同一列的间隔设置的数据信号线通过位于所述第四导电层的至少一个信号连接线电连接。
在示例性实施方式中，所述第一像素电路电连接的两个所述第一发光元件沿第三方向排布，所述第二像素电路电连接的两个所述第二发光元件沿第四方向排布，所述第三像素电路电连接的两个所述第三发光元件位于同一列，所述第四像素电路电连接的两个所述第三发光元件位于同一列。
所述第一像素电路在所述基底的正投影与电连接的一个所述第一发光元件在所述基底的正投影部分交叠；
所述第二像素电路在所述基底的正投影与电连接的一个所述第二发光元件在所述基底的正投影部分交叠；
所述第三像素电路在所述基底的正投影与电连接的一个所述第三发光元件在所述基底的正投影部分交叠；
所述第四像素电路在所述基底的正投影与电连接的一个所述第三发光元件在所述基底的正投影部分交叠，与所述第三像素电路交叠的第三发光元件和与所述第四像素电路交叠的第三发光元件为不同发光元件。
在示例性实施方式中，所述阳极连接线包括：第一阳极连接线、第二阳极连接线、第三阳极连接线和第四阳极连接线；
所述第一阳极连接线分别与所述第一像素电路和所述第一发光元件电连 接，且所述第一阳极连接线的至少部分沿所述第一方向延伸；所述第二阳极连接线分别与所述第二像素电路和所述第二发光元件电连接，且所述第二阳极连接线的至少部分沿所述第一方向延伸；所述第三阳极连接线分别与所述第三像素电路和所述第三发光元件电连接，且所述第三阳极连接线的至少部分沿所述第一方向延伸，所述第三阳极连接线位于所述第三像素电路电连接的第一电源线远离数据信号线的一侧；所述第四阳极连接线分别与所述第四像素电路和所述第三发光元件电连接，且所述第四阳极连接线的至少部分沿所述第一方向延伸，所述第四阳极连接线位于所述第四像素电路电连接的第一电源线远离数据信号线的一侧。
在示例性实施方式中，位于同一列的第一类型像素电路电连接的数据信号线为同一信号线，位于同一列的至少两个相邻第一类型像素电路电连接的第一电源线间隔设置，且位于同一列的间隔设置的第一电源线通过位于所述第四导电层的至少一个信号连接线电连接。
在示例性实施方式中，所述透明导电层还包括：电源连接线，所述电源连接线的至少部分沿第二方向延伸；
所述电源连接线分别与位于同一行的相邻两个第一类型像素电路电连接的第一电源线电连接，所述第一电源线和所述电源连接线通过位于所述第三导电层的连接电极电连接。
在示例性实施方式中，对于同一第一类型像素电路，所述第一电源线包括：沿所述第一方向延伸的电源主体部和沿所述第二方向延伸的电源连接部，所述电源连接部位于所述电源主体部远离所述数据信号线的一侧；
所述电源连接线分别与位于同一行的相邻第一类型像素电路中的其中一个第一类型像素电路的电源连接部和另一个第一类型像素电路的电源主体部电连接。
在示例性实施方式中，所述多个第一类型发光元件按照如下方式排布：
所述多个第二发光元件排布在第j列中，所述第一发光元件和所述第三发光元件交替地排布在第j列的相邻列中，所述多个第二发光元件排布在第i行中，位于同一行的相邻第二发光元件之间设置所述第一发光元件和所述第三发光元件。
在示例性实施方式中，所述多个第一类型像素电路包括：至少一个第一像素电路、至少一个第二像素电路和至少一个第三像素电路；所述第一像素电路与两个所述第一发光元件电连接，所述第二像素电路与两个所述第二发光元件电连接和所述第三像素电路与两个所述第三发光元件电连接。
在示例性实施方式中，所述第一像素电路电连接的两个第一发光元件位于同一行，所述第二像素电路电连接的两个第二发光元件位于同一行，所述第三像素电路电连接的两个所述第三发光元件位于同一行。
在示例性实施方式中，所述第一像素电路在所述基底的正投影与电连接的一个所述第一发光元件在所述基底的正投影部分交叠；
所述第二像素电路在所述基底上的正投影与电连接的一个所述第二发光元件在所述基底上的正投影部分交叠；
所述第三像素电路在所述基底上的正投影与电连接的一个所述第三发光元件在所述基底上的正投影部分交叠。
在示例性实施方式中，所述第一像素电路交叠的所述第一发光元件、所述第二像素电路交叠的所述第二发光元件和所述第三像素电路交叠的所述第三发光元件中的至少两个相邻。
在示例性实施方式中，所述第一像素电路在所述基底的正投影与电连接的一个所述第一发光元件在所述基底的正投影部分交叠；
所述第二像素电路在所述基底上的正投影与电连接的一个所述第二发光元件在所述基底上的正投影部分交叠；
所述第三像素电路在所述基底上的正投影与位于所述第三像素电路电连接的两个所述第三发光元件之间的所述第二发光元件在所述基底上的正投影部分交叠。
在示例性实施方式中，所述第一像素电路在所述基底的正投影与位于所述第一像素电路电连接的两个所述第一发光元件之间的第二发光元件在所述基底的正投影部分交叠；
所述第二像素电路在所述基底上的正投影与电连接的一个所述第二发光元件在所述基底上的正投影部分交叠；
所述第三像素电路在所述基底上的正投影与电连接的一个所述第三发光元件在基底上的正投影部分交叠。
在示例性实施方式中，所述阳极连接线包括：第一阳极连接线、第二阳极连接线和第三阳极连接线；
所述第一阳极连接线分别与所述第一像素电路和所述第一发光元件电连接，且所述第一阳极连接线的至少部分沿所述第二方向延伸；所述第二阳极连接线分别与所述第二像素电路和所述第二发光元件电连接，且所述第二阳极连接线的至少部分沿所述第二方向延伸；所述第三阳极连接线分别与所述第三像素电路和所述第三发光元件电连接，且所述第三阳极连接线的至少部分沿所述第二方向延伸。
在示例性实施方式中，位于同一列的第一类型像素电路电连接的数据信号线为同一信号线，位于同一列的至少两个相邻第一类型像素电路电连接的第一电源线间隔设置，且位于同一列的间隔设置的第一电源线通过位于所述第四导电层的至少一个信号连接线电连接。
在示例性实施方式中，所述多个发光元件还包括位于所述常规显示区的多个第二类型发光元件，所述多个像素电路还包括位于所述常规显示区的多个第二类型像素电路；
所述多个第二类型发光元件中的至少一个第二类型发光元件和所述多个第二类型像素电路中的至少一个第二类型像素电路电连接，且所述第二类型发光元件在所述基底的正投影和电连接的第二类型像素电路在所述基底的正投影存在交叠。
第二方面，本公开还提供了一种显示装置，包括上述显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例， 目的只是示意说明本公开内容。
图1为本公开至少一实施例的显示基板的示意图；
图2为本公开至少一实施例的透光显示区的第一类型发光元件的排布示意图一；
图3为本公开至少一实施例的透光显示区的第一类型发光元件的排布示意图二；
图4为一种示例性实施例提供的透光显示区的第一类型像素电路和第一类型发光元件的排布关系示意图一；
图5为一种示例性实施例提供的透光显示区的第一类型像素电路和第一类型发光元件的排布关系示意图二；
图6为一种示例性实施例提供的透光显示区的第一类型像素电路和第一类型发光元件的排布关系示意图三；
图7为一种示例性实施例提供的透光显示区的第一类型像素电路和第一类型发光元件的排布关系示意图四；
图8为一种示例性实施例提供的透光显示区的第一类型像素电路和第一类型发光元件的排布关系示意图五；
图9为一种示例性实施例提供的透光显示区的第一类型像素电路和第一类型发光元件的排布关系示意图六；
图10为一种第一类型像素电路的等效电路图；
图11为图10提供的第一类型像素电路的工作时序图；
图12为一种示例性实施例提供的透光显示区的局部俯视图一；
图13为一种示例性实施例提供的透光显示区的局部俯视图二；
图14为一种示例性实施例提供的透光显示区的局部俯视图三；
图15A为图12提供的透光显示区形成半导体图案后的示意图；
图15B为图12提供的透光显示区第一导电层图案的示意图；
图15C为图12提供的透光显示区形成第一导电层图案后的示意图；
图15D为图12提供的透光显示区第二导电层图案的示意图；
图15E为图12提供的透光显示区形成第二导电层图案后的示意图；
图15F为图12提供的透光显示区形成第三绝缘层图案后的示意图；
图15G为图12提供的透光显示区第三导电层图案的示意图；
图15H为图12提供的透光显示区形成第三导电层图案后的示意图；
图15I为图12提供的透光显示区形成第四绝缘层图案后的示意图；
图15J为图12提供的透光显示区透明导电层图案的示意图；
图15K为图12提供的透光显示区形成透明导电层图案后的示意图；
图15L为图12提供的透光显示区形成第一平坦层后的示意图；
图15M为图12提供的透光显示区第四导电层图案的示意图；
图15N为图12提供的透光显示区形成第四导电层图案后的示意图；
图15O为图12提供的透光显示区形成第二平坦层图案后的示意图；
图15P为图12提供的透光显示区阳极导电层图案的示意图；
图15Q为图12提供的透光显示区形成阳极导电层图案后的示意图；
图16A为图13提供的透光显示区形成半导体图案后的示意图；
图16B为图13提供的透光显示区第一导电层图案的示意图；
图16C为图13提供的透光显示区形成第一导电层图案后的示意图；
图16D为图13提供的透光显示区第二导电层图案的示意图；
图16E为图13提供的透光显示区形成第二导电层图案后的示意图；
图16F为图13提供的透光显示区形成第三绝缘层图案后的示意图；
图16G为图13提供的透光显示区第三导电层图案的示意图；
图16H为图13提供的透光显示区形成第三导电层图案后的示意图；
图16I为图13提供的透光显示区形成第四绝缘层图案后的示意图；
图16J为图13提供的透光显示区透明导电层图案的示意图；
图16K为图13提供的透光显示区形成透明导电层图案后的示意图；
图16L为图13提供的透光显示区形成第一平坦层后的示意图；
图16M为图13提供的透光显示区第四导电层图案的示意图；
图16N为图13提供的透光显示区形成第四导电层图案后的示意图；
图16O为图13提供的透光显示区形成第二平坦层图案后的示意图；
图16P为图13提供的透光显示区阳极导电层图案的示意图；
图16Q为图13提供的透光显示区形成阳极导电层图案后的示意图；
图17A为图14提供的透光显示区形成半导体图案后的示意图；
图17B为图14提供的透光显示区第一导电层图案的示意图；
图17C为图14提供的透光显示区形成第一导电层图案后的示意图；
图17D为图14提供的透光显示区第二导电层图案的示意图；
图17E为图14提供的透光显示区形成第二导电层图案后的示意图；
图17F为图14提供的透光显示区形成第三绝缘层图案后的示意图；
图17G为图14提供的透光显示区第三导电层图案的示意图；
图17H为图14提供的透光显示区形成第三导电层图案后的示意图；
图17I为图14提供的透光显示区形成第四绝缘层图案后的示意图；
图17J为图14提供的透光显示区透明导电层图案的示意图；
图17K为图14提供的透光显示区形成透明导电层图案后的示意图；
图17L为图14提供的透光显示区形成第一平坦层后的示意图；
图17M为图14提供的透光显示区第四导电层图案的示意图；
图17N为图14提供的透光显示区形成第四导电层图案后的示意图；
图17O为图14提供的透光显示区形成第二平坦层图案后的示意图；
图17P为图14提供的透光显示区阳极导电层图案的示意图；
图17Q为图14提供的透光显示区形成阳极导电层图案后的示意图；
图18为本公开实施例提供的显示装置的结构示意图；
图19为图18沿A-A向的截面图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的 例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。另外，栅极还可以称为控制极。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本公开中的“光透过率”指的是光线透过介质的能力，是透过透明或半透明体的光通量与其入射光通量的百分率。
本公开中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。在本公开中，“大致相同”是指数值相差10％以内的情况。
本公开至少一实施例提供一种显示基板，包括：显示区域和至少部分围绕显示区域的周边区域，显示区域包括透光显示区和位于透光显示区至少一侧的常规显示区，透光显示区的光透过率大于常规显示区的光透过率；显示基板包括：基底和位于基底一侧的多个发光元件和多个像素电路，多个发光元件包括位于透光显示区的多个第一类型发光元件，多个像素电路包括位于透光显示区的多个第一类型像素电路，多个第一类型像素电路中的至少一个第一类型像素电路与出射相同颜色光的至少两个第一类型发光元件电连接，第一类型像素电路被配置为驱动至少两个第一类型发光元件发光；至少一个第一类型像素电路在基底的正投影与至少一个第一类型发光元件在基底的正 投影存在交叠。
本公开实施例提供的显示基板，通过减少透光显示区的第一类型像素电路的数量，利用一个第一类型像素电路驱动至少两个出射相同颜色光的第一类型发光元件，从而可以保证显示基板的显示区域的分辨率(PPI)一致，并提高透光显示区的光透过率，并降低透光显示区在拍照时的衍射。本实施例提供的显示基板可以适用于QHD(Quarter High Definition)显示设备。然而，本实施例对此并不限定。
在示例性实施方式中，至少一个第一类型像素电路在基底的正投影和与至少一个第一类型像素电路电连接的至少两个第一类型发光元件中的至少部分第一类型发光元件在基底的正投影存在交叠。
在示例性实施方式中，显示基板还可以包括：多条第一信号线，至少一个第一类型像素电路与至少一条第一信号线电连接。其中，多条第一信号线包括以下至少之一：扫描信号线、复位信号线、初始信号线、发光信号线。
在示例性实施方式中，多条第一信号线包括多条子信号线；第一信号线的相邻子信号线通过电连接的第一类型像素电路电连接。
在示例性实施方式中，显示基板还可以包括：多条第二信号线，至少一个第一类型像素电路与至少一条第二信号线电连接；多条第二信号线包括以下至少之一：数据信号线和第一电源线，多条数据信号线和多条第一电源线沿第一方向延伸。
在示例性实施方式中，第一类型像素电路电连接的数据信号线和第一电源线位于第一信号线的相邻子信号线之间，且第一类型像素电路电连接的数据信号线和第一电源线在基底上的正投影与第一类型像素电路在基底上的正投影交叠。
在示例性实施方式中，扫描信号线、复位信号线、初始信号线、发光信号线、数据信号线和第一电源线中的至少一种在基底的正投影与第一类型发光元件在基底的正投影部分交叠。
在示例性实施方式中，多个第一类型发光元件至少包括：出射第一颜色光的多个第一发光元件、出射第二颜色光的多个第二发光元件以及出射第三 颜色光的多个第三发光元件。多个第一发光元件中的至少一个第一发光元件的阳极面积大于多个第三发光元件中的至少一个第三发光元件的阳极面积，多个第二发光元件中的至少一个第二发光元件的阳极面积大于至少一个第三发光元件的阳极面积。在一些示例中，第一颜色光可以为红光，第二颜色光可以为蓝光，第三颜色光可以为绿光。
下面通过一些示例对本实施例的方案进行举例说明。
图1为本公开至少一实施例的显示基板的示意图。在示例性实施方式中，如图1所示，显示基板可以包括：显示区域AA和围绕在显示区域AA外围的周边区域BB。显示基板的显示区域AA可以包括：透光显示区A1和位于透光显示区A1至少一侧的常规显示区A2。在一些示例中，透光显示区A1即为前述的透光显示区，透光显示区A1还可以称为屏下摄像头(UDC，Under Display Camera)区域。常规显示区A2还可以称为正常显示区。例如，感光传感器(如，摄像头、红外传感器)等硬件在显示基板上的正投影可以位于显示基板的透光显示区A1内。在一些示例中，如图1所示，透光显示区A1可以为圆形，感光传感器在显示基板上的正投影的尺寸可以小于或等于透光显示区A1的尺寸。然而，本实施例对此并不限定。
在另一些示例中，透光显示区可以为矩形，感光传感器在显示基板上的正投影的尺寸可以小于或等于透光显示区的内切圆的尺寸。
在示例性实施方式中，如图1所示，透光显示区A1可以位于显示区域AA的顶部正中间位置。常规显示区A2可以围绕在透光显示区A1的四周。然而，本实施例对此并不限定。例如，透光显示区A1可以位于显示区域AA的左上角或者右上角等其他位置。
在示例性实施方式中，如图1所示，显示区域AA可以为矩形，例如圆角矩形。透光显示区A1可以为圆形或椭圆形。然而，本实施例对此并不限定。例如，透光显示区可以为矩形、五边形、或六边形等其他形状。
在示例性实施方式中，显示区域AA至少包括规则排布的多个像素单元、沿着第一方向Y延伸的多条栅线(例如包括：扫描信号线、复位信号线、发光信号线)、沿着第二方向X延伸的多条数据信号线和第一电源线。其中，第一方向Y和第二方向X位于同一平面内，且第一方向Y与第二方向X交 叉，例如，第一方向Y垂直于第二方向X。
在示例性实施方式中，显示区域AA的一个像素单元可以包括三个子像素，三个子像素可以分别为红色子像素、绿色子像素和蓝色子像素。然而，本实施例对此并不限定。在一些示例中，一个像素单元可以包括四个子像素，四个子像素可以分别为红色子像素、绿色子像素、蓝色子像素和白色子像素。
在示例性实施方式中，子像素的形状可以是矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列；一个像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形方式排列。然而，本实施例对此并不限定。
在示例性实施方式中，至少一个子像素包括像素电路和发光元件。像素电路配置为驱动电连接的发光元件。例如，像素电路配置为提供驱动电流以驱动发光元件发光。像素电路可以包括多个晶体管和至少一个电容，例如，像素电路可以为3T1C(3个晶体管和1个电容)结构、8T1C(8个晶体管和1个电容)结构、7T1C(7个晶体管和1个电容)结构或者5T1C(5个晶体管和1个电容)结构。在一些示例中，发光元件可以为有机发光二极管(OLED)，发光元件在其对应的像素电路的驱动下发出红光、绿光、蓝光、或者白光等。发光元件的发光颜色可根据需要而定。发光元件可以包括：阳极、阴极以及位于阳极和阴极之间的有机发光层。发光元件的阳极可以与对应的像素电路电连接。然而，本实施例对此并不限定。
在示例性实施方式中，如图1所示，显示基板包括：基底和位于基底一侧的多个发光元件和多个像素电路。多个发光元件可以包括位于透光显示区A1的多个第一类型发光元件L1和位于常规显示区A2的第二类型发光元件L2，多个像素电路可以包括位于透光显示区A1的多个第一类型像素电路P1和位于常规显示区A2的第二类型像素电路P2。
在示例性实施方式中，透光显示区A1设置有多个第一类型发光元件和多个第一类型像素电路。至少一个第一类型像素电路与出射相同颜色光的至少两个第一类型发光元件电连接。即，透光显示区A1内的至少两个同色子像素共用一个第一类型像素电路。常规显示区A2设置有多个第二类型发光元件和多个第二类型像素电路。多个第二类型发光元件和多个第二类型像素 电路一一对应电连接。本示例性实施方式的显示基板在透光显示区A1采用一个第一类型像素电路驱动至少两个第一类型发光元件的设计，可以在保证显示基板的显示区域的分辨率一致的同时，并提高透光显示区的光透过率，并降低拍照时的衍射。然而，本实施例对此并不限定。
图2为本公开至少一实施例的透光显示区的第一类型发光元件的排布示意图一，图3为本公开至少一实施例的透光显示区的第一类型发光元件的排布示意图二。在示例性实施方式中，如图2和图3所示，透光显示区A1的多个第一类型发光元件可以包括：出射第一颜色光的多个第一发光元件11、出射第二颜色光的多个第二发光元件12、出射第三颜色光的多个第三发光元件13。例如，第一颜色光可以为红光，第二颜色光可以为蓝光，第三颜色光可以为绿光。即，第一发光元件11可以为红色发光元件，第二发光元件12可以为蓝色发光元件，第三发光元件13可以为绿色发光元件。然而，本实施例对此并不限定。
在示例性实施方式中，如图2所示，透光显示区A1的多个第一类型发光元件可以按照Pentile结构排布。其中，多个第三发光元件13以一定间隔排布在第i行中，第二发光元件12和第一发光元件11交替地排布在第i行的相邻行中，第一发光元件11和第二发光元件12交替地排布在第j列中，多个第三发光元件13以一定间隔排布在第j列的相邻列中，第一发光元件11和第三发光元件13沿第三方向F1交替地排布，第二发光元件12和第三发光元件13沿第四方向F2交替地排布，第三方向F1和第四方向F4分别与第一方向Y和第二方向X相交，第一方向Y为列方向，第二方向X为行方向。示例性地，多个第三发光元件13以一定间隔排布在第i行中，第二发光元件12和第一发光元件11交替地排布在第i行的相邻行中指的是多个第三发光元件13以一定间隔排布在第i行中，第二发光元件12和第一发光元件11交替地排布在第i行相邻的第i+1行中，多个第三发光元件13以一定间隔排布在第i+1行相邻的第i+2行中，第一发光元件11和第二发光元件12交替地排布在第i+2行相邻的第i+3行中。按照以上规律可以重复排布多行第一类型发光元件。示例性地，第一发光元件11和第二发光元件12交替地排布在第j列中，多个第三发光元件13以一定间隔排布在第j列的相邻列中指 的是第一发光元件11和第二发光元件12交替地排布在第j列中，多个第三发光元件13以一定间隔排布在第j列相邻的第j+1列中，第一发光元件11和第二发光元件12交替地排布在第j+1列相邻的第j+2列中，多个第三发光元件13以一定间隔排布在第j+3列中。按照以上规律可以重复排布多列第一类型发光元件。在本示例中，第一发光元件11和第二发光元件12的尺寸可以均大于第三发光元件13的尺寸。其中，i和j均为整数。
在示例性实施方式中，如图2所示，第一发光元件11的发光区域110、第二发光元件12的发光区域120、以及第三发光元件13的发光区域130可以均为圆形或椭圆形。第一发光元件11的发光区域110可以大于第三发光元件13的发光区域130，第二发光元件12的发光区域120可以大于第三发光元件13的发光区域130。在本示例中，发光元件的发光区域可以为发光元件位于像素定义层的像素开口的部分。
在示例性实施方式中，透光显示区A1的第一类型发光元件的发光区域可以小于常规显示区A2内出射相同颜色光的第二类型发光元件的发光区域。例如，第一类型发光元件的发光区域的面积可以为出射相同颜色光的第二类型发光元件的发光区域的面积的40％至60％，比如，可以约为50％。在本示例中，通过减小透光显示区A1的开口率，可以增加透光显示区A1的光透过区域，从而提高透光显示区A1的光透过率。
在示例性实施方式中，如图3所示，透光显示区A1的多个第一类型发光元件可以按照品字排布。多个第二发光元件12排布在第j列中，第一发光元件11和第三发光元件13交替地排布在第j列的相邻列中，多个第二发光元件12排布在第i行中，位于同一行的相邻第二发光元件12之间设置第一发光元件11和第三发光元件13。示例性地，多个第二发光元件12排布在第j列中，第一发光元件11和第三发光元件13交替地排布在第j列的相邻列中指的是多个第二发光元件12以一定间隔排布在第j列中，第一发光元件11和第三发光元件13交替地排布在第j列相邻的第j+1列中，多个第二发光元件12以一定间隔排布在第j+1列相邻的第j+2列中，第一发光元件11和第二发光元件12交替地排布在第j+2列相邻的第j+3列中。按照以上规律可以重复排布多列第一类型发光元件。
图4为一种示例性实施例提供的透光显示区的第一类型像素电路和第一类型发光元件的排布关系示意图一，图5为一种示例性实施例提供的透光显示区的第一类型像素电路和第一类型发光元件的排布关系示意图二，图6为一种示例性实施例提供的透光显示区的第一类型像素电路和第一类型发光元件的排布关系示意图三，图7为一种示例性实施例提供的透光显示区的第一类型像素电路和第一类型发光元件的排布关系示意图四，图8为一种示例性实施例提供的透光显示区的第一类型像素电路和第一类型发光元件的排布关系示意图五，图9为一种示例性实施例提供的透光显示区的第一类型像素电路和第一类型发光元件的排布关系示意图六。在图4至图9中以矩形框示意第一类型像素电路的位置。图4和图5是以透光显示区A1的多个第一类型发光元件可以按照Pentile结构排布为例进行说明的，图6至图9是以透光显示区A1的多个第一类型发光元件可以按照品字排布为例进行说明的。图4至图9均是以一个第一类型像素电路连接两个第一类型发光元件为例进行说明的。
在示例性实施方式中，如图4至图9所示，第一发光元件(例如，第一发光元件11a和11b)的阳极111的面积大于第三发光元件(例如，第三发光元件13a和13b)的阳极131的面积，第二发光元件(例如，第二发光元件12a和12b)的阳极121的面积大于第三发光元件(例如，第三发光元件13a和13b)的阳极131的面积。
在示例性实施方式中，多个第一类型像素电路包括：至少一个第一像素电路、至少一个第二像素电路、至少一个第三像素电路和至少一个第四像素电路；第一像素电路与两个第一发光元件电连接，第二像素电路与两个第二发光元件电连接，第三像素电路与两个第三发光元件电连接，第四像素电路与两个第三发光元件电连接，第三像素电路和第四像素电路电连接的第三发光元件不同。
在示例性实施方式中，如图4所示，透光显示区的多个第一类型像素电路可以至少包括：第一像素电路15a、第二像素电路15b、第三像素电路15c和第四像素电路15d。第一像素电路15a与出射第一颜色光的两个第一发光元件11a和11b电连接，配置为驱动两个第一发光元件11a和11b发光。第 一像素电路15a在基底的正投影与第一发光元件11a的阳极111在基底的正投影存在交叠，与第一发光元件11b的阳极在基底的正投影没有交叠。第二像素电路15b与出射第二颜色光的两个第二发光元件12a和12b电连接，配置为驱动两个第二发光元件12a和12b发光。第二像素电路15b在基底的正投影与第二发光元件12a和第二发光元件12b的阳极在基底的正投影没有交叠，与位于第二发光元件12a和第二发光元件12b之间的第一发光元件11b在基底的正投影交叠。第三像素电路15c与出射第三颜色光的两个第三发光元件13a和13b电连接，配置为驱动两个第三发光元件13a和13b发光。第三像素电路15c在基底的正投影与第二发光元件12a的阳极在基底的正投影存在交叠，与两个第三发光元件13a和13b的阳极在基底的正投影均没有交叠，与第三像素电路15c交叠的第二发光元件12a位于两个第三发光元件13a和13b所在行的上一行，且位于两个第三发光元件13a和13b所在列的中间列。第四像素电路15d与出射第三颜色光的两个第三发光元件13c和13d电连接，配置为驱动两个第三发光元件13c和13d发光。第四像素电路15d在基底的正投影与第二发光元件12b的阳极在基底的正投影存在交叠，与两个第三发光元件13c和13d的阳极在基底的正投影均没有交叠，与第四像素电路15d交叠的第二发光元件12b位于两个第三发光元件13c和13d所在行的上一行，且位于第三发光元件13c和13d所在列的中间列。
在一些示例性实施例中，如图4所示，第一类型像素电路位于具有较大阳极面积的第一发光元件或第二发光元件的阳极下方，且与具有较小阳极面积的第三发光元件的阳极没有交叠。在本示例中，将第一类型像素电路设置在具有较大阳极面积的第一类型发光元件下，在具有较小阳极面积的第一类型发光元件下不设置第一类型像素电路，可以提高透光显示区的光透光率。
在示例性实施方式中，如图4所示，第一像素电路15a所电连接的两个第一发光元件11a和11b在第二方向X上(即，两个第一发光元件11a和11b位于同一行)，第二像素电路15b所电连接的两个第二发光元件12a和12b在第二方向X上(即，两个第二发光元件12a和12b位于同一行)，第三像素电路15c所电连接的两个第三发光元件13a和13b在第二方向X上(即，两个第三发光元件13a和13b位于同一行)。第四像素电路15d所电连接的 两个第三发光元件13c和13d在第二方向X上(即，两个第三发光元件13c和13d位于同一行)。
在示例性实施方式中，如图5所示，透光显示区的多个第一类型像素电路可以至少包括：第一像素电路15a、第二像素电路15b、第三像素电路15c和第四像素电路15d。第一像素电路15a与出射第一颜色光的两个第一发光元件11a和11b电连接，配置为驱动两个第一发光元件11a和11b发光。第一像素电路15a在基底的正投影与第一发光元件11a的阳极111在基底的正投影存在交叠，与第一发光元件11b的阳极在基底的正投影没有交叠。第二像素电路15b与出射第二颜色光的两个第二发光元件12a和12b电连接，配置为驱动两个第二发光元件12a和12b发光。第二像素电路15b在基底的正投影与第二发光元件12a的阳极在基底的正投影存在交叠，与第二发光元件12b的阳极在基底的正投影没有交叠。第三像素电路15c与出射第三颜色光的两个第三发光元件13a和13b电连接，配置为驱动两个第三发光元件13a和13b发光。第三像素电路15c在基底的正投影与第三发光元件13a的阳极在基底的正投影存在交叠，与第三发光元件13b的阳极在基底的正投影没有交叠。第四像素电路15d与出射第三颜色光的两个第三发光元件13c和13d电连接，配置为驱动两个第三发光元件13c和13d发光。第四像素电路15d在基底的正投影与第三发光元件13c的阳极在基底的正投影存在交叠，与第三发光元件13d的阳极在基底的正投影没有交叠。
在示例性实施方式中，如图5所示，第一像素电路15a所电连接的两个第一发光元件11a和11b在第三方向F1上。第二像素电路15b所电连接的两个第二发光元件12a和12b在第三方向F1上。第三像素电路15c所电连接的两个第三发光元件13a和13b在第一方向Y上(即，两个第三发光元件13a和13b位于同一列)。第四像素电路15d所电连接的两个第三发光元件13c和13d在第一方向Y上(即，两个第三发光元件13c和13d位于同一列)。
在示例性实施方式中，多个第一类型像素电路可以包括：至少一个第一像素电路、至少一个第二像素电路和至少一个第三像素电路；第一像素电路与两个第一发光元件电连接，第二像素电路与两个第二发光元件电连接和第三像素电路与两个第三发光元件电连接。
在示例性实施方式中，如图6所示，透光显示区的多个第一类型像素电路可以至少包括：第一像素电路15a、第二像素电路15b和第三像素电路15c。第一像素电路15a与出射第一颜色光的两个第一发光元件11a和11b电连接，配置为驱动两个第一发光元件11a和11b发光。第一像素电路15a在基底的正投影与第一发光元件11a的阳极111在基底的正投影存在交叠，与第一发光元件11b的阳极在基底的正投影没有交叠。第二像素电路15b与出射第二颜色光的两个第二发光元件12a和12b电连接，配置为驱动两个第二发光元件12a和12b发光。第二像素电路15b在基底的正投影与第二发光元件12a的阳极在基底的正投影存在交叠，与第二发光元件12b在基底的正投影没有交叠。第三像素电路15c与出射第三颜色光的两个第三发光元件13a和13b电连接，配置为驱动两个第三发光元件13a和13b发光。第三像素电路15c在基底的正投影与第三发光元件13a的阳极在基底的正投影存在交叠，与第三发光元件13b的阳极在基底的正投影没有交叠。
在示例性实施方式中，如图7所示，透光显示区的多个第一类型像素电路可以至少包括：第一像素电路15a、第二像素电路15b和第三像素电路15c。第一像素电路15a与出射第一颜色光的两个第一发光元件11a和11b电连接，配置为驱动两个第一发光元件11a和11b发光。第一像素电路15a在基底的正投影与第一发光元件11b的阳极111在基底的正投影存在交叠，与第一发光元件11a的阳极在基底的正投影没有交叠。第二像素电路15b与出射第二颜色光的两个第二发光元件12a和12b电连接，配置为驱动两个第二发光元件12a和12b发光。第二像素电路15b在基底的正投影与第二发光元件12a的阳极在基底的正投影存在交叠，与第二发光元件12b在基底的正投影没有交叠。第三像素电路15c与出射第三颜色光的两个第三发光元件13a和13b电连接，配置为驱动两个第三发光元件13a和13b发光。第三像素电路15c在基底的正投影与第三发光元件13a的阳极在基底的正投影存在交叠，与第三发光元件13b的阳极在基底的正投影没有交叠。
在示例性实施方式中，如图8所示，透光显示区的多个第一类型像素电路可以至少包括：第一像素电路15a、第二像素电路15b和第三像素电路15c。第一像素电路15a与出射第一颜色光的两个第一发光元件11a和11b电连接， 配置为驱动两个第一发光元件11a和11b发光。第一像素电路15a在基底的正投影与第一发光元件11a的阳极111在基底的正投影存在交叠，与第一发光元件11b的阳极在基底的正投影没有交叠。第二像素电路15b与出射第二颜色光的两个第二发光元件12a和12b电连接，配置为驱动两个第二发光元件12a和12b发光。第二像素电路15b在基底的正投影与第二发光元件12a的阳极在基底的正投影存在交叠，与第二发光元件12b在基底的正投影没有交叠。第三像素电路15c与出射第三颜色光的两个第三发光元件13a和13b电连接，配置为驱动两个第三发光元件13a和13b发光。第三像素电路15c在基底的正投影与两个第三发光元件13a和13b的阳极在基底的正投影没有交叠，与位于两个第三发光元件13a和13b之间的第二发光元件12b的阳极在基底上的正投影存在交叠。
在示例性实施方式中，如图9所示，透光显示区的多个第一类型像素电路可以至少包括：第一像素电路15a、第二像素电路15b和第三像素电路15c。第一像素电路15a与出射第一颜色光的两个第一发光元件11a和11b电连接，配置为驱动两个第一发光元件11a和11b发光。第一像素电路15a在基底的正投影与第一发光元件11a和11b的阳极111在基底的正投影没有交叠，与位于第一发光元件11a和11b之间的第二发光元件12b的阳极在基底的正投影存在交叠。第二像素电路15b与出射第二颜色光的两个第二发光元件12a和12b电连接，配置为驱动两个第二发光元件12a和12b发光。第二像素电路15b在基底的正投影与第二发光元件12a的阳极在基底的正投影存在交叠，与第二发光元件12b在基底的正投影没有交叠。第三像素电路15c与出射第三颜色光的两个第三发光元件13a和13b电连接，配置为驱动两个第三发光元件13a和13b发光。第三像素电路15c在基底的正投影与第三发光元件13a的阳极在基底的正投影存在交叠，与第三发光元件13b的阳极在基底上的正投影没有交叠。
在示例性实施方式中，如图6至图9所示，第一像素电路15a所电连接的两个第一发光元件11a和11b在第二方向X上(即，两个第一发光元件11a和11b位于同一行)，第二像素电路15b所电连接的两个第二发光元件12a和12b在第二方向X上(即，两个第二发光元件12a和12b位于同一行)， 第三像素电路15c所电连接的两个第三发光元件13a和13b在第二方向X上(即，两个第三发光元件13a和13b位于同一行)。
在示例性实施方式中，与第一像素电路交叠的第一发光元件、第二像素电路交叠的第二发光元件和第三像素电路交叠的第三发光元件中的至少两个相邻。图7是以与第一像素电路交叠的第一发光元件、第二像素电路交叠的第二发光元件和第三像素电路交叠的第三发光元件位于同一发光单元为例进行说明的，图6、图8和图9与第一像素电路交叠的第一发光元件、第二像素电路交叠的第二发光元件和第三像素电路交叠的第三发光元件位于同一发光单元位于两个发光单元为例进行说明的，发光单元包括：第一发光元件、第二发光元件和第三发光元件。
在示例性实施方式中，在透光显示区，利用一个第一类型像素电路驱动至少两个出射相同颜色光的第一类型发光元件，并且将第一类型像素电路设置在具有第一发光元件、第二发光元件和第三发光元件的阳极下方，可以在确保显示基板的分辨率的基础上，提高光透过率。
图10为一种第一类型像素电路的等效电路图。在示例性实施方式中，如图10所示，本示例性实施例的第一类型像素电路可以为8T1C结构，即包括第一晶体管T1至第七晶体管T7以及电容C。第一类型发光元件EL1和EL2可以出射相同颜色光，且可以各自包括阳极、阴极以及位于阳极和阴极之间的有机发光层。在本示例中，第三晶体管T3为驱动晶体管。
在示例性实施方式中，如图10所示，第一类型像素电路与扫描信号线Gate、复位信号线RST、初始信号线INIT、发光信号线EM、数据信号线Data、第一电源线VDD和第二电源线VSS电连接。示例性地，第一电源线VDD配置为向第一类型像素电路提供恒定的第一电压信号，第二电源线VSS配置为向第一类型像素电路提供恒定的第二电压信号，并且第一电压信号的电压值大于第二电压信号的电压值。扫描信号线Gate配置为向第一类型像素电路提供扫描信号，数据信号线Data配置为向第一类型像素电路提供数据信号，发光信号线EM配置为向第一类型像素电路提供发光控制信号，复位信号线RST配置为向第一类型像素电路提供复位控制信号。在一些示例中，在第n行第一类型像素电路中，复位信号线RST可以与第n-1行第一类型像素电路 的扫描信号线Gate连接。如此，可以减少显示基板的信号线，实现显示基板的窄边框。
在示例性实施方式中，如图10所示，第一晶体管T1的控制极与复位信号线RST电连接，第一晶体管T1的第一极与初始信号线INIT电连接，第一晶体管T1的第二极与第一节点N1电连接。第二晶体管T2的控制极与扫描信号线Gate电连接，第二晶体管T2的第一极与第一节点N1电连接，第二晶体管T2的第二极与第三节点N3电连接。第三晶体管T3的控制极与第一节点N1电连接，第三晶体管T3的第一极与第二节点N2电连接，第三晶体管T3的第二极与第三节点N3电连接。第四晶体管T4的控制极与扫描信号线Gate电连接，第四晶体管T4的第一极与数据信号线Data电连接，第四晶体管T4的第二极与第二节点N2电连接。第五晶体管T5的控制极与发光信号线EM电连接，第五晶体管T5的第一极与第一电源线VDD电连接，第五晶体管T5的第二极与第二节点N2电连接。第六晶体管T6的控制极与发光信号线EM电连接，第六晶体管T6的第一极与第三节点N3电连接，第六晶体管T6的第二极与第四节点N4电连接。第七晶体管T7的控制极与扫描信号线Gate电连接，第七晶体管T7的第一极与初始信号线INIT电连接，第七晶体管T7的第二极与第四节点N4电连接。电容C的第一极板与第一节点N1电连接，电容C的第二极板与第一电源线VDD电连接。
在本示例中，第一节点N1为电容C、第一晶体管T1和第三晶体管T3的连接点，第二节点N2为第五晶体管T5、第四晶体管T4和第三晶体管T3的连接点，第三节点N3为第三晶体管T3、第二晶体管T2和第六晶体管T6的连接点，第四节点N4为第六晶体管T6、第七晶体管T7和两个第一类型发光元件EL1和EL2的连接点。
在示例性实施方式中，第一类型像素电路的第一晶体管T1至第七晶体管T7可以为均是P型晶体管，或者可以均是N型晶体管。
在示例性实施方式中，第一类型像素电路的第一类型晶体管(例如，第一晶体管T1至第七晶体管T7)可以采用低温多晶硅薄膜晶体管或者，采用氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物半导 体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(LTPO，Low Temperature Polycrystalline Oxide)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。然而，本实施例对此并不限定。例如，第一类型像素电路的多个晶体管可以均采用低温多晶硅薄膜晶体管，或者，均采用氧化物薄膜晶体管。
图11为图10提供的第一类型像素电路的工作时序图。下面参照图11对图10所示的第一类型像素电路的工作过程进行说明。其中，第一类型像素电路的第一晶体管T1至第七晶体管T7为P型晶体管。
在示例性实施方式中，如图10和图11所示，在一帧显示时间段，第一类型像素电路的工作过程可以包括：第一阶段S1、第二阶段S2和第三阶段S3。
第一阶段S1，称为复位阶段。复位信号线RST提供的信号为低电平信号，使第一晶体管T1导通。初始信号线INIT提供的初始信号被提供至第一节点N1，对第一节点N1进行初始化，清除电容C中原有数据电压。扫描信号线Gate提供的信号为高电平信号，发光信号线EM提供的发光控制信号EM为高电平信号，使第四晶体管T4、第二晶体管T2、第七晶体管T7、第五晶体管T5以及第六晶体管T6断开。此阶段第一类型发光元件EL1和EL2不发光。
第二阶段S2，称为数据写入阶段或者阈值补偿阶段。扫描信号线Gate提供的信号为低电平信号，数据信号线Data输出数据，此阶段由于第一节点N1的信号为低电平信号，因此，第三晶体管T3导通。扫描信号线Gate提供的信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通，第二晶体管T2和第四晶体管T4导通，使得数据信号线Data输出的数据电压Vdata经过第二节点N2、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第一节点N1，并将数据信号线Data输出的数据电压Vdata与第三晶体管T3的阈值电压之差充入电容C，电容C的第一电极(即第一节点N1)的电压为Vdata-|Vth|，其中，Vdata为数据信号线Data输出的数据电压，Vth 为第三晶体管T3的阈值电压。第七晶体管T7导通，使得初始信号线INIT提供的初始信号Vinit提供至第四节点N4，对两个第一类型发光元件EL1和EL2的阳极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保第一类型发光元件EL1和EL2不发光。复位信号线RST提供的信号为高电平信号，使第一晶体管T1断开。发光信号线EM提供的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段S3，称为发光阶段。发光信号线EM提供的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通。扫描信号线Gate和复位信号线RST提供的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第七晶体管T7以及第一晶体管T1断开。第一电源线VDD输出的第一电压信号通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向第一类型发光元件EL1和EL2的阳极提供驱动电压，驱动两个第一类型发光元件EL1和EL2发光。
在第一类型像素电路的驱动过程中，流过第三晶体管T3的驱动电流由其控制极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K×(Vgs-Vth) 2＝K×[(VDD-Vdata+|Vth|)-Vth] 2＝K×[VDD-Vdata] 2；
其中，I为流过第三晶体管T3的驱动电流，也就是驱动第一类型发光元件的驱动电流，K为常数，Vgs为第三晶体管T3的控制极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vdata为数据信号线Data输出的数据电压，VDD为第一电源线PL1输出的第一电压信号。
由上式中可以看到流经第一类型发光元件的电流与第三晶体管T3的阈值电压无关。因此，本实施例的第一类型像素电路可以较好地补偿第三晶体管T3的阈值电压。
图12为一种示例性实施例提供的透光显示区的局部俯视图一，图13为一种示例性实施例提供的透光显示区的局部俯视图二，图14为一种示例性实施例提供的透光显示区的局部俯视图三。图12是以图4提供的透光显示区为例进行说明的，图13是以图5提供的透光显示区为例进行说明的，图14是以图6提供的透光显示区为例进行说明的。
在示例性实施方式中，第一类型像素电路包括：多个晶体管和至少一个电容；在垂直于显示基板的方向上，透光显示区至少包括：设置在基底上的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层、透明导电层、第一平坦层、第四导电层和第二平坦层。
半导体层至少包括：第一类型像素电路的多个晶体管的有源层；
第一导电层至少包括：第一类型像素电路的多个晶体管的控制极以及电容的第一极板；
第二导电层至少包括：第一类型像素电路的电容的第二极板；
第三导电层至少包括：第一类型像素电路的多个晶体管的第一极和第二极以及多个连接电极；
透明导电层至少包括：多条第一信号线、多条第二信号线和多条阳极连接线，多条阳极连接线中的至少一条阳极连接线与至少一个第一类型像素电路和出射相同颜色光的至少两个第一类型发光元件的阳极电连接；至少一个第一类型像素电路与至少一条第一信号线和至少一条第二信号线电连接；
第四导电层至少包括：多个信号连接线。
在示例性实施方式中，如图12至图14所示，至少一条第一信号线包括多条子信号线；第一信号线的相邻子信号线通过第一类型像素电路电连接。示例性地，多条第一信号线包括以下至少之一：扫描信号线、复位信号线、初始信号线、发光信号线。如图12至图14是以扫描信号线包括两个子信号线Gate_1和Gate_2，复位信号线包括两个子信号线RST_1和RST_2，初始信号线包括两个子信号线INIT_1和INIT_2，发光信号线包括两个子信号线EM_1和EM_2为例进行说明的。
在示例性实施方式中，如图12至图14所示，多条第二信号线包括：多条数据信号线Data和多条第一电源线VDD，数据信号线Data和第一电源线VDD的至少部分沿第一方向Y延伸。第一类型像素电路电连接的数据信号线Data和第一电源线VDD位于第一信号线的相邻子信号线之间，且在基底上的正投影与第一类型像素电路在基底上的正投影交叠。
在示例性实施方式中，如图12所示，第一信号线的子信号线为折线形，且第一信号线的子信号线的至少部分沿第二方向X延伸。
在示例性实施方式中，如图12所示，阳极连接线可以包括：第一阳极连接线AL1、第二阳极连接线AL2、第三阳极连接线AL3和第四阳极连接线AL4。第一阳极连接线AL1、第二阳极连接线AL2、第三阳极连接线AL3和第四阳极连接线AL4可以为折线形。其中，第一阳极连接线AL1分别与第一像素电路和第一发光元件电连接，且第一阳极连接线AL1的至少部分可以沿第二方向X延伸。第二阳极连接线AL2分别与第二像素电路和第二发光元件电连接，且第二阳极连接线AL2的至少部分沿第二方向X延伸。第三阳极连接线AL3分别与第三像素电路和第三发光元件电连接，且第三阳极连接线AL3的至少部分沿第二方向X延伸，第三阳极连接线AL3位于第三像素电路电连接的数据信号线Data和第一电源线VDD之间。第四阳极连接线AL4分别与第四像素电路和第三发光元件电连接，且第四阳极连接线AL4的至少部分沿第二方向X延伸，第四阳极连接线AL4位于第四像素电路电连接的数据信号线Data和第一电源线VDD之间。
在示例性实施方式中，如图12所示，位于同一列的至少两个相邻第一类型像素电路电连接的第一电源线间隔设置，且位于同一列的间隔设置的第一电源线通过位于第四导电层的至少一个信号连接线电连接。
在示例性实施方式中，如图12所示，位于同一列的至少两个相邻第一类型像素电路电连接的数据信号线Data间隔设置，且位于同一列的间隔设置的数据信号线Data通过位于第四导电层的至少一个信号连接线电连接。
在示例性实施方式中，如图13所示，第一信号线的子信号线为折线型，且第一信号线的子信号线的至少部分沿第一方向Y延伸。
在示例性实施方式中，如图13所示，阳极连接线包括：第一阳极连接线AL1、第二阳极连接线AL2、第三阳极连接线AL3和第四阳极连接线AL4。第一阳极连接线AL1、第二阳极连接线AL2、第三阳极连接线AL3和第四阳极连接线AL4可以为折线形。其中，第一阳极连接线AL1分别与第一像素电路和第一发光元件电连接，且第一阳极连接线AL1的至少部分沿第一方向Y延伸。第二阳极连接线AL2分别与第二像素电路和第二发光元件电连接， 且第二阳极连接线AL2的至少部分沿第一方向Y延伸。第三阳极连接线AL3分别与第三像素电路和第三发光元件电连接，且第三阳极连接线AL3的至少部分沿第一方向Y延伸，第三阳极连接线AL3位于第三像素电路电连接的第一电源线VDD远离数据信号线Data的一侧。第四阳极连接线AL4分别与第四像素电路和第三发光元件电连接，且第四阳极连接线AL4的至少部分沿第一方向Y延伸，第四阳极连接线AL4位于第四像素电路电连接的第一电源线VDD远离数据信号线Data的一侧。
在示例性实施方式中，如图13所示，位于同一列的第一类型像素电路电连接的数据信号线Data为同一信号线。
在示例性实施方式中，如图13所示，位于同一列的至少两个相邻第一类型像素电路电连接的第一电源线VDD间隔设置，且位于同一列的间隔设置的第一电源线VDD通过位于第四导电层的至少一个信号连接线电连接。
在示例性实施方式中，如图13所示，透明导电层还可以包括：电源连接线VCL，电源连接线的至少部分沿第二方向X延伸。电源连接线VCL分别与位于同一行的相邻两个像素电路电连接的第一电源线VDD电连接，第一电源线VDD和电源连接线VCL通过位于第三导电层的连接电极电连接。
在示例性实施方式中，如图13所示，对于同一第一类型像素电路，第一电源线VDD可以包括：沿第一方向Y延伸的电源主体部VDDM和至少部分沿第二方向X延伸的电源连接部VDDS，电源连接部VDDS位于电源主体部VDDM远离数据信号线的一侧。电源连接线VDDS分别与位于同一行的相邻第一类型像素电路中的其中一个第一类型像素电路的电源连接部和另一个第一类型像素电路的电源主体部电连接。
在示例性实施方式中，如图14所示，第一信号线的子信号线可以为折线型，第一信号线的子信号线的至少部分可以沿第二方向X延伸。
在示例性实施方式中，如图14所示，阳极连接线可以包括：第一阳极连接线AL1、第二阳极连接线AL2和第三阳极连接线AL3；第一阳极连接线AL1、第二阳极连接线AL2和第三阳极连接线AL3可以为折线形。其中，第一阳极连接线AL1分别与第一像素电路和第一发光元件电连接，且第一阳极连接线AL1的至少部分沿第二方向X延伸；第二阳极连接线AL2分别与第 二像素电路和第二发光元件电连接，且第二阳极连接线AL2的至少部分沿第二方向X延伸；第三阳极连接线AL3分别与第三像素电路和第三发光元件电连接，且第三阳极连接线AL3的至少部分沿第二方向X延伸。
在示例性实施方式中，如图14所示，位于同一列的像素电路电连接的数据信号线Data为同一信号线。
在示例性实施方式中，如图14所示，位于同一列的至少两个相邻第一类型像素电路电连接的第一电源线VDD间隔设置，且位于同一列的间隔设置的第一电源线VDD通过位于第四导电层的至少一个信号连接线电连接。
下面通过显示基板的制备过程的示例说明显示基板的结构。本公开实施例所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。
在示例性实施方式中，图12提供的透光显示区的制备过程可以包括如下操作。
(1)形成半导体层图案。在示例性实施方式中，形成半导体层图案可以包括：在基底上依次沉积半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成半导体层图案，如图15A所示，图15A为图12提供的透光显示区形成半导体图案后的示意图。
在示例性实施方式中，如图15A所示，半导体层图案包括：第一晶体管的有源层T11至第七晶体管的有源层T71。第一晶体管的有源层T11至第七晶体管的有源层T71为相互连接的一体结构。
在示例性实施方式中，如图15A所示，在第二方向X上，第二晶体管的有源层T21、第六晶体管的有源层T61和第七晶体管的有源层T71可以位于本子像素中第三晶体管的有源层T31的同一侧，第四晶体管的有源层T41和第五晶体管的有源层T51可以位于本子像素中第三晶体管的有源层T31的同一侧，第二晶体管的有源层T21和第四晶体管的有源层T41可以位于本子像素的第三晶体管的有源层T31的不同侧。在第一方向Y上，第一晶体管的有源层T11、第二晶体管的有源层T21、第四晶体管的有源层T41和第七晶体管的有源层T71可以位于本子像素中第三晶体管的有源层T31的同一侧，第五晶体管的有源层T51和第六晶体管的有源层T61可以位于本子像素中第三晶体管的有源层T31的另一侧。
在示例性实施方式中，如图15A所示，第一晶体管的有源层T11的形状可以呈“n”字形，第二晶体管的有源层T21的形状可以呈“L”字形，第三晶体管的有源层T31的形状可以呈“Ω”字形，第四晶体管的有源层T41、第五晶体管的有源层T51、第六晶体管的有源层T61和第七晶体管的有源层T71的形状可以呈“I”字形。
(2)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第一绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第一绝缘层，以及位于第一绝缘层上的第一导电层图案，如图15B和图15C所示，其中，图15B为图12提供的透光显示区第一导电层图案的示意图，图15C为图12提供的透光显示区形成第一导电层图案后的示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，如图15B和图15C所示，第一导电层图案可以包括：第一晶体管的控制极T12至第七晶体管的控制极T72以及电容的第一极板C1。
在示例性实施方式中，如图15B和图15C所示，电容的第一极板C1的形状可以为矩形状，且矩形状的角部可以设置倒角，电容的第一极板C1在基底上的正投影与第三晶体管T3的有源层在基底上的正投影至少部分交叠。在示例性实施方式中，电容的第一极板C1可以同时作为第三晶体管的控制 极T32。
在示例性实施方式中，如图15B和图15C所示，第一晶体管的控制极T12的形状可以为沿第二方向X延伸的线形状。
在示例性实施方式中，如图15B和图15C所示，第二晶体管的控制极T22、第四晶体管的控制极T42和第七晶体管的控制极T72可以为一体成型结构，且形状可以为沿第二方向X延伸的线形状。
在示例性实施方式中，如图15B和图15C所示，第五晶体管的控制极T52和第六晶体管的控制极T62可以为一体成型结构，且形状可以为沿第二方向X延伸的线形状。
在示例性实施方式中，如图15C所示，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第七晶体管T7的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第一晶体管的有源层至第七晶体管的有源层的第一区和第二区均被导体化，且导体化后的第三晶体管的有源层的第一区(也是第四晶体管的有源层的第二区和第五晶体管的有源层的第二区)可以同时作为第三晶体管的第一极T33、第四晶体管的第二极T44和第五晶体管的第二极T54，导体化后的第三晶体管的有源层的第二区(也是第二晶体管的有源层的第二区和第六晶体管的有源层的第一区)也是同时作为第二晶体管的第二极T24、第三晶体管的第二极T34和第六晶体管的第一极T63。
(3)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，沉积第二绝缘层薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，在第二绝缘层上形成第二导电层图案。图15D和图15E所示，图15D为图12提供的透光显示区第二导电层图案的示意图，图15E为图12提供的透光显示区形成第二导电层图案后的示意图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，如图15D和图15E所示，第二导电层图案可以包括：第一连接电极VL1和电容的第二极板C2。
在示例性实施方式中，如图15D和图15E所示，第一连接电极VL1的 至少部分可以沿第二方向X延伸。
在示例性实施方式中，如图15D和图15E所示，第二极板C2的轮廓形状可以为“L”状，第二极板C2在基底上的正投影与第一极板C1在基底上的正投影存在重叠区域，第二极板C2作为电容的另一个极板。第一极板C1和第二极板C2构成像素电路的电容。
(4)形成第三绝缘层图案。在示例性实施方式中，形成第三绝缘层图案可以包括：在形成前述图案的基底上，沉积第三绝缘薄膜，采用图案化工艺对第三绝缘薄膜进行图案化，形成覆盖第二导电层的第三绝缘层，第三绝缘层上设置有多个过孔，如图15F所示，其中，图15F为图12提供的透光显示区形成第三绝缘层图案后的示意图。
在示例性实施方式中，如图15F所示，多个过孔可以均包括：设置在第一绝缘层至第三绝缘层的第一过孔V1至第六过孔V6，设置在第二绝缘层和第三绝缘层的第七过孔V7至第十三过孔V13以及设置在第三绝缘层上的第十四过孔V14至第十六过孔V16。其中，第一过孔V1暴露出第一晶体管的有源层和第二晶体管的有源层的连接部，第二过孔V2暴露出第一晶体管的有源层和第七晶体管的有源层的连接部，第三过孔V3暴露出第四晶体管的有源层，第四过孔V4暴露出第五晶体管的有源层，第五过孔V5暴露出第六晶体管的有源层，第六过孔V6暴露出第七晶体管的有源层，第七过孔V7和第八过孔V8分别暴露出第一晶体管的控制极的两端，第九过孔V10和第十过孔V10分别暴露出第二晶体管的控制极、第四晶体管的控制极和第七晶体管的控制极的一体成型结构的两端，第十一过孔V11和第十二过孔V12分别暴露出第五晶体管的控制极和第六晶体管的控制极的一体成型结构的两端，第十三过孔V13暴露出电容的第一极板，第十四过孔V14暴露出电容的第二极板，第十五过孔V15和第十六过孔V16分别暴露出第一连接电极的两端。
(5)形成第三导电层图案。在示例性实施方式中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第三绝缘层上的第三导电层，图15G和图15H所示，图15G为图12提供的透光显示区第三导电层图案的示意图， 图15H为图12提供的透光显示区形成第三导电层图案后的示意图。在示例性实施方式中，第三导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，如图15G和图15H所示，第三导电层图案可以包括：第一晶体管的第一极T13和第二极T14、第二晶体管的第一极T23、第四晶体管的第一极T43、第五晶体管的第一极T53、第六晶体管的第二极T64、第七晶体管的第一极T73和第二极T74、第二连接电极VL2至第十一连接电极VL11以及屏蔽电极SL。
在示例性实施方式中，如图15G和图15H所示，第一晶体管的第一极T13可以同时作为第七晶体管的第一极T73、第一晶体管的第二极T14可以同时作为第二晶体管的第一极T23、第六晶体管的第二极T64可以同时作为第七晶体管的第二极T74、第四晶体管的第一极T43和第五晶体管的第一极T53可以单独设置。第一晶体管的第一极T13和第一晶体管的第二极T14可以为L字型，第四晶体管的第一极T43为块状结构，第五晶体管的第一极T53为水平翻转的“L”字型，第六晶体管的第二极可以为沿第一方向Y延伸的折线型。
在示例性实施方式中，如图15G和图15H所示，第二连接电极VL2至第八连接电极VL8为块状结构，第九连接电极VL9至第十一连接电极VL11为沿第一方向Y延伸的线形状或者折线状。
在示例性实施方式中，如图15G和图15H所示，屏蔽电极SL为块状结构，且在基底上的正投影与第一晶体管的控制极在基底上的正投影部分交叠。
在示例性实施方式中，如图15G和图15H所示，第一晶体管的第一极T13通过第二过孔与第一晶体管的有源层和第七晶体管的有源层的连接点电连接，且通过第十六过孔与第一连接电极电连接，第一晶体管的第二极T14通过第一过孔与第一晶体管的有源层和第二晶体管的有源层的连接点电连接，且第十三过孔与电容的第一极板电连接，第四晶体管的第一极T43通过第三过孔与第四晶体管的有源层电连接，第五晶体管的第一极T53通过第四过孔与第五晶体管的有源层电连接，且通过第十四过孔与电容的第二极板电连接，第六晶体管的第二极T64通过第五过孔与第六晶体管的有源层电连接，且通过第六过孔与第七晶体管的有源层电连接。第二连接电极VL2通过第七过孔 与第一晶体管的控制极电连接。第三连接电极VL3通过第八过孔与第一晶体管的控制极电连接。第四连接电极VL4通过第九过孔与第四晶体管的控制极电连接，第五连接电极VL5通过第十过孔与第四晶体管的控制极电连接，第六连接电极VL6通过第十一过孔与第五晶体管的控制极电连接，第七连接电极VL7通过第十二过孔与第五晶体管的控制极电连接，第八连接电极VL8通过第十五过孔与第一连接电极电连接。
(6)形成第四绝缘层。在示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第三导电层的第四绝缘层，第四绝缘层上设置有多个过孔，如图15I所示。图15I为图12提供的透光显示区形成第四绝缘层图案后的示意图。
在示例性实施方式中，如图15I所示，第四绝缘层图案的多个过孔可以均包括：第十七过孔V17至第三十一过孔V31。其中，第十七过孔V17暴露出第一晶体管的第一极，第十八过孔V18暴露出第四晶体管的第一极，第十九过孔V19暴露出第五晶体管的第一极，第二十过孔V20暴露出第六晶体管的第二极，第二十一过孔V21暴露出第二连接电极，第二十二过孔V22暴露出第三连接电极，第二十三过孔V23暴露出第四连接电极，第二十四过孔V24暴露出第五连接电极，第二十五过孔V25暴露出第六连接电极，第二十六过孔V26暴露出第七连接电极，第二十七过孔V27暴露出第八连接电极，第二十八过孔V28暴露出屏蔽电极，第二十九过孔V29暴露出第九连接电极，第三十过孔V30暴露出第十连接电极，第三十一过孔V31暴露出第十一连接电极。
在示例性实施方式中，第二十九过孔V29的数量可以为两个，两个第二十九过孔可以沿第一方向Y排布，且分别位于第九连接电极的两端。
在示例性实施方式中，第三十过孔V30的数量可以为两个，两个第三十过孔V30可以沿第一方向Y排布，且分别位于第十连接电极的两端。
在示例性实施方式中，第三十一过孔V31的数量可以为两个，两个第三十一过孔V31可以沿第一方向Y排布，且分别位于第十一连接电极的两端。
(7)形成透明导电层图案。在示例性实施方式中，形成透明导电层图案 可以包括：在形成前述图案的基底上，沉积透明导电薄膜，采用图案化工艺对透明导电薄膜进行图案化，形成设置在第四绝缘层上的透明导电层，如图15J和图15K所示，图15J为图12提供的透光显示区透明导电层图案的示意图，图15K为图12提供的透光显示区形成透明导电层图案后的示意图。
在示例性实施方式中，如图15J和图15K所示，透明导电层图案可以包括：数据信号线Data、第一电源线VDD、第一阳极连接线AL1、第二阳极连接线AL2、第三阳极连接线AL3、第四阳极连接线AL4、初始信号线的两个子信号线INIT_1和INIT_2、复位信号线的两个子信号线RST_1和RST_2、扫描信号线的两个子信号线Gate_1和Gate_2、发光信号线的两个子信号线EM_1和EM_2，第十二连接电极VL12和第十三连接电极VL13。
在示例性实施方式中，如图15J和图15K所示，数据信号线Data和第一电源线VDD可以位于数据信号线Data和第一电源线VDD电连接的第一类型像素电路电连接的多个第一信号线的两个子信号线之间，且在基底上的正投影与第一类型像素电路在基底上的正投影存在交叠。
在示例性实施方式中，如图15J和图15K所示，数据信号线Data可以为折线型，数据信号线Data的至少部分可以沿第一方向Y延伸，且位于同一列的相邻第一类型像素电路电连接的数据信号线Data可以为同一信号线，或者可以间隔设置。间隔设置的位于同一列的相邻两个第一类型像素电路电连接的数据信号线Data可以分别通过第二十九过孔与第九连接电极电连接，位于同一列的间隔设置的第一类型像素电路电连接的数据信号线Data可以通过第九连接电极电连接。数据信号线通过第十八过孔与电连接的第一类型像素电路的第四晶体管的第一极电连接。
在示例性实施方式中，如图15J和图15K所示，第一电源线VDD可以为折线型，第一电源线VDD的至少部分可以沿第一方向Y延伸，且位于同一列的相邻第一类型像素电路电连接的第一电源线VDD可以间隔设置。第一电源线通过第十九过孔与电连接的第一类型像素电路的第五晶体管的第一极电连接，且通过第二十八过孔与屏蔽电极电连接。示例性地，间隔设置的位于同一列的相邻两个第一类型像素电路电连接的第一电源线VDD可以通过一个第十连接电极直接电连接，或者可以分别通过第十连接电极、第十二 连接电极和第十连接电极电连接。第一类型像素电路电连接的第一电源线VDD和十二连接电极可以通过第三十过孔与第十连接电极电连接。
在示例性实施方式中，第一阳极连接线AL1至第四阳极连接线AL4可以为折线状。
在示例性实施方式中，如图15J和图15K所示，第一阳极连接线AL1位于间隔设置的第一电源线之间，且第一阳极连接线AL1的至少部分沿第二方向X延伸，第一阳极连接线AL1通过第二十过孔与电连接的第一类型像素电路的第六晶体管的第二极电连接。
在示例性实施方式中，如图15J和图15K所示，第二阳极连接线AL2位于间隔设置的第一电源线之间，且第二阳极连接线AL2的至少部分沿第二方向X延伸，第二阳极连接线AL2通过第二十过孔与电连接的第一类型像素电路的第六晶体管的第二极电连接，且通过第三十一过孔与第十一连接电极电连接。
在示例性实施方式中，如图15J和图15K所示，第三阳极连接线AL3位于电连接的第一类型像素电路电连接的数据信号线Data和第一电源线VDD之间，且第三阳极连接线AL3的至少部分沿第二方向X延伸，第三阳极连接线AL3通过第二十过孔与电连接的第一类型像素电路的第六晶体管的第二极电连接。
在示例性实施方式中，如图15J和图15K所示，第四阳极连接线AL4位于电连接的第一类型像素电路电连接的数据信号线Data和第一电源线VDD之间，且第四阳极连接线AL4的至少部分沿第二方向X延伸，第四阳极连接线AL4通过第二十过孔与电连接的第一类型像素电路的第六晶体管的第二极电连接。
在示例性实施方式中，如图15J和图15K所示，第十三连接电极VL13的至少部分沿第二方向X延伸，且通过第三十一过孔与第十一连接电极电连接。第二阳极连接线AL1分别与电连接的第一类型像素电路、第十一连接电极和第十三连接电极电连接。
在示例性实施方式中，如图15J和图15K所示，初始信号线的两个子信号线INIT_1和INIT_2可以为折线型，初始信号线的两个子信号线INIT_1 和INIT_2的至少部分可以沿第二方向X延伸，初始信号线的子信号线INIT_1通过第二十七过孔与第八连接电极电连接，初始信号线的子信号线INIT_2通过第十七过孔与第一晶体管的第一极电连接。初始信号线的子信号线INIT_1通过第八连接电极与第一连接电极电连接。初始信号线的子信号线INIT_2通过第一晶体管的第一极与第一连接电极电连接。
在示例性实施方式中，如图15J和图15K所示，复位信号线的两个子信号线RST_1和RST_2可以为折线型，复位信号线的两个子信号线RST_1和RST_2的至少部分可以沿第二方向X延伸，复位信号线的子信号线RST_1通过第二十一过孔与第二连接电极电连接，复位信号线的子信号线RST_2通过第二十二过孔与第三连接电极电连接。复位信号线的子信号线RST_1通过第二连接电极与第一晶体管的控制极电连接，复位信号线的子信号线RST_2通过第三连接电极与第一晶体管的控制极电连接。
在示例性实施方式中，如图15J和图15K所示，扫描信号线的两个子信号线Gate_1和Gate_2可以为折线型，扫描信号线的两个子信号线Gate_1和Gate_2的至少部分可以沿第二方向X延伸，扫描信号线的子信号线Gate_1通过第二十三过孔与第四连接电极电连接，扫描信号线的子信号线Gate_2通过第二十四过孔与第五连接电极电连接。扫描信号线的子信号线Gate_1通过第四连接电极与第四晶体管的控制极电连接，扫描信号线的子信号线Gate_2通过第五连接电极与第四晶体管的控制极电连接。
在示例性实施方式中，如图15J和图15K所示，发光信号线的两个子信号线EM_1和EM_2可以为折线型，发光信号线的两个子信号线EM_1和EM_2的至少部分可以沿第二方向X延伸，发光信号线的子信号线EM_1通过第二十五过孔与第六连接电极电连接，发光信号线的子信号线EM_1通过第二十六过孔与第七连接电极电连接。发光信号线的子信号线EM_1通过第六连接电极与第五晶体管的控制极电连接，发光信号线的子信号线EM_2通过第七连接电极与第五晶体管的控制极电连接。
(8)形成第一平坦层图案。在示例性实施方式中，形成第一平坦层图案可以包括：在形成前述图案的基底上，沉积第一平坦薄膜，形成设置在透明导电层上的第一平坦层图案，第一平坦层图案包括多个过孔，如图15L所示， 图15L为图12提供的透光显示区形成第一平坦层后的示意图。
在示例性实施方式中，如图15L所示，第一平坦层图案可以包括：第三十二过孔V32和第三十八过孔V38。其中，第三十二过孔V32暴露出第一阳极连接线，第三十三过孔V33暴露出第二阳极连接线，第三十四过孔V34暴露出第三阳极连接线，第三十五过孔V35暴露出第四阳极连接线，第三十六过孔V36暴露出第十三连接电极，第三十七过孔V37暴露出第一电源线VDD，第三十八过孔V38暴露出第十二连接电极。
在示例性实施方式中，如图15L所示，第三十二过孔V32的数量可以为两个，且分别位于第一阳极连接线的两端。第三十三过孔V33的数量可以为两个，且分别位于第二阳极连接线的两端。第三十四过孔V34的数量可以为两个，且分别位于第三阳极连接线的两端。第三十五过孔V35的数量可以为两个，且分别位于第四阳极连接线的两端。
(9)形成第四导电层图案。在示例性实施方式中，形成第四导电层图案可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第一平坦层上的第四导电层，如图15M和图15N所示，图15M为图12提供的透光显示区第四导电层图案的示意图，图15N为图12提供的透光显示区形成第四导电层图案后的示意图。在示例性实施方式中，第四导电层可以称为第二源漏金属(SD2)层。
在示例性实施方式中，如图15M和图15N所示，第四导电层图案可以包括：第十四连接电极VL14至第二十一连接电极VL21，第一信号连接线VDL1和第二信号连接线VDL2。
在示例性实施方式中，如图15M和图15N所示，第十四连接电极VL14至第二十一连接电极VL21为块状结构。第一信号连接线VDL1和第二信号连接线VDL2可以为折线形，第一信号连接线VDL1和第二信号连接线VDL2的至少部分沿第一方向Y延伸。
在示例性实施方式中，如图15M和图15N所示，第十四连接电极VL14和第十五连接电极VL15通过第三十二过孔与第一阳极连接线电连接，第十六连接电极VL1通过第三十三过孔与第二阳极连接线电连接，第十七连接电极VL17通过第三十六过孔与第十三连接电极电连接，第十八连接电极VL18 和第十九连接电极VL19通过第三十四过孔与第三阳极连接线电连接，第二十过孔V20和第二十一过孔V21通过第三十五过孔与第四阳极连接线电连接。第一信号连接线VDL1通过第三十七过孔与第一类型像素电路电连接的第一电源线VDD电连接，第二信号连接线VDL2通过第三十八过孔与第十二连接电极电连接，且通过第三十七过孔与第一电源线电连接。
在示例性实施方式中，位于同一列的第一类型像素电路电连接的第一电源线通过第一电源连接线、第十连接电极和第二电源连接线连通。位于同一列的第一类型像素电路电连接的数据信号线通过第九连接电极连通。
在示例性实施例中，如图15N所示，第十四连接电极VL14通过第一阳极连接线与第十五连接电极VL15电连接，第十六连接电极VL16通过第二阳极连接线、第十一连接电极和第十三连接电极与第十七连接电极VL17电连接，第十八连接电极VL18通过第三阳极连接线与第十九连接电极VL19电连接，第二十连接电极VL20通过第四阳极连接线与第二十一连接电极VL21电连接。
在示例性实施方式中，多个连接电极起到了承接的作用，可以避免开设较深的过孔导致的连接的不可靠性，提升了显示面板的可靠性。
(10)形成第二平坦层图案。在示例性实施方式中，形成第二平坦层图案可以包括：在形成前述图案的基底上，涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成覆盖第四导电层的第二平坦层，第二平坦层上设置有多个过孔，如图15O所示，其中，图15O为图12提供的透光显示区形成第二平坦层图案后的示意图。
在示例性实施方式中，如图15O所示，第二平坦层图案的多个过孔可以均包括：第三十九过孔V39至第四十六过孔V46。其中，第三十九过孔V39暴露出第十四连接电极，第四十过孔V40暴露出第十五连接电极，第四十一过孔V41暴露出第十六连接电极，第四十二过孔V42暴露出第十七连接电极，第四十三过孔V43暴露出第十八连接电极，第四十四过孔V44暴露出第十九连接电极，第四十五过孔V45暴露出第二十连接电极，第四十六过孔V46暴露出第二十一连接电极。
至此，在基底上制备完成驱动电路层。在平行于显示基板的平面上，驱 动电路层可以包括多个第一类型像素电路、扫描信号线、复位信号线、发光信号线、数据信号线、初始信号线、第一阳极连接线至第四阳极连接线。在垂直于显示面板的平面上，驱动电路层可以包括在基底上依次叠设的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层、透明导电层、第一平坦层、第四导电层和第二平坦层。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性基底可以为但不限于玻璃、石英中的一种或多种，柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施方式中，第一导电层、第二导电层、第三导电层、第四导电层和第五导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
在示例性实施例中，透明导电层可以采用如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层可以称为缓冲(Buffer)层，第二绝缘层可以称为栅绝缘(GI)层，第三绝缘层可以称为层间绝缘(ILD)层，第四绝缘层可以称为钝化(PVX)层。第一平坦层和第二平坦层可以采用有机材料，如树脂等。半导体层可以采用非晶态氧化铟 镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。
在示例性实施方式中，制备完成驱动电路层后，在驱动电路层上制备发光结构层，发光结构层的制备过程可以包括如下操作。
(11)形成阳极导电层图案。在示例性实施方式中，形成阳极导电层图案可以包括：在形成前述图案的基底上，沉积阳极导电薄膜，采用图案化工艺对阳极导电薄膜进行图案化，形成设置在第二平坦层上的阳极导电层图案，如图15P和15Q所示，图15P为图12提供的透光显示区阳极导电层图案的示意图，图15Q为图12提供的透光显示区形成阳极导电层图案后的示意图。
在示例性实施方式中，阳极导电层采用单层结构，如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。
在示例性实施方式中，阳极导电层图案可以包括第一发光元件11a和11b的阳极110、第二发光元件的阳极120、第三发光元件13a至13d的阳极130。
在示例性实施方式中，第一发光元件11a的阳极通过第三十九过孔与第十四连接电极电连接，第一发光元件11b的阳极通过第四十过孔与第十五连接电极电连接，第二发光元件12b的阳极通过第四十一过孔与第十六连接电极电连接，第二发光元件12a的阳极通过第四十二过孔与第十七连接电极电连接，第三发光元件13a的阳极通过第四十三过孔与第十八连接电极电连接，第三发光元件13b的阳极通过第四十四过孔与第十九连接电极电连接，第三发光元件13c的阳极通过第四十五过孔与第二十连接电极电连接，第三发光元件13d的阳极通过第四十六过孔与第二十一连接电极电连接。
在示例性实施方式中，第一发光元件11a的阳极通过第十四连接电极、第一阳极连接线、第十五连接电极与第一发光元件11b的阳极电连接。第二发光元件12a的阳极通过第十六连接电极、第十一连接电极、第十三连接电极和第十七连接电极与第二发光元件12b的阳极电连接。第三发光元件13a的阳极通过第十八连接电极、第三阳极连接线和第十九连接电极与第三发光元件13b的阳极电连接。第三发光元件13c的阳极通过第二十连接电极、第四阳极连接线和第二十一连接电极与第三发光元件13d的阳极电连接。
在示例性实施方式中，第一发光元件11a和11b的阳极110、第二发光元件的阳极120、第三发光元件13a至13d的阳极130中的至少一个可以包括相互连接的主体部和连接部，主体部的形状可以为矩形状，矩形状的角部可以设置圆弧状的倒角，连接部的形状可以为沿着远离主体部方向延伸的条形状。
在示例性实施方式中，后续制备流程可以包括：先形成像素定义层图案，然后采用蒸镀或喷墨打印工艺形成有机发光层，然后在有机发光层上形成阴极，然后形成封装结构层，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
在示例性实施方式中，图13提供的透光显示区的制备过程可以包括如下操作。
(1)形成半导体层图案。在示例性实施方式中，形成半导体层图案可以包括：在基底上依次沉积半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成半导体层图案，如图16A所示，图16A为图13提供的透光显示区形成半导体图案后的示意图。
在示例性实施方式中，图16A提供的半导体层图案与图15A提供的半导体层图案相同，在此不再赘述。
(2)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第一绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第一绝缘层，以及位于第一绝缘层上的第一导电层图案，如图16B和图16C所示，其中，图16B为图13提供的透光显示区第一导电层图案的示意图，图16C为图13提供的透光显示区形成第一导电层图案后的示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，图16B和图16C提供的第一导电层图案与图15B和图15C提供的第一导电层的图案相同，在此不再赘述。
(3)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，沉积第二绝缘层薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，在第二绝缘层上形成第二导电层图案。图16D和图16E所示，图16D为图13提供的透光显示区第二导电层图案的示意图，图16E为图13提供的透光显示区形成第二导电层图案后的示意图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，图16D和图16E提供的第二导电层的图案与图15D和图15E提供的第二导电层的图案相同，在此不再赘述。
(4)形成第三绝缘层图案。在示例性实施方式中，形成第三绝缘层图案可以包括：在形成前述图案的基底上，沉积第三绝缘薄膜，采用图案化工艺对第三绝缘薄膜进行图案化，形成覆盖第二导电层的第三绝缘层，第三绝缘层上设置有多个过孔，如图16F所示，其中，图16F为图13提供的透光显示区形成第三绝缘层图案后的示意图。
在示例性实施方式中，如图16F提供的第三绝缘层图案与图15F提供的第三绝缘层的图案相同，在此不再赘述。
(5)形成第三导电层图案。在示例性实施方式中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第三绝缘层上的第三导电层，图16G至图16H所示，图16G为图13提供的透光显示区第三导电层图案的示意图，图16H为图13提供的透光显示区形成第三导电层图案后的示意图。在示例性实施方式中，第三导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，如图16G和图16H所示，第三导电层图案可以包括：第一晶体管的第一极T13和第二极T14、第二晶体管的第一极T23、第四晶体管的第一极T43、第五晶体管的第一极T53、第六晶体管的第二极T64、第七晶体管的第一极T73和第二极T74、第二连接电极VL2至第十连接电极VL10、屏蔽电极SL和电源连接线VCL。
在示例性实施方式中，如图16G和图16H提供的第一晶体管的第一极T13和第二极T14、第二晶体管的第一极T23、第四晶体管的第一极T43、第 五晶体管的第一极T53、第六晶体管的第二极T64、第七晶体管的第一极T73和第二极T74、第二连接电极VL2至第八连接电极VL8以及屏蔽电极与图15G和15H中的第一晶体管的第一极T13和第二极T14、第二晶体管的第一极T23、第四晶体管的第一极T43、第五晶体管的第一极T53、第六晶体管的第二极T64、第七晶体管的第一极T73和第二极T74、第二连接电极VL2至第八连接电极VL8以及屏蔽电极SL的图案相同，在此不再赘述。
在示例性实施方式中，如图16G和图16H所示，第九连接电极VL9和第十连接电极VL10的至少部分沿第二方向X延伸。电源连接线VCL沿第二方向X延伸。
(6)形成第四绝缘层。在示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第三导电层的第四绝缘层，第四绝缘层上设置有多个过孔，如图16I所示。图16I为图13提供的透光显示区形成第四绝缘层图案后的示意图。
在示例性实施方式中，如图16I所示，第四绝缘层图案的多个过孔可以均包括：第十七过孔V17至第三十一过孔V31。图16I中的第十七过孔V17至第二十八过孔V28与图15I中的第十七过孔V17至第二十八过孔V28相同，不同之处在于，第二十九过孔V29暴露出第九连接电极，第三十过孔V30暴露出第十连接电极，第三十一过孔V31暴露出电源连接线VCL。
在示例性实施方式中，第二十九过孔V29的数量可以为两个，两个第二十九过孔可以沿第二方向X排布，且分别位于第九连接电极的两端。
在示例性实施方式中，第三十过孔V30的数量可以为两个，两个第三十过孔V30可以沿第二方向X排布，且分别位于第十连接电极的两端。
在示例性实施方式中，第三十一过孔V31的数量可以为两个，两个第三十一过孔V31可以沿第二方向X排布，且分别位于电极连接线的两端。
(7)形成透明导电层图案。在示例性实施方式中，形成透明导电层图案可以包括：在形成前述图案的基底上，沉积透明导电薄膜，采用图案化工艺对透明导电薄膜进行图案化，形成设置在第四绝缘层上的透明导电层，如图16J和图16K所示，图16J为图13提供的透光显示区透明导电层图案的示意 图，图16K为图13提供的透光显示区形成透明导电层图案后的示意图。
在示例性实施方式中，如图16J和图16K所示，透明导电层图案可以均包括：数据信号线Data、第一电源线VDD、第一阳极连接线AL1、第二阳极连接线AL2、第三阳极连接线AL3、第四阳极连接线AL4、初始信号线的两个子信号线INIT_1和INIT_2、复位信号线的两个子信号线RST_1和RST_2、扫描信号线的两个子信号线Gate_1和Gate_2、发光信号线的两个子信号线EM_1和EM_2，第十一连接电极VL11和第十二连接电极VL12。
在示例性实施方式中，如图16J和图16K所示，数据信号线Data和第一电源线VDD可以位于数据信号线Data和第一电源线VDD电连接的第一类型像素电路电连接的多个第一信号线的两个子信号线之间，且在基底上的正投影与第一类型像素电路在基底上的正投影存在交叠。
在示例性实施方式中，如图16J和图16K所示，数据信号线Data为折线型，数据信号线Data的至少部分沿第一方向Y延伸，且位于同一列的相邻第一类型像素电路电连接的数据信号线Data可以为同一信号线。数据信号线通过第十八过孔与电连接的第一类型像素电路的第四晶体管的第一极电连接。
在示例性实施方式中，如图16J和图16K所示，第一电源线VDD为折线型，第一电源线VDD的至少部分沿第一方向Y延伸，且位于同一列的相邻第一类型像素电路电连接的第一电源线VDD可以间隔设置。第一电源线通过第十九过孔与电连接的第一类型像素电路的第五晶体管的第一极电连接，且通过第二十八过孔与屏蔽电极电连接。
在示例性实施方式中，如图16J和图16K所示，第一电源线VDD包括：沿第一方向Y延伸的电源主体部VDDM和至少部分沿第二方向X延伸的电源连接部VDDS。
在示例性实施方式中，如图16J和图16K所示，电源连接线VCL的至少部分沿第二方向X延伸，且与位于同一行的相邻第一类型像素电路电连接的第一电源线VDD电连接。其中，位于同一行的相邻第一类型像素电路中的其中一个第一类型像素电路电连接的第一电源线的电源连接部通过第三十一过孔与电源连接线VCL电连接，位于同一行的相邻第一类型像素电路中的另一个第一类型像素电路电连接的第一电源线的电源主体通过第三十一过孔 与电源连接线VCL。电源连接线VCL的设置可以与第一电源线配合形成网状结构，实现显示基板的显示均一性。
在示例性实施方式中，如图16J和图16K所示，第一阳极连接线AL1至第四阳极连接线AL4可以为折线状。
在示例性实施方式中，如图16J和图16K所示，第一阳极连接线AL1位于电连接的第一类型像素电路电连接的第一电源线VDD和相邻列第一类型像素电路的数据信号线Data之间，且第一阳极连接线AL1的至少部分沿第二方向X延伸，第一阳极连接线AL1通过第二十过孔与电连接的第一类型像素电路的第六晶体管的第二极电连接，且通过第二十九过孔与第九连接电极电连接。
在示例性实施方式中，如图16J和图16K所示，第二阳极连接线AL2位于电连接的第一类型像素电路电连接的第一电源线VDD和相邻列第一类型像素电路的数据信号线Data之间，且第二阳极连接线AL2的至少部分沿第二方向X延伸，第二阳极连接线AL2通过第二十过孔与电连接的第一类型像素电路的第六晶体管的第二极电连接，且通过第三十过孔与第十连接电极电连接。
在示例性实施方式中，如图16J和图16K所示，第三阳极连接线AL3位于电连接的第一类型像素电路电连接的第一电源线VDD和位于同一行的相邻第一类型像素电路电连接的数据信号线Data之间。第三阳极连接线AL3的至少部分沿第一方向Y延伸，第三阳极连接线AL3通过第二十过孔与电连接的第一类型像素电路的第六晶体管的第二极电连接。
在示例性实施方式中，如图16J和图16K所示，第四阳极连接线AL4位于电连接的第一类型像素电路电连接的第一电源线VDD和位于同一行的相邻第一类型像素电路电连接的数据信号线Data之间。第四阳极连接线AL4的至少部分可以沿第一方向Y延伸，第四阳极连接线AL4通过第二十过孔与电连接的第一类型像素电路的第六晶体管的第二极电连接。
在示例性实施方式中，如图16J和图16K所示，初始信号线的两个子信号线INIT_1和INIT_2可以为折线状，初始信号线的两个子信号线INIT_1和INIT_2的至少部分可以沿第一方向Y延伸，初始信号线的子信号线INIT_1 通过第二十七过孔与第八连接电极电连接，初始信号线的子信号线INIT_2通过第十七过孔与第一晶体管的第一极电连接。初始信号线的子信号线INIT_1通过第八连接电极与第一连接电极电连接。初始信号线的子信号线INIT_2通过第一晶体管的第一极与第一连接电极电连接。
在示例性实施方式中，如图16J和图16K所示，复位信号线的两个子信号线RST_1和RST_2可以为折线状，复位信号线的两个子信号线RST_1和RST_2的至少部分可以沿第二方向Y延伸，复位信号线的子信号线RST_1通过第二十一过孔与第二连接电极电连接，复位信号线的子信号线RST_2通过第二十二过孔与第三连接电极电连接。复位信号线的子信号线RST_1通过第二连接电极与第一晶体管的控制极电连接，复位信号线的子信号线RST_2通过第三连接电极与第一晶体管的控制极电连接。
在示例性实施方式中，如图16J和图16K所示，扫描信号线的两个子信号线Gate_1和Gate_2可以为折线状，扫描信号线的两个子信号线Gate_1和Gate_2的至少部分可以沿第二方向Y延伸，扫描信号线的子信号线Gate_1通过第二十三过孔与第四连接电极电连接，扫描信号线的子信号线Gate_2通过第二十四过孔与第五连接电极电连接。扫描信号线的子信号线Gate_1通过第四连接电极与第四晶体管的控制极电连接，扫描信号线的子信号线Gate_2通过第五连接电极与第四晶体管的控制极电连接。
在示例性实施方式中，如图16J和图16K所示，发光信号线的两个子信号线EM_1和EM_2可以为折线状，发光信号线的两个子信号线EM_1和EM_2的至少部分可以沿第二方向Y延伸，发光信号线的子信号线EM_1通过第二十五过孔与第六连接电极电连接，发光信号线的子信号线EM_1通过第二十六过孔与第七连接电极电连接。发光信号线的子信号线EM_1通过第六连接电极与第五晶体管的控制极电连接，发光信号线的子信号线EM_2通过第七连接电极与第五晶体管的控制极电连接。
(8)形成第一平坦层图案。在示例性实施方式中，形成第一平坦层图案可以包括：在形成前述图案的基底上，沉积第一平坦薄膜，形成设置在透明导电层上的第一平坦层图案，第一平坦层图案包括多个过孔，如图16L所示，图16L为图13提供的透光显示区形成第一平坦层后的示意图。
在示例性实施方式中，如图16L所示，第一平坦层图案可以包括：第三十二过孔V32和第三十八过孔V38。其中，第三十二过孔暴露出第一电源线，第三十三过孔V33暴露出第一阳极连接线，第三十四过孔V34暴露出第二阳极连接线，第三十五过孔V35暴露出第三阳极连接线，第三十六过孔V36暴露出第四阳极连接线，第三十七过孔V37暴露出第十一连接电极，第三十八过孔V38暴露出第十二连接电极。
在示例性实施方式中，如图16L所示，第三十三过孔V33的数量可以为两个，且分别位于第一阳极连接线的两端。第三十四过孔V34的数量可以为两个，且分别位于第二阳极连接线的两端。第三十五过孔V35的数量可以为两个，且分别位于第三阳极连接线的两端。第三十六过孔V36的数量可以为两个，且分别位于第四阳极连接线的两端。
(9)形成第四导电层图案。在示例性实施方式中，形成第四导电层图案可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第一平坦层上的第四导电层，如图16M和图16N所示，图16M为图13提供的透光显示区第四导电层图案的示意图，图16N为图13提供的透光显示区形成第四导电层图案后的示意图。在示例性实施方式中，第四导电层可以称为第二源漏金属(SD2)层。
在示例性实施方式中，如图16M和图16N所示，第四导电层图案可以包括：第十三连接电极VL13至第二十连接电极VL20和信号连接线VDL。
在示例性实施方式中，如图16M和图16N所示，第十三连接电极VL13至第二十连接电极VL20为块状结构。信号连接线VDL可以为折线状，信号连接线VDL的至少部分可以沿第一方向Y延伸。
在示例性实施方式中，如图16M和图16N所示，第十三连接电极VL13通过第三十三过孔与第一阳极连接线电连接，第十四连接电极VL14通过第三十四过孔与第二阳极连接线电连接，第十五连接电极VL15和第十六连接电极VL16通过第三十五过孔与第三阳极连接线电连接，第十七连接电极VL17和第十八连接电极VL18通过第三十六过孔与第四阳极连接线电连接，第十九连接电极VL19通过第三十七过孔与第十一连接电极电连接，第二十连接电极VL20通过第三十八过孔与第十二连接电极电连接。信号连接线 VDL通过第三十二过孔与第一类型像素电路电连接的第一电源线电连接。
在示例性实施方式中，位于同一列的第一类型像素电路电连接的第一电源线通过信号连接线电连接。
在示例性实施例中，如图16N所示，第十三连接电极VL13通过第一阳极连接线、第九连接电极和第十一连接电极与第十九连接电极VL19电连接，第十四连接电极VL14通过第二阳极连接线、第十连接电极和第十二连接电极与第二十连接电极VL20电连接，第十五连接电极VL15通过第三阳极连接线与第十六连接电极VL16电连接，第十七连接电极VL17通过第四阳极连接线与第十八连接电极VL18电连接。
在示例性实施方式中，多个连接电极起到了承接的作用，可以避免开设较深的过孔导致的连接的不可靠性，提升了显示面板的可靠性。
(10)形成第二平坦层图案。在示例性实施方式中，形成第二平坦层图案可以包括：在形成前述图案的基底上，涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成覆盖第四导电层的第二平坦层，第二平坦层上设置有多个过孔，如图16O所示，其中，图16O为图13提供的透光显示区形成第二平坦层图案后的示意图。
在示例性实施方式中，如图16O所示，第二平坦层图案的多个过孔可以均包括：第三十九过孔V39至第四十六过孔V46。其中，第三十九过孔V39暴露出第十三连接电极，第四十过孔V40暴露出第十四连接电极，第四十一过孔V41暴露出第十五连接电极，第四十二过孔V42暴露出第十六连接电极，第四十三过孔V43暴露出第十七连接电极，第四十四过孔V44暴露出第十八连接电极，第四十五过孔V45暴露出第十九连接电极，第四十六过孔V46暴露出第二十连接电极。
至此，在基底上制备完成驱动电路层。在平行于显示基板的平面上，驱动电路层可以包括多个第一类型像素电路、扫描信号线、复位信号线、发光信号线、数据信号线、初始信号线、第一阳极连接线至第四阳极连接线。在垂直于显示面板的平面上，驱动电路层可以包括在基底上依次叠设的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层、透明导电层、第一平坦层、第四导电层和第二平坦 层。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性基底可以为但不限于玻璃、石英中的一种或多种，柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施方式中，第一导电层、第二导电层、第三导电层、第四导电层和第五导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
在示例性实施例中，透明导电层可以采用如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层可以称为缓冲(Buffer)层，第二绝缘层可以称为栅绝缘(GI)层，第三绝缘层可以称为层间绝缘(ILD)层，第四绝缘层可以称为钝化(PVX)层。第一平坦层和第二平坦层可以采用有机材料，如树脂等。半导体层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。
在示例性实施方式中，制备完成驱动电路层后，在驱动电路层上制备发光结构层，发光结构层的制备过程可以包括如下操作。
(11)形成阳极导电层图案。在示例性实施方式中，形成阳极导电层图案可以包括：在形成前述图案的基底上，沉积阳极导电薄膜，采用图案化工艺对阳极导电薄膜进行图案化，形成设置在第二平坦层上的阳极导电层图案，如图16P和16Q所示，图16P为图13提供的透光显示区阳极导电层图案的示意图，图16Q为图13提供的透光显示区形成阳极导电层图案后的示意图。
在示例性实施方式中，阳极导电层采用单层结构，如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。
在示例性实施方式中，图16P提供的阳极导电层图案与图15P提供的阳极导电层图案相同，在此不再赘述。
在示例性实施方式中，第一发光元件11a的阳极通过第三十九过孔与第十三连接电极电连接，第一发光元件11b的阳极通过第四十五过孔与第十九连接电极电连接，第二发光元件12a的阳极通过第四十过孔与第十四连接电极电连接，第二发光元件12b的阳极通过第四十六过孔与第二十连接电极电连接，第三发光元件13a的阳极通过第四十一过孔与第十五连接电极电连接，第三发光元件13b的阳极通过第四十二过孔与第十六连接电极电连接，第三发光元件13c的阳极通过第四十三过孔与第十七连接电极电连接，第三发光元件13d的阳极通过第四十四过孔与第十八连接电极电连接。
在示例性实施方式中，第一发光元件11a的阳极通过第十三连接电极、第一阳极连接线、第九连接电极、第十一连接电极和第十九连接电极与第一发光元件11b的阳极电连接。第二发光元件12a的阳极通过第十四连接电极、第二阳极连接线、第十连接电极、第十二连接电极和第二十连接电极与第二发光元件12b的阳极电连接。第三发光元件13a的阳极通过第十五连接电极、第三阳极连接线和第十六连接电极与第三发光元件13b的阳极电连接。第三发光元件13c的阳极通过第十七连接电极、第四阳极连接线和第十八连接电极与第三发光元件13d的阳极电连接。
在示例性实施方式中，后续制备流程可以包括：先形成像素定义层图案，然后采用蒸镀或喷墨打印工艺形成有机发光层，然后在有机发光层上形成阴极，然后形成封装结构层，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装 层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
在示例性实施方式中，图14提供的透光显示区的制备过程可以包括如下操作。
(1)形成半导体层图案。在示例性实施方式中，形成半导体层图案可以包括：在基底上依次沉积半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成半导体层图案，如图17A所示，图17A为图14提供的透光显示区形成半导体图案后的示意图。
在示例性实施方式中，图17A提供的半导体层图案与图15A提供的半导体层图案相同，在此不再赘述。
(2)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第一绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第一绝缘层，以及位于第一绝缘层上的第一导电层图案，如图17B和图17C所示，其中，图17B为图14提供的透光显示区第一导电层图案的示意图，图17C为图14提供的透光显示区形成第一导电层图案后的示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，图17B和图17C提供的第一导电层图案与图15B和图15C提供的第一导电层的图案相同，在此不再赘述。
(3)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，沉积第二绝缘层薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，在第二绝缘层上形成第二导电层图案。图17D和图17E所示，图17D为图14提供的透光显示区第二导电层图案的示意图，图17E为图14提供的透光显示区形成第二导电层图案后的示意图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，图17D和图17E提供的第二导电层的图案与图15D和图15E提供的第二导电层的图案相同，在此不再赘述。
(4)形成第三绝缘层图案。在示例性实施方式中，形成第三绝缘层图案可以包括：在形成前述图案的基底上，沉积第三绝缘薄膜，采用图案化工艺对第三绝缘薄膜进行图案化，形成覆盖第二导电层的第三绝缘层，第三绝缘层上设置有多个过孔，如图17F所示，其中，图17F为图14提供的透光显示区形成第三绝缘层图案后的示意图。
在示例性实施方式中，如图17F提供的第三绝缘层图案与图15F提供的第三绝缘层的图案相同，在此不再赘述。
(5)形成第三导电层图案。在示例性实施方式中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第三绝缘层上的第三导电层，图17G至图17H所示，图17G为图14提供的透光显示区第三导电层图案的示意图，图17H为图14提供的透光显示区形成第三导电层图案后的示意图。在示例性实施方式中，第三导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，如图17G和图17H所示，第三导电层图案可以包括：第一晶体管的第一极T13和第二极T14、第二晶体管的第一极T23、第四晶体管的第一极T43、第五晶体管的第一极T53、第六晶体管的第二极T64、第七晶体管的第一极T73和第二极T74、第二连接电极VL2至第十二连接电极VL12以及屏蔽电极SL。其中，
在示例性实施方式中，如图17G和图17H提供的第一晶体管的第一极T13和第二极T14、第二晶体管的第一极T23、第四晶体管的第一极T43、第五晶体管的第一极T53、第六晶体管的第二极T64、第七晶体管的第一极T73和第二极T74、第二连接电极VL2至第八连接电极VL8以及屏蔽电极与图15G和15H中的第一晶体管的第一极T13和第二极T14、第二晶体管的第一极T23、第四晶体管的第一极T43、第五晶体管的第一极T53、第六晶体管的第二极T64、第七晶体管的第一极T73和第二极T74、第二连接电极VL2至第八连接电极VL8以及屏蔽电极SL的图案相同，在此不再赘述。
在示例性实施方式中，如图17G和图17H所示，第九连接电极VL9和第十二连接电极VL12沿第二方向X延伸，第十连接电极VL10和第十一连接电极VL11的至少部分沿第二方向X延伸。
(6)形成第四绝缘层。在示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第三导电层的第四绝缘层，第四绝缘层上设置有多个过孔，如图17I所示。图17I为图14提供的透光显示区形成第四绝缘层图案后的示意图。
在示例性实施方式中，如图17I所示，第四绝缘层图案的多个过孔可以均包括：第十七过孔V17至第三十二过孔V32。图17I中的第十七过孔V17至第二十八过孔V28与图15I中的第十七过孔V17至第二十八过孔V28相同，不同之处在于，第二十九过孔V29暴露出第九连接电极，第三十过孔V30暴露出第十连接电极，第三十一过孔V31暴露出第十一连接电极，第三十二过孔V32暴露出第十二连接电极。
在示例性实施方式中，第二十九过孔V29的数量可以为两个，两个第二十九过孔可以沿第二方向X排布，且分别位于第九连接电极的两端。
在示例性实施方式中，第三十过孔V30的数量可以为两个，两个第三十过孔V30可以沿第二方向X排布，且分别位于第十连接电极的两端。
在示例性实施方式中，第三十一过孔V31的数量可以为两个，两个第三十一过孔V31可以沿第二方向X排布，且分别位于第十一连接电极的两端。
在示例性实施方式中，第三十二过孔V32的数量可以为两个，两个第三十二过孔V32可以沿第二方向X排布，且分别位于第十二连接电极的两端。
(7)形成透明导电层图案。在示例性实施方式中，形成透明导电层图案可以包括：在形成前述图案的基底上，沉积透明导电薄膜，采用图案化工艺对透明导电薄膜进行图案化，形成设置在第四绝缘层上的透明导电层，如图17J和图17K所示，图17J为图14提供的透光显示区透明导电层图案的示意图，图17K为图14提供的透光显示区形成透明导电层图案后的示意图。
在示例性实施方式中，如图17J和图17K所示，透明导电层图案可以均包括：数据信号线Data、第一电源线VDD、第一阳极连接线AL1、第二阳极连接线AL2、第三阳极连接线AL3、初始信号线的两个子信号线INIT_1和INIT_2、复位信号线的两个子信号线RST_1和RST_2、扫描信号线的两个子信号线Gate_1和Gate_2、发光信号线的两个子信号线EM_1和EM_2， 第十三连接电极VL13至第十七连接电极VL17。
在示例性实施方式中，如图17J和图17K所示，数据信号线Data和第一电源线VDD可以位于数据信号线Data和第一电源线VDD电连接的第一类型像素电路电连接的多个第一信号线的两个子信号线之间，且在基底上的正投影与第一类型像素电路在基底上的正投影存在交叠。
在示例性实施方式中，如图17J和图17K所示，数据信号线Data可以为线性状，数据信号线Data的至少部分可以沿第一方向Y延伸，且位于同一列的相邻第一类型像素电路电连接的数据信号线Data可以为同一信号线，数据信号线通过第十八过孔与电连接的第一类型像素电路的第四晶体管的第一极电连接。
在示例性实施方式中，如图17J和图17K所示，第一电源线VDD可以为线性状，第一电源线VDD的至少部分可以沿第一方向Y延伸，且位于同一列的相邻第一类型像素电路电连接的第一电源线VDD可以间隔设置，第一电源线通过第十九过孔与电连接的第一类型像素电路的第五晶体管的第一极电连接，且通过第二十八过孔与屏蔽电极电连接。
在示例性实施方式中，如图17J和图17K所示，第一阳极连接线AL1至第四阳极连接线AL4为折线状。
在示例性实施方式中，如图17J和图17K所示，第一阳极连接线AL1位于电连接的第一类型像素电路电连接的第一电源线VDD和相邻列第一类型像素电路的数据信号线Data之间，且第一阳极连接线AL1的至少部分可以沿第二方向X延伸，第一阳极连接线AL1通过第二十过孔与电连接的第一类型像素电路的第六晶体管的第二极电连接，通过第三十过孔与第十连接电极电连接。
在示例性实施方式中，如图17J和图17K所示，第二阳极连接线AL2位于电连接的第一类型像素电路电连接的第一电源线VDD和相邻列第一类型像素电路的数据信号线Data之间，且第二阳极连接线AL2的至少部分可以沿第二方向X延伸，第二阳极连接线AL2通过第二十过孔与电连接的第一类型像素电路的第六晶体管的第二极电连接，且通过第二十九过孔与第九连接电极电连接。
在示例性实施方式中，如图17J和图17K所示，第三阳极连接线AL3位于电连接的第一类型像素电路电连接的第一电源线VDD和位于同一行的相邻第一类型像素电路电连接的数据信号线Data之间，且第三阳极连接线AL3的至少部分可以沿第一方向Y延伸，第三阳极连接线AL3通过第三十二过孔与第十二连接电极电连接。
在示例性实施方式中，如图17J和图17K所示，初始信号线的两个子信号线INIT_1和INIT_2可以为折线状，初始信号线的两个子信号线INIT_1和INIT_2的至少部分可以沿第一方向Y延伸，初始信号线的子信号线INIT_1通过第二十七过孔与第八连接电极电连接，初始信号线的子信号线INIT_2通过第十七过孔与第一晶体管的第一极电连接。初始信号线的子信号线INIT_1通过第八连接电极与第一连接电极电连接。初始信号线的子信号线INIT_2通过第一晶体管的第一极与第一连接电极电连接。
在示例性实施方式中，如图17J和图17K所示，复位信号线的两个子信号线RST_1和RST_2可以为折线状，复位信号线的两个子信号线RST_1和RST_2的至少部分可以沿第二方向Y延伸，复位信号线的子信号线RST_1通过第二十一过孔与第二连接电极电连接，复位信号线的子信号线RST_2通过第二十二过孔与第三连接电极电连接。复位信号线的子信号线RST_1通过第二连接电极与第一晶体管的控制极电连接，复位信号线的子信号线RST_2通过第三连接电极与第一晶体管的控制极电连接。
在示例性实施方式中，如图17J和图17K所示，扫描信号线的两个子信号线Gate_1和Gate_2可以为折线状，扫描信号线的两个子信号线Gate_1和Gate_2的至少部分可以沿第二方向Y延伸，扫描信号线的子信号线Gate_1通过第二十三过孔与第四连接电极电连接，扫描信号线的子信号线Gate_2通过第二十四过孔与第五连接电极电连接。扫描信号线的子信号线Gate_1通过第四连接电极与第四晶体管的控制极电连接，扫描信号线的子信号线Gate_2通过第五连接电极与第四晶体管的控制极电连接。
在示例性实施方式中，如图17J和图17K所示，发光信号线的两个子信号线EM_1和EM_2可以为折线状，初发光信号线的两个子信号线EM_1和EM_2的至少部分可以沿第二方向Y延伸，发光信号线的子信号线EM_1通 过第二十五过孔与第六连接电极电连接，发光信号线的子信号线EM_1通过第二十六过孔与第七连接电极电连接。发光信号线的子信号线EM_1通过第六连接电极与第五晶体管的控制极电连接，发光信号线的子信号线EM_2通过第七连接电极与第五晶体管的控制极电连接。
在示例性实施方式中，如图17J和图17K所示，第十三连接电极VL13通过通过第三十过孔与第十连接电极电连接，且通过第三十一过孔与第十一连接电极电连接。
在示例性实施方式中，如图17J和图17K所示，第十四连接电极VL14通过第三十一过孔与第十一连接电极电连接。第十三连接电极通过第一阳极连接线、第十连接电极、第十三连接电极和第十一连接电极与第十四连接电极电连接。
在示例性实施方式中，如图17J和图17K所示，第十五连接电极VL15通过第二十过孔与电连接的第一类型像素电路的第六晶体管的第二极电连接。
在示例性实施方式中，如图17J和图17K所示，第十六连接电极VL16通过第二十九过孔与第九连接电极电连接。第十六连接电极通过第九连接电极与第二阳极连接线AL2电连接
在示例性实施方式中，如图17J和图17K所示，第十七连接电极VL17通过第三十二过孔与第十二连接电极电连接。第十七连接电极VL17通过第十二连接电极与第三阳极连接线AL3电连接。
(8)形成第一平坦层图案。在示例性实施方式中，形成第一平坦层图案可以包括：在形成前述图案的基底上，沉积第一平坦薄膜，形成设置在透明导电层上的第一平坦层图案，第一平坦层图案包括多个过孔，如图17L所示，图17L为图14提供的透光显示区形成第一平坦层后的示意图。
在示例性实施方式中，如图17L所示，第一平坦层图案可以包括：第三十三过孔V33和第四十过孔V40。其中，第三十三过孔V33暴露出第一电源线，第三十四过孔V34暴露出第一阳极连接线，第三十五过孔V35暴露出第十四连接电极，第三十六过孔V36暴露出第十六连接电极，第三十七过孔V37暴露出第二阳极连接线，第三十八过孔V38暴露出第十五连接电极，第三十九过孔V39暴露出第三阳极连接线，第四十过孔V40暴露出第十七连接 电极。
(9)形成第四导电层图案。在示例性实施方式中，形成第四导电层图案可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第一平坦层上的第四导电层，如图17M和图17N所示，图17M为图14提供的透光显示区第四导电层图案的示意图，图17N为图14提供的透光显示区形成第四导电层图案后的示意图。在示例性实施方式中，第四导电层可以称为第二源漏金属(SD2)层。
在示例性实施方式中，如图17M和图17N所示，第四导电层图案可以包括：第十八连接电极VL18至第二十三连接电极VL23和信号连接线VDL。
在示例性实施方式中，如图17M和图17N所示，第十八连接电极VL18至第二十一连接电极VL21以及第二十三连接电极VL23为块状结构。第二十二连接电极VL22为水平翻转后的“7”字型，信号连接线VDL可以为折线状，信号连接线VDL的至少部分可以沿第一方向Y延伸。
在示例性实施方式中，如图17M和图17N所示，信号连接线VDL通过第三十三过孔与第一电源线电连接。
在示例性实施方式中，如图17M和图17N所示，第十八连接电极VL18通过第三十五过孔与十四连接电极电连接，第十九连接电极VL19通过第三十四过孔与第一阳极连接线电连接，第二十连接电极VL20通过第三十六过孔与第十六连接电极电连接，第二十一连接电极VL21通过第三十七过孔与第二阳极连接线电连接，第二十二连接电极VL22通过第三十八过孔与第十五连接电极电连接，且通过第三十九过孔与第三阳极连接线电连接，第二十三连接电极VL23通过第四十过孔与第十七连接电极电连接。
在示例性实施方式中，位于同一列的第一类型像素电路电连接的第一电源线通过信号连接线VDL电连接。
在示例性实施例中，如图17N所示，第十八连接电极VL18通过第十四连接电极、第十一连接电极、第十三连接电极、第十连接电极和第一阳极连接线与第十九连接电极VL19电连接，第二十连接电极VL20通过第十六连接电极、第九连接电极和第一阳极连接线与第二十一连接电极VL21电连接，第二十二连接电极VL22通过第三阳极连接线、第十二连接电极和第十七连 接电极与第二十三连接电极VL23电连接。
在示例性实施方式中，多个连接电极起到了承接的作用，可以避免开设较深的过孔导致的连接的不可靠性，提升了显示面板的可靠性。
(10)形成第二平坦层图案。在示例性实施方式中，形成第二平坦层图案可以包括：在形成前述图案的基底上，涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成覆盖第四导电层的第二平坦层，第二平坦层上设置有多个过孔，如图17O所示，其中，图17O为图14提供的透光显示区形成第二平坦层图案后的示意图。
在示例性实施方式中，如图17O所示，第二平坦层图案的多个过孔可以均包括：第四十一过孔V41至第四十六过孔V46。其中，第四十一过孔V41暴露出第十八连接电极，第四十二过孔V42暴露出第十九连接电极，第四十三过孔V43暴露出第二十连接电极，第四十四过孔V44暴露出第二十一连接电极，第四十五过孔V45暴露出第二十二连接电极，第四十六过孔V46暴露出第二十三连接电极。
至此，在基底上制备完成驱动电路层。在平行于显示基板的平面上，驱动电路层可以包括多个第一类型像素电路、扫描信号线、复位信号线、发光信号线、数据信号线、初始信号线、第一阳极连接线至第四阳极连接线。在垂直于显示面板的平面上，驱动电路层可以包括在基底上依次叠设的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层、透明导电层、第一平坦层、第四导电层和第二平坦层。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性基底可以为但不限于玻璃、石英中的一种或多种，柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和 第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施方式中，第一导电层、第二导电层、第三导电层、第四导电层和第五导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
在示例性实施例中，透明导电层可以采用如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层可以称为缓冲(Buffer)层，第二绝缘层可以称为栅绝缘(GI)层，第三绝缘层可以称为层间绝缘(ILD)层，第四绝缘层可以称为钝化(PVX)层。第一平坦层和第二平坦层可以采用有机材料，如树脂等。半导体层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。
在示例性实施方式中，制备完成驱动电路层后，在驱动电路层上制备发光结构层，发光结构层的制备过程可以包括如下操作。
(11)形成阳极导电层图案。在示例性实施方式中，形成阳极导电层图案可以包括：在形成前述图案的基底上，沉积阳极导电薄膜，采用图案化工艺对阳极导电薄膜进行图案化，形成设置在第二平坦层上的阳极导电层图案，如图17P和16Q所示，图17P为图14提供的透光显示区阳极导电层图案的示意图，图17Q为图14提供的透光显示区形成阳极导电层图案后的示意图。
在示例性实施方式中，阳极导电层采用单层结构，如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。
在示例性实施方式中，第一发光元件11b的阳极通过第四十一过孔与第十八连接电极电连接，第一发光元件11a的阳极通过第四十二过孔与第十九 连接电极电连接，第二发光元件12b的阳极通过第四十三过孔与第二十连接电极电连接，第二发光元件12a的阳极通过第四十四过孔与第二十一连接电极电连接，第三发光元件13a的阳极通过第四十五过孔与第二十二连接电极电连接，第三发光元件13b的阳极通过第四十六过孔与第二十三连接电极电连接。
在示例性实施方式中，第一发光元件11a的阳极通过第十八连接电极、第十四连接电极、第十一连接电极、第十三连接电极、第十连接电极、第一阳极连接线和第十九连接电极与第一发光元件11b的阳极电连接。第二发光元件12a的阳极通过第二十连接电极、第十六连接电极、第九连接电极、第一阳极连接线和第二十一连接电极与第二发光元件12b的阳极电连接。第三发光元件13a的阳极通过第二十二连接电极VL22、第三阳极连接线、第十二连接电极、第十七连接电极和第二十三连接电极VL23与第三发光元件13b的阳极电连接。
在示例性实施方式中，后续制备流程可以包括：先形成像素定义层图案，然后采用蒸镀或喷墨打印工艺形成有机发光层，然后在有机发光层上形成阴极，然后形成封装结构层，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
本公开前述所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开在此不做限定。
在示例性实施方式中，本公开显示面板可以应用于具有像素电路的显示装置中，如OLED、量子点显示(QLED)、发光二极管显示(Micro LED或Mini LED)或量子点发光二极管显示(QDLED)等，本公开在此不做限定。
图18为本公开实施例提供的显示装置的结构示意图，图19为图18沿A-A向的截面图。如图18和图19所示，本公开实施例还提供一种显示装置，显示装置包括前述任一实施例提供的显示基板1和感光传感器2，感光传感器位于显示基板1的透光显示区A1内，且位于远离显示基板1的出光侧的 一侧。
在示例性实施方式中，显示基板可以为柔性OLED显示基板、QLED显示基板、Micro-LED显示基板、或者Mini-LED显示基板。显示装置可以为：OLED显示器、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开实施例并不以此为限。
在示例性实施方式中，当透光显示区A1为矩形时，感光传感器2在基底上的正投影面积小于等于透光显示区A1的内切圆的面积。
在示例性实施方式中，感光传感器2可以包括相机模组(例如，前置摄像模组)、3D结构光模组(例如，3D结构光传感器)、飞行时间法3D成像模组(例如，飞行时间法传感器)、红外感测模组(例如，红外感测传感器)等至少之一。
在示例性实施方式中，前置摄像模组通常在用户自拍或视频通话时启用，显示装置的显示区显示自拍所得到的图像供用户观看。前置摄像模组例如包括镜头、图像传感器、图像处理芯片等。景物通过镜头生成的光学图像投射到图像传感器表面(图像传感器包括CCD和CMOS两种)变换为电信号，通过图像处理芯片模数转换后变为数字图像信号，再送到处理器中加工处理，在显示屏上输出该景物的图像。
在示例性实施方式中，3D结构光传感器和飞行时间法(Time of Flight，ToF)传感器可以用于人脸识别以对显示装置进行解锁。
本公开实施例提供的显示装置，可以在透光显示区区显示图像，以保持整个显示装置的显示完整性。
本公开中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人 员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (31)

  1. 一种显示基板，包括：显示区域和至少部分围绕所述显示区域的周边区域，所述显示区域包括透光显示区和位于所述透光显示区至少一侧的常规显示区，所述透光显示区的光透过率大于所述常规显示区的光透过率；
    所述显示基板包括：基底和位于所述基底一侧的多个发光元件和多个像素电路，所述多个发光元件包括位于所述透光显示区的多个第一类型发光元件，所述多个像素电路包括位于所述透光显示区的多个第一类型像素电路，所述多个第一类型像素电路中的至少一个第一类型像素电路与出射相同颜色光的至少两个第一类型发光元件电连接，所述第一类型像素电路被配置为驱动所述至少两个第一类型发光元件发光；
    所述至少一个第一类型像素电路在所述基底的正投影与所述至少一个第一类型发光元件在所述基底的正投影存在交叠。
  2. 根据权利要求1所述的显示基板，其中，所述至少一个第一类型像素电路在所述基底的正投影和与所述至少一个第一类型像素电路电连接的至少两个第一类型发光元件中的至少部分第一类型发光元件在所述基底的正投影存在交叠。
  3. 根据权利要求1或2所述的显示基板，还包括：多条第一信号线，所述至少一个第一类型像素电路与至少一条第一信号线电连接；
    所述多条第一信号线包括以下至少之一：扫描信号线、复位信号线、初始信号线、发光信号线。
  4. 根据权利要求3所述的显示基板，其中，所述第一信号线包括：多条子信号线；所述第一信号线的相邻子信号线通过电连接的所述第一类型像素电路电连接。
  5. 根据权利要求3或4所述的显示基板，还包括：多条第二信号线，所述至少一个第一类型像素电路与至少一条第二信号线电连接；
    所述多条第二信号线包括以下至少之一：数据信号线和第一电源线，所述多条数据信号线和所述多条第一电源线沿第一方向延伸；所述第一类型像素电路电连接的数据信号线和第一电源线位于所述第一信号线的相邻子信号 线之间，且所述第一类型像素电路电连接的数据信号线和第一电源线在所述基底上的正投影与所述第一类型像素电路在所述基底上的正投影交叠。
  6. 根据权利要求5所述的显示基板，其中，所述扫描信号线、所述复位信号线、所述初始信号线、所述发光信号线、所述数据信号线和所述第一电源线中的至少一种在所述基底的正投影与所述第一类型发光元件在所述基底的正投影部分交叠。
  7. 根据权利要求5或6所述的显示基板，其中，所述多个第一类型发光元件至少包括：出射第一颜色光的多个第一发光元件、出射第二颜色光的多个第二发光元件以及出射第三颜色光的多个第三发光元件；
    所述多个第一发光元件中的至少一个第一发光元件的阳极面积大于所述多个第三发光元件中的至少一个第三发光元件的阳极面积，所述多个第二发光元件中的至少一个第二发光元件的阳极面积大于所述至少一个第三发光元件的阳极面积，所述多个第二发光元件中的至少一个第二发光元件的阳极面积大于所述多个第一发光元件中的至少一个第一发光元件的阳极面积；
    所述第一颜色光为红光，所述第二颜色光为蓝光，所述第三颜色光为绿光。
  8. 根据权利要求7所述的显示基板，其中，所述第一类型像素电路包括：多个晶体管和至少一个电容；在垂直于所述显示基板的方向上，所述透光显示区至少包括：设置在所述基底上的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层、透明导电层、第一平坦层、第四导电层和第二平坦层；
    所述半导体层至少包括：所述第一类型像素电路的多个晶体管的有源层；
    所述第一导电层至少包括：所述第一类型像素电路的多个晶体管的控制极以及电容的第一极板；
    所述第二导电层至少包括：所述第一类型像素电路的电容的第二极板；
    所述第三导电层至少包括：所述第一类型像素电路的多个晶体管的第一极和第二极以及多个连接电极；
    所述透明导电层至少包括：多条第一信号线、多条第二信号线和多条阳 极连接线，所述多条阳极连接线中的至少一条阳极连接线与至少一个第一类型像素电路和出射相同颜色光的至少两个第一类型发光元件的阳极电连接；
    所述第四导电层至少包括：多个信号连接线。
  9. 根据权利要求8所述的显示基板，其中，所述多个第一类型发光元件按照如下方式排布：
    所述多个第三发光元件以一定间隔排布在第i行中，所述第二发光元件和所述第一发光元件交替地排布在第i行的相邻行中，所述第一发光元件和所述第二发光元件交替地排布在第j列中，所述多个第三发光元件以一定间隔排布在第j列的相邻列中，所述第一发光元件和所述第三发光元件沿第三方向交替地排布，所述第二发光元件和所述第三发光元件沿第四方向交替地排布，所述第三方向和所述第四方向分别与所述第一方向和第二方向相交，所述第一方向为列方向，所述第二方向为行方向。
  10. 根据权利要求9所述的显示基板，其中，所述多个第一类型像素电路包括：至少一个第一像素电路、至少一个第二像素电路、至少一个第三像素电路和至少一个第四像素电路；所述第一像素电路与两个所述第一发光元件电连接，所述第二像素电路与两个所述第二发光元件电连接，所述第三像素电路与两个所述第三发光元件电连接，所述第四像素电路与两个所述第三发光元件电连接，所述第三像素电路和所述第四像素电路电连接的第三发光元件不同。
  11. 根据权利要求10所述的显示基板，其中，所述第一像素电路电连接的两个所述第一发光元件位于同一行，所述第二像素电路电连接的两个所述第二发光元件位于同一行，所述第三像素电路电连接的两个所述第三发光元件位于同一行，所述第四像素电路电连接的两个所述第三发光元件位于同一行。
  12. 根据权利要求11所述的显示基板，其中，所述第一像素电路在所述基底的正投影与电连接的一个所述第一发光元件在所述基底的正投影部分交叠；
    所述第二像素电路在所述基底上的正投影与位于电连接的两个所述第二发光元件之间的所述第一发光元件在所述基底上的正投影部分交叠；
    所述第三像素电路在所述基底上的正投影与所述第二发光元件在所述基底上的正投影部分交叠，与所述第三像素电路交叠的所述第二发光元件位于所述第三像素电路电连接的两个所述第三发光元件所在行的相邻行，且位于所述第三像素电路电连接的两个所述第三发光元件所在列的中间列；
    所述第四像素电路在所述基底上的正投影与所述第二发光元件在所述基底上的正投影部分交叠，与所述第四像素电路交叠的所述第二发光元件位于所述第四像素电路电连接的两个所述第三发光元件所在行的相邻行，且位于所述第四像素电路电连接的两个所述第三发光元件所在列的中间列，与所述第三像素电路交叠的所述第二发光元件和与所述第四像素电路交叠的所述第二发光元件为不同发光元件。
  13. 根据权利要求10至12任一项所述的显示基板，其中，所述阳极连接线包括：第一阳极连接线、第二阳极连接线、第三阳极连接线和第四阳极连接线；
    所述第一阳极连接线分别与所述第一像素电路和所述第一发光元件电连接，且所述第一阳极连接线的至少部分沿所述第二方向延伸；所述第二阳极连接线分别与所述第二像素电路和所述第二发光元件电连接，且所述第二阳极连接线的至少部分沿所述第二方向延伸；所述第三阳极连接线分别与所述第三像素电路和所述第三发光元件电连接，且所述第三阳极连接线的至少部分沿所述第二方向延伸，所述第三阳极连接线位于所述第三像素电路电连接的数据信号线和第一电源线之间；所述第四阳极连接线分别与所述第四像素电路和所述第三发光元件电连接，且所述第四阳极连接线的至少部分沿所述第二方向延伸，所述第四阳极连接线位于所述第四像素电路电连接的数据信号线和第一电源线之间。
  14. 根据权利要求13所述的显示基板，其中，位于同一列的至少两个相邻第一类型像素电路电连接的第一电源线间隔设置，且位于同一列的间隔设置的第一电源线通过位于所述第四导电层的至少一个信号连接线电连接；
    位于同一列的至少两个相邻第一类型像素电路电连接的数据信号线间隔设置，且位于同一列的间隔设置的数据信号线通过位于所述第四导电层的至少一个信号连接线电连接。
  15. 根据权利要求10所述的显示基板，其中，所述第一像素电路电连接的两个所述第一发光元件沿第三方向排布，所述第二像素电路电连接的两个所述第二发光元件沿第四方向排布，所述第三像素电路电连接的两个所述第三发光元件位于同一列，所述第四像素电路电连接的两个所述第三发光元件位于同一列。
  16. 根据权利要求15所述的显示基板，其中，所述第一像素电路在所述基底的正投影与电连接的一个所述第一发光元件在所述基底的正投影部分交叠；
    所述第二像素电路在所述基底的正投影与电连接的一个所述第二发光元件在所述基底的正投影部分交叠；
    所述第三像素电路在所述基底的正投影与电连接的一个所述第三发光元件在所述基底的正投影部分交叠；
    所述第四像素电路在所述基底的正投影与电连接的一个所述第三发光元件在所述基底的正投影部分交叠，与所述第三像素电路交叠的第三发光元件和与所述第四像素电路交叠的第三发光元件为不同发光元件。
  17. 根据权利要求15或16所述的显示基板，其中，所述阳极连接线包括：第一阳极连接线、第二阳极连接线、第三阳极连接线和第四阳极连接线；
    所述第一阳极连接线分别与所述第一像素电路和所述第一发光元件电连接，且所述第一阳极连接线的至少部分沿所述第一方向延伸；所述第二阳极连接线分别与所述第二像素电路和所述第二发光元件电连接，且所述第二阳极连接线的至少部分沿所述第一方向延伸；所述第三阳极连接线分别与所述第三像素电路和所述第三发光元件电连接，且所述第三阳极连接线的至少部分沿所述第一方向延伸，所述第三阳极连接线位于所述第三像素电路电连接的第一电源线远离数据信号线的一侧；所述第四阳极连接线分别与所述第四像素电路和所述第三发光元件电连接，且所述第四阳极连接线的至少部分沿所述第一方向延伸，所述第四阳极连接线位于所述第四像素电路电连接的第一电源线远离数据信号线的一侧。
  18. 根据权利要求17所述的显示基板，其中，位于同一列的第一类型像素电路电连接的数据信号线为同一信号线，位于同一列的至少两个相邻第一 类型像素电路电连接的第一电源线间隔设置，且位于同一列的间隔设置的第一电源线通过位于所述第四导电层的至少一个信号连接线电连接。
  19. 根据权利要求18所述的显示基板，其中，所述透明导电层还包括：电源连接线，所述电源连接线的至少部分沿第二方向延伸；
    所述电源连接线分别与位于同一行的相邻两个第一类型像素电路电连接的第一电源线电连接，所述第一电源线和所述电源连接线通过位于所述第三导电层的连接电极电连接。
  20. 根据权利要求19所述的显示基板，其中，对于同一第一类型像素电路，所述第一电源线包括：沿所述第一方向延伸的电源主体部和沿所述第二方向延伸的电源连接部，所述电源连接部位于所述电源主体部远离所述数据信号线的一侧；
    所述电源连接线分别与位于同一行的相邻第一类型像素电路中的其中一个第一类型像素电路的电源连接部和另一个第一类型像素电路的电源主体部电连接。
  21. 根据权利要求8所述的显示基板，其中，所述多个第一类型发光元件按照如下方式排布：
    所述多个第二发光元件排布在第j列中，所述第一发光元件和所述第三发光元件交替地排布在第j列的相邻列中，所述多个第二发光元件排布在第i行中，位于同一行的相邻第二发光元件之间设置所述第一发光元件和所述第三发光元件。
  22. 根据权利要求21所述的显示基板，其中，所述多个第一类型像素电路包括：至少一个第一像素电路、至少一个第二像素电路和至少一个第三像素电路；所述第一像素电路与两个所述第一发光元件电连接，所述第二像素电路与两个所述第二发光元件电连接和所述第三像素电路与两个所述第三发光元件电连接。
  23. 根据权利要求22所述的显示基板，其中，所述第一像素电路电连接的两个第一发光元件位于同一行，所述第二像素电路电连接的两个第二发光元件位于同一行，所述第三像素电路电连接的两个所述第三发光元件位于同 一行。
  24. 根据权利要求23所述的显示基板，其中，所述第一像素电路在所述基底的正投影与电连接的一个所述第一发光元件在所述基底的正投影部分交叠；
    所述第二像素电路在所述基底上的正投影与电连接的一个所述第二发光元件在所述基底上的正投影部分交叠；
    所述第三像素电路在所述基底上的正投影与电连接的一个所述第三发光元件在所述基底上的正投影部分交叠。
  25. 根据权利要求24所述的显示基板，其中，所述第一像素电路交叠的所述第一发光元件、所述第二像素电路交叠的所述第二发光元件和所述第三像素电路交叠的所述第三发光元件中的至少两个相邻。
  26. 根据权利要求23所述的显示基板，其中，所述第一像素电路在所述基底的正投影与电连接的一个所述第一发光元件在所述基底的正投影部分交叠；
    所述第二像素电路在所述基底上的正投影与电连接的一个所述第二发光元件在所述基底上的正投影部分交叠；
    所述第三像素电路在所述基底上的正投影与位于所述第三像素电路电连接的两个所述第三发光元件之间的所述第二发光元件在所述基底上的正投影部分交叠。
  27. 根据权利要求23所述的显示基板，其中，所述第一像素电路在所述基底的正投影与位于所述第一像素电路电连接的两个所述第一发光元件之间的第二发光元件在所述基底的正投影部分交叠；
    所述第二像素电路在所述基底上的正投影与电连接的一个所述第二发光元件在所述基底上的正投影部分交叠；
    所述第三像素电路在所述基底上的正投影与电连接的一个所述第三发光元件在基底上的正投影部分交叠。
  28. 根据权利要求23至27任一项所述的显示基板，其中，所述阳极连接线包括：第一阳极连接线、第二阳极连接线和第三阳极连接线；
    所述第一阳极连接线分别与所述第一像素电路和所述第一发光元件电连接，且所述第一阳极连接线的至少部分沿所述第二方向延伸；所述第二阳极连接线分别与所述第二像素电路和所述第二发光元件电连接，且所述第二阳极连接线的至少部分沿所述第二方向延伸；所述第三阳极连接线分别与所述第三像素电路和所述第三发光元件电连接，且所述第三阳极连接线的至少部分沿所述第二方向延伸。
  29. 根据权利要求28所述的显示基板，其中，位于同一列的第一类型像素电路电连接的数据信号线为同一信号线，位于同一列的至少两个相邻第一类型像素电路电连接的第一电源线间隔设置，且位于同一列的间隔设置的第一电源线通过位于所述第四导电层的至少一个信号连接线电连接。
  30. 根据权利要求1所述的显示基板，其中，所述多个发光元件还包括位于所述常规显示区的多个第二类型发光元件，所述多个像素电路还包括位于所述常规显示区的多个第二类型像素电路；
    所述多个第二类型发光元件中的至少一个第二类型发光元件和所述多个第二类型像素电路中的至少一个第二类型像素电路电连接，且所述第二类型发光元件在所述基底的正投影和电连接的第二类型像素电路在所述基底的正投影存在交叠。
  31. 一种显示装置，包括如权利要求1至30中任一项所述的显示基板。
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