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WO2024178663A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2024178663A1
WO2024178663A1 PCT/CN2023/078955 CN2023078955W WO2024178663A1 WO 2024178663 A1 WO2024178663 A1 WO 2024178663A1 CN 2023078955 W CN2023078955 W CN 2023078955W WO 2024178663 A1 WO2024178663 A1 WO 2024178663A1
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WO
WIPO (PCT)
Prior art keywords
transistor
initial
signal line
substrate
sub
Prior art date
Application number
PCT/CN2023/078955
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English (en)
French (fr)
Other versions
WO2024178663A9 (zh
Inventor
徐倩
黄琰
张毅
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2023/078955 priority Critical patent/WO2024178663A1/zh
Priority to CN202380007991.3A priority patent/CN118891974A/zh
Publication of WO2024178663A1 publication Critical patent/WO2024178663A1/zh
Publication of WO2024178663A9 publication Critical patent/WO2024178663A9/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • TFT thin film transistors
  • the present disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels, a plurality of reset signal lines and a plurality of second initial signal lines arranged on the substrate, the sub-pixels being electrically connected to the reset signal lines and the second initial signal lines, respectively, the sub-pixels comprising: a pixel circuit and a light-emitting device, the light-emitting device comprising a first electrode, the pixel circuit comprising: a first transistor, the reset signal line being configured to provide a control signal to a gate electrode of the first transistor, and the second initial signal line being configured to provide an initial signal to the first electrode of the light-emitting device;
  • the reset signal line at least partially extends along a first direction, and at least one of the second initial signal lines comprises: a first initial connection portion extending along the first direction and a second initial connection portion extending along a second direction, the second direction intersecting the first direction;
  • the orthographic projection of the first initial connection portion on the substrate does not overlap with the orthographic projection of the reset signal line on the substrate, and the orthographic projection of the second initial connection portion on the substrate partially overlaps with the orthographic projection of the reset signal line on the substrate.
  • the orthographic projection of the first initial connection portion of the second initial signal line connected to the subpixel on the substrate is located between the orthographic projection of the reset signal line connected to the subpixel on the substrate and the orthographic projection of the light emitting signal line connected to the subpixel on the substrate.
  • the first initial connection portion is disposed at the same layer as the second initial connection portion, and is an integral structure with the second initial connection portion.
  • first initial connection portion and the second initial connection portion are disposed in different layers, and the second initial connection portion is connected to the first initial connection portion through a via hole.
  • the reset signal line includes: a first sub-reset signal line and a second sub-reset signal line disposed in different layers and connected to each other;
  • the first initial connection portion is located on a side of the second initial connection portion close to the substrate, and is disposed in the same layer as the first sub-reset signal line or the second sub-reset signal line.
  • the first initial connection portion is located on a side of the second initial connection portion away from the substrate. And it is arranged in the same layer as the first electrode.
  • a minimum distance between the first initial connection portion and the first electrode of an adjacent light emitting device is about 1 micrometer to 3 micrometers.
  • the method further includes: a plurality of first scan signal lines and a plurality of first initial signal lines disposed on the substrate, wherein any one of the first scan signal lines and the first initial signal lines at least partially extends along the first direction;
  • At least one of the second initial connection lines comprises: a plurality of second initial connection portions, and the plurality of second initial connection portions are arranged along the first direction;
  • the orthographic projection of the second initial connection portion on the substrate also partially overlaps with the orthographic projections of the first scanning signal line and the first initial signal line on the substrate.
  • At least one of the second initial signal lines further includes: a plurality of first initial connection portions and a plurality of third initial connection portions extending along the first direction; the plurality of first initial connection portions are arranged along the first direction, and the plurality of third initial connection portions are arranged along the first direction;
  • Two adjacent second initial connection parts are connected through the first initial connection part or the third initial connection part, the second initial connection part is connected to one of the adjacent second initial connection parts through the first initial connection part, and the second initial connection part is connected to another adjacent second initial connection part through the third initial connection part.
  • the positive projection of the third initial connection portion of the second initial signal line connected to the sub-pixel on the substrate is located on a side of the positive projection of the first scanning signal line connected to the sub-pixel on the substrate away from the positive projection of the reset signal line connected to the sub-pixel on the substrate.
  • the second initial connection portion and the third initial connection portion are disposed in the same layer and are an integral structure
  • the second initial connection portion is located between the film layer where the reset signal line is located and the film layer where the first power line is located.
  • At least one of the second initial signal lines includes: a first initial connection portion and a plurality of second initial connection portions, and the plurality of second initial connection portions are connected to the first initial connection portion.
  • the present invention further comprises: a plurality of first connection lines extending at least partially along the second direction; the first connection lines and the second initial connection portion are disposed in the same layer;
  • At least one of the first connection lines is connected to a plurality of the first initial signal lines.
  • the invention further comprises: a second connection line extending at least partially along the second direction; the second connection line is disposed in the same layer as the second initial connection portion;
  • At least one of the second connection lines is connected to the first initial connection portions of the plurality of second initial signal lines.
  • the pixel circuit further includes: a flat portion and a plurality of second scan signal lines; the pixel circuit further includes: a second transistor, the first transistor and the second transistor are oxide transistors, the second scan signal line at least partially extends along the first direction and is configured to provide a control signal to a gate electrode of the second transistor;
  • the flat portion is arranged on the same layer as the first power line and is connected to each other; the orthographic projection of the flat portion on the substrate at least partially overlaps with the orthographic projections of the active layer of the first transistor, the active layer of the second transistor and the first electrode of at least one light-emitting device on the substrate.
  • the present disclosure further provides a display substrate, comprising: a substrate and a plurality of sub-pixels, a plurality of reset signal lines and a plurality of second initial signal lines arranged on the substrate, wherein the sub-pixels are electrically connected to the reset signal lines and the second initial signal lines, respectively, and the sub-pixels comprise: a pixel circuit and a light-emitting device, wherein the light-emitting device comprises a first electrode,
  • the pixel circuit comprises: a first transistor, the reset signal line is configured to provide a control signal to a gate electrode of the first transistor, and the second initial signal line is configured to provide an initial signal to a first electrode of the light emitting device;
  • the reset signal line at least partially extends along a first direction, and at least one of the second initial signal lines includes: a first initial connection portion and a third initial connection portion extending along the first direction and a second initial connection portion extending along a second direction, the second direction intersecting the first direction;
  • a distance between an orthographic projection of the third initial connection portion on the substrate and an orthographic projection of the reset signal line on the substrate is smaller than a distance between an orthographic projection of the third initial connection portion on the substrate and an orthographic projection of the first initial connection portion on the substrate.
  • the present disclosure further provides a display device, comprising: the above-mentioned display substrate.
  • FIG1 is a schematic structural diagram of a display device
  • FIG2 is a schematic diagram of a planar structure of a display substrate
  • FIG3 is a schematic diagram of a planar structure of another display substrate
  • FIG4A is a schematic diagram of an equivalent circuit of a pixel circuit
  • FIG4B is a working timing diagram of the pixel circuit provided in FIG4A ;
  • FIG5 is a structural schematic diagram 1 of a display structure provided by an embodiment of the present disclosure.
  • FIG6 is a schematic diagram of a portion of a film layer in a display substrate provided in FIG5 ;
  • FIG7 is a cross-sectional view of the display substrate provided in FIG5 ;
  • FIG8 is a second structural diagram of a display structure provided by an embodiment of the present disclosure.
  • FIG9 is a schematic diagram of a portion of a film layer of a display substrate provided in FIG8 ;
  • FIG10 is a cross-sectional view of the display substrate provided in FIG8 ;
  • FIG11 is a third structural diagram of a display structure provided in an embodiment of the present disclosure.
  • FIG12 is a schematic diagram of a portion of a film layer of a display substrate provided in FIG11;
  • FIG13 is a cross-sectional view of the display substrate provided in FIG11;
  • FIG14 is a fourth structural diagram of a display structure provided by an embodiment of the present disclosure.
  • FIG15 is a schematic diagram of a portion of a film layer of a display substrate provided in FIG14;
  • FIG16 is a cross-sectional view of the display substrate provided in FIG14;
  • FIG17 is a schematic plan view of the first semiconductor layer in FIGS. 5 , 8 , 11 and 14 ;
  • FIG18 is a schematic plan view of the first conductive layer in FIG5, FIG8, FIG11 and FIG14;
  • FIG19 is a schematic plan view of FIG5, FIG8, FIG11 and FIG14 after forming a first conductive layer
  • FIG20 is a schematic plan view of the second conductive layer in FIGS. 5 , 8 , 11 and 14 ;
  • FIG21 is a schematic plan view of FIG5, FIG8, FIG11 and FIG14 after forming a second conductive layer
  • FIG22 is a schematic plan view of the second semiconductor layer in FIG5, FIG8, FIG11 and FIG14;
  • FIG23 is a schematic plan view of FIG5, FIG8, FIG11 and FIG14 after forming a second semiconductor layer
  • FIG24 is a schematic plan view of the third conductive layer in FIG5 ;
  • FIG25 is a schematic plan view of FIG5 after forming a third conductive layer
  • FIG26 is a schematic plan view of the third conductive layer in FIG8 and FIG11;
  • FIG27 is a schematic plan view of FIG8 and FIG11 after a third conductive layer is formed
  • FIG28 is a schematic plan view of the third conductive layer in FIG14;
  • FIG29 is a schematic plan view of FIG14 after forming a third conductive layer
  • FIG31 is a schematic plan view of FIG8 and FIG11 after a fifth insulating layer is formed
  • FIG32 is a schematic plan view of FIG14 after a fifth insulating layer is formed
  • FIG33 is a schematic plan view of the fourth conductive layer in FIG5 and FIG8;
  • FIG34 is a schematic plan view of FIG5 after forming a fourth conductive layer
  • FIG35 is a schematic plan view of FIG8 after forming a fourth conductive layer
  • FIG36 is a schematic plan view of the fourth conductive layer in FIG11 ;
  • FIG37 is a plan view schematically showing FIG11 after forming a fourth conductive layer
  • FIG38 is a schematic plan view of the fourth conductive layer in FIG14;
  • FIG39 is a plan view schematically showing FIG14 after forming a fourth conductive layer
  • FIG40 is a schematic plan view of the display substrate provided in FIG5 after a first flat layer is formed
  • FIG41 is a schematic plan view of the display substrate provided in FIG8 after a first flat layer is formed
  • FIG42 is a schematic plan view of the display substrate provided in FIG11 after a first flat layer is formed
  • FIG43 is a schematic plan view of the display substrate provided in FIG14 after a first flat layer is formed
  • FIG44 is a schematic plan view of the fifth conductive layer in FIGS. 5 , 8 , 11 and 14 ;
  • FIG45 is a plan view schematically showing FIG5 after forming a fifth conductive layer
  • FIG46 is a schematic plan view of FIG8 after the fifth conductive layer is formed
  • FIG47 is a schematic plan view of FIG11 after forming a fifth conductive layer
  • FIG48 is a schematic plan view of FIG14 after a fifth conductive layer is formed
  • FIG49 is a schematic plan view of the display substrate provided in FIG5 after a second flat layer is formed
  • FIG50 is a schematic plan view of the display substrate provided in FIG8 after a second flat layer is formed
  • FIG51 is a schematic plan view of the display substrate provided in FIG11 after a second flat layer is formed;
  • FIG52 is a schematic plan view of the display substrate provided in FIG14 after a second flat layer is formed
  • FIG53 is a schematic plan view of the sixth conductive layer in FIG5 and FIG11;
  • FIG54 is a schematic plan view of FIG5 after a sixth conductive layer is formed
  • FIG55 is a schematic plan view of FIG11 after forming a sixth conductive layer
  • FIG56 is a schematic plan view of the sixth conductive layer in FIG8 ;
  • FIG57 is a plan view schematically showing FIG8 after forming a sixth conductive layer
  • FIG58 is a schematic plan view of the sixth conductive layer in FIG14;
  • FIG59 is a plan view schematically showing the structure of FIG14 after the sixth conductive layer is formed.
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the "source electrode” and the “drain electrode” may be interchanged.
  • electrical connection includes the situation where the components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the “element having some electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced by “conductive film”.
  • insulating film may be replaced by “insulating layer”.
  • the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different.
  • the materials of the precursors forming the multiple structures arranged in the same layer are the same, and the materials finally formed may be the same or different.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.
  • the display substrate uses low-temperature polysilicon (LTPS) technology, which has the advantages of high resolution, high response speed, high brightness, and high aperture ratio. Although it is popular in the market, LTPS technology also has some defects, such as high production cost and high power consumption.
  • LTPS technology also has some defects, such as high production cost and high power consumption.
  • the backplane (Low Temperature Poly-Silicon + Oxide, LTPO) technology solution formed by combining low-temperature polysilicon transistors with oxide transistors came into being.
  • LTPO technology has smaller leakage current and faster pixel response.
  • the display substrate has an additional layer of oxide, which reduces the energy consumption required to excite the pixels, thereby reducing the power consumption when the screen is displayed.
  • the aging degree of the driving transistors in different pixel circuits in display products using LTPO technology is different, and the display substrate cannot monitor the threshold voltage of the driving transistor, which reduces the display effect, service life and reliability of the display substrate.
  • FIG1 is a schematic diagram of the structure of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, wherein the timing controller is connected to the data driver, the scan driver, and the light emitting driver, respectively, the data driver is connected to a plurality of data signal lines (D1 to Dn), respectively, the scan driver is connected to a plurality of scan signal lines (S1 to Sm), respectively, and the light emitting driver is connected to a plurality of light emitting signal lines (E1 to Eo), respectively.
  • the timing controller is connected to the data driver, the scan driver, and the light emitting driver, respectively
  • the data driver is connected to a plurality of data signal lines (D1 to Dn), respectively
  • the scan driver is connected to a plurality of scan signal lines (S1 to Sm), respectively
  • the light emitting driver is connected to a plurality of light emitting signal lines (E1 to Eo), respectively.
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit may include a pixel circuit, and the pixel circuit may be connected to the scan signal line, the light emitting signal line, and the data signal line, respectively.
  • the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, may provide a clock signal suitable for the specifications of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specifications of the light emitting driver, an emission stop signal, etc.
  • the data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using grayscale values and control signals received from the timing controller. For example, the data driver can sample grayscale values using a clock signal, and apply data voltages corresponding to grayscale values to data signal lines D1 to Dn in units of pixel rows, where n can be a natural number.
  • the scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with conduction level pulses to scan signal lines S1 to Sm.
  • the scan driver can be constructed in the form of a shift register, and can sequentially transmit scan start signals provided in the form of conduction level pulses to the next level circuit under the control of the clock signal to generate scan signals, where m can be a natural number.
  • the light-emitting driver can generate emission signals to be provided to light-emitting signal lines E1, E2, E3, ... and Eo by receiving clock signals, emission stop signals, etc. from the timing controller.
  • the light emitting driver may sequentially provide an emission signal having an off-level pulse to the light emitting signal lines E1 to Eo.
  • the light emitting driver may be constructed in the form of a shift register, and may generate an emission stop signal provided in the form of an off-level pulse to the next stage circuit in a manner of sequentially transmitting the emission stop signal provided in the form of an off-level pulse to the next stage circuit under the control of a clock signal. Transmit a signal, o can be a natural number.
  • FIG. 2 is a schematic diagram of a planar structure of a display substrate
  • FIG. 3 is a schematic diagram of a planar structure of another display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix, wherein the plurality of pixel units P include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and at least one third sub-pixel P3 emitting a third color light, and the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel circuit and a light-emitting device.
  • the pixel circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the scanning signal line, the data signal line, and the light-emitting signal line, and the pixel circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device.
  • the light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel circuits of the sub-pixels in which they are located, and the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel circuit of the sub-pixel in which they are located.
  • the first sub-pixel P1 may be a red sub-pixel (R) emitting red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light
  • the third sub-pixel P3 may be a green sub-pixel (G) emitting green light.
  • the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal, and the three sub-pixels may be arranged in horizontal parallel, vertical parallel or in a herringbone manner, which is not limited in the present disclosure.
  • a pixel unit may include three sub-pixels, which may be arranged in horizontal parallel, vertical parallel, or in a herringbone pattern, etc., which is not limited in the present disclosure.
  • FIG2 is an example of horizontal parallel arrangement.
  • a pixel unit may include four sub-pixels, and the four sub-pixels may be a first sub-pixel, a second sub-pixel, and two third sub-pixels.
  • the four sub-pixels may be arranged in a horizontal parallel, a vertical parallel, or a square manner, which is not limited in the present disclosure.
  • FIG3 is illustrated by taking the arrangement of four sub-pixels in a square manner as an example.
  • the light emitting device may be an organic light emitting diode (OLED) including a stacked electrode (anode), an organic light emitting layer, and a second electrode (cathode).
  • OLED organic light emitting diode
  • the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).
  • HIL stacked hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • EML emitting layer
  • HBL hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • the hole injection layers of all sub-pixels may be a common layer connected together
  • the electron injection layers of all sub-pixels may be a common layer connected together
  • the hole transport layers of all sub-pixels may be a common layer connected together
  • the electron transport layers of all sub-pixels may be a common layer connected together
  • the hole blocking layers of all sub-pixels may be a common layer connected together
  • the light-emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated
  • the electron blocking layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.
  • FIG4A is a schematic diagram of an equivalent circuit of a pixel circuit.
  • the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • the pixel circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 capacitor C.
  • the gate electrode of the first transistor T1 is electrically connected to the reset signal terminal Reset, the first electrode of the first transistor T1 is electrically connected to the first initial signal terminal Vinit1, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the gate electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3; the third transistor T3
  • the gate electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the gate electrode of the fifth transistor T5 is electrically connected to the light emitting signal terminal EM, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the
  • the gate electrode of the sixth transistor T6 is electrically connected to the light emitting signal terminal EM, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4;
  • the gate electrode of the seventh transistor T7 is electrically connected to the first scanning signal terminal Gate1, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal terminal Vinit2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4;
  • the first plate C1 of the capacitor C is electrically connected to the first node N1, and the second plate C2 of the capacitor C is electrically connected to the first power supply terminal VDD.
  • the first transistor T1 may be referred to as a node reset transistor, and when the signal of the reset signal terminal Reset is a valid level signal, the initial signal of the first initial signal terminal Vinit1 is written into the first node N1.
  • the second transistor T2 may be referred to as a compensation transistor, and when the signal of the second scan signal terminal Gate2 is a valid level signal, the signal of the third node N3 is written into the first node N1 to compensate for the signal of the first node N1.
  • the third transistor T3 may be referred to as a driving transistor, and the third transistor T3 determines a driving current flowing between the first power supply terminal VDD and the second power supply terminal VSS according to a potential difference between its gate electrode and the first electrode.
  • the fourth transistor T4 may be referred to as a write transistor, and when the signal of the first scan signal terminal Gate1 is an active level signal, the initial signal of the data signal terminal Data is written into the second node N2.
  • the fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors.
  • the fifth transistor T5 and the sixth transistor T6 enable the light emitting device to emit light by forming a driving current path between the first power terminal VDD and the second power terminal VSS.
  • the seventh transistor T7 may be referred to as an anode reset transistor, and writes the initial signal of the second initial signal terminal Vinit2 into the first electrode of the light emitting device L when the signal of the first scan signal terminal Gate1 is a valid level signal.
  • the transistor can be divided into an N-type transistor and a P-type transistor.
  • the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages)
  • the turn-off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages).
  • the turn-on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages)
  • the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages).
  • the first transistor T1 to the seventh transistor T7 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor.
  • the active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS for short), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide).
  • LTPS low-temperature polysilicon
  • Oxide oxide semiconductor
  • the low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current.
  • the low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display substrate to form an LTPO display substrate, which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.
  • the first transistor T1 and the second transistor T2 are opposite to the third transistor T3 to the seventh transistor T7.
  • the first transistor T1 and the second transistor T2 may be N-type transistors
  • the third transistor T3 to the seventh transistor T7 may be P-type transistors.
  • the first transistor T1 and the second transistor T2 may be oxide transistors, and the third transistor The transistors T3 to T7 may be low temperature polysilicon transistors.
  • the voltage value of the signal at the first initial signal terminal Vinit1 is constant and is a DC signal.
  • the voltage value of the signal at the first initial signal terminal Vinit1 may be -3V.
  • the voltage value of the signal at the second initial signal terminal Vinit2 is constant and is a DC signal.
  • the voltage value of the signal at the second initial signal terminal Vinit2 may be 0V.
  • the light emitting device L′ may be electrically connected to the fourth node N4 and the second power supply terminal VSS, respectively.
  • the first power supply terminal VDD continuously provides a high level signal
  • the second power supply terminal VSS continuously provides a low level signal
  • FIG4B is a working timing diagram of the pixel circuit provided in FIG4A. The following is an explanation of an exemplary embodiment of the present disclosure through the working process of the pixel circuit in the display stage shown in FIG4A.
  • FIG4B is explained by taking the first transistor T1 and the second transistor T2 as N-type transistors, and the third transistor T3 to the seventh transistor T7 as P-type transistors as an example.
  • the pixel circuit in FIG4B includes the first transistor T1 to the seventh transistor T7, a capacitor C and 8 signal terminals (data signal terminal Data, a first scanning signal terminal Gate1, a second scanning signal terminal Gate2, a reset signal terminal Reset, a first initial signal terminal Vinit1, a second initial signal terminal Vinit2, a light emitting signal terminal EM and a first power supply terminal VDD).
  • the operation process of the pixel circuit may include:
  • the first stage P1 is called the initialization stage.
  • the signal at the reset signal terminal Reset is a high-level signal, the first transistor T1 is turned on, and the signal at the first initial signal terminal Vinit1 is written into the first node N1 through the turned-on first transistor T1, and the first node N1 is initialized (resettled), and the pre-stored voltage inside it is cleared to complete the initialization.
  • the second stage P2 is called the data writing stage or the threshold compensation stage, the first scanning signal terminal Gate1 is a low level signal, the second scanning signal terminal Gate2 is a low level signal, and the data signal terminal Data outputs a data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scanning signal terminal Gate1 is a low-level signal
  • the fourth transistor T4 is turned on and the seventh transistor T7 is turned on
  • the signal of the second scanning signal terminal Gate2 is a high-level signal
  • the second transistor T2 is turned on
  • the data voltage output by the data signal terminal Data is provided to the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal terminal Data and the threshold voltage of the third transistor T3 is charged into the capacitor C until the voltage of the first node N1 is Vd-
  • the third stage P3 is called the light-emitting stage.
  • the signal at the light-emitting signal terminal EM is a low-level signal.
  • the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the power supply voltage output by the first power supply terminal VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, thereby driving the light-emitting device L to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage of the first node N1 is Vd-
  • )-Vth]2 K*[(Vdd-Vd]2
  • I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the threshold voltage of the third transistor T3
  • Vd is the data voltage output by the data signal terminal Data
  • Vdd is the power supply voltage output by the first power supply terminal VDD.
  • a signal line that provides an initial signal to the second initial signal terminal of a pixel circuit is arranged across a signal line that provides a control signal to the reset signal terminal of the pixel circuit.
  • the signal line that provides a control signal to the reset signal terminal of the pixel circuit may produce foreign matter protrusions such as particles.
  • the protrusion generated by the signal line that provides a control signal to the reset signal terminal of the pixel circuit may short-circuit the signal line that provides an initial signal to the second initial signal line of the pixel circuit, thereby causing poor display.
  • FIG5 is a schematic diagram of the structure of the display structure provided in the embodiment of the present disclosure
  • FIG6 is a schematic diagram of a part of the film layer in the display substrate provided in FIG5
  • FIG7 is a cross-sectional view of the display substrate provided in FIG5
  • FIG8 is a schematic diagram of the structure of the display structure provided in the embodiment of the present disclosure
  • FIG9 is a schematic diagram of a part of the film layer of the display substrate provided in FIG8
  • FIG10 is a cross-sectional view of the display substrate provided in FIG8
  • FIG11 is a schematic diagram of the structure of the display structure provided in the embodiment of the present disclosure
  • FIG12 is a schematic diagram of a part of the film layer of the display substrate provided in FIG11
  • FIG13 is a cross-sectional view of the display substrate provided in FIG11
  • FIG14 is a schematic diagram of the structure of the display structure provided in the embodiment of the present disclosure
  • FIG15 is a schematic diagram of a part of the film layer of the display substrate provided in FIG14
  • the display substrate provided in the embodiment of the present disclosure may include: a substrate 10, a plurality of sub-pixels arranged on the substrate 10, a plurality of reset signal lines RL and a plurality of second initial signal lines INITL2, the sub-pixels are electrically connected to the reset signal lines RL and the second initial signal lines INITL2, respectively, the sub-pixels include: a pixel circuit, the pixel circuit includes: a pixel circuit and a light-emitting device, the light-emitting device includes a first electrode, the pixel circuit includes: a first transistor, the reset signal line RL is configured to provide a control signal to the gate electrode of the first transistor, and the second initial signal line INITL2 is configured to provide an initial signal to the first electrode of the light-emitting device.
  • the reset signal line RL at least partially extends along the first direction D1, and at least one second initial signal line INITL2 includes: a first initial connection portion INITL2A extending along the first direction and a second initial connection portion INITL2B extending along the second direction D2, the second direction D2 intersecting the first direction D1; the orthographic projection of the first initial connection portion INITL2A on the substrate does not overlap with the orthographic projection of the reset signal line RL on the substrate, and the orthographic projection of the second initial connection portion INITL2B on the substrate partially overlaps with the orthographic projection of the reset signal line RL on the substrate.
  • two rows and four columns of sub-pixels are used as an example for explanation, the two rows are the i-th row and the i+1-th row, and the four columns are the j-th column to the j+3-th column.
  • the reset signal line RL may have a double-layered structure.
  • the display substrate may be an LTPO display substrate.
  • the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and a conductive foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the display substrate includes: a substrate, a plurality of sub-pixels arranged on the substrate, a plurality of reset signal lines and a plurality of second initial signal lines, the sub-pixels are electrically connected to the reset signal lines and the second initial signal lines respectively, the sub-pixels include: a pixel circuit and a light-emitting device, the light-emitting device includes a first electrode, the pixel circuit includes: a first transistor, the reset signal line is configured to provide a control signal to the gate electrode of the first transistor, and the second initial signal line is configured to provide an initial signal to the first electrode of the light-emitting device; the reset signal line at least partially extends along the first direction, and at least one second initial signal line includes: a first initial connection portion extending along the first direction and a second initial connection portion extending along the second direction, the second direction intersects with the first direction; the orthogonal projection of the first initial connection portion on the substrate does not overlap with the orthogonal projection of the reset signal line on
  • the orthogonal projection of the first initial connection portion of the second initial signal line on the substrate does not overlap with the orthogonal projection of the reset signal line on the substrate, and the orthogonal projection of the second initial connection portion on the substrate partially overlaps with the orthogonal projection of the reset signal line on the substrate.
  • the partial overlap can reduce the area of the overlap region between the second initial signal line and the reset signal line, reasonably utilize the wiring space, effectively prevent the occurrence of short circuit in the process, and improve the display effect of the display substrate.
  • the light emitting device may include a first light emitting device emitting red light, a second light emitting device emitting blue light, and a third light emitting device and a fourth light emitting device emitting green light.
  • the area of the first electrode AL2 of the second light-emitting device is larger than the area of the first electrode AL1 of the first light-emitting device, and the areas of the first electrode AL3 of the third light-emitting device and the first electrode AL4 of the fourth light-emitting device are smaller than the area of the first electrode AL1 of the first light-emitting device.
  • the display substrate may further include: a plurality of first initial signal lines INITL1, a plurality of first scanning signal lines GL1, a plurality of second scanning signal lines GL2, a plurality of light emitting signal lines EL, a plurality of data signal lines DL and a plurality of first power lines VDDL arranged on the substrate, and the sub-pixels are electrically connected to the first initial signal line INITL1, the first scanning signal line GL1, the second scanning signal line GL2, the light emitting signal line EL, the data signal line DL and the first power line VDDL, respectively.
  • the pixel circuit may include: a second transistor (also a compensation transistor), a fourth transistor (also a write transistor) and a seventh transistor (also an anode reset transistor), the second transistor (also a compensation transistor) and the fourth transistor (also a write transistor) are of different types, the first transistor (also a node reset transistor) and the second transistor (also a compensation transistor) are of the same transistor type, and the fourth transistor (also a write transistor) and the seventh transistor (also an anode reset transistor) are of the same transistor type.
  • the first initial signal line INITL1 is configured to provide an initial signal to the first transistor (also a node reset transistor)
  • the first scanning signal line GL1 is configured to provide a control signal to the fourth transistor (also a write transistor) and the seventh transistor (also an anode reset transistor)
  • the second scanning signal line GL2 is configured to provide a control signal to the second transistor (also a compensation transistor).
  • any one of the first initial signal line INITL1, the first scan signal line GL1, the second scan signal line GL2 and the light emitting signal line EL at least partially extends along the first direction D1; the data signal line DL and the first power line VDDL may extend along the second direction D2.
  • the orthographic projection of the reset signal line RL connected to the sub-pixel on the substrate is located between the orthographic projection of the first initial signal line INITL1 connected to the sub-pixel and the orthographic projection of the first scanning signal line GL1 connected to the sub-pixel on the substrate
  • the second scanning signal line GL2 connected to the sub-pixel is located on the side of the orthographic projection of the first scanning signal line GL1 connected to the sub-pixel on the substrate away from the reset signal line RL connected to the sub-pixel
  • the light-emitting signal line EL connected to the sub-pixel is located between the orthographic projections of the second scanning signal line GL2 connected to the sub-pixel and the first initial signal line INITL1 connected to the sub-pixel on the substrate.
  • the reset signal line RL may include a first sub-reset signal line and a second sub-reset signal line disposed in different layers and connected to each other, wherein an orthographic projection of the first sub-reset signal line on the substrate at least partially overlaps an orthographic projection of the second sub-reset signal line on the substrate.
  • the second scan signal line GL2 may include a first sub-scan signal line and a second sub-scan signal line disposed in different layers and connected to each other, and an orthographic projection of the first sub-scan signal line on the substrate at least partially overlaps with an orthographic projection of the second sub-scan signal line on the substrate.
  • the reset signal line RL is disposed on the same layer as the second scan signal line GL2
  • the first sub reset signal line is disposed on the same layer as the first sub scan signal line
  • the second sub reset signal line is disposed on the same layer as the second sub scan signal line.
  • the first scanning signal line GL1 and the light emitting signal line EL are disposed on the same layer
  • the reset signal line RL and the second scanning signal line GL2 are disposed on the same layer and are located between the first scanning signal line GL1 and the light emitting signal line EL.
  • the line GL1 is located at a side away from the substrate
  • the first power line VDDL and the data signal line DL are located at a side away from the substrate of the first initial signal line INITL1.
  • adjacent data signal lines DL are symmetrical with respect to a virtual straight line extending in the second direction D2 .
  • adjacent first power lines VDDL are symmetrical with respect to a virtual straight line extending in the second direction D2 .
  • the first power line VDDL is connected to one of the adjacent power lines and is spaced apart from another adjacent power line, and two data signal lines DL are disposed between the two spaced apart first power lines VDDL.
  • the orthographic projection of the first initial connection portion INITL2A in the second initial signal line connected to the sub-pixel on the substrate is located between the orthographic projection of the reset signal line RL connected to the sub-pixel on the substrate and the orthographic projection of the light-emitting signal line EL connected to the sub-pixel on the substrate.
  • the first initial connection portion INITL2A is disposed on the same layer as the second initial connection portion INITL2B, and is an integral structure with the second initial connection portion INITL2B.
  • the first initial connection portion INITL2A and the second initial connection portion INITL2B are disposed in different layers, and the second initial connection portion INITL2B is connected to the first initial connection portion INITL2A through a via.
  • the first initial connection portion INITL2A is located on a side of the second initial connection portion INITL2B close to the substrate and is disposed on the same layer as the first sub-reset signal line or the second sub-reset signal line.
  • FIG. 5 and FIG. 14 illustrate the case where the first initial connection portion INITL2A and the second sub-reset signal line are disposed on the same layer as an example.
  • the first initial connection portion INITL2A is located on a side of the second initial connection portion INITL2B away from the substrate 10 , and is disposed in the same layer as the first electrode.
  • the minimum distance between the first initial connection portion INITL2A and the first electrode of the adjacent light emitting device is about 1 micrometer to 3 micrometers.
  • the minimum distance between the first initial connection portion INITL2A and the first electrode of the adjacent light emitting device may be about 2 micrometers.
  • At least one second initial connection portion INITL2B includes: a plurality of second initial connection portions INITL2B, and the plurality of second initial connection portions INITL2B are arranged along the first direction D1; the orthographic projection of the second initial connection portion INITL2B on the substrate also overlaps with the orthographic projection portions of the first scanning signal line GL1 and the first initial signal line INITL1 on the substrate.
  • At least one second initial signal line further includes: a plurality of first initial connection portions INITL2A and a plurality of third initial connection portions INITL2C extending along the first direction D1; the plurality of first initial connection portions INITL2A are arranged along the first direction D1, and the plurality of third initial connection portions INITL2C are arranged along the first direction D1.
  • the positive projection of the third initial connection portion INITL2C of the second initial signal line connected to the sub-pixel on the substrate is located on a side of the positive projection of the first scanning signal line GL1 connected to the sub-pixel on the substrate away from the positive projection of the reset signal line RL connected to the sub-pixel on the substrate.
  • the second initial connection portion INITL2B and the third initial connection portion INITL2C are disposed in the same layer and are an integral structure; the second initial connection portion INITL2B is located at the reset signal Between the film layer where the line EL is located and the film layer where the first power line VDDL is located.
  • the shape of the integrated structure of the second initial connection portion INITL2B and the third initial connection portion INITL2C may be a "7" shape.
  • the overall routing of the second initial signal line INITL2 in FIGS. 5 , 6 , 8 , 9 , 11 and 12 presents a plurality of “J” shapes arranged along the second direction.
  • the second initial connection portions of adjacent second initial signal lines in the same column may be connected to each other and form an integral structure.
  • the second initial connection portions of adjacent second initial signal lines in the same column may be connected to each other so that multiple second initial signal lines may form a mesh structure, thereby reducing the load of the signal lines and improving the display uniformity of the display substrate.
  • the second initial connection portions located in adjacent rows may be connected in different columns, and the first initial connection portions do not overlap with the reset signal line.
  • the overall routing of the second initial signal line INITL2 presents a plurality of inverted “T” shapes arranged along the second direction.
  • the display substrate further includes: a plurality of first connection lines L1 extending at least partially along the second direction; the first connection lines L1 and the second initial connection portion INITL2B are disposed in the same layer; and at least one first connection line L1 is connected to the plurality of first initial signal lines INITL1.
  • the present disclosure can form a mesh structure with the first connection lines and the first initial signal lines, thereby reducing the load of the signal lines and improving the display uniformity of the display substrate.
  • the display substrate further includes: a second connection line L2 extending at least partially along the second direction; the second connection line L2 and the second initial connection portion INITL2B are disposed in the same layer; at least one second connection line L2 is connected to the first initial connection portion INITL2A of the plurality of second initial signal lines.
  • the present disclosure can form a mesh structure of the second connection lines and the second initial signal lines by disposing the second connection lines, thereby reducing the load of the signal lines and improving the display uniformity of the display substrate.
  • the display substrate further includes: a flat portion; the flat portion is disposed on the same layer as the first power line VDDL and is connected to each other; the orthographic projection of the flat portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the first transistor, the active layer of the second transistor, the first scan signal line GL1, the second scan signal line GL2, the first initial signal line INITL1 and the first electrode of at least one light-emitting device on the substrate.
  • the present disclosure can improve the flatness of the first electrode of the light-emitting device by providing the flat portion, thereby improving the display effect of the display substrate.
  • the arrangement of the second initial signal line in the display substrate provided by the present disclosure can also reduce the overlapping area between the second initial signal line and the first electrode of the light-emitting device, thereby reducing the parasitic capacitance between the two and improving the display effect of the display substrate.
  • the second initial signal line of the present disclosure can be used not only in a display substrate including two initial signal lines, but also in a display substrate including three initial signal lines, wherein the third initial signal line can be configured to provide an initial signal to the first electrode of the driving transistor.
  • FIGS. 5 to 14 are described by taking a display substrate including two initial signal lines as an example.
  • the display substrate may include: a driving circuit layer and a light emitting structure layer sequentially stacked on a substrate; the driving circuit layer includes at least a pixel circuit, a first initial signal line, a first scanning line, and a second scanning line.
  • the light-emitting structure layer at least includes: a light-emitting device;
  • the driving circuit layer includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer stacked in sequence;
  • the first conductive layer at least includes: a first scanning signal line GL1 and a light emitting signal line EL;
  • the second conductive layer at least includes: a first initial signal line INITL1, a first sub-reset signal line of the reset signal line RL, and a first sub-scanning signal line of the second scan signal line GL2;
  • the third conductive layer at least includes: a second sub-reset signal line of the reset signal line RL and a second sub-scanning signal line of the second scan signal line GL2;
  • the fourth conductive layer at least includes: a second initial connection portion INITL2A of the second initial signal line INITL2.
  • the fifth conductive layer at least includes: a data signal line DL, a first power line VDDL and a flat portion.
  • the light emitting structure layer may include: a sixth conductive layer.
  • the sixth conductive layer includes at least: a first electrode of the light emitting device.
  • the third initial connection part INITL2C may be located in the fourth conductive layer.
  • the first initial connection part INITL2A may be located in the third conductive layer, the fourth conductive layer, or the sixth conductive layer.
  • the first initial connection part INITL2A may be located at the third conductive layer.
  • the driving structure layer 20 of the display substrate may further include: a first insulating layer 21, a second insulating layer 22, a third insulating layer 23, a fourth insulating layer 24, a fifth insulating layer 25, a sixth insulating layer 26, a first planar layer 27 and a second planar layer 28.
  • the first insulating layer 21 is located between the first semiconductor layer 31 and the first conductive layer 32
  • the second insulating layer 22 is located between the first conductive layer 32 and the second conductive layer 33
  • the third insulating layer 23 is located between the second conductive layer 33 and the second semiconductor layer 34
  • the fourth insulating layer 24 is located between the second semiconductor layer 34 and the third conductive layer 35
  • the fifth insulating layer 25 is located between the third conductive layer 35 and the fourth conductive layer 36
  • the sixth insulating layer 26 and the first planar layer 27 are located between the fourth conductive layer 36 and the fifth conductive layer 37
  • the second planar layer 28 is located between the fifth conductive layer 37 and the sixth conductive layer 41.
  • the embodiment of the present disclosure also provides a display substrate, comprising: a substrate and a plurality of sub-pixels, a plurality of reset signal lines and a plurality of second initial signal lines arranged on the substrate, the sub-pixels are electrically connected to the reset signal lines and the second initial signal lines respectively, the sub-pixels comprise: a pixel circuit and a light-emitting device, the light-emitting device comprises a first electrode, the pixel circuit comprises: a first transistor, the reset signal line is configured to provide a control signal to a gate electrode of the first transistor, and the second initial signal line is configured to provide an initial signal to the first electrode of the light-emitting device;
  • the reset signal line at least partially extends along the first direction, and the at least one second initial signal line includes: a first initial connection portion and a third initial connection portion extending along the first direction and a second initial connection portion extending along the second direction, the second direction intersecting the first direction;
  • a distance between an orthographic projection of the third initial connection portion on the substrate and an orthographic projection of the reset signal line on the substrate is smaller than a distance between an orthographic projection of the third initial connection portion on the substrate and an orthographic projection of the first initial connection portion on the substrate.
  • a parasitic capacitance exists between the active layer of the first transistor located in the second semiconductor layer (also the active layer of the second transistor) of the pixel circuit of the sub-pixel and the first scanning signal line GL1 located in the first conductive layer, and is called the parasitic capacitance of the sub-pixel.
  • the parasitic capacitances of different sub-pixels are different.
  • the parasitic capacitances of the red sub-pixel and the green sub-pixel may be the same, and may be different from the parasitic capacitance of the blue sub-pixel.
  • the present disclosure can balance the data ranges between different sub-pixels, adjust the black state voltage, and improve the image quality by differentially designing the parasitic capacitances of different sub-pixels. So as to improve the display effect of the display substrate.
  • the different parasitic capacitances of different sub-pixels can be achieved by making the overlapping areas between the active layer of the first transistor located in the second semiconductor layer (also the active layer of the second transistor) of the pixel circuits of the different sub-pixels and the first scanning signal line located in the first conductive layer different.
  • the following is an exemplary explanation through the preparation process of the display substrate.
  • the "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials.
  • Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition
  • coating can be any one or more of spraying, spin coating and inkjet printing
  • etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure.
  • Thin film refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the "A and B are arranged in the same layer” in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • FIG. 17 to FIG. 59 are schematic diagrams of a manufacturing process of a display substrate provided by an exemplary embodiment.
  • FIG. 17 to FIG. 59 are illustrated by taking two rows and four columns of sub-pixels as an example.
  • a manufacturing process of the display substrate of FIG. 5, FIG. 8, FIG. 11 and FIG. 14 provided by an exemplary embodiment may include:
  • Forming a first semiconductor layer pattern may include: sequentially depositing a first semiconductor thin film on a substrate, patterning the first semiconductor thin film through a patterning process, and forming a first semiconductor layer pattern covering the substrate, as shown in FIG. 17 , which is a plan view schematic diagram of the first semiconductor layer in FIGS. 5 , 8 , 11 , and 14 .
  • the first semiconductor layer may include at least an active layer T31 of a third transistor located in at least one sub-pixel, an active layer T41 of a fourth transistor, an active layer T51 of a fifth transistor, an active layer T61 of a sixth transistor, and an active layer T71 of a seventh transistor.
  • the active layers T31 of the third transistor to T71 of the seventh transistor are an integral structure connected to each other.
  • the active layers T31 of the third transistor to T71 of the seventh transistor of adjacent sub-pixels are symmetrically disposed with respect to a virtual straight line extending in the second direction D2.
  • the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor may be located on the same side of the active layer T31 of the third transistor in the present subpixel
  • the active layer T61 of the sixth transistor may be located on the same side of the active layer T31 of the third transistor in the present subpixel
  • the active layer T61 of the sixth transistor and the active layer T41 of the fourth transistor may be located on different sides of the active layer T31 of the third transistor in the present subpixel.
  • the active layer T51 of the fifth transistor, the active layer T61 of the sixth transistor, and the active layer T71 of the seventh transistor in the i-th row of subpixels may be located on a side of the active layer T31 of the third transistor in the present subpixel away from the i+1-th row of subpixels, and the active layer T41 of the fourth transistor in the i-th row of subpixels may be located on a side of the active layer T31 of the third transistor in the present subpixel close to the i+1-th row of subpixels.
  • the active layer T31 of the third transistor may be shaped like an inverted “ ⁇ ”.
  • the active layer T41 of the fourth transistor, the active layer T51 of the fifth transistor, and the active layer T61 of the sixth transistor may be shaped like an “I”.
  • the active layer T71 of the seventh transistor may be shaped like an “L”.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the first region T31_1 of the active layer 13 of the third transistor may simultaneously serve as the second region T41_2 of the active layer T41 of the fourth transistor and the second region T51_2 of the active layer T51 of the fifth transistor
  • the second region T31_2 of the active layer T31 of the third transistor may simultaneously serve as the first region T61_1 of the active layer T61 of the sixth transistor
  • the second region T61_2 of the active layer T61 of the sixth transistor may serve as the second region T71_2 of the active layer T71 of the seventh transistor
  • the first region T41_1 of the active layer T41 of the fourth transistor, the first region T51_1 of the active layer T51 of the fifth transistor, and the first region T71_1 of the active layer T71 of the seventh transistor may be separately provided.
  • forming the first conductive layer pattern may include: depositing a first insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film by a patterning process, forming a first insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the first insulating layer, as shown in FIGS. 18 and 19, wherein FIG. 18 is a plan view schematically showing the first conductive layer in FIGS. 5, 8, 11 and 14, and FIG. 19 is a plan view schematically showing the first conductive layer after the first conductive layer is formed in FIGS. 5, 8, 11 and 14.
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer may include at least: a first scan signal line GL1 , a light emitting signal line EL, and a first plate C1 of a capacitor located in at least one sub-pixel.
  • the first plates C1 of the pixel circuits of adjacent sub-pixels are symmetrically arranged with respect to a virtual straight line extending along the second direction D2.
  • the shape of the first electrode plate C1 may be rectangular, the corners of the rectangle may be chamfered, and the orthographic projection of the first electrode plate C1 on the substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor on the substrate.
  • the first electrode plate C1 may simultaneously serve as a plate of the capacitor and the gate electrode T32 of the third transistor T3.
  • the shape of the first scan signal line GL1 may be a line shape whose main part extends along the first direction D1, and the first scan signal line GL1 connected to the i-th row of sub-pixels may be located on a side of the first electrode plate C1 of the capacitor of the sub-pixel close to the i+1-th row of sub-pixels.
  • the area where the first scan signal line GL1 overlaps with the active layer of the fourth transistor of the sub-pixel may serve as the gate electrode T42 of the fourth transistor, and the area where the first scan signal line GL1 overlaps with the active layer of the seventh transistor of the sub-pixel may serve as the gate electrode T72 of the seventh transistor.
  • the shape of the light-emitting signal line EL can be a line shape in which the main part extends along the first direction D1.
  • the light-emitting signal line EL can be located on the side of the first electrode C1 of the sub-pixel away from the i+1th row of sub-pixels.
  • the area where the light-emitting signal line EL overlaps with the active layer of the fifth transistor of the sub-pixel serves as the gate electrode T52 of the fifth transistor, and the area where the light-emitting signal line EL overlaps with the active layer of the sixth transistor of the sub-pixel serves as the gate electrode T62 of the sixth transistor.
  • the first scanning signal line GL1 and the light-emitting signal line EL can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which can not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.
  • the first conductive layer can be used as a shield to perform conductorization on the first semiconductor layer, and the first semiconductor layer in the area shielded by the first conductive layer forms the channel area of the third transistor T3 to the seventh transistor T7, and the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of the third transistor to the seventh active layer are both conductorized.
  • the first area T31_1 of the active layer 13 of the third transistor (also the second area T41_2 of the active layer T41 of the fourth transistor and the second area T51_2 of the active layer T51 of the fifth transistor) can be reused as the first electrode T33 of the third transistor (also the second electrode T44 of the fourth transistor and the second electrode T54 of the fifth transistor).
  • the gate electrode T32 of the third transistor is disposed across the active layer of the third transistor.
  • the gate electrode T42 of the fourth transistor is arranged across the active layer of the fourth transistor, the gate electrode T52 of the fifth transistor is arranged across the active layer of the fifth transistor, the gate electrode T62 of the sixth transistor is arranged across the active layer of the sixth transistor, and the gate electrode T72 of the seventh transistor is arranged across the active layer of the seventh transistor. That is to say, the extension direction of the gate electrode of at least one transistor is perpendicular to the extension direction of the active layer.
  • FIGS. 20 and 21 wherein FIG. 20 is a plan view schematically showing the second conductive layer in FIGS. 5, 8, 11 and 14, and FIG. 21 is a plan view schematically showing the second conductive layer after being formed in FIGS. 5, 8, 11 and 14.
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the second conductive layer may include at least: a first initial signal line INITL1, a first sub-reset signal line RLA of the reset signal line, a first sub-scanning signal line GL2A of the second scan signal line, and a second plate C2 of the capacitor located at at least one sub-pixel.
  • the second plates C2 of the pixel circuits of adjacent sub-pixels are disposed symmetrically with respect to a virtual straight line extending along the second direction D2.
  • the second electrode plate C2 may include a main body portion C21 and a connecting portion C22 connected to each other, wherein the connecting portion C22 of the sub-pixel is located on a side of the main body portion C22 of the sub-pixel close to the previous or next column of sub-pixels.
  • the outline of the main body C21 can be rectangular, and the corners of the rectangle can be chamfered.
  • the orthographic projection of the main body C21 on the substrate overlaps at least partially with the orthographic projection of the first electrode plate on the substrate.
  • the second electrode plate can serve as another electrode plate of the capacitor, and the first electrode plate C1 and the second electrode plate C2 constitute the capacitor of the pixel circuit.
  • the main body C21 is provided with an opening, and the shape of the opening can be rectangular, and can be located in the middle of as shown in FIG20, so that as shown in FIG20, a ring structure is formed.
  • the opening exposes the second insulating layer covering the first electrode plate, and the orthographic projection of the first electrode plate on the substrate includes the orthographic projection of the opening on the substrate.
  • the opening exposes the first electrode plate, so that the second electrode of the first transistor (also the second electrode of the second transistor) formed subsequently is connected to the first electrode plate.
  • connection portion C22 may be rectangular.
  • the second electrodes in adjacent sub-pixels located in the same row are symmetrically arranged with respect to a virtual line along the second direction D2.
  • the second electrode plate C2 is spaced apart from the second electrode plate C2 of one of the adjacent sub-pixels in the same row, and is interconnected with the second electrode plate of another adjacent sub-pixel in the same row, and is an integrated structure.
  • the second electrode plate of the sub-pixel in the i-th row and j-column is spaced apart from the second electrode plate of the sub-pixel in the i-th row and j+1-column
  • the second electrode plate of the sub-pixel in the i-th row and j+2-column is spaced apart from the second electrode plate of the sub-pixel in the i-th row and j+3-column
  • the connecting portion of the second electrode plate of the sub-pixel in the i-th row and j+1-column is connected to the connecting portion of the second electrode plate of the sub-pixel in the i-th row and j+2-column.
  • the second electrodes of some adjacent sub-pixels in the same row are interconnected, which can ensure the display uniformity of the display substrate to a certain extent.
  • the shape of the first initial signal line INITL1 may be a line shape whose main part extends along the first direction D1, and the first initial signal line INITL1 connected to the i-th row of sub-pixels may be located on a side of the second electrode plate C2 of the sub-pixel close to the i+1-th row of sub-pixels.
  • the positive projection of the first initial signal line INITL1 connected to the sub-pixel on the substrate is located on a side where the positive projection of the first scanning signal line connected to the sub-pixel on the substrate is away from the positive projection of the first electrode plate of the sub-pixel on the substrate.
  • the shape of the first sub-reset signal line RLA of the reset signal line may be a line shape with a main portion extending along the first direction D1, and the first sub-reset signal line RLA may be located at the second The area between the electrode plate C2 and the first initial signal line INITL1 and overlapping with the active layer of the first transistor of the sub-pixel formed subsequently serves as the first gate electrode T12A of the first transistor.
  • the positive projection of the first sub-reset signal line RLA connected to the sub-pixel on the substrate is located between the positive projection of the first scanning signal line connected to the sub-pixel on the substrate and the positive projection of the first initial signal line INITL1 connected to the sub-pixel on the substrate.
  • the shape of the first sub-scanning signal line GL2A of the second scan signal line may be a line shape whose main part extends along the first direction D1, and the first sub-scanning signal line GL2A of the second scan signal line may be located between the second electrode plate C2 of the connected sub-pixel and the first sub-reset signal line RLA of the reset signal line, and the area overlapping with the active layer of the second transistor of the sub-pixel formed subsequently serves as the first gate electrode T22A of the second transistor.
  • the positive projection of the first sub-scanning signal line GL2A connected to the sub-pixel on the substrate is located between the positive projection of the first electrode plate of the sub-pixel on the substrate and the positive projection of the first scan signal line connected to the sub-pixel on the substrate.
  • the first initial signal line INITL1, the first sub-reset signal line RLA of the reset signal line, and the first sub-scanning signal line GL2A of the second scan signal line can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which can not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.
  • FIGS. 22 and 23 wherein FIG. 22 is a plan schematic diagram of the second semiconductor layer in FIGS. 5, 8, 11 and 14, and FIG. 23 is a plan schematic diagram of the second semiconductor layer after the second semiconductor layer is formed in FIGS. 5, 8, 11 and 14.
  • the second semiconductor layer may include at least an active layer T11 of a first transistor and an active layer T21 of a second transistor located in at least one sub-pixel.
  • the active layer T11 of the first transistor and the active layer T21 of the second transistor are an integral structure connected to each other.
  • the active layers T11 of the first transistor and the active layers T21 of the second transistor of adjacent sub-pixels are symmetrically disposed with respect to a virtual straight line extending in the second direction D2.
  • the active layer T21 of the second transistor in the i-th row of sub-pixels may be located on a side of the active layer T11 of the first transistor in the sub-pixel away from the i+1-th row of sub-pixels.
  • the active layer T11 of the first transistor and the active layer T21 of the second transistor may have an “I” shape or an “L” shape.
  • an orthographic projection of an active layer T11 of a first transistor of the sub-pixel on the substrate at least partially overlaps with an orthographic projection of a first sub-reset signal line of a reset signal line connected to the sub-pixel and a first initial signal line connected to the sub-pixel on the substrate.
  • an orthographic projection of an active layer T21 of a second transistor of the sub-pixel on the substrate overlaps an orthographic projection of a first sub-scanning signal line GL2A of a second scan signal line connected to the sub-pixel on the substrate.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the second region T11_2 of the active layer T11 of the first transistor may simultaneously serve as the first region T21_1 of the active layer T21 of the second transistor, and the first region T11_1 of the active layer T11 of the first transistor and the second region T21_2 of the active layer T21 of the second transistor may be separately provided.
  • the second active layer T11 of the first transistor of the sub-pixel at least partially overlaps with the orthographic projection of the first scanning signal line connected to the sub-pixel on the substrate.
  • the active layer T11 of the first transistor is disposed across the first gate electrode of the first transistor
  • the active layer T21 of the second transistor is disposed across the first gate electrode of the second transistor.
  • FIGS. 24 to 29 wherein FIG. 24 is a plan view schematically showing the third conductive layer in FIG. 5, FIG. 25 is a plan view schematically showing the third conductive layer after being formed in FIG. 5, FIG. 26 is a plan view schematically showing the third conductive layer in FIG. 8 and FIG. 11, FIG. 27 is a plan view schematically showing the third conductive layer after being formed in FIG.
  • FIG. 28 is a plan view schematically showing the third conductive layer in FIG. 14, and FIG. 29 is a plan view schematically showing the third conductive layer after being formed in FIG. 14.
  • the third conductive layer may be referred to as a third gate metal (GATE3) layer.
  • the third conductive layer may include at least a second sub reset signal line RLB of the reset signal line and a second sub scanning signal line GL2B of the second scanning signal line.
  • the shape of the second sub-reset signal line RLB of the reset signal line can be a line shape in which the main part extends along the first direction D1, and the positive projection of the second sub-reset signal line RLB of the reset signal line on the substrate at least partially overlaps with the positive projection of the first sub-reset signal line of the reset signal line on the substrate, and is electrically connected to the first sub-reset signal line of the reset signal line.
  • the positive projection of the second sub-reset signal line RLB connected to the sub-pixel on the substrate is located between the positive projection of the first scan signal line connected to the sub-pixel and the positive projection of the first initial signal line INITL1 connected to the sub-pixel on the substrate.
  • the area where the second sub-reset signal line RLB of the reset signal line overlaps with the active layer of the first transistor of the sub-pixel serves as the second gate electrode T12B of the first transistor.
  • the first gate electrode and the second gate electrode of the first transistor constitute the gate electrode of the first transistor.
  • the shape of the second sub-scanning signal line GL2B of the second scan signal line can be a line shape in which the main part extends along the second direction D1, and the orthographic projection of the second sub-scanning signal line GL2B of the second scan signal line on the substrate at least partially overlaps with the orthographic projection of the first sub-scanning signal line of the second scan signal line on the substrate, and is electrically connected to the first sub-scanning signal line of the second scan signal line.
  • the positive projection of the second sub-scanning signal line GL2B connected to the sub-pixel on the substrate is located between the positive projection of the first electrode plate of the sub-pixel on the substrate and the positive projection of the first scanning signal line connected to the sub-pixel on the substrate.
  • the area where the second sub-scanning signal line GL2B of the second scanning signal line overlaps with the active layer of the first transistor of the sub-pixel serves as the second gate electrode T22B of the second transistor.
  • the first gate electrode and the second gate electrode of the second transistor constitute the gate electrode of the second transistor.
  • the second sub-reset signal line RLB of the reset signal line and the second sub-scanning signal line GL2B of the second scan signal line can be designed with equal width, or can be designed with unequal width, can be a straight line, or can be a broken line, which can not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance between the signal lines.
  • the present disclosure is not limited here.
  • the third conductive layer in the display substrate provided in FIG. 5 may further include: a plurality of first initial connection portions INITL2A of the second initial signal line.
  • one second initial signal line may include a plurality of first initial connection portions INITL2A arranged at intervals and extending along the first direction D1.
  • the plurality of first initial connection portions INITL2A located on the same second initial signal line are arranged along the first direction D1.
  • the third conductive layer in the display substrate provided in Figure 14 may further include: a first initial connection portion INITL2A of a second initial signal line.
  • a second initial signal line may include a first initial connection portion INITL2A extending along the second direction D1.
  • the shape of the first initial connection portion INITL2A may be a line shape in which the main portion extends along the first direction D1.
  • the first initial connection portion INITL2A of the second initial signal line connected to the sub-pixel is located on a side of the second sub-reset signal line RLB of the reset signal line connected to the sub-pixel away from the second sub-scanning signal line GL2B of the second scan signal line
  • the orthogonal projection of the first initial connection portion INITL2A of the second initial signal line connected to the sub-pixel on the substrate is located on a side of the orthogonal projection of the first initial signal line connected to the sub-pixel on the substrate away from the second sub-reset signal line RLB of the reset signal line connected to the sub-pixel.
  • the positive projection of the first initial connection portion INITL2A of the second initial signal line connected to the sub-pixel on the substrate does not overlap with the positive projection of the second sub-reset signal line RLB of the reset signal line connected to the sub-pixel and the first initial signal line connected to the sub-pixel on the substrate.
  • the second semiconductor layer can be conductorized using the third conductive layer as a shield, the second semiconductor layer in the area shielded by the third conductive layer forms a channel region from the first transistor to the second transistor, and the second semiconductor layer in the area not shielded by the third conductive layer is conductorized, that is, the first area and the second area from the first transistor to the second active layer are both conductorized.
  • FIGS. 30 to 32 forming a fifth insulating layer pattern, comprising: depositing a fifth insulating film on a substrate having the aforementioned pattern, patterning the fifth insulating film through a patterning process to form a fifth insulating layer pattern covering the aforementioned pattern, wherein the fifth insulating layer is provided with a plurality of via patterns, as shown in FIGS. 30 to 32 , wherein FIG. 30 is a plan schematic diagram of FIG. 5 after the fifth insulating layer is formed, FIG. 31 is a plan schematic diagram of FIG. 8 and FIG. 11 after the fifth insulating layer is formed, and FIG. 32 is a plan schematic diagram of FIG. 14 after the fifth insulating layer is formed.
  • the multiple via holes of the fifth insulating layer include at least: a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, a sixth via hole V6, a seventh via hole V7, an eighth via hole V8, a ninth via hole V9 and a tenth via hole V10 located in at least one sub-pixel.
  • the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the fourth transistor on the substrate, the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer in the first via hole V1 are etched away to expose the surface of the first area of the active layer of the fourth transistor, and the first via hole V1 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of the active layer of the fourth transistor through the via hole.
  • the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the fifth transistor on the substrate, the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer in the second via V2 are etched away to expose the surface of the first area of the active layer of the fifth transistor, and the second via V2 is configured to connect the first electrode of the subsequently formed fifth transistor to the first area of the active layer of the fifth transistor through the via.
  • the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the second area of the active layer of the third transistor (also the first area of the active layer of the sixth transistor) on the substrate, the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer in the third via hole V3 are etched away to expose the surface of the second area of the active layer of the third transistor (also the first area of the active layer of the sixth transistor), and the third via hole V3 is configured to connect the second electrode of the subsequently formed second transistor (also the second electrode of the third transistor and the first electrode of the sixth transistor) to the second area of the active layer of the third transistor (also the first area of the active layer of the sixth transistor) through the via hole.
  • the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the sixth transistor (also the second region of the active layer of the seventh transistor) on the substrate, the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer in the fourth via hole V4 are etched away to expose the surface of the second region of the active layer of the sixth transistor (also the second region of the active layer of the seventh transistor), and the fourth via hole V4 is configured to The second electrode of the sixth transistor (also the second electrode of the seventh transistor) formed subsequently is connected to the second region of the active layer of the sixth transistor (also the second region of the active layer of the seventh transistor) through the via hole.
  • the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the seventh transistor on the substrate, the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer in the fifth via V5 are etched away to expose the surface of the first area of the active layer of the seventh transistor, and the fifth via V5 is configured to connect a subsequently formed first initial connection portion (which is also the first electrode of the seventh transistor) to the first area of the active layer of the seventh transistor through the via.
  • the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the first plate of the capacitor on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via V6 are etched away to expose the surface of the first plate of the capacitor, and the sixth via V6 is configured to connect the second electrode of the subsequently formed first transistor (also the first electrode of the second transistor) to the first plate of the capacitor through the via.
  • the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the second plate of the capacitor on the substrate, the fourth insulating layer and the third insulating layer in the seventh via V7 are etched away to expose the surface of the second plate of the capacitor, and the seventh via V7 is configured to connect the first electrode of the subsequently formed fifth transistor to the second plate of the capacitor through the via.
  • the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the first initial signal line on the substrate, the fourth insulating layer and the third insulating layer in the eighth via V8 are etched away to expose the surface of the first initial signal line, and the eighth via V8 is configured to connect the first electrode of the subsequently formed first transistor to the first initial signal line through the via.
  • the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the first transistor on the substrate, the fourth insulating layer in the ninth via V9 is etched away to expose the surface of the first area of the active layer of the first transistor, and the ninth via V9 is configured to connect the first electrode of the subsequently formed first transistor to the first area of the active layer of the first transistor through the via.
  • the orthographic projection of the tenth via V10 on the substrate is located within the range of the orthographic projection of the second area of the active layer of the first transistor (also the first area of the active layer of the second transistor) on the substrate, the fourth insulating layer in the tenth via V10 is etched away to expose the surface of the second area of the active layer of the first transistor (also the first area of the active layer of the second transistor), and the tenth via V10 is configured to connect the second electrode of the subsequently formed first transistor (also the first electrode of the second transistor) to the second area of the active layer of the first transistor (also the first area of the active layer of the second transistor) through the via.
  • the orthographic projection of the eleventh via V11 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the second transistor on the substrate, the fourth insulating layer in the eleventh via V11 is etched away to expose the surface of the second region of the active layer of the second transistor, and the eleventh via V11 is configured to connect the second electrode of the subsequently formed second transistor (which is also the first electrode of the sixth transistor) to the second region of the active layer of the second transistor through the via.
  • the eighth via holes V8 of two adjacent sub-pixels in the display substrate provided in FIGS. 5 , 8 , and 11 are the same via hole.
  • the eighth via holes V8 of two adjacent sub-pixels are the same via hole.
  • the number of via holes in the display substrate provided in FIGS. 5 , 8 , and 11 can be reduced, and the manufacturing process of the display substrate can be simplified.
  • the eighth via holes of two adjacent sub-pixels in the display substrate provided in FIG14 are different via holes, and are symmetrically arranged relative to the symmetry axis of the adjacent sub-pixels along the second direction D2.
  • the eighth via holes of two adjacent sub-pixels in the present disclosure are different via holes, which is conducive to the arrangement of the first connection line, and can realize the connection of the first connection line with the first electrode of the first transistor and the first initial signal line at the same time, and can improve the uniformity of the display substrate.
  • the fifth absolute value of the display panel provided in FIGS. 5 and 14 is
  • the plurality of via hole patterns of the insulation layer further include: a twelfth via hole V12.
  • the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the first initial connection portion of the second initial signal line on the substrate, and the twelfth via V12 is configured to connect the second initial connection portion of the second initial signal line formed subsequently to the first initial connection portion of the second initial signal line through the via.
  • the distance between a virtual straight line extending along the second direction D2 passing through the twelfth via hole of the display substrate provided in Figure 5 and a virtual straight line extending along the second direction D2 passing through the fifth via hole is greater than the distance between a virtual straight line extending along the second direction D2 passing through the twelfth via hole of the display substrate provided in Figure 14 and a virtual straight line extending along the second direction passing through the fifth via hole D2.
  • the distance between a virtual straight line extending along the first direction D1 through the twelfth via hole of the display substrate provided in Figure 5 and a virtual straight line extending along the first direction D1 through the fifth via hole is smaller than the distance between a virtual straight line extending along the first direction D1 through the twelfth via hole of the display substrate provided in Figure 14 and a virtual straight line extending along the first direction D1 through the fifth via hole D2.
  • an orthographic projection of the twelfth via hole of the display substrate provided in FIG. 5 on the substrate does not overlap with an orthographic projection of the first semiconductor layer pattern on the substrate.
  • an orthographic projection of the twelfth via hole of the display substrate provided in FIG. 14 on the substrate at least partially overlaps with an orthographic projection of the first semiconductor layer pattern on the substrate.
  • a virtual straight line extending along the second direction in the display substrate provided in FIG. 14 passes through the sixth via hole V6 and the twelfth via hole V12 .
  • FIGS. 33 to 39 wherein FIG. 33 is a plan view schematically showing the fourth conductive layer in FIGS. 5 and 8, FIG. 34 is a plan view schematically showing the fourth conductive layer in FIG. 5 after it is formed, FIG. 35 is a plan view schematically showing the fourth conductive layer in FIG. 8 after it is formed, FIG. 36 is a plan view schematically showing the fourth conductive layer in FIG. 11, FIG. 37 is a plan view schematically showing the fourth conductive layer in FIG. 11 after it is formed, FIG.
  • FIG. 38 is a plan view schematically showing the fourth conductive layer in FIG. 14, and FIG. 39 is a plan view schematically showing the fourth conductive layer in FIG. 14 after it is formed.
  • the fourth conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the fourth conductive layer may include at least: a second initial connection portion INITL2B of a second initial signal line and a first electrode T13 of a first transistor, a second electrode T14 of a first transistor, a first electrode T23 of a second transistor, a second electrode T24 of a second transistor, a second electrode T34 of a third transistor, a first electrode T43 of a fourth transistor, a first electrode T53 of a fifth transistor, a first electrode T63 of a sixth transistor, a second electrode T64 of a sixth transistor, a first electrode T73 of a seventh transistor, and a second electrode T74 of a seventh transistor located at at least one sub-pixel.
  • the first electrodes and the second electrodes of the plurality of transistors of adjacent sub-pixels are symmetrically arranged along a virtual straight line extending in the second direction D2.
  • the adjacent sub-pixels located in the same row as the sub-pixels include: a first adjacent sub-pixel and a second adjacent sub-pixel, the sub-pixel and the first electrode of the first transistor and the first electrode of the first transistor of the first adjacent sub-pixel are an integral structure, and are spaced apart from the first electrode of the first transistor of the second adjacent sub-pixel.
  • the first adjacent sub-pixel is a sub-pixel in the previous column of the sub-pixel, and the second adjacent sub-pixel is a sub-pixel in the next column of the sub-pixel.
  • the first electrode of the first transistor of the sub-pixel located in the i-th row and j-th column is an integral structure with the first electrode of the first transistor of the sub-pixel located in the i-th row and j+1 column
  • the first electrode of the first transistor of the sub-pixel located in the i-th row and j+2 column is an integral structure with the first electrode of the first transistor of the sub-pixel located in the i-th row and j+3 column
  • the first electrode of the first transistor of the sub-pixel located in the i-th row and j+1 column is spaced apart from the first electrode of the first transistor of the sub-pixel located in the i-th row and j+2 column.
  • the first electrode of the subpixel and the fifth transistor are spaced from the first electrode of the fifth transistor of the first adjacent subpixel, and are integrally structured with the first electrode of the first transistor of the second adjacent subpixel.
  • the first electrode of the fifth transistor of the subpixel located in the i-th row and j-th column is spaced from the first electrode of the fifth transistor of the subpixel located in the i-th row and j+1-th column
  • the first electrode of the fifth transistor of the subpixel located in the i-th row and j+2-th column is spaced from the first electrode of the fifth transistor of the subpixel located in the i-th row and j+3-th column
  • the first electrode of the first transistor of the subpixel located in the i-th row and j+1-th column is integrally structured.
  • the first electrode T13 of the first transistor at least partially extends along the second direction D1.
  • the first electrode T13 of the first transistor is connected to the first region of the active layer of the first transistor through the ninth via hole and is electrically connected to the first initial signal line through the eighth via hole.
  • the second electrode T14 of the first transistor and the first electrode T23 of the second transistor are an integral structure, and the shape is a line shape extending along the first direction D2.
  • the second electrode T14 of the first transistor (also the first electrode T23 of the second transistor) is connected to the first electrode plate of the capacitor through the sixth via hole, and is connected to the second region of the active layer of the first transistor (also the first region of the active layer of the second transistor) through the tenth via hole.
  • the second electrode T24 of the second transistor, the second electrode T34 of the third transistor, and the first electrode T63 of the sixth transistor are an integrated structure, and are in the shape of a line extending along the first direction D2.
  • the second electrode T24 of the second transistor (also the second electrode T34 of the third transistor and the first electrode T63 of the sixth transistor) is connected to the second region of the active layer of the third transistor (also the first region of the active layer of the sixth transistor) through the third via hole, and is connected to the second region of the active layer of the second transistor through the eleventh via hole.
  • the shape of the first electrode T43 of the fourth transistor is a line shape extending along the first direction D2.
  • the first electrode T43 of the fourth transistor is connected to the first region of the active layer of the fourth transistor through the first via hole.
  • the shape of the first electrode T53 of the fifth transistor can be an inverted "h" shape, and the first electrode T53 of the fifth transistor is connected to the first region of the active layer of the fifth transistor through the second via hole, and is electrically connected to the second electrode plate of the capacitor through the seventh via hole.
  • the shape of the second electrode T64 of the sixth transistor is a line shape extending along the second direction D2
  • the second electrode T64 of the sixth transistor is connected to the second region of the active layer of the sixth transistor (also the second region of the active layer of the sixth transistor) through a fourth via hole.
  • At least one second initial signal line in the display panel provided in Figures 5, 8, 11 and 14 includes a plurality of second initial connection portions INITL2B, wherein at least a portion of the second initial connection portion INITL2B extends along the second direction D2, and the plurality of second initial connection portions INITL2B located on the same second initial signal line are arranged in the first direction D1.
  • the orthographic projection of the second initial connection portion INITL2B on the substrate in the display panel provided in Figures 5, 8, 11 and 14 partially overlaps with the orthographic projections of the first scan signal line, the reset signal line and the first initial signal line on the substrate.
  • the second initial connection portion INITL2B of the second initial signal line is an integral structure with the first electrode T13 of the seventh transistor.
  • the second initial connection portion INITL2B of the second initial signal line (also the first electrode T13 of the seventh transistor) is connected to the first region of the active layer of the seventh transistor through a fifth via hole.
  • the fourth conductive layer in the display substrate provided in FIGS. 5 and 8 may further include: a third initial connection portion INITL2C of the second initial signal line.
  • the fourth conductive layer in the display substrate provided in FIG. 11 may further include: a plurality of first initial connection portions INITL2A and a plurality of third initial connection portions INITL2C of the second initial signal lines.
  • a display substrate is provided for FIGS. 5, 8 and 11, at least one second initial signal line includes a plurality of third initial connection portions INITL2C, and the plurality of third initial connection portions INITL2C are arranged at intervals.
  • the third initial connection portions INITL2C are arranged between portions of adjacent second initial connection portions INITL2B. At least a portion of the third initial connection portion INITL2C extends along the first direction D1, and the plurality of third initial connection portions INITL2C located on the same second initial signal line are arranged along the first direction D1.
  • a display substrate is provided for Figures 5, 8 and 11, and for the same sub-pixel, the orthographic projection of the third initial connection portion INITL2C in the second initial signal line on the substrate is located between the orthographic projection of the second scanning signal line connected to the sub-pixel on the substrate and the orthographic projection of the first scanning signal line connected to the sub-pixel on the substrate.
  • the third initial connection portion INITL2C and the second initial connection portion INITL2B are connected to each other and are an integral structure.
  • the second initial connection portion INITL2B (also the first electrode of the seventh transistor) is connected to the second initial connection portion through the twelfth via hole.
  • the second initial connection portion INITL2B is connected to one of the adjacent second initial connection portions INITL2B through a first initial connection portion located in the third conductive layer, and is connected to another adjacent second initial connection portion INITL2B through a third initial connection portion.
  • the shape of the first initial connection portion INITL2A in the display substrate provided in FIG11 is a line shape extending at least partially along the first direction D1.
  • a plurality of first initial connection portions INITL2A are arranged along the first direction D1.
  • the positive projection of the first initial connection portion INITL2A of the second initial signal line connected to the sub-pixel in the display substrate provided in Figure 11 on the substrate is located on the side of the positive projection of the first initial signal line connected to the sub-pixel on the substrate away from the positive projection of the reset signal line connected to the sub-pixel on the substrate.
  • the second initial connection portion INITL2B in the display substrate provided in Figure 11 is electrically connected to the first initial connection portion INITL2A and the third initial connection portion INITL2C, respectively, and is an integral structure.
  • the second initial connection portion INITL2B is connected to one of the adjacent second initial connection portions INITL2B through the first initial connection portion located in the third conductive layer, and is connected to the other adjacent second initial connection portion INITL2B through the third initial connection portion.
  • the fourth conductive layer in the display substrate provided in FIG. 14 may further include: a first connection line L1 and a second connection line L2 .
  • the shape of the first connection line L1 is a line shape extending at least partially along the first direction D2, and the first connection line L1 is respectively connected to the first electrodes of the first transistors of some two sub-pixels spaced apart from the first electrodes of the fifth transistor, and is an integral structure.
  • the first connection line L1 is disposed between the first electrodes of the first transistors of the two connected sub-pixels.
  • the second connection line L2 is in the shape of a line extending at least partially along the first direction D2, and the first connection line L1 is disposed between the first electrodes of the first transistors of the other two sub-pixels spaced apart from each other by the first electrodes of the fifth transistor.
  • the second connection line L2 is connected to the first initial connection portion of the second initial signal line through the twelfth via hole.
  • FIG. 40 is a plan schematic diagram of the display substrate provided in FIG. 5 after the first flat layer is formed
  • FIG. 41 is a plan schematic diagram of the display substrate provided in FIG. 8 after the first flat layer is formed
  • FIG. 42 is a plan schematic diagram of the display substrate provided in FIG. 11 after the first flat layer is formed
  • FIG. 43 is a plan schematic diagram of the display substrate provided in FIG. 14 after the first flat layer is formed.
  • the plurality of via holes in the first planar layer of the display substrate provided in FIGS. 5 and 14 include at least: thirteenth to fifteenth via holes V13 to V15 located in at least one sub-pixel.
  • the orthographic projection of the thirteenth via V13 on the substrate is located within the range of the orthographic projection of the first electrode of the fourth transistor on the substrate, the sixth insulating layer in the thirteenth via V13 is etched away to expose the surface of the first electrode of the fourth transistor, and the thirteenth via V13 is configured to connect a subsequently formed data signal line to the first electrode of the fourth transistor through the via.
  • the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the first electrode of the fifth transistor on the substrate, the sixth insulating layer in the fourteenth via V14 is etched away to expose the surface of the first electrode of the fifth transistor, and the fourteenth via V14 is configured to connect a subsequently formed first power line to the first electrode of the fifth transistor through the via.
  • the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the second electrode of the sixth transistor (also the second electrode of the seventh transistor) on the substrate, the sixth insulating layer in the fifteenth via hole V15 is etched away to expose the surface of the second electrode of the sixth transistor (also the second electrode of the seventh transistor), and the fifteenth via hole V15 is configured to connect a subsequently formed first power line to the second electrode of the sixth transistor (also the second electrode of the seventh transistor) through the via hole.
  • the plurality of via holes in the first planar layer of the display substrate provided in FIGS. 8 and 11 include at least twelfth to fourteenth via holes V12 to V14 located at at least one sub-pixel.
  • the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the first electrode of the fourth transistor on the substrate, the sixth insulating layer in the twelfth via hole V12 is etched away to expose the surface of the first electrode of the fourth transistor, and the twelfth via hole V12 is configured to connect a subsequently formed data signal line to the first electrode of the fourth transistor through the via hole.
  • the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the first electrode of the fifth transistor on the substrate, the sixth insulating layer in the thirteenth via hole V13 is etched away to expose the surface of the first electrode of the fifth transistor, and the thirteenth via hole V13 is configured to connect a subsequently formed first power line to the first electrode of the fifth transistor through the via hole.
  • the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the second electrode of the sixth transistor (also the second electrode of the seventh transistor) on the substrate, the sixth insulating layer in the fourteenth via hole V14 is etched away to expose the surface of the second electrode of the sixth transistor (also the second electrode of the seventh transistor), and the fourteenth via hole V14 is configured to connect a subsequently formed first power line to the second electrode of the sixth transistor (also the second electrode of the seventh transistor) through the via hole.
  • FIG. 44 is a plan view of the fifth conductive layer in FIGS. 5, 8, 11 and 14,
  • FIG. 45 is a plan view of the fifth conductive layer in FIG. 5
  • FIG. 46 is a plan view of the fifth conductive layer in FIG. 8
  • FIG. 47 is a plan view of the fifth conductive layer in FIG. 11,
  • FIG. 48 is a plan view of the fifth conductive layer in FIG. 14.
  • the fifth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the fifth conductive layer may include at least a data signal line DL, a first power line VDDL, a flat portion BL, and a connection electrode L located at at least one sub-pixel.
  • a plurality of data signal lines DL are arranged along the first direction D1
  • a plurality of first power lines VDDL are arranged along the first direction D1.
  • the data signal line DL may be in the shape of a line extending at least partially along the second direction D2.
  • the first power line VDDL may be in the shape of a line extending at least partially along the second direction D2.
  • the first power line VDDL connected to the sub-pixel is located on a side of the data signal line DL connected to the sub-pixel close to the next column of sub-pixels.
  • adjacent data signal lines DL are symmetrical with respect to a virtual straight line extending in the second direction D2.
  • Adjacent first power lines VDD are symmetrical with respect to a virtual straight line extending in the second direction D2.
  • the data signal line DL and the first power line VDDL connected to the subpixel are located on the same side of the connection electrode of the subpixel, and the data signal line DL is located on a side of the first power line VDDL away from the connection electrode.
  • the first power line VDDL is connected to one of the adjacent power lines and is spaced apart from another adjacent power line.
  • Two data signal lines DL are disposed between the two spaced apart first power lines.
  • the first power lines connected to adjacent sub-pixels may be spaced apart, and the spaced apart first power lines may be mirror-symmetrical about the first connection line L1 or the second connection line L2.
  • the flat portion BL is disposed between two adjacent first power lines VDDL and is connected to the adjacent two first power lines VDDL.
  • the shape of the flat portion BL may be a square.
  • orthographic projections of the flat portion BL on the substrate may at least partially overlap orthographic projections of the channel regions of the active layers of the first transistor and the second transistor on the substrate.
  • an orthographic projection of the flat portion BL on the substrate at least partially overlaps with orthographic projections of the second scan signal line, the first scan signal line, and the first preliminary signal line on the substrate.
  • a structure consisting of a first power line connecting two adjacent columns of sub-pixels and two flat portions of adjacent rows of sub-pixels includes a plurality of annular regions.
  • the structure of the annular region may be a symmetrical structure or an asymmetrical structure.
  • FIGS. 44 to 48 illustrate the case where the structure of the annular region is a symmetrical structure.
  • adjacent flat portions in the same row may be arranged symmetrically or asymmetrically, which may be determined according to the shape of the first electrode of the connected light emitting device.
  • FIGS. 44 to 48 illustrate that adjacent flat portions in the same row may be arranged symmetrically.
  • the orthographic projection of the first initial connection portion on the substrate is located within the annular area formed by the first power lines of two adjacent columns of sub-pixels and two flat portions of adjacent sub-pixel rows.
  • the shape of the connection electrode L may be a line shape at least partially along the second direction D2 or a line shape extending along the first direction D1.
  • the connection electrode is configured to be connected to the first electrode of the light emitting device formed subsequently.
  • the shape of the connection electrode connected to the first electrode of different light emitting devices may be different.
  • the data signal line DL is connected to the fourth through-hole through the thirteenth through-hole.
  • the first power line VDDL is connected to the first electrode of the fifth transistor through the fourteenth via hole, and the connection electrode L is connected to the second electrode of the sixth transistor (also the second electrode of the seventh transistor) through the fifteenth via hole.
  • the data signal line DL is electrically connected to the first electrode of the fourth transistor through the twelfth via hole.
  • the first power line VDDL is connected to the first electrode of the fifth transistor through the thirteenth via hole, and the connection electrode L is connected to the second electrode of the sixth transistor (also the second electrode of the seventh transistor) through the fourteenth via hole.
  • FIGS. 49 to 52 wherein FIG. 49 is a plan schematic diagram of the display substrate provided in FIG. 5 after the second flat layer is formed thereon, FIG. 50 is a plan schematic diagram of the display substrate provided in FIG. 8 after the second flat layer is formed thereon, FIG. 51 is a plan schematic diagram of the display substrate provided in FIG. 11 after the second flat layer is formed thereon, and FIG. 52 is a plan schematic diagram of the display substrate provided in FIG. 14 after the second flat layer is formed thereon.
  • the plurality of via holes in the second planar layer of the display substrate provided in FIGS. 5 and 14 include at least a sixteenth via hole V16 located at at least one sub-pixel.
  • the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the connecting electrode on the substrate, exposing the surface of the connecting electrode, and the sixteenth via hole V16 is configured to connect the first electrode of the subsequently formed light-emitting device to the connecting electrode through the via hole.
  • the plurality of via holes in the second planar layer of the display substrate provided in FIG. 8 includes at least a fifteenth via hole V15 and a sixteenth via hole V16 located at at least one sub-pixel.
  • the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the connecting electrode on the substrate, exposing the surface of the connecting electrode, and the fifteenth via hole V15 is configured to connect the first electrode of the subsequently formed light-emitting device to the connecting electrode through the via hole.
  • the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the second initial connection portion of the second initial signal line on the substrate, exposing the surface of the second initial connection portion of the second initial signal line, and the sixth insulating layer in the sixteenth via hole V16 is etched away, and the sixteenth via hole V16 is configured to connect the first initial connection portion of the second initial signal line formed subsequently to the second initial connection portion of the second initial signal line through the via hole.
  • the plurality of via holes in the second planar layer of the display substrate provided in FIG. 11 includes at least a fifteenth via hole V15 located at at least one sub-pixel.
  • the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the connecting electrode on the substrate, exposing the surface of the connecting electrode, and the fifteenth via hole V15 is configured to connect the first electrode of the subsequently formed light-emitting device to the connecting electrode through the via hole.
  • the drive circuit layer is prepared on the substrate.
  • the drive circuit layer may include a plurality of pixel circuits, and the pixel circuits are connected to the first scan signal line, the second scan signal line, the light emitting signal line, the first initial signal line, the second initial signal line, the reset signal line, the data signal line and the first power supply line.
  • the drive circuit layer may be arranged on the substrate.
  • the drive circuit layer may include a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a second semiconductor layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a fourth conductive layer, a sixth insulating layer, a first planar layer, a fifth conductive layer and a second planar layer sequentially arranged on the substrate.
  • the first semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer.
  • the second semiconductor layer may be a metal oxide layer.
  • the metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing silicon, indium and tin.
  • the metal oxide layer may be a single layer, a double layer, or a multilayer.
  • the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.
  • the first planarization layer and the second planarization layer may employ an organic material such as resin or the like.
  • a light emitting structure layer is prepared on the driving circuit layer.
  • the preparation process of the light emitting structure layer may include the following operations.
  • forming the sixth conductive layer pattern may include: depositing a sixth conductive film on the substrate on which the aforementioned pattern is formed, patterning the sixth conductive film using a patterning process to form a sixth conductive layer disposed on the second flat layer, wherein the sixth conductive layer includes at least a plurality of first electrode patterns, as shown in FIGS. 53 to 59, wherein FIG. 53 is a plan view schematically showing the sixth conductive layer in FIGS. 5 and 11, FIG. 54 is a plan view schematically showing the sixth conductive layer in FIG. 5 after it is formed, FIG. 55 is a plan view schematically showing the sixth conductive layer in FIG. 11 after it is formed, FIG.
  • FIG. 56 is a plan view schematically showing the sixth conductive layer in FIG. 8
  • FIG. 57 is a plan view schematically showing the sixth conductive layer in FIG. 8 after it is formed
  • FIG. 58 is a plan view schematically showing the sixth conductive layer in FIG. 14
  • FIG. 59 is a plan view schematically showing the sixth conductive layer in FIG. 14 after it is formed.
  • the sixth conductive layer in the display panel of FIGS. 5, 8, 11 and 14 may include: a plurality of first electrode patterns.
  • the plurality of first electrode patterns may include a first electrode AL1 of a first light emitting device, a first electrode AL2 of a second light emitting device, a first electrode AL3 of a third light emitting device and a first electrode AL4 of a fourth light emitting device, the first electrode AL1 of the first light emitting device being located at a red sub-pixel emitting red light, the first electrode AL2 of the second light emitting device being located at a blue sub-pixel emitting blue light, the first electrode AL3 of the third light emitting device being located at a first green sub-pixel emitting green light, and the first electrode AL4 of the fourth light emitting device being located at a second green sub-pixel emitting green light.
  • the first electrode AL1 of the first light emitting device and the first electrode AL2 of the second light emitting device may be alternately disposed along the second direction D1
  • the first electrode AL3 of the third light emitting device and the first electrode AL4 of the fourth light emitting device may be alternately disposed along the second direction D1.
  • the first electrode AL1 of the first light emitting device and the first electrode AL2 of the second light emitting device may be alternately disposed along the first direction D2
  • the first electrode AL3 of the third light emitting device and the first electrode AL4 of the fourth light emitting device may be alternately disposed along the first direction D2.
  • the first electrode AL1 of the first light-emitting device, the first electrode AL2 of the second light-emitting device, the first electrode AL3 of the third light-emitting device, and the first electrode AL4 of the fourth light-emitting device can be respectively connected to the connecting electrode of the sub-pixel through the via hole that exposes the connecting electrode of the sub-pixel.
  • the first electrode of the light-emitting device in the display substrate provided in FIG. 5 is electrically connected to the connecting electrode through the sixteenth via hole.
  • the first electrode of the light-emitting device of the display substrate provided in FIG. 11 is connected to the connecting electrode through the fifteenth via hole.
  • FIG. 54 the first electrode of the light-emitting device in the display substrate provided in FIG. 5 is electrically connected to the connecting electrode through the sixteenth via hole.
  • the first electrode of the light-emitting device of the display substrate provided in FIG. 11 is connected to the connecting electrode through the fifteenth via hole.
  • the first electrode of the light-emitting device of the display substrate provided in FIG. 8 is connected to the connecting electrode through the fifteenth via hole.
  • the first electrode of the light-emitting device of the display substrate provided in FIG. 14 is connected to the connecting electrode through the sixteenth via hole.
  • the shapes and areas of the first electrodes of the four sub-pixels in one pixel unit may be the same, or may be different.
  • At least one of the first electrode AL1 of the first light emitting device, the first electrode AL2 of the second light emitting device, the first electrode AL3 of the third light emitting device, and the first electrode AL4 of the fourth light emitting device may include the same
  • the anode main body and the anode connecting portion are connected to each other, and the anode connecting portion is connected to the connecting electrode.
  • the first electrode AL1 of the first light emitting device may include a first anode body and a first anode connection part connected to each other, the shape of the first anode body may be rectangular, the corner of the rectangular shape may be provided with an arc-shaped chamfer, and the shape of the first anode connection part may be a strip shape.
  • the first electrode AL2 of the second light emitting device may include a second anode body and a second anode connection part connected to each other, the shape of the second anode body may be rectangular, the corner of the rectangular shape may be provided with an arc-shaped chamfer, and the shape of the second anode connection part may be a strip shape.
  • the first electrode AL3 of the third light emitting device may include a third anode body and a third anode connection part connected to each other, the shape of the third anode body may be rectangular, the corner of the rectangular shape may be provided with an arc-shaped chamfer, and the shape of the third anode connection part may be a strip shape.
  • the first electrode AL4 of the fourth light emitting device may include a fourth anode body and a fourth anode connection part connected to each other, the shape of the fourth anode body may be rectangular, the corner of the rectangular shape may be provided with an arc-shaped chamfer, and the shape of the fourth anode connection part may be a strip shape.
  • the sixth conductive layer in the display substrate provided in Figure 8 may further include: a plurality of first initial connection portions INITL2A of at least one second initial signal line.
  • the second initial connection portion INITL2A extends along the first direction D1, and the plurality of first initial connection portions INITL2A are arranged along the first direction D1.
  • an orthographic projection of the first initial connection portion INITL2A of the second initial signal line on the substrate at least partially overlaps an orthographic projection of the second initial connection portion on the substrate.
  • the positive projection of the first initial connection portion INITL2A of the second initial signal line connected to the sub-pixel on the substrate is located on a side of the positive projection of the first initial signal line connected to the sub-pixel on the substrate away from the positive projection of the reset signal line connected to the sub-pixel on the substrate.
  • a minimum distance between the second preliminary connection portion and the first electrode of the adjacent light emitting device may be about 1 micrometer to 3 micrometers.
  • a minimum distance between the second preliminary connection portion and the first electrode of the adjacent light emitting device may be about 2 micrometers.
  • the first initial connection portion INITL2A of the second initial signal line is connected to the second initial connection portion through a sixteenth via hole.
  • the sixth conductive layer has a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO/Ag/ITO.
  • Forming a cathode conductive layer pattern may include: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, depositing a pixel definition film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition film through a patterning process to form a pixel definition layer pattern exposing the sixth conductive layer pattern, coating an organic light-emitting material on the substrate on which the pixel definition layer pattern is formed, patterning the organic light-emitting material through a patterning process to form an organic structure layer pattern, depositing a cathode conductive film on the substrate on which the organic material layer pattern is formed, and patterning the cathode conductive film through a patterning process to form a cathode conductive layer.
  • the subsequent preparation process may include: forming a packaging structure layer on the cathode conductive layer, the packaging structure layer may include a stacked first packaging layer, a second packaging layer and a third packaging layer, the first packaging layer and the third packaging layer may be made of inorganic materials, the second packaging layer may be made of organic materials, and the second packaging layer is arranged between the first packaging layer and the third packaging layer, which can ensure that external water vapor cannot enter the light-emitting structure layer.
  • the organic structure layer may include at least: an organic light emitting layer of a light emitting device.
  • the cathode conductive layer may include at least: cathodes of a plurality of light emitting devices.
  • the cathode layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or a conductive alloy material thereof, such as aluminum neodymium alloy (AlNd) or molybdenum.
  • Niobium alloy (MoNb) may be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum and titanium.
  • the display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.
  • the embodiment of the present disclosure further provides a display device, including: a display substrate.
  • the display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.
  • the display device can be: a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • AMOLED active-matrix organic light emitting diode
  • the thickness and size of the layer or microstructure are exaggerated. It is understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, the element may be “directly” “on” or “under” the other element, or there may be intermediate elements.

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Abstract

一种显示基板和显示装置，其中，显示基板包括：基底(10)以及设置在基底(10)上的多个子像素以及多条复位信号线(RL)和多条第二初始信号线(INITL2)，子像素包括：像素电路和发光器件(L)，发光器件(L)包括第一电极，像素电路包括：第一晶体管(T1)，复位信号线(RL)至少部分沿第一方向(D1)延伸，至少一条第二初始信号线包括：沿第一方向(D1)延伸的第一初始连接部(INITL2A)和沿第二方向(D2)延伸的第二初始连接部(INITL2B)；第一初始连接部(INITL2A)在基底(10)上的正投影与复位信号线(RL)在基底(10)上的正投影不交叠，第二初始连接部(INITL2B)在基底(10)上的正投影与复位信号线(RL)在基底(10)上的正投影部分交叠。

Description

显示基板和显示装置 技术领域
本公开涉及但不限于显示技术领域，具体涉及一种显示基板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种显示基板，包括：基底和设置在所述基底上的多个子像素、多条复位信号线和多条第二初始信号线，所述子像素分别与复位信号线和第二初始信号线电连接，所述子像素包括：像素电路和发光器件，所述发光器件包括第一电极，所述像素电路包括：第一晶体管，所述复位信号线被配置为向第一晶体管的栅电极提供控制信号，所述第二初始信号线被配置为向发光器件的第一电极提供初始信号；
所述复位信号线至少部分沿第一方向延伸，至少一条所述第二初始信号线包括：沿第一方向延伸的第一初始连接部和沿第二方向延伸的第二初始连接部，所述第二方向与所述第一方向相交；
所述第一初始连接部在基底上的正投影与所述复位信号线在基底上的正投影不交叠，所述第二初始连接部在基底上的正投影与所述复位信号线在基底上的正投影部分交叠。
在示例性实施方式中，还包括：设置在所述基底上的多条发光信号线，所述发光信号线至少部分沿所述第一方向延伸；
子像素所连接的所述第二初始信号线中的第一初始连接部在基底上的正投影位于子像素所连接的所述复位信号线在基底上的正投影与子像素所连接的所述发光信号线在基底上的正投影之间。
在示例性实施方式中，所述第一初始连接部与所述第二初始连接部同层设置，且与所述第二初始连接部为一体结构。
在示例性实施方式中，所述第一初始连接部与第二初始连接部异层设置，所述第二初始连接部通过过孔与第一初始连接部连接。
在示例性实施方式中，所述复位信号线包括：异层设置，且相互连接的第一子复位信号线和第二子复位信号线；
所述第一初始连接部位于所述第二初始连接部靠近所述基底的一侧，且与所述第一子复位信号线或者所述第二子复位信号线同层设置。
在示例性实施方式中，所述第一初始连接部位于所述第二初始连接部远离基底的一侧， 且与所述第一电极同层设置。
在示例性实施方式中，所述第一初始连接部与相邻的发光器件的第一电极之间的最小距离约为1微米至3微米。
在示例性实施方式中，还包括：设置在所述基底上的多条第一扫描信号线和多条第一初始信号线，所述第一扫描信号线和所述第一初始信号线中的任一条至少部分沿所述第一方向延伸；
至少一条所述第二初始连接线包括：多个第二初始连接部，且多个所述第二初始连接部沿第一方向排布；
所述第二初始连接部在所述基底上的正投影还与所述第一扫描信号线和所述第一初始信号线在所述基底上的正投影部分交叠。
在示例性实施方式中，至少一条所述第二初始信号线还包括：多个第一初始连接部和多个沿所述第一方向延伸的第三初始连接部；多个所述第一初始连接部沿所述第一方向排布，多个所述第三初始连接部沿所述第一方向排布；
相邻两个第二初始连接部通过第一初始连接部或者第三初始连接部连接，第二初始连接部与其中一个相邻的第二初始连接部通过第一初始连接部连接，第二初始连接部与另一个相邻的第二初始连接部通过第三初始连接部连接。
在示例性实施方式中，子像素所连接的所述第二初始信号线的所述第三初始连接部在基底上的正投影位于子像素所连接的所述第一扫描信号线在基底上的正投影远离子像素所连接的所述复位信号线在基底上的正投影的一侧。
在示例性实施方式中，所述第二初始连接部和所述第三初始连接部同层设置，且为一体结构；
所述第二初始连接部位于所述复位信号线所在的膜层和所述第一电源线所在的膜层之间。
在示例性实施方式中，至少一条所述第二初始信号线包括：一个第一初始连接部和多个第二初始连接部，多个所述第二初始连接部与所述第一初始连接部连接。
在示例性实施方式中，还包括：至少部分沿所述第二方向延伸的多条第一连接线；所述第一连接线与所述第二初始连接部同层设置；
至少一条所述第一连接线与多条所述第一初始信号线连接。
在示例性实施方式中，还包括：至少部分沿所述第二方向延伸的第二连接线；所述第二连接线与所述第二初始连接部同层设置；
至少一条所述第二连接线与多条所述第二初始信号线的所述第一初始连接部连接。
在示例性实施方式中，还包括：平坦部和多条第二扫描信号线；所述像素电路还包括：第二晶体管，所述第一晶体管和所述第二晶体管为氧化物晶体管，所述第二扫描信号线至少部分沿所述第一方向延伸，且被配置为向所述第二晶体管的栅电极提供控制信号；
所述平坦部与所述第一电源线同层设置，且相互连接；所述平坦部在基底上的正投影与第一晶体管的有源层、第二晶体管的有源层和至少一个发光器件的第一电极在基底上的正投影至少部分交叠。
第二方面，本公开还提供了一种显示基板，包括：基底和设置在所述基底上的多个子像素、多条复位信号线和多条第二初始信号线，所述子像素分别与复位信号线和第二初始信号线电连接，所述子像素包括：像素电路和发光器件，所述发光器件包括第一电极，所 述像素电路包括：第一晶体管，所述复位信号线被配置为向第一晶体管的栅电极提供控制信号，所述第二初始信号线被配置为向发光器件的第一电极提供初始信号；
所述复位信号线至少部分沿第一方向延伸，至少一条所述第二初始信号线包括：沿第一方向延伸的第一初始连接部和第三初始连接部以及沿第二方向延伸的第二初始连接部，所述第二方向与所述第一方向相交；
所述第三初始连接部在基底上的正投影与所述复位信号线在基底上的正投影之间的距离小于所述第三初始连接部在基底上的正投影与所述第一初始连接部在基底上的正投影之间的距离。
第三方面，本公开还提供了一种显示装置，包括：上述显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示基板的平面结构示意图；
图3为另一显示基板的平面结构示意图；
图4A为一种像素电路的等效电路示意图；
图4B为图4A提供的像素电路的工作时序图；
图5为本公开实施例提供的显示结构的结构示意图一；
图6为图5提供的显示基板中部分膜层的示意图；
图7为图5提供的显示基板的截面图；
图8为本公开实施例提供的显示结构的结构示意图二；
图9为图8提供的显示基板部分膜层的示意图；
图10为图8提供的显示基板的截面图；
图11为本公开实施例提供的显示结构的结构示意图三；
图12为图11提供的显示基板部分膜层的示意图；
图13为图11提供的显示基板的截面图；
图14为本公开实施例提供的显示结构的结构示意图四；
图15为图14提供的显示基板部分膜层的示意图；
图16为图14提供的显示基板的截面图；
图17为图5、图8、图11和图14中第一半导体层的平面示意图；
图18为图5、图8、图11和图14中第一导电层的平面示意图；
图19为图5、图8、图11和图14形成第一导电层后的平面示意图；
图20为图5、图8、图11和图14中第二导电层的平面示意图；
图21为图5、图8、图11和图14形成第二导电层后的平面示意图；
图22为图5、图8、图11和图14中第二半导体层的平面示意图；
图23为图5、图8、图11和图14形成第二半导体层后的平面示意图；
图24为图5中第三导电层的平面示意图；
图25为图5形成第三导电层后的平面示意图；
图26为图8和图11中第三导电层的平面示意图；
图27为图8和图11形成第三导电层后的平面示意图；
图28为图14中第三导电层的平面示意图；
图29为图14形成第三导电层后的平面示意图；
图30为图5形成第五绝缘层后的平面示意图；
图31为图8和图11形成第五绝缘层后的平面示意图；
图32为图14形成第五绝缘层后的平面示意图；
图33为图5和图8中第四导电层的平面示意图；
图34为图5形成第四导电层后的平面示意图；
图35为图8形成第四导电层后的平面示意图；
图36为图11中第四导电层的平面示意图；
图37为图11形成第四导电层后的平面示意图；
图38为图14中第四导电层的平面示意图；
图39为图14形成第四导电层后的平面示意图；
图40为图5提供的显示基板形成第一平坦层后的平面示意图；
图41为图8提供的显示基板形成第一平坦层后的平面示意图；
图42为图11提供的显示基板形成第一平坦层后的平面示意图；
图43为图14提供的显示基板形成第一平坦层后的平面示意图；
图44为图5、图8、图11和图14中第五导电层的平面示意图；
图45为图5形成第五导电层后的平面示意图；
图46为图8形成第五导电层后的平面示意图；
图47为图11形成第五导电层后的平面示意图；
图48为图14形成第五导电层后的平面示意图；
图49为图5提供的显示基板形成第二平坦层后的平面示意图；
图50为图8提供的显示基板形成第二平坦层后的平面示意图；
图51为图11提供的显示基板形成第二平坦层后的平面示意图；
图52为图14提供的显示基板形成第二平坦层后的平面示意图；
图53为图5和图11中第六导电层的平面示意图；
图54为图5形成第六导电层后的平面示意图；
图55为图11形成第六导电层后的平面示意图；
图56为图8中第六导电层的平面示意图；
图57为图8形成第六导电层后的平面示意图；
图58为图14中第六导电层的平面示意图；
图59为图14形成第六导电层后的平面示意图。
详述
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
在本说明书中，所采用的“同层设置”是指两种(或两种以上)结构通过同一次图案化工艺得以图案化而形成的结构，它们的材料可以相同或不同。例如，形成同层设置的多种结构的前驱体的材料是相同的，最终形成的材料可以相同或不同。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
显示基板中所用的是低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)技术，LTPS技术拥有高分辨率、高反应速度、高亮度、高开口率等优势。尽管受到了市场欢迎，但LTPS技术也存在一些缺陷，如生产成本较高，所需功耗较大等，此时，低温多晶硅晶体管与氧化物晶体管结合形成的背板(Low Temperature Poly-Silicon+Oxide，简称LTPO)技术方案应运而生。相比于LTPS技术，LTPO技术的漏电流更小，像素点反应更快，显示基板多加了一层氧化物，降低了激发像素点所需的能耗，从而降低屏幕显示时的功耗。采用LTPO技术的显示产品中不同像素电路中的驱动晶体管的老化程度不同，且显示基板无法对驱动晶体管的阈值电压进行监控，降低了显示基板的显示效果、使用寿命和可靠性。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括像素电路，像素电路可以分别与扫描信号线、发光信号线和数据信号线连接。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生 发射信号，o可以是自然数。
图2为一种显示基板的平面结构示意图，图3为另一显示基板的平面结构示意图。如图2和图3所示，显示基板可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和至少一个出射第三颜色光线的第三子像素P3，第一子像素P1、第二子像素P2和第三子像素P3均包括像素电路和发光器件。第一子像素P1、第二子像素P2和第三子像素P3中的像素电路分别与扫描信号线、数据信号线和发光信号线连接，像素电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向所述发光器件输出相应的电流。第一子像素P1、第二子像素P2和第三子像素P3中的发光器件分别与所在子像素的像素电路连接，发光器件被配置为响应所在子像素的像素电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形，三个子像素可以采用水平并列、竖直并列或品字方式排列，本公开在此不做限定。
在示例性实施方式中，如图2所示，一个像素单元可以包括三个子像素，三个子像素可以采用水平并列、竖直并列或品字方式等排列，本公开在此不做限定。图2是以水平并列方式排列为例进行说明的。
在示例性实施方式中，如图3所示，一个像素单元可以包括四个子像素，四个子像素可以为一个第一子像素、一个第二子像素和两个第三子像素。四个子像素可以采用水平并列、竖直并列或正方形等方式排列，本公开在此不做限定。图3是以四个子像素正方形方式排列为例进行说明的。
在示例性实施方式中，发光器件可以是有机电致发光二极管(OLED)，包括叠设的一电极(阳极)、有机发光层和第二电极(阴极)。
在示例性实施方式中，有机发光层可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在示例性实施方式中，所有子像素的空穴注入层可以是连接在一起的共通层，所有子像素的电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层可以是连接在一起的共通层，所有子像素的电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，相邻子像素的电子阻挡层可以有少量的交叠，或者可以是隔离的。
图4A为一种像素电路的等效电路示意图。在示例性实施方式中，像素电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。如图4A所示，像素电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)和1个电容C。
如图4A所示，第一晶体管T1的栅电极与复位信号端Reset电连接，第一晶体管T1的第一极与第一初始信号端Vinit1电连接，第一晶体管T1的第二极与第一节点N1电连接；第二晶体管T2的栅电极与第二扫描信号端Gate2电连接，第二晶体管T2的第一极与第一节点N1电连接，第二晶体管T2的第二极与第三节点N3电连接；第三晶体管T3 的栅电极与第一节点N1电连接，第三晶体管T3的第一极与第二节点N2电连接，第三晶体管T3的第二极与第三节点N3电连接；第四晶体管T4的栅电极与第一扫描信号端Gate1电连接，第四晶体管T4的第一极与数据信号端Data电连接，第四晶体管T4的第二极与第二节点N2电连接；第五晶体管T5的栅电极与发光信号端EM电连接，第五晶体管T5的第一极与第一电源端VDD电连接，第五晶体管T5的第二极与第二节点N2电连接；第六晶体管T6的栅电极与发光信号端EM电连接，第六晶体管T6的第一极与第三节点N3电连接，第六晶体管T6的第二极与第四节点N4电连接；第七晶体管T7的栅电极与第一扫描信号端Gate1电连接，第七晶体管T7的第一极与第二初始信号端Vinit2电连接，第七晶体管T7的第二极与第四节点N4电连接；电容C的第一极板C1与第一节点N1电连接，电容C的第二极板C2与第一电源端VDD电连接。
在示例性实施方式中，第一晶体管T1可以称为节点复位晶体管，当复位信号端Reset的信号为有效电平信号时，将第一初始信号端Vinit1的初始信号写入第一节点N1。
在示例性实施方式中，第二晶体管T2可以称为补偿晶体管，当第二扫描信号端Gate2的信号为有效电平信号时，将第三节点N3的信号写入第一节点N1，以对第一节点N1的信号进行补偿。
在示例性实施方式中，第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其栅电极与第一极之间的电位差来确定在第一电源端VDD与第二电源端VSS之间流经的驱动电流。
在示例性实施方式中，第四晶体管T4可以称为写入晶体管，当第一扫描信号端Gate1的信号为有效电平信号时，将数据信号端Data的初始信号写入第二节点N2。
在示例性实施方式中，第五晶体管T5和第六晶体管T6可以称为发光晶体管。当发光信号端EM的信号为有效电平信号时，第五晶体管T5和第六晶体管T6通过在第一电源端VDD与第二电源端VSS之间形成驱动电流路径而使发光器件发光。
在示例性实施方式中，第七晶体管T7可以称为阳极复位晶体管，当第一扫描信号端Gate1的信号为有效电平信号时，将第二初始信号端Vinit2的初始信号写入发光器件L的第一电极。
按照晶体管的特性区分可以将晶体管分为N型晶体管和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)，关闭电压为高电平电压(例如，5V、10V或其它合适的电压)。当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其它合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成LTPO显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在示例性实施方式中，第一晶体管T1和第二晶体管T2与第三晶体管T3至第七晶体管T7的晶体管类型相反。示例性地，第一晶体管T1和第二晶体管T2可以为N型晶体管，第三晶体管T3至第七晶体管T7可以为P型晶体管。
在示例性实施方式中，第一晶体管T1和第二晶体管T2可以为氧化物晶体管，第三 晶体管T3至第七晶体管T7可以为低温多晶硅晶体管。
在示例性实施方式中，第一初始信号端Vinit1的信号的电压值恒定，且为直流信号，第一初始信号端Vinit1的信号的电压值可以为-3V。
在示例性实施方式中，第二初始信号端Vinit2的信号的电压值恒定，且为直流信号，第二初始信号端Vinit2的信号的电压值可以为0V。
在示例性实施方式中，发光器件L，可以分别与第四节点N4和第二电源端VSS电连接。
在示例性实施方式中，第一电源端VDD持续提供高电平信号，第二电源端VSS持续提供低电平信号。
图4B为图4A提供的像素电路的工作时序图。下面通过图4A示例的像素电路在显示阶段的工作过程说明本公开示例性实施例。图4B是以第一晶体管T1和第二晶体管T2为N型晶体管，第三晶体管T3至第七晶体管T7为P型晶体管为例进行说明的，图4B中的像素电路包括第一晶体管T1到第七晶体管T7、1个电容C和8个信号端(数据信号端Data、第一扫描信号端Gate1、第二扫描信号端Gate2、复位信号端Reset、第一初始信号端Vinit1、第二初始信号端Vinit2、发光信号端EM和第一电源端VDD)。
结合图4A和图4B，像素电路的工作过程可以包括：
第一阶段P1，称为初始化阶段，复位信号端Reset的信号为高电平信号，第一晶体管T1导通，第一初始信号端Vinit1的信号通过导通的第一晶体管T1写入第一节点N1，对第一节点N1进行初始化(复位)，清空其内部的预存电压，完成初始化。
第二阶段P2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号端Gate1为低电平信号，第二扫描信号端Gate2为低电平信号，数据信号端Data输出数据电压。此阶段由于第一节点N1为低电平信号，因此第三晶体管T3导通。第一扫描信号端Gate1的信号为低电平信号，第四晶体管T4导通和第七晶体管T7导通，第二扫描信号端Gate2的信号为高电平信号，第二晶体管T2导通，数据信号端Data输出的数据电压经过导通的第四晶体管T4、第二节点N2、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第一节点N1，并将数据信号端Data输出的数据电压与第三晶体管T3的阈值电压之差充入电容C，直至第一节点N1的电压为Vd-|Vth|，Vd为数据信号端Data输出的数据电压，Vth为第三晶体管T3的阈值电压，第七晶体管T7导通，第二初始信号端Vinit2的信号通过导通的第七晶体管T7写入第四节点N4，对发光器件L的第一电极进行初始化(复位)，清空其内部的预存电压，完成初始化。
第三阶段P3，称为发光阶段，发光信号端EM的信号为低电平信号，第五晶体管T5和第六晶体管T6导通，第一电源端VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向发光器件L的第一极提供驱动电压，驱动发光器件L发光。
在像素电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由栅电极和第一极之间的电压差决定。由于第一节点N1的电压为Vd-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth)2＝K*[(Vdd-Vd+|Vth|)-Vth]2＝K*[(Vdd-Vd]2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号端Data输出的数据电压，Vdd为第一电源端VDD输出的电源电压。
在一种LTPO显示基板中，在电路设计中向像素电路的第二初始信号端提供初始信号的信号线跨设在向像素电路的复位信号端提供控制信号的信号线上。向像素电路的复位信号端提供控制信号的信号线在制作过程中会产生颗粒等异物凸起。由于向像素电路的第二初始信号端提供初始信号的信号线与在向像素电路的复位信号端提供控制信号的信号线交叠区域较大，使得向像素电路的复位信号端提供控制信号的信号线产生的凸起可能会与向像素电路的第二初始信号线提供初始信号的信号线之间短接，从而引发显示不良。
图5为本公开实施例提供的显示结构的结构示意图一，图6为图5提供的显示基板中部分膜层的示意图，图7为图5提供的显示基板的截面图，图8为本公开实施例提供的显示结构的结构示意图二，图9为图8提供的显示基板部分膜层的示意图，图10为图8提供的显示基板的截面图，图11为本公开实施例提供的显示结构的结构示意图三，图12为图11提供的显示基板部分膜层的示意图，图13为图11提供的显示基板的截面图，图14为本公开实施例提供的显示结构的结构示意图四，图15为图14提供的显示基板部分膜层的示意图，图16为图14提供的显示基板的截面图，如图5至图16所示，本公开实施例提供的显示基板可以包括：基底10、设置在基底10上的多个子像素、多条复位信号线RL和多条第二初始信号线INITL2，子像素分别与复位信号线RL和第二初始信号线INITL2电连接，子像素包括：像素电路，像素电路包括：像素电路和发光器件，发光器件包括第一电极，像素电路包括：第一晶体管，复位信号线RL被配置为向第一晶体管的栅电极提供控制信号，第二初始信号线INITL2被配置为向发光器件的第一电极提供初始信号。
在示例性实施方式中，如图5、图8、图11和图14所示，复位信号线RL至少部分沿第一方向D1延伸，至少一条第二初始信号线INITL2包括：沿第一方向延伸的第一初始连接部INITL2A和沿第二方向D2延伸的第二初始连接部INITL2B，第二方向D2与第一方向D1相交；第一初始连接部INITL2A在基底上的正投影与复位信号线RL在基底上的正投影不交叠，所述第二初始连接部INITL2B在基底上的正投影与复位信号线RL在基底上的正投影部分交叠。在示例性实施方式中，如图5、图8、图11和图14是以两行四列子像素为例进行说明的，两行分别是第i行和第i+1行，四列分别是第j列至第j+3列。
在示例性实施方式中，复位信号线RL可以为双层结构。
在示例性实施方式中，显示基板可以为LTPO显示基板。
在示例性实施方式中，基底可以为刚性基底或柔性基底，其中，刚性基底可以为但不限于玻璃、导电箔片中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
本公开实施例提供的显示基板包括：基底、设置在基底上的多个子像素、多条复位信号线和多条第二初始信号线，子像素分别与复位信号线和第二初始信号线电连接，子像素包括：像素电路和发光器件，发光器件包括第一电极，像素电路包括：第一晶体管，复位信号线被配置为向第一晶体管的栅电极提供控制信号，第二初始信号线被配置为向发光器件的第一电极提供初始信号；复位信号线至少部分沿第一方向延伸，至少一条第二初始信号线包括：沿第一方向延伸的第一初始连接部和沿第二方向延伸的第二初始连接部，第二方向与第一方向相交；第一初始连接部在基底上的正投影与复位信号线在基底上的正投影不交叠，第二初始连接部在基底上的正投影与复位信号线在基底上的正投影部分交叠。。本公开通过第二初始信号线中的第一初始连接部在基底上的正投影与复位信号线在基底上的正投影不交叠，第二初始连接部在基底上的正投影与复位信号线在基底上的正投影部 分交叠可以减少第二初始信号线与复位信号线之间的交叠区域的面积，合理利用布线空间，有效防止工艺过程中的短路现象发生，提升显示基板的显示效果。
在示例性实施方式中，发光器件可以包括：第一发光器件、第二发光器件、第三发光器件和第四发光器件，第一发光器件发红光，第二发光器件发蓝光，第三发光器件和第四发光器件发绿光。
在示例性实施方式中，如图5、图8、图11和图14所示，第二发光器件的第一电极AL2的面积大于第一发光器件的第一电极AL1的面积，第三发光器件的第一电极AL3与第四发光器件的第一电极AL4的面积小于第一发光器件的第一电极AL1的面积。
在示例性实施方式中，如图5至图16所示，显示基板还可以包括：设置在基底上的多条第一初始信号线INITL1、多条第一扫描信号线GL1、多条第二扫描信号线GL2、多条发光信号线EL、多条数据信号线DL和多条第一电源线VDDL，子像素分别与第一初始信号线INITL1、第一扫描信号线GL1、第二扫描信号线GL2、发光信号线EL、数据信号线DL和第一电源线VDDL电连接。
在示例性实施方式中，像素电路可以包括：第二晶体管(也是补偿晶体管)、第四晶体管(也是写入晶体管)和第七晶体管(也是阳极复位晶体管)，第二晶体管(也是补偿晶体管)和第四晶体管(也是写入晶体管)类型不同，第一晶体管(也是节点复位晶体管)和第二晶体管(也是补偿晶体管)的晶体管类型相同，第四晶体管(也是写入晶体管)和第七晶体管(也是阳极复位晶体管)的晶体管类型相同。
在示例性实施方式中，第一初始信号线INITL1被配置为向第一晶体管(也是节点复位晶体管)提供初始信号，第一扫描信号线GL1被配置为向第四晶体管(也是写入晶体管)和第七晶体管(也是阳极复位晶体管)提供控制信号，第二扫描信号线GL2被配置为向第二晶体管(也是补偿晶体管)提供控制信号。
在示例性实施方式中，如图5至图16所示，第一初始信号线INITL1、第一扫描信号线GL1、第二扫描信号线GL2和发光信号线EL中的任一条至少部分沿第一方向D1延伸；数据信号线DL和第一电源线VDDL可以沿第二方向D2延伸。
在示例性实施方式中，如图5至图16所示，子像素所连接的复位信号线RL在基底上的正投影位于子像素所连接的第一初始信号线INITL1在基底上的正投影和子像素所连接的第一扫描信号线GL1在基底上的正投影之间，子像素所连接的第二扫描信号线GL2位于子像素所连接的第一扫描信号线GL1在基底上的正投影远离子像素所连接的复位信号线RL的一侧，子像素所连接的发光信号线EL位于子像素所连接的第二扫描信号线GL2和子像素所连接的第一初始信号线INITL1在基底上的正投影之间。
在示例性实施方式中，复位信号线RL可以包括：异层设置，且相互连接的第一子复位信号线和第二子复位信号线，第一子复位信号线在基底上的正投影与第二子复位信号线在基底上的正投影至少部分交叠。
在示例性实施方式中，第二扫描信号线GL2可以包括：异层设置，且相互连接的第一子扫描信号线和第二子扫描信号线，第一子扫描信号线在基底上的正投影与第二子扫描信号线在基底上的正投影至少部分交叠。
在示例性实施方式中，复位信号线RL和第二扫描信号线GL2同层设置，第一子复位信号线与第一子扫描信号线同层设置，第二子复位信号线与第二子扫描信号线同层设置。
在示例性实施方式中，第一扫描信号线GL1和发光信号线EL同层设置，第一初始信号线INITL1、复位信号线RL和第二扫描信号线GL2同层设置，且位于第一扫描信号 线GL1远离基底的一侧，第一电源线VDDL和数据信号线DL位于第一初始信号线INITL1远离基底的一侧。
在示例性实施方式中，如图5、图8、图11和图14所示，相邻数据信号线DL相对于沿第二方向D2延伸的虚拟直线对称。
在示例性实施方式中，如图5、图8、图11和图14所示，相邻第一电源线VDDL相对于沿第二方向D2延伸的虚拟直线对称。
在示例性实施方式中，如图5、图8、图11和图14所示，第一电源线VDDL与其中一条相邻电源线连接，且与另一条相邻电源线间隔设置，间隔设置的两条第一电源线VDDL之间设置有两条数据信号线DL。
在示例性实施方式中，如图5、图8、图11和图14所示，子像素所连接的第二初始信号线中的第一初始连接部INITL2A在基底上的正投影位于子像素所连接的复位信号线RL在基底上的正投影与子像素所连接的发光信号线EL在基底上的正投影之间。
在示例性实施方式中，如图11所示，第一初始连接部INITL2A与第二初始连接部INITL2B同层设置，且与第二初始连接部INITL2B为一体结构。
在示例性实施方式中，如图5、图8或者图14所示，第一初始连接部INITL2A与第二初始连接部INITL2B异层设置，第二初始连接部INITL2B通过过孔与第一初始连接部INITL2A连接。
在示例性实施方式中，第一初始连接部INITL2A位于第二初始连接部INITL2B靠近基底的一侧，且与第一子复位信号线或者第二子复位信号线同层设置。图5和图14是以第一初始连接部INITL2A与第二子复位信号线同层设置为例进行说明的。
在示例性实施方式中，如图8所示，第一初始连接部INITL2A位于第二初始连接部INITL2B远离基底10的一侧，且与第一电极同层设置。
在示例性实施方式中，如图8所示，第一初始连接部INITL2A与相邻的发光器件的第一电极之间的最小距离约为1微米至3微米。示例性地，第一初始连接部INITL2A与相邻的发光器件的第一电极之间的最小距离可以约为2微米。
在示例性实施方式中，如图5、图8、图11和图14所示，至少一条第二初始连接部INITL2B包括：多个第二初始连接部INITL2B，且多个第二初始连接部INITL2B沿第一方向D1排布；第二初始连接部INITL2B在基底上的正投影还与第一扫描信号线GL1和第一初始信号线INITL1在基底上的正投影部分交叠。
在示例性实施方式中，如图5、图8和图11所示，至少一条第二初始信号线还包括：多个第一初始连接部INITL2A和多个沿第一方向D1延伸的第三初始连接部INITL2C；多个第一初始连接部INITL2A沿第一方向D1排布，多个第三初始连接部INITL2C沿第一方向D1排布。其中，相邻两个第二初始连接部INITL2B通过第一初始连接部INITL2A或者第三初始连接部INITL2C连接，第二初始连接部INITL2B与其中一个相邻的第二初始连接部INITL2B通过第一初始连接部INITL2A连接，第二初始连接部INITL2B与另一个相邻的第二初始连接部INITL2B通过第三初始连接部INITL2C连接。
在示例性实施方式中，如图5、图8和图11所示，子像素所连接的第二初始信号线的第三初始连接部INITL2C在基底上的正投影位于子像素所连接的第一扫描信号线GL1在基底上的正投影远离子像素所连接的复位信号线RL在基底上的正投影的一侧。
在示例性实施方式中，如图5、图8和图11所示，第二初始连接部INITL2B和第三初始连接部INITL2C同层设置，且为一体结构；第二初始连接部INITL2B位于复位信号 线EL所在的膜层和第一电源线VDDL所在的膜层之间。
在示例性实施方式中，如图5、图8和图11所示，第二初始连接部INITL2B和第三初始连接部INITL2C的一体结构的形状可以为“7”字形
在示例性实施方式中，如图5、图6、图8、图9、图11和图12中的第二初始信号线INITL2整体走线呈现沿第二方向排布的多个“几”字型。
在示例性实施方式中，位于同一列的相邻第二初始信号线的第二初始连接部可以相互连接且呈一体结构。位于同一列的相邻第二初始信号线的第二初始连接部可以相互连接可以使得多条第二初始信号线呈网状结构，降低了信号线的负载，可以提升显示基板的显示均一性。
在示例性实施方式中，位于相邻行的第二初始连接部，其第二初始连接部可以在不同列连通，且第一初始连接部与复位信号线不交叠。
在示例性实施方式中，如图14所示，至少一条第二初始信号线包括：一个第一初始连接部INITL2A和多个第二初始连接部INITL2B，多个第二初始连接部INITL2B与第一初始连接部INITL2A连接。
在示例性实施方式中，如图14和图15所示，第二初始信号线INITL2整体走线呈现沿第二方向排布的多个倒立的“T”字型。
在示例性实施方式中，如图14所示，显示基板还包括：至少部分沿第二方向延伸的多条第一连接线L1；第一连接线L1与第二初始连接部INITL2B同层设置；至少一条第一连接线L1与多条第一初始信号线INITL1连接。本公开通过设置第一连接线，可以使第一连接线和第一初始信号线形成网状结构，降低了信号线的负载，可以提升显示基板的显示均一性。
在示例性实施方式中，如图14所示，显示基板还包括：至少部分沿第二方向延伸的第二连接线L2；第二连接线L2与第二初始连接部INITL2B同层设置；至少一条第二连接线L2与多条第二初始信号线的第一初始连接部INITL2A连接。本公开通过设置第二连接线，可以使第二连接线和第二初始信号线形成网状结构，降低了信号线的负载，可以提升显示基板的显示均一性。
在示例性实施方式中，如图5、图8、图11和图14所示，显示基板还包括：平坦部；平坦部与第一电源线VDDL同层设置，且相互连接；平坦部在基底上的正投影与第一晶体管的有源层、第二晶体管的有源层、第一扫描信号线GL1、第二扫描信号线GL2、第一初始信号线INITL1和至少一个发光器件的第一电极在基底上的正投影至少部分交叠。本公开通过设置平坦部可以提升发光器件的第一电极的平坦性，提升可显示基板的显示效果。
本公开提供的显示基板中第二初始信号线的设置还可以减少第二初始信号线与发光器件的第一电极之间的交叠面积，从而减少二者之间的寄生电容，提升显示基板的显示效果。
在示例性实施方式中，本公开的第二初始信号线的设置不仅可以用于包括两条初始信号线的显示基板中，还可以用于包括三条初始信号线的显示基板，其中，第三条初始信号线可以被配置为向驱动晶体管的第一极提供初始信号。图5至图14是以包括两条初始信号线的显示基板为例进行说明的。
在示例性实施方式中，如图5至图14所示，显示基板可以包括：依次叠设在基底上的驱动电路层和发光结构层；驱动电路层至少包括像素电路、第一初始信号线、第一扫描 信号线、第二扫描信号线、发光信号线、第二初始信号线、第一电源线、数据信号线和平坦部，发光结构层至少包括：发光器件；驱动电路层包括依次叠设的第一半导体层、第一导电层、第二导电层、第二半导体层、第三导电层、第四导电层和第五导电层；
第一导电层至少包括：第一扫描信号线GL1和发光信号线EL；
第二导电层至少包括：第一初始信号线INITL1、复位信号线RL的第一子复位信号线、第二扫描信号线GL2的第一子扫描信号线；
第三导电层至少包括：复位信号线RL的第二子复位信号线和第二扫描信号线GL2的第二子扫描信号线；
第四导电层至少包括：第二初始信号线INITL2的第二初始连接部INITL2A。
第五导电层至少包括：数据信号线DL、第一电源线VDDL和平坦部。
在示例性实施方式中，发光结构层可以包括：第六导电层。
第六导电层至少包括：发光器件的第一电极。
在示例性实施方式中，如图5、图8和图11所示，第三初始连接部INITL2C可以位于第四导电层。第一初始连接部INITL2A可以位于第三导电层、第四导电层或者第六导电层。
在示例性实施方式中，如图14所示，第一初始连接部INITL2A可以位于第三导电层。
在示例性实施方式中，如图7、图10、图13和图16所示，显示基板的驱动结构层20还可以包括：第一绝缘层21、第二绝缘层22、第三绝缘层23、第四绝缘层24、第五绝缘层25、第六绝缘层26、第一平坦层27和第二平坦层28。第一绝缘层21位于第一半导体层31和第一导电层32之间，第二绝缘层22位于第一导电层32和第二导电层33之间，第三绝缘23位于第二导电层33和第二半导体层34之间，第四绝缘层24位于第二半导体层34和第三导电层35之间，第五绝缘层25位于第三导电层35和第四导电层36之之间，第六绝缘层26和第一平坦层27位于第四导电层36和第五导电层37之间，第二平坦层28位于第五导电层37和第六导电层41之间。
本公开实施例还提供了一种显示基板，包括：基底和设置在基底上的多个子像素、多条复位信号线和多条第二初始信号线，子像素分别与复位信号线和第二初始信号线电连接，子像素包括：像素电路和发光器件，发光器件包括第一电极，像素电路包括：第一晶体管，复位信号线被配置为向第一晶体管的栅电极提供控制信号，第二初始信号线被配置为向发光器件的第一电极提供初始信号；
复位信号线至少部分沿第一方向延伸，至少一条第二初始信号线包括：沿第一方向延伸的第一初始连接部和第三初始连接部以及沿第二方向延伸的第二初始连接部，第二方向与第一方向相交；
第三初始连接部在基底上的正投影与复位信号线在基底上的正投影之间的距离小于第三初始连接部在基底上的正投影与第一初始连接部在基底上的正投影之间的距离。
在示例性实施方式中，如图5、图8、图11和图14所示，子像素的像素电路的位于第二半导体层的第一晶体管的有源层(也是第二晶体管的有源层)与位于第一导电层的第一扫描信号线GL1之间存在寄生电容，且称为子像素的寄生电容。
在示例性实施方式中，不同子像素的寄生电容不同。示例性地，红色子像素与绿色子像素的寄生电容可以相同，且可以与蓝色子像素的寄生电容不同。本公开可以通过将不同子像素的寄生电容差异化设计，可以平衡不同子像素之间的数据范围，调整黑态电压，进 而提升显示基板的显示效果。
在示例性实施方式中，不同子像素的寄生电容不同可以通过使得不同子像素的像素电路的位于第二半导体层的第一晶体管的有源层(也是第二晶体管的有源层)与位于第一导电层的第一扫描信号线之间的交叠面积不同实现。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开在此不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施方式中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
图17至图59为一个示例性实施例提供的显示基板的制备过程示意图。图17至图59是以两行四列子像素为例进行说明的。如图17至图59所示，一种示例性实施例提供的图5、图8、图11和图14的显示基板的制备过程可以包括：
(1)形成第一半导体层图案。在示例性实施方式中，形成第一半导体层图案可以包括：在基底上依次沉积第一半导体薄膜，通过图案化工艺对第一半导体薄膜进行图案化，形成覆盖基底的第一半导体层图案，如图17所示，图17为图5、图8、图11和图14中第一半导体层的平面示意图。
在示例性实施方式中，如图17所示，第一半导体层至少可以包括：位于至少一个子像素的第三晶体管的有源层T31、第四晶体管的有源层T41、第五晶体管的有源层T51、第六晶体管的有源层T61和第七晶体管的有源层T71。
在示例性实施方式中，第三晶体管的有源层T31至第七晶体管的有源层T71为相互连接的一体结构。
在示例性实施方式中，相邻子像素的第三晶体管的有源层T31至第七晶体管的有源层T71相对于沿第二方向D2延伸的虚拟直线对称设置。
在示例性实施方式中，在第一方向D1上，第四晶体管的有源层T41和第五晶体管的有源层T51可以位于本子像素中第三晶体管的有源层T31的同一侧，第六晶体管的有源层T61可以位于本子像素中第三晶体管的有源层T31的同一侧，第六晶体管的有源层T61和第四晶体管的有源层T41可以位于本子像素的第三晶体管的有源层T31的不同侧。在第二方向D2上，第i行子像素中第五晶体管的有源层T51、第六晶体管的有源层T61和第七晶体管的有源层T71可以位于本子像素中第三晶体管的有源层T31远离第i+1行子像素的一侧，第i行子像素中的第四晶体管的有源层T41可以位于本子像素中第三晶体管的有源层T31靠近第i+1行子像素的一侧。
在示例性实施方式中，第三晶体管的有源层T31的形状可以呈倒立的“Ω”字形。第四晶体管的有源层T41、第五晶体管的有源层T51和第六晶体管的有源层T61的形状可以呈“I”字形。第七晶体管的有源层T71的形状可以呈“L”字形，
在示例性实施方式中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第三晶体管的有源层13的第一区T31_1可以同时作为第四晶体管的有源层T41的第二区T41_2和第五晶体管的有源层T51的第二区T51_2，第三晶体管的有源层T31的第二区T31_2可以同时作为第六晶体管的有源层T61的第一区T61_1，第六晶体管的有源层T61的第二区T61_2可以作为第七晶体管的有源层T71的第二区T71_2，第四晶体管的有源层T41的第一区T41_1、第五晶体管的有源层T51的第一区T51_1和第七晶体管的有源层T71的第一区T71_1可以单独设置。
(2)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第一绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖第一半导体层图案的第一绝缘层，以及设置在第一绝缘层上的第一导电层图案，如图18和图19所示，图18为图5、图8、图11和图14中第一导电层的平面示意图，图19为图5、图8、图11和图14形成第一导电层后的平面示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，如图18和图19所示，第一导电层至少可以包括：第一扫描信号线GL1、发光信号线EL以及位于至少一个子像素的电容的第一极板C1。
在示例性实施方式中，相邻子像素的像素电路的第一极板C1相对于沿第二方向D2延伸的虚拟直线对称设置。
在示例性实施方式中，第一极板C1的形状可以为矩形状，矩形状的角部可以设置倒角，第一极板C1在基底上的正投影与第三晶体管的有源层在基底上的正投影至少部分交叠。在示例性实施方式中，第一极板C1可以同时作为电容的一个极板和第三晶体管T3的栅电极T32。
在示例性实施方式中，第一扫描信号线GL1的形状可以为主体部分沿着第一方向D1延伸的线形状，第i行子像素所连接的第一扫描信号线GL1可以位于本子像素的电容的第一极板C1靠近第i+1行子像素的一侧。第一扫描信号线GL1与本子像素的第四晶体管的有源层相重叠的区域可以作为第四晶体管的栅电极T42，第一扫描信号线GL1与本子像素的第七晶体管的有源层相重叠的区域可以作为第七晶体管的栅电极T72。
在示例性实施方式中，发光信号线EL的形状可以为主体部分沿着第一方向D1延伸的线形状，发光信号线EL可以位于本子像素的第一极板C1远离第i+1行子像素的一侧，发光信号线EL与本子像素的第五晶体管的有源层相重叠的区域作为第五晶体管的栅电极T52，发光信号线EL与本子像素的第六晶体管的有源层相重叠的区域作为第六晶体管的栅电极T62。
在示例性实施方式中，第一扫描信号线GL1和发光信号线EL可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
在示例性实施方式中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对第一半导体层进行导体化处理，被第一导电层遮挡区域的第一半导体层形成第三晶体管T3至第七晶体管T7的沟道区域，未被第一导电层遮挡区域的第一半导体层被导体化，即第三晶体管至第七有源层的第一区和第二区均被导体化。导体化后的第三晶体管的有源层13的第一区T31_1(也是第四晶体管的有源层T41的第二区T41_2和第五晶体管的有源层T51的第二区T51_2)可以复用为第三晶体管的第一极T33(也是第四晶体管的第二极T44和第五晶体管的第二极T54)。
在示例性实施方式中，第三晶体管的栅电极T32跨设在第三晶体管的有源层上，第 四晶体管的栅电极T42跨设在第四晶体管的有源层上，第五晶体管的栅电极T52跨设在第五晶体管的有源层上，第六晶体管的栅电极T62跨设在第六晶体管的有源层上，第七晶体管的栅电极T72跨设在第七晶体管的有源层上，也就是说，至少一个晶体管的栅电极的延伸方向与有源层的延伸方向相互垂直。
(3)形成第二导电层图案，包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第二导电薄膜，通过图案化工艺对第二绝缘薄膜和第二导电薄膜进行图案化，形成第二绝缘层以及位于第二绝缘层上的第二导电层图案，如图20和图21所示，图20为图5、图8、图11和图14中第二导电层的平面示意图，图21为图5、图8、图11和图14形成第二导电层后的平面示意图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，如图20和图21所示，第二导电层至少可以包括：第一初始信号线INITL1、复位信号线的第一子复位信号线RLA、第二扫描信号线的第一子扫描信号线GL2A以及位于至少一个子像素的电容的第二极板C2。
在示例性实施方式中，相邻子像素的像素电路的第二极板C2相对于沿第二方向D2延伸的虚拟直线对称设置。
在示例性实施方式中，如图20所示，第二极板C2可以包括：相互连接的主体部C21和连接部C22，本子像素的连接部C22位于本子像素的主体部C22靠近前一列或者后一列子像素的一侧。
在示例性实施方式中，如图20所示，主体部C21轮廓可以为矩形状，矩形状的角部可以设置倒角，主体部C21在基底上的正投影与第一极板在基底上的正投影至少部分交叠，第二极板可以作为电容的另一个极板，第一极板C1和第二极板C2构成像素电路的电容。主体部C21设置有开口，开口的形状可以为矩形状，可以位于如图20所示，的中部，使如图20所示，形成环形结构。开口暴露出覆盖第一极板的第二绝缘层，且第一极板在基底上的正投影包含开口在基底上的正投影。在示例性实施方式中，开口暴露出第一极板，使后续形成的第一晶体管的第二极(也是第二晶体管的第二极)与第一极板连接。
在示例性实施方式中，如图20所示，连接部C22轮廓可以为矩形状。
在示例性实施方式中，位于同一行的相邻子像素中的第二极相对于沿第二方向D2的一条虚拟线对称设置。
在示例性实施方式中，对于任一子像素，第二极板C2与位于同一行的其中一个相邻子像素的第二极板C2间隔设置，且与位于同一行的另一个相邻子像素的第二极板相互连接，且为一体结构。示例性地，第i行第j列子像素的第二极板与第i行第j+1列子像素的第二极板间隔设置，第i行第j+2列子像素的第二极板与第i行第j+3列子像素的第二极板间隔设置，第i行第j+1列子像素的第二极板的连接部与第i行第j+2列子像素的第二极板的连接部连接。本公开中，位于同一行的部分相邻子像素的第二极板相互连接可以在一定程度上保证显示基板的显示均一性。
在示例性实施方式中，第一初始信号线INITL1的形状可以为主体部分沿着第一方向D1延伸的线形状，第i行子像素所连接的第一初始信号线INITL1可以位于本子像素的第二极板C2靠近第i+1行子像素的一侧。对于同一子像素，子像素所连接的第一初始信号线INITL1在基底上的正投影位于子像素所连接的第一扫描信号线在基底上的正投影远离子像素的第一极板在基底上的正投影的一侧。
在示例性实施方式中，复位信号线的第一子复位信号线RLA的形状可以为主体部分沿着第一方向D1延伸的线形状，第一子复位信号线RLA可以位于所连接子像素的第二 极板C2和第一初始信号线INITL1之间，且与后续形成的本子像素的第一晶体管的有源层相重叠的区域作为第一晶体管的第一栅电极T12A，对于同一子像素，子像素所连接的第一子复位信号线RLA在基底上的正投影位于子像素所连接的第一扫描信号线在基底上的正投影和子像素所连接的第一初始信号线INITL1在基底上的正投影之间。
在示例性实施方式中，第二扫描信号线的第一子扫描信号线GL2A的形状可以为主体部分沿着第一方向D1延伸的线形状，第二扫描信号线的第一子扫描信号线GL2A可以位于所连接子像素的第二极板C2和复位信号线的第一子复位信号线RLA之间，且与后续形成的本子像素的第二晶体管的有源层相重叠的区域作为第二晶体管的第一栅电极T22A。对于同一子像素，子像素所连接的第一子扫描信号线GL2A在基底上的正投影位于子像素的第一极板在基底上的正投影和子像素所连接的第一扫描信号线在基底上的正投影之间。
在示例性实施方式中，第一初始信号线INITL1、复位信号线的第一子复位信号线RLA、第二扫描信号线的第一子扫描信号线GL2A可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
(4)形成第二半导体层图案，包括：在形成前述图案的基底上，包括：在基底上依次沉积第三绝缘薄膜和第二半导体薄膜，通过图案化工艺对第三绝缘薄膜和第二半导体薄膜进行图案化，形成第三绝缘层以及位于第三绝缘层上的第二半导体层图案，如图22和图23所示，图22为图5、图8、图11和图14中第二半导体层的平面示意图，图23为图5、图8、图11和图14形成第二半导体层后的平面示意图。
在示例性实施方式中，如图22和图23所示，第二半导体层至少可以包括：位于至少一个子像素的第一晶体管的有源层T11和第二晶体管的有源层T21。
在示例性实施方式中，第一晶体管的有源层T11和第二晶体管的有源层T21为相互连接的一体结构。
在示例性实施方式中，相邻子像素的第一晶体管的有源层T11和第二晶体管的有源层T21相对于沿第二方向D2延伸的虚拟直线对称设置。
在示例性实施方式中，在第二方向D2上，第i行子像素中第二晶体管的有源层T21可以位于本子像素中第一晶体管的有源层T11远离第i+1行子像素的一侧。
在示例性实施方式中，第一晶体管的有源层T11和第二晶体管的有源层T21的形状可以呈“I”字形，或者“L”字形。
在示例性实施方式中，对于同一子像素，子像素的第一晶体管的有源层T11在基底上的正投影与子像素所连接的复位信号线的第一子复位信号线和子像素所连接的第一初始信号线在基底上的正投影至少部分交叠。
在示例性实施方式中，对于同一子像素，子像素的第二晶体管的有源层T21在基底上的正投影与子像素所连接的第二扫描信号线的第一子扫描信号线GL2A在基底上的正投影交叠。
在示例性实施方式中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第一晶体管的有源层T11的第二区T11_2可以同时作为第二晶体管的有源层T21的第一区T21_1，第一晶体管的有源层T11的第一区T11_1和第二晶体管的有源层T21的第二区T21_2可以单独设置。
在示例性实施方式中，对于同一子像素，子像素的第一晶体管的有源层T11的第二 区T11_2(也是第二晶体管的有源层T21的第一区T21_1)在基底上的正投影与子像素所连接的第一扫描信号线在基底上的正投影至少部分交叠。
在示例性实施方式中，第一晶体管的有源层T11跨设在第一晶体管的第一栅电极上，第二晶体管的有源层T21跨设在第二晶体管的第一栅电极上。
(5)形成第三导电层，包括：在形成前述图案的基底上，依次沉积第四绝缘薄膜和第三导电薄膜，通过图案化工艺对第四绝缘薄膜和第三导电薄膜进行图案化，形成第四绝缘层图案以及位于第四绝缘层上的第三导电层图案，如图24至图29所示，图24为图5中第三导电层的平面示意图，图25为图5形成第三导电层后的平面示意图，图26为图8和图11中第三导电层的平面示意图，图27为图8和图11形成第三导电层后的平面示意图，图28为图14中第三导电层的平面示意图，图29为图14形成第三导电层后的平面示意图。在示例性实施方式中，第三导电层可以称为第三栅金属(GATE3)层。
在示例性实施方式中，如图24至图29所示，第三导电层至少可以包括：复位信号线的第二子复位信号线RLB和第二扫描信号线的第二子扫描信号线GL2B。
在示例性实施方式中，如图24至图29所示，复位信号线的第二子复位信号线RLB的形状可以为主体部分沿着第一方向D1延伸的线形状，复位信号线的第二子复位信号线RLB在基底上的正投影与复位信号线的第一子复位信号线在基底上的正投影至少部分交叠，且与复位信号线的第一子复位信号线电连接。
在示例性实施方式中，如图24至图29所示，对于同一子像素，子像素所连接的第二子复位信号线RLB在基底上的正投影位于子像素所连接的第一扫描信号线在基底上的正投影和子像素所连接的第一初始信号线INITL1在基底上的正投影之间。复位信号线的第二子复位信号线RLB与本子像素的第一晶体管的有源层相重叠的区域作为第一晶体管的第二栅电极T12B。第一晶体管的第一栅电极和第二栅电极组成第一晶体管的栅电极。
在示例性实施方式中，如图24至图29所示，第二扫描信号线的第二子扫描信号线GL2B的形状可以为主体部分沿着第二方向D1延伸的线形状，第二扫描信号线的第二子扫描信号线GL2B在基底上的正投影与第二扫描信号线的第一子扫描信号线在基底上的正投影至少部分交叠，且与第二扫描信号线的第一子扫描信号线电连接。
在示例性实施方式中，如图24至图29所示，对于同一子像素，子像素所连接的第二子扫描信号线GL2B在基底上的正投影位于子像素的第一极板在基底上的正投影和子像素所连接的第一扫描信号线在基底上的正投影之间。第二扫描信号线的第二子扫描信号线GL2B与本子像素的第如图晶体管的有源层相重叠的区域作为第二晶体管的第二栅电极T22B。第二晶体管的第一栅电极和第二栅电极组成第二晶体管的栅电极。
在示例性实施方式中，复位信号线的第二子复位信号线RLB和第二扫描信号线的第二子扫描信号线GL2B可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
在示例性实施方式中，如图24和图25所示，图5提供的显示基板中第三导电层还可以包括：第二初始信号线的多个第一初始连接部INITL2A。其中，一条第二初始信号线可以包括多个间隔设置，且沿第一方向D1延伸的第一初始连接部INITL2A。位于同一条第二初始信号线的多个第一初始连接部INITL2A沿第一方向D1排布
在示例性实施方式中，如图28和图29所示，图14提供的显示基板中第三导电层还可以包括：第二初始信号线的第一初始连接部INITL2A。其中，一条第二初始信号线可以包括一个沿第二方向D1延伸的第一初始连接部INITL2A。
在示例性实施方式中，如图24、图25、图28和图29所示，第一初始连接部INITL2A的形状可以为主体部分沿着第一方向D1延伸的线形状。对于同一子像素，子像素所连接的第二初始信号线的第一初始连接部INITL2A位于子像素所连接的复位信号线的第二子复位信号线RLB远离第二扫描信号线的第二子扫描信号线GL2B的一侧，且子像素所连接的第二初始信号线的第一初始连接部INITL2A在基底上的正投影位于子像素所连接的第一初始信号线在基底上的正投影远离子像素所连接的复位信号线的第二子复位信号线RLB的一侧。
在示例性实施方式中，如图24、图25、图28和图29所示，子像素所连接的第二初始信号线的第一初始连接部INITL2A在基底上的正投影与子像素所连接的复位信号线的第二子复位信号线RLB和子像素所连接的第一初始信号线在基底上的正投影不交叠。
在示例性实施方式中，形成第三导电层图案后，可以利用第三导电层作为遮挡，对第二半导体层进行导体化处理，被第三导电层遮挡区域的第二半导体层形成第一晶体管至第二晶体管的沟道区域，未被第三导电层遮挡区域的第二半导体层被导体化，即第一晶体管至第二有源层的第一区和第二区均被导体化。
(6)形成第五绝缘层图案，包括：在形成有前述图案的基底上，沉积第五绝缘薄膜，通过图案化工艺对第五绝缘薄膜进行图案化，形成覆盖前述图案的第五绝缘层图案，第五绝缘层开设有多个过孔图案，如图30至图32所示，图30为图5形成第五绝缘层后的平面示意图，图31为图8和图11形成第五绝缘层后的平面示意图，图32为图14形成第五绝缘层后的平面示意图。
在示例性实施方式中，如图30至图32所示，第五绝缘层的多个过孔至少包括：位于至少一个子像素的第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9和第十过孔V10。
在示例性实施方式中，第一过孔V1在基底上的正投影位于第四晶体管的有源层的第一区在基底上的正投影的范围之内，第一过孔V1内的第四绝缘层、第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第四晶体管的有源层的第一区的表面，第一过孔V1被配置为使后续形成的第四晶体管的第一极通过该过孔与第四晶体管的有源层的第一区连接。
在示例性实施方式中，第二过孔V2在基底上的正投影位于第五晶体管的有源层的第一区在基底上的正投影的范围之内，第二过孔V2内的第四绝缘层、第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第五晶体管的有源层的第一区的表面，第二过孔V2被配置为使后续形成的第五晶体管的第一极通过该过孔与第五晶体管的有源层的第一区连接。
在示例性实施方式中，第三过孔V3在基底上的正投影位于第三晶体管的有源层的第二区(也是第六晶体管的有源层的第一区)在基底上的正投影的范围之内，第三过孔V3内的第四绝缘层、第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第三晶体管的有源层的第二区(也是第六晶体管的有源层的第一区)的表面，第三过孔V3被配置为使后续形成的第二晶体管的第二极(也是第三晶体管的第二极和第六晶体管的第一极)通过该过孔与第三晶体管的有源层的第二区(也是第六晶体管的有源层的第一区)连接。
在示例性实施方式中，第四过孔V4在基底上的正投影位于第六晶体管的有源层的第二区(也是第七晶体管的有源层的第二区)在基底上的正投影的范围之内，第四过孔V4内的第四绝缘层、第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第六晶体管的有源层的第二区(也是第七晶体管的有源层的第二区)的表面，第四过孔V4被配置为使 后续形成的第六晶体管的第二极(也是第七晶体管的第二极)通过该过孔与第六晶体管的有源层的第二区(也是第七晶体管的有源层的第二区)连接。
在示例性实施方式中，第五过孔V5在基底上的正投影位于第七晶体管的有源层的第一区在基底上的正投影的范围之内，第五过孔V5内的第四绝缘层、第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第七晶体管的有源层的第一区的表面，第五过孔V5被配置为使后续形成的第一初始连接部(也是第七晶体管的第一极)通过该过孔与第七晶体管的有源层的第一区连接。
在示例性实施方式中，第六过孔V6在基底上的正投影位于电容的第一极板在基底上的正投影的范围之内，第六过孔V6内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出电容的第一极板的表面，第六过孔V6被配置为使后续形成的第一晶体管的第二极(也是第二晶体管的第一极)通过该过孔与电容的第一极板连接。
在示例性实施方式中，第七过孔V7在基底上的正投影位于电容的第二极板在基底上的正投影的范围之内，第七过孔V7内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出电容的第二极板的表面，第七过孔V7被配置为使后续形成的第五晶体管的第一极通过该过孔与电容的第二极板连接。
在示例性实施方式中，第八过孔V8在基底上的正投影位于第一初始信号线在基底上的正投影的范围之内，第八过孔V8内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一初始信号线的表面，第八过孔V8被配置为使后续形成的第一晶体管的第一极通过该过孔与第一初始信号线连接。
在示例性实施方式中，第九过孔V9在基底上的正投影位于第一晶体管的有源层的第一区在基底上的正投影的范围之内，第九过孔V9内的第四绝缘层被刻蚀掉，暴露出第一晶体管的有源层的第一区的表面，第九过孔V9被配置为使后续形成的第一晶体管的第一极通过该过孔与第一晶体管的有源层的第一区连接。
在示例性实施方式中，第十过孔V10在基底上的正投影位于第一晶体管的有源层的第二区(也是第二晶体管的有源层的第一区)在基底上的正投影的范围之内，第十过孔V10内的第四绝缘层被刻蚀掉，暴露出第一晶体管的有源层的第二区(也是第二晶体管的有源层的第一区)的表面，第十过孔V10被配置为使后续形成的第一晶体管的第二极(也是第二晶体管的第一极)通过该过孔与第一晶体管的有源层的第二区(也是第二晶体管的有源层的第一区)连接。
在示例性实施方式中，第十一过孔V11在基底上的正投影位于第二晶体管的有源层的第二区在基底上的正投影的范围之内，第十一过孔V11内的第四绝缘层被刻蚀掉，暴露出第二晶体管的有源层的第二区的表面，第十一过孔V11被配置为使后续形成的第二晶体管的第二极(也是第六晶体管的第一极)通过该过孔与第二晶体管的有源层的第二区连接。
在示例性实施方式中，如图30和图31所示，图5、图8和图11提供的显示基板中相邻两个子像素的第八过孔V8为同一过孔。相邻两个子像素的第八过孔V8为同一过孔。可以减少图5、图8和图11提供的显示基板的过孔数量，可以简化显示基板的制作工艺。
在示例性实施方式中，如图32所示，图14提供的显示基板中的相邻两个子像素的第八过孔为不同过孔，且相对于相邻子像素的沿第二方向D2的对称轴对称设置。本公开中的相邻两个子像素的第八过孔为不同过孔有利于第一连接线的设置，可以实现第一连接线同时与第一晶体管的第一极和第一初始信号线的连接，可以提升显示基板的均一性。
在示例性实施方式中，如图30和图32所示，图5和图14提供的显示面板中第五绝 缘层的多个过孔图案还包括：第十二过孔V12。
在示例性实施方式中，第十二过孔V12在基底上的正投影位于第二初始信号线的第一初始连接部在基底上的正投影的范围之内，第十二过孔V12被配置为使后续形成的第二初始信号线的第二初始连接部通过该过孔与第二初始信号线的第一初始连接部连接。
在示例性实施方式中，如图30和图32所示，图5提供的显示基板的穿过第十二过孔的沿第二方向D2延伸的虚拟直线与穿过第五过孔的沿第二方向D2延伸的虚拟直线之间的距离大于图14提供的显示基板的穿过第十二过孔的沿第二方向D2延伸的虚拟直线与穿过第五过孔D2的沿第二方向延伸的虚拟直线之间的距离。
在示例性实施方式中，如图30和图32所示，图5提供的显示基板的穿过第十二过孔的沿第一方向D1延伸的虚拟直线与穿过第五过孔的沿第一方向D1延伸的虚拟直线之间的距离小于图14提供的显示基板的穿过第十二过孔的沿第一方向D1延伸的虚拟直线与穿过第五过孔D2的沿第一方向D1延伸的虚拟直线之间的距离。
在示例性实施方式中，如图30所示，图5提供的显示基板的第十二过孔在基底上的正投影与第一半导体层图案在基底上的正投影不交叠。
在示例性实施方式中，如图32所示，图14提供的显示基板的第十二过孔在基底上的正投影与第一半导体层图案在基底上的正投影至少部分交叠。
在示例性实施方式中，如图32所示，图14提供的显示基板中沿第二方向延伸的虚拟直线经过第六过孔V6和第十二过孔V12。
(7)形成第四导电层图案，包括：在形成前述图案的基底上，沉积第四导电薄膜，通过图案化工艺对第四导电薄膜进行图案化，形成第四导电层图案，如图33至图39所示，图33为图5和图8中第四导电层的平面示意图，图34为图5形成第四导电层后的平面示意图，图35为图8形成第四导电层后的平面示意图，图36为图11中第四导电层的平面示意图，图37为图11形成第四导电层后的平面示意图，图38为图14中第四导电层的平面示意图，图39为图14形成第四导电层后的平面示意图。在示例性实施方式中，第四导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，如图33至图39所示，第四导电层至少可以包括：第二初始信号线的第二初始连接部INITL2B以及位于至少一个子像素的第一晶体管的第一极T13、第一晶体管的第二极T14、第二晶体管的第一极T23、第二晶体管的第二极T24、第三晶体管的第二极T34、第四晶体管的第一极T43、第五晶体管的第一极T53、第六晶体管的第一极T63、第六晶体管的第二极T64、第七晶体管的第一极T73和第七晶体管的第二极T74。
在示例性实施方式中，相邻子像素的多个晶体管的第一极和第二极沿第二方向D2延伸的虚拟直线对称设置。
在示例性实施方式中，如图33至图37所示，图5、图8和图11提供的显示基板中，与子像素位于同一行的相邻子像素包括：第一相邻子像素和第二相邻子像素，子像素与第一晶体管的第一极与第一相邻子像素的第一晶体管的第一极为一体结构，与第二相邻子像素的第一晶体管的第一极间隔设置。第一相邻子像素为与子像素前一列的子像素，第二相邻子像素为子像素后一列的子像素。示例性地，位于第i行第j列子像素的第一晶体管的第一极与位于第i行第j+1列子像素的第一晶体管的第一极为一体结构，位于第i行第j+2列子像素的第一晶体管的第一极与位于第i行第j+3列子像素的第一晶体管的第一极为一体结构，位于第i行第j+1列子像素的第一晶体管的第一极与位于第i行第j+2列子像素的第一晶体管的第一极间隔设置。
在示例性实施方式中，如图33至图39所示，图5、图8、图11和图14提供的显示基板中，子像素与第五晶体管的第一极与第一相邻子像素的第五晶体管的第一极间隔设置，与第二相邻子像素的第一晶体管的第一极为一体结构。示例性地，位于第i行第j列子像素的第五晶体管的第一极与位于第i行第j+1列子像素的第五晶体管的第一极间隔设置，位于第i行第j+2列子像素的第五晶体管的第一极与位于第i行第j+3列子像素的第五晶体管的第一极为间隔设置，位于第i行第j+1列子像素的第一晶体管的第一极与位于第i行第j+2列子像素的第五晶体管的第一极为一体结构。
在示例性实施方式中，如图33至图39所示，第一晶体管的第一极T13至少部分沿第二方向D1延伸。第一晶体管的第一极T13通过第九过孔与第一晶体管的有源层的第一区连接，且通过第八过孔与第一初始信号线电连接。
在示例性实施方式中，如图33至图39所示，第一晶体管的第二极T14和第二晶体管的第一极T23为一体结构，且的形状为沿第一方向D2延伸的线形状。第一晶体管的第二极T14(也是第二晶体管的第一极T23)通过第六过孔与电容的第一极板连接，且通过第十过孔与第一晶体管的有源层的第二区(也是第二晶体管的有源层的第一区)连接。
在示例性实施方式中，如图33至图39所示，第二晶体管的第二极T24、第三晶体管的第二极T34和第六晶体管的第一极T63为一体结构，且形状为沿第一方向D2延伸的线形状。第二晶体管的第二极T24(也是第三晶体管的第二极T34和第六晶体管的第一极T63)通过第三过孔与第三晶体管的有源层的第二区(也是第六晶体管的有源层的第一区)连接，通过第十一过孔与第二晶体管的有源层的第二区连接。
在示例性实施方式中，如图33至图39所示，第四晶体管的第一极T43的形状为沿第一方向D2延伸的线形状。第四晶体管的第一极T43通过第一过孔与第四晶体管的有源层的第一区连接。
在示例性实施方式中，如图33至图39所示，第五晶体管的第一极T53的形状可以为倒立的“h”字形，第五晶体管的第一极T53通过第二过孔与第五晶体管的有源层的第一区连接，且通过第七过孔与电容的第二极板电连接。
在示例性实施方式中，如图33至图39所示，第六晶体管的第二极T64(也是第七晶体管的第二极T74)的形状为沿第二方向D2延伸的线形状，第六晶体管的第二极T64(也是第七晶体管的第二极T74)通过第四过孔与第六晶体管的有源层的第二区(也是第六晶体管的有源层的第二区)连接。
在示例性实施方式中，如图33至图39所示，图5、图8、图11和图14提供的显示面板中至少一条第二初始信号线包括多个第二初始连接部INITL2B，其中，第二初始连接部INITL2B的至少部分沿第二方向D2延伸，且位于同一第二初始信号线的多个第二初始连接部INITL2B第一方向D1排布。
在示例性实施方式中，如图33至图39所示，图5、图8、图11和图14提供的显示面板中第二初始连接部INITL2B在基底上的正投影与第一扫描信号线、复位信号线和第一初始信号线在基底上的正投影部分交叠。
在示例性实施方式中，如图33至图39所示，第二初始信号线的第二初始连接部INITL2B与第七晶体管的第一极T13为一体结构。第二初始信号线的第二初始连接部INITL2B(也是第七晶体管的第一极T13)通过第五过孔与第七晶体管的有源层的第一区连接。
在示例性实施方式中，如图33至图35所示，图5和图8提供显示基板中第四导电层还可以包括：第二初始信号线的第三初始连接部INITL2C。
在示例性实施方式中，如图36和图37所示，图11提供显示基板中第四导电层还可以包括：第二初始信号线的多个第一初始连接部INITL2A和多个第三初始连接部INITL2C。
在示例性实施方式中，如图33至图37所示，对于图5、图8和图11提供显示基板，至少一条第二初始信号线包括多个第三初始连接部INITL2C，且多个第三初始连接部INITL2C间隔设置。第三初始连接部INITL2C且设置在部分相邻第二初始连接部INITL2B之间。第三初始连接部INITL2C的至少部分沿第一方向D1延伸，且位于同一第二初始信号线的多个第三初始连接部INITL2C沿第一方向D1排布。
在示例性实施方式中，如图34、图35和图36所示，对于图5、图8和图11提供显示基板，对于同一子像素，第二初始信号线中的第三初始连接部INITL2C在基底上的正投影位于子像素所连接的第二扫描信号线在基底上的正投影与子像素所连接的第一扫描信号线在基底上的正投影之间。
在示例性实施方式中，如图33至图37所示，如图33和图36所示，第三初始连接部INITL2C与第二初始连接部INITL2B相互连接，且为一体结构。
在示例性实施方式中，如图34所示，对于图5提供的显示基板，对于同一第二初始信号线，第二初始连接部INITL2B(也是第七晶体管的第一极)通过第十二过孔与第二初始连接部连接。
在示例性实施方式中，如图34所示，对于图5提供的显示基板，第二初始连接部INITL2B与其中一个相邻第二初始连接部INITL2B通过位于第三导电层的第一初始连接部连接，且与另一个相邻第二初始连接部INITL2B通过第三初始连接部连接。
在示例性实施方式中，如图36和图37所示，图11提供的显示基板中第一初始连接部INITL2A的形状为至少部分沿第一方向D1延伸的线形状。多个第一初始连接部INITL2A沿第一方向D1排布。
在示例性实施方式中，如图36和图37所示，图11提供的显示基板中子像素所连接的第二初始信号线的第一初始连接部INITL2A在基底上的正投影位于子像素所连接的第一初始信号线在基底上的正投影远离子像素所连接的复位信号线在基底上的正投影的一侧。
在示例性实施方式中，如图36和图37所示，图11提供的显示基板中第二初始连接部INITL2B分别与第一初始连接部INITL2A和第三初始连接部INITL2C电连接，且为一体结构。第二初始连接部INITL2B与其中一个相邻第二初始连接部INITL2B通过位于第三导电层的第一初始连接部连接，且与另一个相邻第二初始连接部INITL2B通过第三初始连接部连接。
在示例性实施方式中，如图38和图39所示，图14提供的显示基板中第四导电层还可以包括：第一连接线L1和第二连接线L2。
在示例性实施方式中，如图38和图39所示，第一连接线L1的形状为至少部分沿第一方向D2延伸的线形状，第一连接线L1分别与第五晶体管的第一极间隔设置的部分两个子像素的第一晶体管的第一极连接，且为一体结构。第一连接线L1设置在所连接的两个子像素的第一晶体管的第一极之间。
在示例性实施方式中，如图38和图39所示，第二连接线L2的形状为至少部分沿第一方向D2延伸的线形状，第一连接线L1设置在第五晶体管的第一极间隔设置的另一部分两个子像素的第一晶体管的第一极之间。第二连接线L2通过第十二过孔与第二初始信号线的第一初始连接部连接。
(8)形成第一平坦层图案，包括：在形成有前述图案的基底上，沉积第六绝缘薄膜，通过图案化工艺对第六绝缘薄膜进行图案化，形成第六绝缘层，在第六绝缘层上涂覆第一平坦薄膜，通过图案化工艺对第一平坦薄膜进行图案化，形成覆盖前述图案的第一平坦层图案，第一平坦层开设有多个过孔图案，如图40至图43所示，图40为图5提供的显示基板形成第一平坦层后的平面示意图，图41为图8提供的显示基板形成第一平坦层后的平面示意图，图42为图11提供的显示基板形成第一平坦层后的平面示意图，图43为图14提供的显示基板形成第一平坦层后的平面示意图。
在示例性实施方式中，如图40和图43所示，图5和图14提供的显示基板中第一平坦层的多个过孔至少包括：位于至少一个子像素的第十三过孔V13至第十五过孔V15。
在示例性实施方式中，如图40和图43所示，第十三过孔V13在基底上的正投影位于第四晶体管的第一极在基底上的正投影的范围之内，第十三过孔V13内的第六绝缘层被刻蚀掉，暴露出第四晶体管的第一极的表面，第十三过孔V13被配置为使后续形成的数据信号线通过该过孔与第四晶体管的第一极连接。
在示例性实施方式中，如图40和图43所示，第十四过孔V14在基底上的正投影位于第五晶体管的第一极在基底上的正投影的范围之内，第十四过孔V14内的第六绝缘层被刻蚀掉，暴露出第五晶体管的第一极的表面，第十四过孔V14被配置为使后续形成的第一电源线通过该过孔与第五晶体管的第一极连接。
在示例性实施方式中，如图40和图43所示，第十五过孔V15在基底上的正投影位于第六晶体管的第二极(也是第七晶体管的第二极)在基底上的正投影的范围之内，第十五过孔V15内的第六绝缘层被刻蚀掉，暴露出第六晶体管的第二极(也是第七晶体管的第二极)的表面，第十五过孔V15被配置为使后续形成的第一电源线通过该过孔与第六晶体管的第二极(也是第七晶体管的第二极)连接。
在示例性实施方式中，如图41和图42所示，图8和图11提供的显示基板中第一平坦层的多个过孔至少包括：位于至少一个子像素的第十二过孔V12至第十四过孔V14。
在示例性实施方式中，如图41和图42所示，第十二过孔V12在基底上的正投影位于第四晶体管的第一极在基底上的正投影的范围之内，第十二过孔V12内的第六绝缘层被刻蚀掉，暴露出第四晶体管的第一极的表面，第十二过孔V12被配置为使后续形成的数据信号线通过该过孔与第四晶体管的第一极连接。
在示例性实施方式中，如图41和图42所示，第十三过孔V13在基底上的正投影位于第五晶体管的第一极在基底上的正投影的范围之内，第十三过孔V13内的第六绝缘层被刻蚀掉，暴露出第五晶体管的第一极的表面，第十三过孔V13被配置为使后续形成的第一电源线通过该过孔与第五晶体管的第一极连接。
在示例性实施方式中，如图41和图42所示，第十四过孔V14在基底上的正投影位于第六晶体管的第二极(也是第七晶体管的第二极)在基底上的正投影的范围之内，第十四过孔V14内的第六绝缘层被刻蚀掉，暴露出第六晶体管的第二极(也是第七晶体管的第二极)的表面，第十四过孔V14被配置为使后续形成的第一电源线通过该过孔与第六晶体管的第二极(也是第七晶体管的第二极)连接。
(9)形成第五导电层图案，包括：在形成前述图案的基底上，沉积第五导电薄膜，通过图案化工艺对第五导电薄膜进行图案化，形成第五导电层图案，如图44至图48所示，图44为图5、图8、图11和图14中第五导电层的平面示意图，图45为图5形成第五导电层后的平面示意图，图46为图8形成第五导电层后的平面示意图，图47为图11形成第五导电层后的平面示意图，图48为图14形成第五导电层后的平面示意图。在示例性实 施方式中，第五导电层可以称为第二源漏金属(SD2)层。
在示例性实施方式中，如图44至图48所示，第五导电层至少可以包括：数据信号线DL、第一电源线VDDL、平坦部BL以及位于至少一个子像素的连接电极L。多条数据信号线DL沿第一方向D1排布，多条第一电源线VDDL沿第一方向D1排布。
在示例性实施方式中，如图44至图48所示，数据信号线DL的形状可以为至少部分沿第二方向D2延伸的线形状。第一电源线VDDL的形状可以为至少部分沿第二方向D2延伸的线形状。子像素所连接的第一电源线VDDL位于子像素所连接数据信号线DL靠近下一列子像素的一侧。
在示例性实施方式中，如图44至图48所示，相邻数据信号线DL相对于沿第二方向D2延伸的虚拟直线对称。相邻第一电源线VDD相对于沿第二方向D2延伸的虚拟直线对称。
在示例性实施方式中，子像素所连接的数据信号线DL和第一电源线VDDL位于子像素的连接电极的同一侧，且数据信号线DL位于第一电源线VDDL远离连接电极的一侧。
在示例性实施方式中，如图44至图48所示，第一电源线VDDL与其中一条相邻电源线连接，且与另一条相邻电源线之间间隔设置。间隔设置的两条第一电源线之间设置有两条数据信号线DL。或者相邻子像素所连接的第一电源线可以间隔设置，间隔设置的第一电源线可以关于第一连接线L1或第二连接线L2镜像对称。
在示例性实施方式中，如图44至图48所示，平坦部BL设置在两个相邻的第一电源线VDDL之间，且与相邻的两个第一电源线VDDL连接。
在示例性实施方式中，如图44至图48所示，平坦部BL的形状可以为方形。
在示例性实施方式中，如图44至图48所示，平坦部BL在基底上的正投影可以与第一晶体管的有源层的沟道区和第二晶体管的有源层的沟道区在基底上的正投影至少部分交叠。
在示例性实施方式中，如图44至图48所示，平坦部BL在基底上的正投影与第二扫描信号线、第一扫描信号线和第一初始信号线在基底上的正投影至少部分交叠。
在示例性实施方式中，如图44至图48所示，相邻两列子像素连接的第一电源线以及相邻子像素行的两个平坦部所组成的结构中包括多个环形区域。
在示例性实施方式中，环形区域的结构可以为对称结构，或者可以为不对称结构，图44至图48是以环形区域的结构为对称结构为例进行说明的。
在示例性实施方式中，位于同一行的相邻平坦部可以对称设置，或者可以不对称设置，可以根据所连接的发光器件的第一电极的形状确定。图44至图48是以位于同一行的相邻平坦部可以对称设置为例进行说明的。
在示例性实施方式中，如图44和图47所示，图5和图10提供的显示基板中，第一初始连接部在基底上的正投影位于相邻两列子像素的第一电源线、以及相邻子像素行两个平坦部构成的环形区域内。
在示例性实施方式中，如图44至图48所示，连接电极L的形状可以为至少部分沿第二方向D2的线形状或者沿第一方向D1延伸的线形状。连接电极被配置为与后续形成的发光器件的第一电极连接。不同发光器件的第一电极连接的连接电极的形状可以不同。
在示例性实施方式中，如图45和图48所示，数据信号线DL通过第十三过孔与第四 晶体管的第一极电连接。第一电源线VDDL通过第十四过孔与第五晶体管的第一极连接，连接电极L通过第十五过孔与第六晶体管的第二极(也是第七晶体管的第二极)连接。
在示例性实施方式中，如图46和图47所示，数据信号线DL通过第十二过孔与第四晶体管的第一极电连接。第一电源线VDDL通过第十三过孔与第五晶体管的第一极连接，连接电极L通过第十四过孔与第六晶体管的第二极(也是第七晶体管的第二极)连接。
(10)形成第二平坦层图案，包括：在形成有前述图案的基底上，涂覆第如图平坦薄膜，通过图案化工艺对第二平坦薄膜进行图案化，形成覆盖前述图案的第二平坦层图案，第二平坦层开设有多个过孔图案，如图49至图52所示，图49为图5提供的显示基板形成第二平坦层后的平面示意图，图50为图8提供的显示基板形成第二平坦层后的平面示意图，图51为图11提供的显示基板形成第二平坦层后的平面示意图，图52为图14提供的显示基板形成第二平坦层后的平面示意图。
在示例性实施方式中，如图49和图52所示，图5和图14提供的显示基板中第二平坦层的多个过孔至少包括：位于至少一个子像素的第十六过孔V16。
在示例性实施方式中，如图49和图52所示，第十六过孔V16在基底上的正投影位于连接电极在基底上的正投影的范围之内，暴露出连接电极的表面，第十六过孔V16被配置为使后续形成的发光器件的第一电极通过该过孔与连接电极连接。
在示例性实施方式中，如图50所示，图8提供的显示基板中第二平坦层的多个过孔至少包括：位于至少一个子像素的第十五过孔V15和第十六过孔V16。
在示例性实施方式中，如图50所示，第十五过孔V15在基底上的正投影位于连接电极在基底上的正投影的范围之内，暴露出连接电极的表面，第十五过孔V15被配置为使后续形成的发光器件的第一电极通过该过孔与连接电极连接。
在示例性实施方式中，如图50所示，第十六过孔V16在基底上的正投影位于第二初始信号线的第二初始连接部在基底上的正投影的范围之内，暴露出第二初始信号线的第二初始连接部的表面，第十六过孔V16内的第六绝缘层被刻蚀掉，第十六过孔V16被配置为使后续形成的第二初始信号线的第一初始连接部通过该过孔与第二初始信号线的第二初始连接部连接。
在示例性实施方式中，如图51所示，图11提供的显示基板中第二平坦层的多个过孔至少包括：位于至少一个子像素的第十五过孔V15。
在示例性实施方式中，如图51所示，第十五过孔V15在基底上的正投影位于连接电极在基底上的正投影的范围之内，暴露出连接电极的表面，第十五过孔V15被配置为使后续形成的发光器件的第一电极通过该过孔与连接电极连接。
至此，在基底上制备完成驱动电路层。在平行于显示基板的平面内，驱动电路层可以包括多个像素电路，像素电路与第一扫描信号线、第二扫描信号线、发光信号线、第一初始信号线、第二初始信号线、复位信号线、数据信号线和第一电源线连接。驱动电路层可以设置在基底上。驱动电路层可以包括在基底上依次设置的第一半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第二半导体层、第四绝缘层、第三导电层、第五绝缘层、第四导电层、第六绝缘层、第一平坦层、第五导电层和第二平坦层。
在示例性实施方式中，第一半导体层可以为非晶硅层或者多晶硅层。
在一种示例示例性实施例中，第二半导体层可以为金属氧化物层。其中，金属氧化物层可以采用包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧 化物或者包含铟或镓和锌的氧化物。金属氧化物层可以单层，或者可以是双层，或者可以是多层。
在示例性实施方式中，第一导电层、第二导电层、第三导电层、第四导电层和第五导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层、第五绝缘层和第六绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。
在示例性实施方式中，第一平坦层和第二平坦层可以采用有机材料，如树脂等。
在示例性实施方式中，制备完成驱动电路层后，在驱动电路层上制备发光结构层，发光结构层的制备过程可以包括如下操作。
(10)形成第六导电层图案。在示例性实施方式中，形成第六导电层图案可以包括：在形成前述图案的基底上，沉积第六导电薄膜，采用图案化工艺对第六导电薄膜进行图案化，形成设置在第二平坦层上的第六导电层，第六导电层至少包括多个第一电极图案，如图53至图59所示，图53为图5和图11中第六导电层的平面示意图，图54为图5形成第六导电层后的平面示意图，图55为图11形成第六导电层后的平面示意图，图56为图8中第六导电层的平面示意图，图57为图8形成第六导电层后的平面示意图，图58为图14中第六导电层的平面示意图，图59为图14形成第六导电层后的平面示意图。
在示例性实施方式中，如图53至图59所示，图5、图8、图11和图14的显示面板中第六导电层可以包括：多个第一电极图案。多个第一电极图案可以包括第一发光器件的第一电极AL1、第二发光器件的第一电极AL2、第三发光器件的第一电极AL3和第四发光器件的第一电极AL4，第一发光器件的第一电极AL1位于出射红色光线的红色子像素，第二发光器件的第一电极AL2可以位于出射蓝色光线的蓝色子像素，第三发光器件的第一电极AL3可以位于出射绿色光线的第一绿色子像素，第四发光器件的第一电极AL4可以位于出射绿色光线的第二绿色子像素。
在示例性实施方式中，第一发光器件的第一电极AL1和第二发光器件的第一电极AL2可以沿着第二方向D1交替设置，第三发光器件的第一电极AL3和第四发光器件的第一电极AL4可以沿着第二方向D1交替设置。或者，第一发光器件的第一电极AL1和第二发光器件的第一电极AL2可以沿着第一方向D2交替设置，第三发光器件的第一电极AL3和第四发光器件的第一电极AL4可以沿着第一方向D2交替设置。
在示例性实施方式中，第一发光器件的第一电极AL1、第二发光器件的第一电极AL2、第三发光器件的第一电极AL3和第四发光器件的第一电极AL4可以分别通过暴露出所在子像素的连接电极的过孔与所在子像素的连接电极。示例性地，如图54所示，图5提供的显示基板中发光器件的第一电极通过第十六过孔与连接电极电连接。如图55所示，图11提供的显示基板的发光器件的第一电极通过第十五过孔与连接电极连接。如图57所示，图8提供的显示基板的发光器件的第一电极通过十五过孔与连接电极连接。如图59所示，图14提供的显示基板的发光器件的第一电极通过第十六过孔与连接电极连接。
在示例性实施方式中，一个像素单元中四个子像素的第一电极形状和面积可以相同，或者可以不同。
在示例性实施方式中，第一发光器件的第一电极AL1、第二发光器件的第一电极AL2、第三发光器件的第一电极AL3和第四发光器件的第一电极AL4中的至少一个可以包括相 互连接的阳极主体部和阳极连接部，阳极连接部与连接电极连接。
在示例性实施方式中，第一发光器件的第一电极AL1可以包括相互连接的第一阳极主体部和第一阳极连接部，第一阳极主体部的形状可以为矩形状，矩形状的角部可以设置圆弧状的倒角，第一阳极连接部的形状可以为条形状。在示例性实施方式中，第二发光器件的第一电极AL2可以包括相互连接的第二阳极主体部和第二阳极连接部，第二阳极主体部的形状可以为矩形状，矩形状的角部可以设置圆弧状的倒角，第二阳极连接部的形状可以为条形状。在示例性实施方式中，第三发光器件的第一电极AL3可以包括相互连接的第三阳极主体部和第三阳极连接部，第三阳极主体部的形状可以为矩形状，矩形状的角部可以设置圆弧状的倒角，第三阳极连接部的形状可以为条形状。在示例性实施方式中，第四发光器件的第一电极AL4可以包括相互连接的第四阳极主体部和第四阳极连接部，第四阳极主体部的形状可以为矩形状，矩形状的角部可以设置圆弧状的倒角，第四阳极连接部的形状可以为条形状。
在示例性实施方式中，如图56和图57所示，图8提供的显示基板中第六导电层还可以包括：至少一条第二初始信号线的多个第一初始连接部INITL2A。第二初始连接部INITL2A沿第一方向D1延伸，多个第一初始连接部INITL2A沿第一方向D1排布。
在示例性实施方式中，如图57所示，第二初始信号线的第一初始连接部INITL2A在基底上的正投影与第二初始连接部在基底上的正投影至少部分交叠。
在示例性实施方式中，如图57所示，对于同一子像素，子像素所连接的第二初始信号线的第一初始连接部INITL2A在基底上的正投影位于子像素所连接的第一初始信号线在基底上的正投影远离子像素所连接的复位信号线基底上的正投影的一侧。
在示例性实施方式中，第二初始连接部与相邻的发光器件的第一电极之间的最小距离可以约为1微米至3微米。示例性地，第二初始连接部与相邻的发光器件的第一电极之间的最小距离可以约为2微米。
在示例性实施方式中，第二初始信号线的第一初始连接部INITL2A通过第十六过孔与第二初始连接部连接。
在示例性实施方式中，第六导电层采用单层结构，如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。
(11)形成阴极导电层图案。在示例性实施方式中，形成阴极导电层可以包括：在形成前述图案的基底上，涂覆像素定义薄膜，在形成前述图案的基底上，沉积像素定义薄膜，通过图案化工艺对像素定义薄膜进行图案化，形成暴露出第六导电层图案的像素定义层图案，在形成有像素定义层图案的基底上，涂覆有机发光材料，通过图案化工艺对有机发光材料进行图案化，形成有机结构层图案，在形成有机材料层图案的基底上，沉积阴极导电薄膜，通过图案化工艺对阴极导电薄膜进行图案化，形成阴极导电层。
在示例性实施方式中，后续制备流程可以包括：在阴极导电层上形成封装结构层，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
在示例性实施方式中，有机结构层至少可以包括：发光器件的有机发光层。
在示例性实施方式中，阴极导电层至少可以包括：多个发光器件的阴极。
在示例性实施方式中，阴极层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述导电的合金材料，如铝钕合金(AlNd)或钼 铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。示例性地，第四导电层可以为钛、铝和钛形成的三层堆叠结构。
本公开实施例通过的显示基板可以适用于任何分辨率的显示产品中。
本公开实施例还提供了一种显示装置，包括：显示基板。
显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
在示例性实施方式中，显示装置可以为：液晶面板、电子纸、OLED面板、有源矩阵有机发光二极管(active-matrix organic light emitting diode，简称AMOLED)面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (17)

  1. 一种显示基板，包括：基底和设置在所述基底上的多个子像素、多条复位信号线和多条第二初始信号线，所述子像素分别与复位信号线和第二初始信号线电连接，所述子像素包括：像素电路和发光器件，所述发光器件包括第一电极，所述像素电路包括：第一晶体管，所述复位信号线被配置为向第一晶体管的栅电极提供控制信号，所述第二初始信号线被配置为向发光器件的第一电极提供初始信号；
    所述复位信号线至少部分沿第一方向延伸，至少一条所述第二初始信号线包括：沿第一方向延伸的第一初始连接部和沿第二方向延伸的第二初始连接部，所述第二方向与所述第一方向相交；
    所述第一初始连接部在基底上的正投影与所述复位信号线在基底上的正投影不交叠，所述第二初始连接部在基底上的正投影与所述复位信号线在基底上的正投影部分交叠。
  2. 根据权利要求1所述的显示基板，还包括：设置在所述基底上的多条发光信号线，所述发光信号线至少部分沿所述第一方向延伸；
    子像素所连接的所述第二初始信号线中的第一初始连接部在基底上的正投影位于子像素所连接的所述复位信号线在基底上的正投影与子像素所连接的所述发光信号线在基底上的正投影之间。
  3. 根据权利要求2所述的显示基板，其中，所述第一初始连接部与所述第二初始连接部同层设置，且与所述第二初始连接部为一体结构。
  4. 根据权利要求2所述的显示基板，其中，所述第一初始连接部与第二初始连接部异层设置，所述第二初始连接部通过过孔与第一初始连接部连接。
  5. 根据权利要求4所述的显示基板，其中，所述复位信号线包括：异层设置，且相互连接的第一子复位信号线和第二子复位信号线；
    所述第一初始连接部位于所述第二初始连接部靠近所述基底的一侧，且与所述第一子复位信号线或者所述第二子复位信号线同层设置。
  6. 根据权利要求4所述的显示基板，其中，所述第一初始连接部位于所述第二初始连接部远离基底的一侧，且与所述第一电极同层设置。
  7. 根据权利要求6所述的显示基板，其中，所述第一初始连接部与相邻的发光器件的第一电极之间的最小距离约为1微米至3微米。
  8. 根据权利要求3至6任一项所述的显示基板，还包括：设置在所述基底上的多条第一扫描信号线和多条第一初始信号线，所述第一扫描信号线和所述第一初始信号线中的任一条至少部分沿所述第一方向延伸；
    至少一条所述第二初始连接线包括：多个第二初始连接部，且多个所述第二初始连接部沿第一方向排布；
    所述第二初始连接部在所述基底上的正投影还与所述第一扫描信号线和所述第一初始信号线在所述基底上的正投影部分交叠。
  9. 根据权利要求8所述的显示基板，其中，至少一条所述第二初始信号线还包括：多个第一初始连接部和多个沿所述第一方向延伸的第三初始连接部；多个所述第一初始连接部沿所述第一方向排布，多个所述第三初始连接部沿所述第一方向排布；
    相邻两个第二初始连接部通过第一初始连接部或者第三初始连接部连接，第二初始连 接部与其中一个相邻的第二初始连接部通过第一初始连接部连接，第二初始连接部与另一个相邻的第二初始连接部通过第三初始连接部连接。
  10. 根据权利要求9所述的显示基板，其中，子像素所连接的所述第二初始信号线的所述第三初始连接部在基底上的正投影位于子像素所连接的所述第一扫描信号线在基底上的正投影远离子像素所连接的所述复位信号线在基底上的正投影的一侧。
  11. 根据权利要求9或10所述的显示基板，其中，所述第二初始连接部和所述第三初始连接部同层设置，且为一体结构；
    所述第二初始连接部位于所述复位信号线所在的膜层和所述第一电源线所在的膜层之间。
  12. 根据权利要求5或6所述的显示基板，其中，至少一条所述第二初始信号线包括：一个第一初始连接部和多个第二初始连接部，多个所述第二初始连接部与所述第一初始连接部连接。
  13. 根据权利要求12所述的显示基板，还包括：至少部分沿所述第二方向延伸的多条第一连接线；所述第一连接线与所述第二初始连接部同层设置；
    至少一条所述第一连接线与多条所述第一初始信号线连接。
  14. 根据权利要求12或13所述的显示基板，还包括：至少部分沿所述第二方向延伸的第二连接线；所述第二连接线与所述第二初始连接部同层设置；
    至少一条所述第二连接线与多条所述第二初始信号线的所述第一初始连接部连接。
  15. 根据权利要求2所述的显示基板，还包括：平坦部和多条第二扫描信号线；所述像素电路还包括：第二晶体管，所述第一晶体管和所述第二晶体管为氧化物晶体管，所述第二扫描信号线至少部分沿所述第一方向延伸，且被配置为向所述第二晶体管的栅电极提供控制信号；
    所述平坦部与所述第一电源线同层设置，且相互连接；所述平坦部在基底上的正投影与第一晶体管的有源层、第二晶体管的有源层和至少一个发光器件的第一电极在基底上的正投影至少部分交叠。
  16. 一种显示基板，包括：基底和设置在所述基底上的多个子像素、多条复位信号线和多条第二初始信号线，所述子像素分别与复位信号线和第二初始信号线电连接，所述子像素包括：像素电路和发光器件，所述发光器件包括第一电极，所述像素电路包括：第一晶体管，所述复位信号线被配置为向第一晶体管的栅电极提供控制信号，所述第二初始信号线被配置为向发光器件的第一电极提供初始信号；
    所述复位信号线至少部分沿第一方向延伸，至少一条所述第二初始信号线包括：沿第一方向延伸的第一初始连接部和第三初始连接部以及沿第二方向延伸的第二初始连接部，所述第二方向与所述第一方向相交；
    所述第三初始连接部在基底上的正投影与所述复位信号线在基底上的正投影之间的距离小于所述第三初始连接部在基底上的正投影与所述第一初始连接部在基底上的正投影之间的距离。
  17. 一种显示装置，包括：如权利要求1至15任一项所述的显示基板或者如权利要求16所述的显示基板。
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