WO2023105965A1

WO2023105965A1 - Solid-state imaging element, and imaging device

Info

Publication number: WO2023105965A1
Application number: PCT/JP2022/039734
Authority: WO
Inventors: 靖久栃木; 勇佑松村; 克彦半澤
Original assignee: ソニーセミコンダクタソリューションズ株式会社
Priority date: 2021-12-06
Filing date: 2022-10-25
Publication date: 2023-06-15
Also published as: JPWO2023105965A1

Abstract

[Problem] To provide, with the present disclosure: a solid-state imaging element that can execute arithmetic processing and suppress enlargement of the solid-state imaging element; and an imaging device. [Solution] In order to solve the above problem, the present disclosure provides a solid-state imaging element that comprises: a plurality of pixel areas constituted by a plurality of pixels; and a plurality of first power storage units corresponding to the pixel areas respectively. The plurality of pixels in the pixel areas have a photoelectric conversion unit, a power storage unit corresponding to the photoelectric conversion unit, a first element that establishes a conductive state or a non-conductive state between the photoelectric conversion unit and the power storage unit, and a second element that establishes a conductive state or a non-conductive state between the power storage units of vertically and/or horizontally adjacent pixels. At least any of the second elements included in the plurality of pixels is connected to the first power storage units.

Description

Solid-state imaging device and imaging device

The present disclosure relates to solid-state imaging devices and imaging devices.

Processing of image data captured by a solid-state image sensor is generally performed by an external device to the solid-state image sensor. If the basic operation of image processing such as convolution operation is performed by the solid-state imaging device of the imaging device, the speed of cooperation with external equipment will be increased, and the user's convenience will be improved.

Japanese Patent Application No. 2019-519793

On the other hand, if you try to use the solid-state imaging device of the imaging device to perform arithmetic processing such as convolution, there is a risk that the solid-state imaging device will become large.

Therefore, the present disclosure provides a solid-state imaging device and an imaging device that are capable of performing arithmetic processing while suppressing an increase in the size of the solid-state imaging device.

In order to solve the above problems, according to the present disclosure, a plurality of pixel regions each composed of a plurality of pixels;
a plurality of first charge storage units corresponding to each of the pixel regions;
A plurality of pixels in the pixel region are
a photoelectric conversion unit;
a power storage unit corresponding to the photoelectric conversion unit;
a first element that establishes a conducting state or a non-conducting state between the photoelectric conversion unit and the electricity storage unit;
a second element that brings into a conducting state or a non-conducting state with the electricity storage portion of a pixel that is adjacent to at least one of the vertical direction and the horizontal direction;
A solid-state imaging device is provided in which at least one of the second elements of the plurality of pixels is connected to the first electricity storage unit.

The plurality of pixels may be of a front side illumination type or a back side illumination type.

The accumulation time of the photoelectric conversion unit may be controlled by the first element.

The pixels are
further comprising a third element that establishes a conducting state or a non-conducting state between the photoelectric conversion unit and a predetermined potential line;
The accumulation time of the photoelectric conversion unit may be controlled by the third element.

a second power storage unit that accumulates accumulated charges;
and a fourth element that establishes a conductive state or a non-conductive state between the first power storage unit and the second power storage unit.

When the number of pixels in the pixel region is nHxnV, the number of the second elements in the pixel region may be 2xnHxnV.

When the number of pixels in the pixel region is nHxnV, the number of the second elements in the pixel region may be nHxnV+nH or nHxnV+nV.

The photoelectric conversion element in the pixel region and the second element may be configured in different layers.

The photoelectric conversion unit may be made of at least one of silicon, indium gallium arsenide, and organic germanium.

The first and second elements may be composed of at least one of silicon, an oxide semiconductor, and an organic semiconductor.

The first element may be brought into a conducting state after the photoelectric conversion period of the photoelectric conversion unit is finished.

The photoelectric conversion period of the photoelectric conversion unit may be controlled according to the weight value of the arithmetic processing.

The pixel area may be changeable with respect to the corresponding first power storage unit.

The range of the pixel area with respect to the first power storage unit may be changed according to the calculation range of the calculation process.

The first power storage unit, the power storage unit, and the second power storage unit may be floating diffusion units.

An amplifier circuit that amplifies a signal corresponding to the charge accumulated in the first electricity storage unit as a voltage signal may be further provided.

The amplifier circuit may constitute a source follower circuit, and the voltage signal may be read based on time information of pulse width modulation.

an analog-to-digital converter that is electrically connected to the fifth element and that converts into digital data corresponding to accumulated electric charges by photoelectric conversion for each pixel region;
You may also prepare.

In order to solve the above problems, according to the present disclosure,
a solid-state imaging device;
and an arithmetic processing unit capable of performing a convolution operation,
An imaging apparatus is provided in which the information on the pixel region corresponding to the weight value and the calculation range is supplied from the arithmetic processing unit.

In the arithmetic processing unit,
first digital data generated by an analog-to-digital converter after the photoelectric conversion period of the photoelectric converter is controlled according to the positive weight value of the arithmetic processing and transferred to the first electricity storage unit;
The photoelectric conversion period of the photoelectric conversion unit is controlled according to the absolute value of the negative weight value of the arithmetic processing, and the second digital signal generated by the analog-to-digital conversion unit after being transferred to the first storage unit You may calculate the difference of data and.

1 is a block diagram showing a configuration example of an imaging device according to an embodiment of the present technology; FIG. The figure which shows an example of the laminated structure of a solid-state image sensor. FIG. 2 is a block diagram showing a configuration example of a solid-state imaging device; FIG. 4 is a diagram schematically showing pixels arranged in a matrix in a pixel array section; FIG. 4 is a diagram showing a configuration example of a reading unit; FIG. 4 is a diagram showing a configuration example of a pixel array section; 4A and 4B are diagrams showing configurations of pixels; FIG. FIG. 2 is a circuit diagram showing a configuration example of a pixel circuit; FIG. 7 is a plan view of the light receiving chip of the pixel array section shown in FIG. 6 as seen from the back side; FIG. 7 is a plan view of another configuration example of the light-receiving chip of the pixel array section shown in FIG. 6 as viewed from the back side; FIG. 4 is a diagram schematically showing a cross section of a main part of a pixel array section; FIG. 4 is a diagram showing addition ranges for respective timings and corresponding floating diffusions; FIG. 13 is a diagram showing addition ranges at timings different from those in FIG. 12; FIG. 14 is a diagram showing addition ranges at timings different from those in FIG. 13 ; (1) The figure which shows an example of the weight value of 3x3 in Formula. FIG. 13 is a timing chart showing a processing example of the addition range A11 at timing t1 in FIG. 12; FIG. FIG. 13 is a timing chart showing another processing example of the addition range at timing t1 in FIG. 12; FIG. FIG. 4 is a circuit diagram showing a configuration example of a pixel circuit AFD according to a modification of the first embodiment; FIG. 4 is a circuit diagram showing a configuration example of a pixel circuit according to a second embodiment; FIG. 20 is a plan view of the pixel array portion shown in FIG. 19; FIG. 11 is a diagram showing a configuration example of a pixel array section according to the third embodiment; FIG. 22 is a plan view of the pixel array portion shown in FIG. 21; FIG. 11 is a diagram showing a configuration example of a pixel array section according to the fourth embodiment; FIG. 12 is a diagram showing a configuration example of a pixel according to the fourth embodiment; FIG. 24 is a plan view of the light-receiving chip of the pixel array section shown in FIG. 23 as viewed from the rear side; FIG. 11 is a timing chart showing an example of processing according to the fourth embodiment of the addition range; FIG. The figure which shows typically the example of a process with respect to the weight value of (1) Formula which concerns on 5th Embodiment.

Hereinafter, embodiments of a solid-state imaging device and an imaging device will be described with reference to the drawings. Although the main components of the imaging sensor and the imaging device will be mainly described below, the solid-state imaging device and the imaging device may have components and functions that are not illustrated or described. The following description does not exclude components or features not shown or described.

(First embodiment)
FIG. 1 is a block diagram showing a configuration example of an imaging device 100 according to an embodiment of the present technology. This imaging apparatus 100 includes an imaging lens 110 , a solid-state imaging device 200 , a recording section 120 , a control section 130 , an analysis section 140 , a communication section 150 and a speaker section 160 . The imaging device 100 is, for example, a smart phone, a mobile phone, a PC (Personal Computer), or the like.

The imaging lens 110 collects incident light and guides it to the solid-state imaging device 200 . The solid-state imaging device 200 has a plurality of gradation pixels. The gradation pixel outputs a luminance signal corresponding to the amount of received light. Further, the solid-state imaging device 200 is capable of weighted addition of luminance signals of a plurality of pixels for gradation, for example. In addition, below, the pixel for gradation may be called a pixel.

The solid-state imaging device 200 can perform predetermined signal processing such as weighted addition at the analog signal stage, and outputs the processed data to the recording unit 120 via the signal line 209 .

The recording unit 120 records data from the solid-state imaging device 200 and the like. The control unit 130 controls the imaging device 100 as a whole. For example, the control unit 130 controls the solid-state imaging device 200 to capture image data.

The analysis unit 140 can perform recognition processing using, for example, a neural network. The analysis unit 140 has an arithmetic processing unit 142 . The arithmetic processing unit 142 can cause the solid-state imaging device 200 to perform arithmetic processing such as convolution on data of each pixel captured by the solid-state imaging device 200 in the analog signal stage.

In addition, the analysis unit 140 can also perform predetermined analysis processing, image processing, etc., using the calculation result of the calculation processing unit 142, for example. For example, the arithmetic processing such as the convolution operation performed by the arithmetic processing unit 142 as described above is performed by the solid-state imaging device 200 at the stage of the analog signal, and the subsequent arithmetic processing is performed by the arithmetic processing unit 142 .

The communication unit 150 performs wireless communication with an external device. Thereby, content or the like is received from an external server and recorded in the recording unit 120 via the control unit 130 . The control unit 130 causes the display unit 170 to display an image based on this content, for example.

The speaker unit 160 has a highly directional speaker and can transmit audio information only to the user. The speaker unit 160 can change the direction in which sound is transmitted.

FIG. 2 is a diagram showing an example of the layered structure of the solid-state imaging device 200 according to the embodiment of the present technology. This solid-state imaging device 200 includes a detection chip 202 and a light receiving chip 201 stacked on the detection chip 202 . These substrates are electrically connected through connections such as vias. In addition to vias, Cu--Cu bonding or bumps may be used for connection. Note that functions corresponding to the recording unit 120, the control unit 130, and the analysis unit 140 shown in FIG. 1 may be configured in the detection chip 202. FIG. In this case, the configuration related to imaging and imaging processing of the imaging device 100 is configured within the layered structure of the solid-state imaging device 200 . Also, the light receiving chip 201 and the detection chip 202 may be configured in the same layer.

FIG. 3 is a block diagram showing a configuration example of the solid-state imaging device 200. As shown in FIG. As shown in FIG. 3, the solid-state imaging device 200 according to the present disclosure includes a pixel array section 30, an accumulation control circuit 210, a first access control circuit 211a, a second access control circuit 211b, and a third access control circuit. 211 c , a reading unit 212 , a signal processing unit 213 , a second signal processing unit 214 , a timing control circuit 214 and an output interface 215 . For example, the pixel array unit 30 is configured in the light receiving chip 201, and includes an accumulation control circuit 210, a first access control circuit 211a, a second access control circuit 211b, a third access control circuit 211c, a reading unit 212, The signal processing section 213 , the second signal processing section 214 , the timing control circuit 214 and the output interface 215 may be configured within the detection chip 202 .

Here, the configuration of the pixel array section 30 will be described based on FIG. FIG. 4 is a diagram schematically showing pixels Pix arranged in a matrix in the pixel array section 30. As shown in FIG. As shown in FIG. 4, in the pixel array section 30, a plurality of pixels Pix are two-dimensionally arranged in a matrix (array). Also, one floating diffusion FDa is arranged for a processing area Afd corresponding to a predetermined number of pixels Pix. In the pixel array section 30 according to the present embodiment, a floating diffusion FD is configured for each pixel Pix, and accumulated charges for each floating diffusion FD are integrated by the floating diffusion FDa. Details of the pixel Pix, the processing area Afd, and the floating diffusion FDa will be described later. The pixel array unit 30 has a configuration in which the present technology is applied to a so-called backside illumination type image sensor in which the back side is illuminated with light. Of course, the present technology may be applied to a front side illuminated image sensor.

The pixel array section 30 is, for example, a CMOS image sensor. For example, the processing area Afd corresponds to the addition range of the floating diffusion FDa described later with reference to FIGS. 11 to 13. FIG. This configuration example of the pixel array unit 30 is an example suitable for, for example, a 3×3 weighting filter, but is not limited to this.

As shown in FIG. 3 again, the accumulation control circuit 210 controls the photoelectric conversion units of the pixels Pix. That is, the accumulation control circuit 210 can control resetting of accumulated charges in each of the plurality of photoelectric conversion units, generation of accumulated charges according to weight values, and the like. The accumulation control circuit 210 executes a control command according to the weight value of the arithmetic processing section 142 (see FIG. 1) via the control section 130 (see FIG. 1). Details of the photoelectric conversion unit will also be described later.

The first access control circuit 211a can control the connection of the floating diffusions FD of the plurality of pixels Pix in the row direction, for example, via signal lines HSW1 to HSW3 (see FIG. 6). The second access control circuit 211b can control the connection of the floating diffusions FD of the plurality of pixels Pix in the column direction, for example, via signal lines VSW1 to VSW3 (see FIG. 6).

The third access control circuit 211c cooperates with the first access control circuit 211a and the second access control circuit 211b, resets the accumulated charges of the floating diffusions FD and FDa, charges the floating diffusions FD and FDa, and stores the charges of the floating diffusions FD and FDa. It is possible to control the amplification of the luminance signal according to the accumulated charge of the . Details of control examples of the storage control circuit 210, the first access control circuit 211a, the second access control circuit 211b, and the third access control circuit 211c will also be described later.

A configuration example of the reading unit 212 will be described based on FIG. FIG. 5 is a diagram showing a configuration example of the reading unit 212. As shown in FIG. The reading unit 212 has a plurality of constant current sources 220 and a plurality of analog-to-digital conversion units ADC230. A plurality of constant current sources 220 and a plurality of AD converters ADC230 are provided corresponding to a plurality of signal lines VSL, respectively.

One end of the constant current source 220 is connected to the corresponding signal line VSL, and the other end is grounded. The constant current source 21 generates a current corresponding to the accumulated charge of the selected floating diffusion FDa (see FIG. 4) as the image luminance signal Sig for the corresponding signal line VSL.

The AD conversion unit ADC230 is configured to perform AD conversion based on the signal Sig on the corresponding signal line VSL. That is, the AD conversion unit ADC230 converts the analog gradation luminance signal Sig supplied via the vertical signal line VSL into a digital signal by time division. The AD converter ADC230 supplies the generated digital signal to the signal processor 213 .

As shown in FIG. 3 again, the signal processing section 213 performs predetermined signal processing on the digital signal from the reading section 212 . The signal processing unit 213 supplies the data indicating the processing result and the detection signal to the recording unit 120 via the signal line 209 .

The timing control circuit 214 controls the timing of each component of the solid-state imaging device 200 based on the time stamp information. For example, the timing control circuit 212d performs the processes of the accumulation control circuit 210, the first access control circuit 211a, the second access control circuit 211b, the third access control circuit 211c, the reading unit 212, and the signal processing unit 213. Control timing. The output interface 215 outputs image data, which is a digital signal supplied from the signal processing unit 213 , to the recording unit 120 .

Here, a detailed configuration example of the pixel array section 30 will be described with reference to FIGS. 6 to 10. FIG. FIG. 6 is a diagram showing a configuration example of the pixel array section 30. As shown in FIG. For example, it is a configuration example of 3×3 pixels Pix on the upper left with respect to FDa in FIG. FIG. 7 is a diagram showing a configuration example of a pixel Pix. As shown in FIG. 7, the pixel Pix has switching elements TR1 to TR3, a photoelectric converter PD, and a floating diffusion FD. The photoelectric conversion part PD is an element that generates charges proportional to incident light, and is made of at least one of silicon, indium gallium arsenide, and organic germanium, for example. The switching elements TR1 to TR3 are composed of, for example, at least one of silicon, an oxide semiconductor, and an organic semiconductor.

As shown in FIG. 6, the accumulation control lines TRG1-9 connect between each pixel Pix and the accumulation control circuit 210 (see FIG. 3). Pulsed control signals Trg1-Trg9 are supplied from the storage control circuit 210 to the storage control lines TRG1-TRG9.

The horizontal control lines HSW1-HSW3 connect between the pixels Pix in each row and the first access control circuit 211a (see FIG. 3). Pulsed control signals Hsw1-3 are supplied to the horizontal control lines HSW1-HSW3 from the first access control circuit 211a (see FIG. 3).

The vertical control lines VSW1-3 connect between the pixels Pix in each column and the second access control circuit 211b (see FIG. 3). Pulse-shaped control signals Vsw1-3 are supplied to the vertical control lines VSW1-3 from the second access control circuit 211b.

The control lines RSTL and RSEL (see FIG. 8 described later) connect between each pixel circuit AFD and the third access control circuit 211c (see FIG. 3). The control lines RSTL and RSEL are supplied with pulse-shaped control signals Rst and Sel from the third access control circuit 211c. In addition, the third access control circuit 211c can perform the reset operation and accumulation operation of the floating diffusions FD and FDa in conjunction with the accumulation control circuit 210, the first access control circuit 211a and the second access control circuit 211b. is.

As shown in FIG. 7, the switching elements TR1 to T3 are, for example, N-type MOS (Metal Oxide Semiconductor) transistors. The floating diffusion FD is configured using, for example, a diffusion layer formed on the surface of the semiconductor substrate.

One end of the switching element TR1 is connected to the floating diffusion FD on the left, the other end of the switching element TR1 on the left, and one end of the switching element TR2 on the left. The other end of the switching element TR1 is connected to the floating diffusion FD, one end of the switching element TR1 on the right, and one end of the switching element TR2. Furthermore, the gate of the switching element TR1 is connected to the horizontal control line HSW. As a result, the switching element TR1 is in a connected state (on) when the control signals Hsw1-Hsw3 supplied via the horizontal control lines HSW1-3 are high, and is in a non-connected state (off) when the control signals Hsw1-3 are low. In this embodiment, the connected state (ON) of the switching element may be referred to as the conducting state, and the disconnected state (OFF) may be referred to as the non-conducting state.

One end of the switching element TR2 is connected to the other end of the upper adjacent switching element TR2, the floating diffusion FD, and one end of the right adjacent switching element TR1. The other end of the switching element TR2 is connected to one end of the adjacent switching element TR2 on the lower side. Furthermore, the gate of the switching element TR2 is connected to the vertical control line VSW. As a result, the switching element TR2 is in a connected state (on) when the control signals Vsw1-3 supplied via the horizontal control lines VSW1-3 are high, and is in a non-connected state (off) when the control signals Vsw1-3 are low. Note that the switching element TR2 may be referred to as a vertical transfer transistor.

One end of the switching element TR3 is connected to one end of the photoelectric conversion unit PD, and the other end is connected to the floating diffusion FD. Also, the gate of the switching element TR3 is connected to the storage control line TRG. As a result, the switching element TR3 is in a connected state (on) when the control signal Trg supplied via the storage control line TRG is high, and is in a non-connected state (off) when it is low. Note that the switching element TR3 may be referred to as a TRG transistor. As shown in FIG. 6, when the number of pixels in the addition range (filter range) is nHxnV, the number of switching elements TR1 and TR2 in the addition range is 2xnHxnV. Here, nH indicates the number of pixels in the row direction of the filter range, and nV indicates the number of pixels in the vertical direction of the filter range.

FIG. 8 is a circuit diagram showing a configuration example of the pixel circuit AFD. The pixel circuit AFD has a control line RSTL and a control line RSEL. One ends of the control lines RSTL and RSEL are connected to the third access control circuit 211c (see FIG. 3) as described above. A pulse-shaped control signal Rst is supplied to the control line RSTL by the third access control circuit 211c. Similarly, the control line SELL is supplied with a pulse-shaped control signal Sel by the third access control circuit 211c.

The pixel circuit AFD has three switching elements RST, AMP, SEL and a floating diffusion FDa. The switching elements RST, AMP, and SEL are, for example, N-type MOS (Metal Oxide Semiconductor) transistors. The floating diffusion FDa is configured using, for example, a diffusion layer formed on the surface of the semiconductor substrate. The switching elements ST, AMP, and SEL are made of, for example, at least one of silicon, an oxide semiconductor, and an organic semiconductor.

One end of the switching element RST is connected to the floating diffusion FDa, and the other end is connected to the power supply VDD. Also, the gate of the switching element RST is connected to the control line RSTL. As a result, the switching element RST is in a connected state (on) when the control signal Rst supplied via the control line RSTL is high, and is in a non-connected state (off) when it is low. Note that the switching element RST may be referred to as a reset transistor.

One end of the switching element AMP is connected to the power supply VDD, and the other end is connected to one end of the switching element SEL. Also, the gate of the switching element AMP is connected to the floating diffusion FDa. As a result, the switching element AMP supplies a voltage signal corresponding to the charge accumulated in the floating diffusion FDa to one end of the switching element SEL. Note that the switching element AMP may be referred to as an amplification transistor.

One end of the switching element SEL is connected to the other end of the switching element AMP, and the other end is connected to the signal line VSL. Also, the gate of the switching element SEL is connected to the control line RSEL. As a result, the switching element SEL is in a connected state (on) when the control signal Rsel supplied via the main line RSEL is high, and is in a non-connected state (off) when it is low. Note that the switching element SEL may be referred to as a route selection transistor.

With this configuration, for example, the switching element RST is rendered conductive based on the control signal Rst, and similarly, the switching elements TR1 and TR2 are rendered conductive based on the control signals Hsw1-3 and the control signals Vsw1-3. , the floating diffusion FDa, and the floating diffusion FD of each pixel are discharged. Then, the switching element RST becomes non-conductive based on the control signal Rst, and similarly, the switching elements TR1 and TR2 become non-conductive based on the control signals Hsw1-3 and the control signals Vsw1-3.

Next, after the exposure period of each photoelectric conversion unit PD ends, the switching elements TR1 and TR2 are brought into conduction based on the control signals Hsw1 to Hsw3 and the control signals Vsw1 to Vsw3. It accumulates charges transferred from the photoelectric conversion unit PD via the floating diffusion FD.

Next, the pixel circuit AFD is electrically connected to the signal line VSL by turning on the switching element SEL based on the control signal Sel. Thereby, the switching element AMP is connected to the constant current source 220 (see FIG. 5) of the reading section 212 and operates as a so-called source follower. A voltage signal corresponding to the voltage of the floating diffusion FDa at that time is output to the ADC 230 as the image luminance signal Sig as described above. Thus, the switching element AMP constitutes a source follower circuit, and the voltage signal is read based on the time information of pulse width modulation (PWM).

FIG. 9 is a plan view of the light-receiving chip 201 of the pixel array section 30 shown in FIG. 6 as seen from the rear side. As shown in FIG. 9, the photoelectric conversion units PD of each pixel Pix are arranged in a two-dimensional array. Switching elements TR1 to TR3 are arranged around the photoelectric conversion part PD. The other end of the switching element TR2 of the lower right pixel Pix in the upper left 3×3 pixel Pix drawing (see FIG. 6), the floating diffusion FDa and the gate of the switching element AMP, and one end of the switching element RST are Connected. Thus, the floating diffusion FD of each pixel is finally accumulated in the floating diffusion FDa and read out as the image luminance signal Sig.

FIG. 10 is a plan view of another configuration example when the light receiving chip 201 of the pixel array section 30 shown in FIG. 6 is viewed from the back side. In FIG. 10, the diffusion layer of the floating diffusion FD of three pixels is shared, and the number of floating diffusions FD is suppressed more than the pixel array section 30 of FIG. In FIG. 10, the control lines TRG1-9, HSW1-3, and VSW1-3 are omitted, but the control lines are connected to the gates of the switching elements in the same manner as in FIG.

FIG. 11 is a diagram schematically showing a cross section of a main part of the pixel array section 30. FIG. As shown in FIG. 11, a light receiving chip 201 (see FIG. 2) corresponds to the semiconductor layer 100S, and a detection chip 202 corresponds to the semiconductor layers 100T, 200T and 200S. In FIG. 11, the semiconductor layers 100S and 100T are indicated by the substrate 201a, and the semiconductor layers 200T and 200S are indicated by the substrate 201b. The

substrates

201a and 201b are electrically connected by, for example, through

electrodes

120E and 121E. The photoelectric conversion part PD, floating diffusion FD, and VSS contact region 118 have planar regions. The photoelectric conversion part PD is composed of, for example, a p-well layer 115 and an n-type semiconductor region 114 .

The switching element TR3 may be composed of a planar transistor. At this time, for example, a transfer gate TG is provided on the surface of the semiconductor layer 100S. For example, the side surfaces of this transfer gate TG are covered with sidewalls SW. The sidewall SW contains silicon nitride (SiN), for example. A gate insulating film is provided between the semiconductor layer 100S and the transfer gate TG. The transfer gate TG of each pixel Pix is provided, for example, so as to surround the floating diffusion FD in plan view.

The semiconductor layer 100S is provided with a pixel separation section 117 that separates the pixels ix from each other. The pixel separation portion 117 is formed extending in the normal direction of the semiconductor layer 100S (the direction perpendicular to the surface of the semiconductor layer 100S). The pixel separation section 117 is provided so as to separate the pixels Pix from each other, and has, for example, a grid-like planar shape (see FIG. 4). The pixel separation unit 117 electrically and optically separates the pixels Pix from each other, for example. The pixel separation section 117 includes, for example, a light shielding film 117A and an insulating film 117B. For example, tungsten (W) or the like is used for the light shielding film 117A. The insulating film 117B is provided between the light shielding film 117A and the p-well layer 115 or the n-type semiconductor region 114. As shown in FIG. The insulating film 117B is made of, for example, silicon oxide (SiO). The pixel separation section 117 has, for example, an FTI (Full Trench Isolation) structure and penetrates the semiconductor layer 100S. Although not shown, the pixel separation section 117 is not limited to the FTI structure penetrating the semiconductor layer 100S. For example, a DTI (Deep Trench Isolation) structure that does not penetrate the semiconductor layer 100S may be used. The pixel separation portion 117 extends in the normal direction of the semiconductor layer 100S and is formed in a partial region of the semiconductor layer 100S.

For example, a pinning region 116 is provided in the semiconductor layer 100S. The pinning region 116 is provided on the side surface of the pixel isolation portion 117 , specifically between the pixel isolation portion 117 and the p-well layer 115 or the n-type semiconductor region 114 . The pinning region 116 is composed of, for example, a p-type semiconductor region.

Next, operation examples will be described in more detail based on FIGS. 12 to 15. FIG. 12 to 14 are diagrams exemplifying the range of calculation processing of weighting calculation. FIG. 12 is a diagram showing addition ranges A11 to A22 at timings t1 to t3 and corresponding floating diffusions FD11 to FD22. Similarly, FIG. 13 shows the range of addition at timings t4 to t6, and FIG. 14 shows the range of addition at timings t7 to t9. 12 to 15, the addition ranges A11 to A22 and the corresponding floating diffusions FDa11 to FDa22 relatively indicate arbitrary regions of the pixel array section 30. FIG.

The addition range of the floating diffusion FDa11 is the addition range A11, the addition range of the floating diffusion FDa12 is the addition range A12, the addition range of the floating diffusion FDa21 is the addition range A21, and the addition range of the floating diffusion FDa22 is the addition range A22. be. Other floating diffusions FDan similarly have addition ranges An. In other words, in the 3×3 addition ranges A11 to A22, as shown in equation (1), the addition ranges overlap, so nine times of addition processing at timings t1 to t9 are performed within the imaging element 200. FIG. That is, nine images are captured at timings t1 to t9.

FIG. 15 is a diagram showing an example of 3×3 weight values w _ij in equation (1). For example, equation (1) is an example of addition processing used in the processing of the arithmetic processing unit 142 (see FIG. 1). The arithmetic processing unit 142 supplies, for example, the weight value _wij information of the equation (1) to the accumulation control circuit 210 (see FIG. 3) via the control unit 130 . In this embodiment, the weight value _wij may be referred to as a filter value, and the addition range may be referred to as a filter.

That is, in the weighting operation, as shown in equation (1), the image luminance signal Sigij is calculated by adding the weight value _wij to the luminance value _pij . where i, j indicate the position of the pixel Pix in the pixel array. That is, i indicates the position in the horizontal direction in the pixel array section 30, and j indicates the position in the vertical direction. Also, n and m are predetermined natural numbers and correspond to the range of addition. For example, n=m=1 for a 3×3 addition range. The luminance value p _ij corresponds to the charge accumulated in the photoelectric conversion unit PD in the pixel range Pix at positions i and j. In this case, the brightness values p _ij are added with different weight values w _ij during addition processing of image brightness signals Sigij (i−n≦i≦i+n, j−m≦j≦j+m). For example, when n=m=1, the luminance value _pij is added nine times with different weight values _wij . As can be seen from these, the addition range A11 in FIGS. 12 to 14 shows an example of the addition range in which the brightness value p _ij of the equation (1) is included in the addition process.

At timing t1, the charge proportional to the charge accumulated in the 3×3 floating diffusion FD in the addition range A11 is finally accumulated in the floating diffusion FDa11. Similarly, the charge proportional to the charge accumulated in the 3×3 floating diffusion FD in the addition range A12 is finally accumulated in the floating diffusion FDa12. Similarly, the charge proportional to the charge accumulated in the 3×3 floating diffusion FD in the addition range A21 is finally accumulated in the floating diffusion FDa11. Similarly, the charge proportional to the charge accumulated in the 3×3 floating diffusion FD in the addition range A22 is finally accumulated in the floating diffusion FDa22.

Next, at timing t2, the addition range A11 to A22 shifts to the right by one pixel range, and at timing t3, the addition range A11 to A22 further shifts to the right by one pixel range. As shown in FIG. 13, at timing t4, the addition range A11 to A22 shifts downward by one pixel range from the position at timing t1, and at timing t5, the addition range A11 to A22 further shifts to the right by one pixel. At timing t6, the addition range A11 to A22 is further shifted to the right by one pixel range. As shown in FIG. 14, next, at timing t5, the addition range A11 to A22 shifts downward by one pixel range from timing t4, and at timing t5, the addition range A11 to A22 shifts one pixel to the right. At timing t6, the addition range A11 to A22 is further shifted to the right by one pixel range. In this manner, in the calculation process of the weighting calculation shown in, for example, formula (1), the addition process is performed while changing the addition range A11 to A22 nine times.

More specifically, the accumulation control circuit 210 (see FIG. 3) supplies each pixel Pix with signals Trg1 to TrgH*V having time information proportional to the weight value _wij . Then, the photoelectric conversion unit PD of each pixel Pix performs photoelectric conversion based on the signals Trg1 to TrgH*V for a period of time proportional to the weight value _wij to accumulate charges. That is, in the present embodiment, a calculation corresponding to the weight value _wij is performed by performing photoelectric conversion for a time proportional to the weight value _wij . Then, the accumulated charge for each pixel Pix is finally transferred to the floating diffusion FDa.

FIG. 16 is a timing chart showing a processing example of the addition range A11 at timing t1 in FIG. A processing example of the addition range A11 will be described based on FIG. 16 while referring to FIGS.

As shown in FIG. 16, the vertical axis indicates Trg1-9, Rst, and Rsel in order from the top. The horizontal axis indicates time. The switching element RST of the pixel circuit AFD is turned on by the high level signal Rst, and the switching elements TR1 and TR2 are turned on based on the control signals Hsw1-3 and control signals Vsw1-3. As shown in FIGS. 12 to 14, the ranges of the switching elements TR1 and TR2 connected to the floating diffusion FDa are changed according to the area A11 from timings t1 to t9.

As a result, when the control signals Trg1 to Trg9 become high level signals, each switching element TR3 becomes conductive, and the charges in each photoelectric conversion unit PD and each floating diffusion FD and the charges in the floating diffusion FDa are supplied to the power supply VDD. Ejected and initialized. Then, when the control signals Trg1 to Trg9 transition from high level signals to low level signals, each photoelectric conversion unit PD accumulates electric charge according to the amount of received light for an accumulation time proportional to the weight value _wij .

After the signal Rst becomes a low level signal and the switching element RST becomes conductive, the signal Rst becomes a high level signal again. As a result, the charges in each floating diffusion FD and the charges in the floating diffusion FDa are discharged to the power supply VDD and initialized again. Subsequently, when the signal Rst becomes a low level signal again and the control signals Trg1 to Trg9 become a high level signal, the charges in each photoelectric conversion unit PD are transferred to each floating diffusion FD, and further transferred to the floating diffusion FDa. . That is, the charge corresponding to the processing result equivalent to the addition processing of formula (1) is transferred into the floating diffusion FDa. Then, when the signal Rsel becomes a high level signal, the switching element SEL becomes conductive, and the signal Sig proportional to the charge accumulated in the floating diffusion FDa is output to the conversion unit ADC 230 of the reading unit 212 (see FIG. 5) via the VSL line. be done.

The other addition ranges A12 to An are similarly driven at the same time, and charges corresponding to the addition ranges A12 to An are accumulated in each floating diffusion FDa. Then, as described above, each electric charge of the floating diffusion FDa connected to the same VS1 line is sequentially amplified and converted into a digital luminance signal in a time division manner.

FIG. 17 is a timing chart showing another processing example of the addition range A11 at timing t1 in FIG. A processing example of the addition range A11 will be described based on FIG. 16 while referring to FIGS. In the processing example shown in FIG. 16, the end points of the light receiving times of the photoelectric conversion units PD are aligned, whereas in the processing example shown in FIG. differ.

As shown in FIG. 17, the vertical axis indicates Trg1-9, Rst, and Rsel in order from the top. The horizontal axis indicates time. The switching element RST of the pixel circuit AFD is turned on by the high level signal Rst, and the switching elements TR1 and TR2 are turned on based on the control signals Hsw1-3 and control signals Vsw1-3. Thus, when the control signals Trg1 to Trg9 become high level signals, the charges in each photoelectric conversion unit PD, each floating diffusion FD, and the charges in the floating diffusion FDa are discharged to the power supply VDD and initialized. Then, when the control signals Trg1 to Trg9 transition from high level signals to low level signals, each photoelectric conversion unit PD accumulates electric charge according to the amount of received light for an accumulation time proportional to the weight value _wij .

The signal Rst becomes a low level signal, the switching element RST becomes conductive, the signal Rst becomes a high level signal again, and the charges in each floating diffusion FD and the charges in the floating diffusion FDa are discharged to the power supply VDD and initialized again. be done. Subsequently, the signal Rst becomes a low level signal again, and when the control signals Trg1 to Trg9 become high level signals according to the accumulation time proportional to the weight value _wij , the time proportional to the weight value _wij in each photoelectric conversion unit PD is reached. is transferred into each floating diffusion FD and further transferred into the floating diffusion FDa. That is, the charge corresponding to the processing result equivalent to the addition processing of formula (1) is transferred into the floating diffusion FDa. Then, when the signal Rsel becomes a high level signal, the switching element SEL becomes conductive, and the signal Sig proportional to the charge accumulated in the floating diffusion FDa is output to the conversion unit ADC 230 of the reading unit 212 (see FIG. 5) via the VSL line. be done.

As described above, according to the present embodiment, the photoelectric conversion unit _PD of each pixel Pix can A charge is accumulated by photoelectric conversion. As a result, since the charges accumulated in each pixel Pix are added, it is possible to perform a weighting operation (for example, equation (1)) using an analog signal.

In addition, since the charge accumulated in the floating diffusion FD of each pixel Pix can be transferred to the floating diffusion FDa, it is possible to change the position of the addition range A11 without providing only one floating diffusion FDa corresponding to the addition range A11. It becomes possible. As a result, even when the luminance value p _ij is added with a different weight value w _ij during addition processing of the image luminance signal Sigij (i−n≦i≦i+n, j−m≦j≦j+m), the floating diffusion FDa It becomes possible to cope without increasing the number. As a result, an increase in the size of the arithmetic element 200 can be suppressed.

(Modification 1 of the first embodiment)
In the imaging device 100 according to Modification Example 1 of the first embodiment, the pixel circuit AFD further includes a floating diffusion FDb, and the capacitance of the floating diffusion of the pixel circuit AFD can be switched. Differs from 100. Differences from the imaging apparatus 100 according to the first embodiment will be described below.

FIG. 18 is a circuit diagram showing a configuration example of a pixel circuit AFD according to a modification of the first embodiment. The pixel circuit AFD further has a floating diffusion FDb, a control line FGL, and a switching element FG. One end of the control line FGL is connected to the third access control circuit 211c (see FIG. 3). A control signal Fg is supplied to the control line FGL by the third access control circuit 211c. The switching element FG is, for example, an N-type MOS (Metal Oxide Semiconductor) transistor.

One end of the switching element RST is connected to the floating diffusion FDb, and the other end is connected to the power supply VDD. One end of the switching element FG is connected to the floating diffusion FDa, and the other end is connected to the floating diffusion FDb. Also, the gate of the switching element FG is connected to the control line FGL.

With this configuration, by making the switching element FG conductive, the floating diffusion FDa and the floating diffusion FDb are connected in parallel, making it possible to increase the capacitance. Therefore, it is possible to switch between using the floating diffusion FDa and using the floating diffusion FDa and the floating diffusion FDb according to the imaging light amount of the imaging device 200 .

When using the floating diffusion FDa and the floating diffusion FDb, the switching element FG and the switching element RST are brought into conduction based on the control signals Fg and Rst. Thereby, the charges accumulated in the floating diffusion FD and the floating diffusion FD2 are discharged. Next, based on the control signal Rst, the switching element RST is turned off. As a result, after the exposure period T ends, each switching element TR3 becomes conductive based on the control signal Trg. and store charges transferred via the floating diffusion FD.

Next, the pixel circuit AFD is electrically connected to the signal line VSL by turning on the switching element SEL based on the control signal Sel. Thereby, the switching element AMP is connected to the constant current source 220 (see FIG. 5) of the reading section 212 and operates as a so-called source follower. A voltage corresponding to the voltages of the floating diffusion FDa and the floating diffusion FDb at that time is output to the ADC 230 as the image luminance signal Sig as described above.

When only the floating diffusion FDa is used, the switching element FG and the switching element RST are brought into conduction based on the control signals Fg and Rst. Thereby, the charges accumulated in the floating diffusion FDa and the floating diffusion FDb are discharged. Next, the switching element FG is turned off based on the control signal Fgt. As a result, after the exposure period T is completed, each switching element TR3 is turned on based on the control signal Trg, and the floating diffusion FDa is switched from each photoelectric conversion unit PD. Accumulates the charges transferred via the element TR3 and the floating diffusion FD. After that, the same processing as described above is performed.

As described above, in the imaging device 100 according to the modified example of the first embodiment, the pixel circuit AFD further includes the floating diffusion FDb. This makes it possible to switch the capacitance of the floating diffusion in accordance with the amount of light received by the solid-state imaging device 200, and to adjust the imaging sensitivity and the storage charge capacity.

(Second embodiment)
The imaging device 100 according to the second embodiment differs from the imaging device 100 according to the first embodiment in that the number of switching elements TR1 in the Afd region (see FIG. 4) of the pixel array section 30 is reduced to one row. do. Differences from the imaging apparatus 100 according to the first embodiment will be described below.

FIG. 19 is a diagram showing a configuration example of the pixel array section 30 according to the second embodiment. For example, it is a configuration example of 3×3 pixels Pix on the upper left with respect to FDa in FIG. The configuration differs from that of the pixel array section 30 according to the first embodiment in that only three switching elements TR1 are arranged for one row. In the example of the 3×3 addition range (filter range), if the switching elements TR1 are three elements for one row, the range of the photoelectric conversion unit PD and the floating diffusion FD connected to the floating diffusion FDa11 can be changed, for example, from FIGS. The addition range A11 in FIG. 14 can be changed.

Similarly, when the switching element TR1 is arranged for each pixel Pix, in the example of the addition range of 3×3, the switching element TR2 may be three elements for one column. Also in this case, the range of the photoelectric conversion unit PD and the floating diffusion FD connected to the floating diffusion FDa11 can be changed to, for example, the addition range A11 of FIGS. 12 to 14. FIG. Thus, when the number of pixels in the addition range is nHxnV, the number of switching elements TR1 and TR2 in the addition range is nHxnV+nH or nHxnV+nV. Here, nH indicates the number of pixels in the addition range in the row direction, and nV indicates the number of pixels in the addition range in the vertical direction.

20 is a plan view of the pixel array section 30 shown in FIG. 19. FIG. As shown in FIG. 20, the pixel array section 30 according to the second embodiment has a configuration in which the number of switching elements TR1 in the Afd region (see FIG. 4) of the pixel array section 30 is reduced to one row or one column. be.

As described above, in the imaging device 100 according to the present embodiment, the number of switching elements TR1 in the Afd region of the pixel array section 30 is reduced to one row or one column. Accordingly, the size of the pixel array section 30 can be reduced by reducing the number of switching elements TR1 or TR2.

(Third embodiment)
The imaging device 100 according to the third embodiment is different from the second embodiment in that the pixel array section 30 is configured by a photoelectric conversion layer (PD layer) and a pixel transistor layer (pixel Tr layer) via the connection section C10. It is different from the imaging device 100 according to the form. Differences from the imaging apparatus 100 according to the second embodiment will be described below.

FIG. 21 is a diagram showing a configuration example of the pixel array section 30 according to the third embodiment. For example, it is a configuration example of 3×3 pixels Pix on the upper left with respect to FDa in FIG. 22 is a plan view of the pixel array section 30 shown in FIG. 21. FIG. As shown in FIGS. 21 and 22, the pixel array section 30 according to the third embodiment includes a photoelectric conversion layer (PD layer) and a pixel transistor layer (pixel Tr layer) via a connection section C10. . The photoelectric conversion layer includes a photoelectric conversion unit PD of each pixel Pix and a switching element TR3. On the other hand, the pixel transistor layer includes switching elements TR1 and TR2, switching element SEL. AMP and RST are configured.

As described above, the imaging device 100 according to the present embodiment reduces the number of switching elements TR1 in the Afd region (see FIG. 4) of the pixel array section 30 to one row or one column, and (PD layer) and a pixel transistor layer (pixel Tr layer). Accordingly, by reducing the number of switching elements TR1 or TR2, the size of the pixel array section 30 can be reduced, and the plane area of the pixel array section 30 can be reduced.

(Fourth embodiment)
The imaging apparatus 100 according to the fourth embodiment is different from the imaging apparatus 100 according to the first embodiment in that it further includes a switching element TR4 capable of initializing the photoelectric conversion unit PD of the pixel array unit 30 independently of the floating diffusion FD. differ. Differences from the imaging apparatus 100 according to the first embodiment will be described below. FIG. 23 is a diagram showing a configuration example of the pixel array section 30 according to the fourth embodiment. For example, it is a configuration example of 3×3 pixels Pix on the upper left with respect to FDa in FIG. In FIG. 23, the wiring of TRG1-9 is omitted. FIG. 24 is a diagram showing a configuration example of a pixel Pix according to the fourth embodiment.

As shown in FIGS. 23 and 24, the pixel Pix differs from the pixel Pix according to the first embodiment in that it further includes a switching element TR4. One end of the switching element TR4 is connected to the pixel Pix, and the other end is connected to the power supply VDD. Also, the gate of the switching element TR4 is connected to the control line OFG. The control lines OFG 1 - 9 are connected to the accumulation control circuit 210 . As a result, the switching element TR4 is connected (ON) when the control signal Ofg supplied from the storage control circuit 210 via the main line OFG is high, and is disconnected (OFF) when it is low. Note that the switching element TR4 may be referred to as an OFG transistor. Also, as in the imaging device 100 according to the second embodiment, the number of switching elements TR1 or TR2 may correspond to one row or one column. That is, in an example of 3×3 addition filters, the number of switching elements TR1 or TR2 may be three.

FIG. 25 is a plan view of the light-receiving chip 201 of the pixel array section 30 shown in FIG. 23, viewed from the rear side. As shown in FIG. 25, the photoelectric conversion units PD of each pixel Pix are arranged in a two-dimensional array. Switching elements TR1 to TR4 are arranged around the photoelectric conversion part PD. The other end of the switching element TR2 of the lower right pixel Pix in the upper left 3×3 pixel Pix drawing (see FIG. 6), the floating diffusion FDa and the gate of the switching element AMP, and one end of the switching element RST are Connected. Thus, the charge of the floating diffusion FD of each pixel Pix is finally accumulated in the floating diffusion FDa and read out as the image luminance signal Sig.

FIG. 26 is a timing chart showing a processing example of the addition range A11 at timing t1 in FIG. 12 according to the fourth embodiment. As shown in FIG. 26, the vertical axis indicates the control signals Ofg1-9, Trg1-9, Rst and Rsel in order from the top. The horizontal axis indicates time.

When the control signals Ofg1 to Ofg9 become high level signals, each switching element TR4 becomes conductive, and the electric charge in each photoelectric conversion unit PD is discharged to the power supply VDD and initialized. Then, when the control signals Ofg1 to Ofg9 transition from high level signals to low level signals, each photoelectric conversion unit PD accumulates charges according to the amount of received light for an accumulation time proportional to the weight value _wij .

The signal Rsel becomes a high level signal and the switching element SEL becomes conductive. Subsequently, the switching element RST of the pixel circuit AFD is turned on by the high level signal Rst, and the switching elements TR1 and TR2 are turned on based on the control signals Hsw1-3 and control signals Vsw1-3. As a result, the charges in each floating diffusion FD and the charges in the floating diffusion FDa are discharged to the power supply VDD and initialized.

Subsequently, when the signal Rst becomes a low level signal and the control signals Trg1 to Trg9 simultaneously become a high level signal, the charges in each photoelectric conversion unit PD are transferred to each floating diffusion FD, and further transferred to the floating diffusion FDa. That is, the charge corresponding to the processing result equivalent to the addition processing of formula (1) is transferred into the floating diffusion FDa. Then, since the switching element SEL is in a conductive state, a signal Sig proportional to the charge accumulated in the floating diffusion FDa is output to the conversion unit ADC 230 of the readout unit 212 (see FIG. 5) through the VSL line.

In addition, since the charge accumulated in the floating diffusion FD of each pixel Pix can be transferred to the floating diffusion FDa, it is possible to change the position of the addition range A11 without providing only one floating diffusion FDa corresponding to the addition range A11. It becomes possible. As a result, even when the luminance value p _ij is added with a different weight value w _ij during addition processing of the image luminance signal Sigij (i−n≦i≦i+n, j−m≦j≦j+m), the floating diffusion FDa It becomes possible to cope without increasing the number. As a result, an increase in the size of the arithmetic element 200 can be suppressed. In this case, since each pixel Pix has the switching element TR4, the photoelectric conversion unit PD of the pixel array unit 30 can be initialized independently of the floating diffusion FD.
(Fifth embodiment)
The image pickup apparatus 100 according to the fifth embodiment differs from the image pickup apparatus 100 according to the first embodiment in that it can be driven when the weight value w _ij (F104) in equation (1) has a negative value. do. Differences from the imaging apparatus 100 according to the first embodiment will be described below.

FIG. 27 is a diagram schematically showing a processing example for the weight value w _ijj (F104) of the formula (1) according to the fifth embodiment. As shown in FIG. 27, in the first frame F100, positive access control circuit 210, first access control circuit 211a, second access control circuit 211b, and third access control circuit 211c control Accumulation of each photoelectric conversion element PD is performed for an accumulation time length corresponding to the weight value _wij having a value. Then, the charge of each pixel Pix is transferred to the floating diffusion FDa through the floating diffusion FD. After that, it is converted into a first digital signal by the AD conversion unit ADC230 (see FIG. 5) and recorded in the recording unit 120 (see FIG. 1). It is assumed that the accumulation time of the length corresponding to the weight value _wij having a negative value is zero.

In the second frame F102, the weight value w ij having a negative value is controlled by the accumulation control circuit 210, the first access control circuit 211a, the second access control circuit 211b, and the third access control circuit 211c _. Accumulation of each photoelectric conversion element PD is performed for an accumulation time length corresponding to the absolute value of (F104). Then, the charge between the photoelectric conversion units PD of each pixel Pix is transferred to the floating diffusion FDa via the floating diffusion FD. After that, it is converted into a second digital signal by the AD conversion section ADC 230 (see FIG. 5) and recorded in the recording section 120 (see FIG. 1). It is assumed that the accumulation time of the length corresponding to the weight value _wij having a positive value is zero.

Then, the arithmetic processing unit 142 calculates the difference between the first digital signal in the first frame F100 and the second digital signal in the second frame F102 recorded in the recording unit 120 (see FIG. 1), generates a digital signal corresponding to the weight value w _ij (F104) of . In this case, the calculation result corresponding to the weight value w _ij (F104) of the equation (1) is generated as a numerical value.

As described above, the imaging apparatus 100 according to the fifth embodiment performs accumulation in each photoelectric conversion element PD for an accumulation time length corresponding to the weight value _wij having a positive value, and obtains the first digital signal. Convert. Subsequently, accumulation is performed in each photoelectric conversion element PD for an accumulation time length corresponding to the absolute value of the weight value _wij having a negative value, and is converted into a second digital signal. Subsequently, the arithmetic processing unit 142 subtracts the second digital signal from the first digital signal. This makes it possible to drive arithmetic processing when the weight value w _ij (F104) in equation (1) has a negative value.

This technology can be configured as follows.

(1)
a plurality of pixel regions composed of a plurality of pixels;
a plurality of first charge storage units corresponding to each of the pixel regions;
A plurality of pixels in the pixel region are
a photoelectric conversion unit;
a power storage unit corresponding to the photoelectric conversion unit;
a first element that establishes a conducting state or a non-conducting state between the photoelectric conversion unit and the electricity storage unit;
a second element that brings into a conducting state or a non-conducting state with the electricity storage portion of a pixel that is adjacent to at least one of the vertical direction and the horizontal direction;
A solid-state imaging device, wherein at least one of the second elements included in the plurality of pixels is connected to the first electricity storage section.

(2)
The solid-state imaging device according to (1), wherein the plurality of pixels are front side illumination type or back side illumination type.

(3)
The solid-state imaging device according to (2), wherein the accumulation time of the photoelectric conversion unit is controlled by the first element.

(4)
The pixels are
further comprising a third element that establishes a conducting state or a non-conducting state between the photoelectric conversion unit and a predetermined potential line;
The solid-state imaging device according to (2), wherein the accumulation time of the photoelectric conversion unit is controlled by the third element.

(5)
a second power storage unit that accumulates accumulated charges;
a fourth element (FG) that establishes a conducting state or a non-conducting state between the first power storage unit and the second power storage unit;
The solid-state imaging device according to (1), further comprising:

(6)
The solid-state imaging device according to (1), wherein the number of the second elements in the pixel region is 2xnHxnV when the number of pixels in the pixel region is nHxnV.

(7)
The solid-state imaging device according to (1), wherein the number of the second elements in the pixel region is nHxnV+nH or nHxnV+nV, where nHxnV is the number of pixels in the pixel region.

(8)
The solid-state imaging device according to (1), wherein the photoelectric conversion element in the pixel region and the second element are configured in different layers.

(9)
The solid-state imaging device according to (1), wherein the photoelectric conversion section is made of at least one of silicon, indium gallium arsenide, and organic germanium.

(10)
The solid-state imaging device according to (1), wherein the first and second elements are composed of at least one of silicon, an oxide semiconductor, and an organic semiconductor.

(11)
The solid-state imaging device according to (1), wherein the first element is rendered conductive after the photoelectric conversion period of the photoelectric conversion section ends.

(12)
The solid-state imaging device according to (3), wherein a photoelectric conversion period of the photoelectric conversion unit is controlled according to a weight value of arithmetic processing.

(13)
The solid-state imaging device according to (1), wherein the pixel area can be changed with respect to the corresponding first electricity storage unit.

(14)
The solid-state imaging device according to (12), wherein the range of the pixel region for the first electricity storage unit is changed according to the computation range of computation processing.

(15)
The solid-state imaging device according to (5), wherein the first electricity storage unit, the electricity storage unit, and the second electricity storage unit are floating diffusion units.

(16)
The solid-state imaging device according to (1), further comprising an amplifier circuit that amplifies a signal corresponding to the charge accumulated in the first electricity storage unit as a voltage signal.

(17)
The solid-state imaging device according to (16), wherein the amplifier circuit constitutes a source follower circuit, and the voltage signal is read based on time information of pulse width modulation.

(18)
(14) the solid-state imaging device; and
and an arithmetic processing unit capable of performing a convolution operation,
The imaging device, wherein the weight value and the information of the pixel area corresponding to the calculation range are supplied from the calculation processing unit.

(19)
In the arithmetic processing unit,
first digital data generated by an analog-to-digital converter after the photoelectric conversion period of the photoelectric converter is controlled according to the positive weight value of the arithmetic processing and transferred to the first electricity storage unit;
The photoelectric conversion period of the photoelectric conversion unit is controlled according to the absolute value of the negative weight value of the arithmetic processing, and the second digital signal generated by the analog-to-digital conversion unit after being transferred to the first storage unit The imaging device according to (18), which calculates the difference between the data and the.

Aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that can be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. That is, various additions, changes, and partial deletions are possible without departing from the conceptual idea and spirit of the present disclosure derived from the content defined in the claims and equivalents thereof.

100: imaging device,
142: arithmetic processing unit,
200: image sensor,
210: Accumulation control circuit,
A11 to A22: addition range (pixel range),
FG: switching element (fourth element),
FD: Floating diffusion (storage unit),
FDa: floating diffusion (first power storage unit),
FDb floating diffusion (second power storage unit),
PD: photoelectric conversion unit,
TR1: switching element (second element),
TR2: switching element (second element),
TR3: switching element (first element),
TR4: Switching element (third element).

Claims

a plurality of pixel regions composed of a plurality of pixels;
a plurality of first charge storage units corresponding to each of the pixel regions;
A plurality of pixels in the pixel region are
a photoelectric conversion unit;
a power storage unit corresponding to the photoelectric conversion unit;
a first element that establishes a conducting state or a non-conducting state between the photoelectric conversion unit and the electricity storage unit;
a second element that brings into a conducting state or a non-conducting state with the electricity storage portion of a pixel that is adjacent to at least one of the vertical direction and the horizontal direction;
A solid-state imaging device, wherein at least one of the second elements included in the plurality of pixels is connected to the first electricity storage unit.
The solid-state imaging device according to claim 1, wherein the plurality of pixels are front side illumination type or back side illumination type.
3. The solid-state imaging device according to claim 2, wherein the accumulation time of said photoelectric conversion unit is controlled by said first element.
The pixels are
further comprising a third element that establishes a conducting state or a non-conducting state between the photoelectric conversion unit and a predetermined potential line;
3. The solid-state imaging device according to claim 2, wherein the accumulation time of said photoelectric conversion section is controlled by said third element.
a second power storage unit that accumulates accumulated charges;
2. The solid-state imaging device according to claim 1, further comprising: a fourth element that brings a conductive state or a non-conductive state between said first power storage unit and said second power storage unit.
2. The solid-state imaging device according to claim 1, wherein the number of said second elements in said pixel region is 2xnHxnV when the number of pixels in said pixel region is nHxnV.
2. The solid-state imaging device according to claim 1, wherein the number of said second elements in said pixel region is nHxnV+nH or nHxnV+nV when the number of pixels in said pixel region is nHxnV.
The solid-state imaging device according to claim 1, wherein the photoelectric conversion element in the pixel region and the second element are configured in different layers.
The solid-state imaging device according to claim 1, wherein the photoelectric conversion section is composed of at least one of silicon, indium gallium arsenide, and organic germanium.
The solid-state imaging device according to claim 1, wherein the first and second elements are composed of at least one of silicon, an oxide semiconductor, and an organic semiconductor.
2. The solid-state imaging device according to claim 1, wherein the first element is rendered conductive after the photoelectric conversion period of the photoelectric conversion section ends.
The solid-state imaging device according to claim 3, wherein the photoelectric conversion period of the photoelectric conversion unit is controlled according to the weight value of arithmetic processing.
The solid-state imaging device according to claim 1, wherein the pixel area can be changed with respect to the corresponding first power storage unit.
13. The solid-state imaging device according to claim 12, wherein the range of said pixel region for said first electricity storage unit is changed according to the computation range of computation processing.
The solid-state imaging device according to claim 5, wherein the first electricity storage unit, the electricity storage unit, and the second electricity storage unit are floating diffusion units.
2. The solid-state imaging device according to claim 1, further comprising an amplifier circuit that amplifies a signal corresponding to the charge accumulated in said first electricity storage unit as a voltage signal.
17. The solid-state imaging device according to claim 16, wherein said amplifier circuit constitutes a source follower circuit, and said voltage signal is read based on time information of pulse width modulation.
The solid-state imaging device according to claim 14;
and an arithmetic processing unit capable of performing a convolution operation,
The imaging device, wherein the weight value and the information of the pixel area corresponding to the calculation range are supplied from the calculation processing unit.
In the arithmetic processing unit,
first digital data generated by an analog-to-digital converter after the photoelectric conversion period of the photoelectric converter is controlled according to the positive weight value of the arithmetic processing and transferred to the first electricity storage unit;
The photoelectric conversion period of the photoelectric conversion unit is controlled according to the absolute value of the negative weight value of the arithmetic processing, and the second digital signal generated by the analog-to-digital conversion unit after being transferred to the first storage unit 19. The imaging device according to claim 18, which calculates a difference between data and .