JP2018050028A - Solid state image pickup device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state image pickup device that improves a light shielding property of a charge holding area to reduce variations in the amount of signal charge due to light made incident on the charge holding area, and reduces variations in transfer property due to the influence of a change in potential of wires in a wiring layer on the potential of the charge holding area.SOLUTION: The present solid state image pickup device comprises: a light receiving element, a charge holding area, and a floating diffusion area arranged on a semiconductor substrate; a first transfer gate that includes a gate electrode arranged on an area between the light receiving element and charge holding area on the semiconductor substrate with a gate insulating film therebetween; a second transfer gate that includes a gate electrode arranged on an area between the charge holding area and floating diffusion area on the semiconductor substrate with a gate insulating film therebetween; a wiring layer that includes wires arranged on the semiconductor substrate with a plurality of interlayer insulating films; and a light shielding film that is arranged on the semiconductor substrate side with respect to the wiring layer and shields the charge holding area from light.SELECTED DRAWING: Figure 7

Description

  The present invention relates to a solid-state imaging device and an electronic apparatus using the same.

  Conventionally, CCDs have been the mainstream as solid-state imaging devices. However, in recent years, CMOS sensors that can be driven at a low voltage and can also be embedded with peripheral circuits have been remarkably developed. The CMOS sensor has been developed into a device that surpasses CCDs in terms of mass, with countermeasures by manufacturing processes such as complete transfer technology and dark current prevention structure and measures such as CDS (correlated double sampling). doing. The factor of the CMOS sensor leap is that the image quality has been greatly improved. One of them is the improvement of charge transfer technology.

  As a related technique, Patent Document 1 discloses a solid-state imaging device having a high spatial resolution by arranging a plurality of semiconductor elements that can realize complete transfer of signal charges as pixels. The semiconductor element includes a first conductive type semiconductor region, a second conductive type light receiving surface embedded region that is embedded in the upper portion of the semiconductor region, and a light receiving surface embedded in the upper portion of the semiconductor region. A charge accumulation region of the second conductivity type that accumulates the signal charge generated by the buried region, a charge readout region that accepts the signal charge accumulated in the charge accumulation region, and a signal from the light receiving surface buried region to the charge accumulation region First potential control means for transferring charges, and second potential control means for transferring signal charges from the charge storage region to the charge readout region.

Japanese Patent Laying-Open No. 2008-103647 (paragraphs 0006-0007, FIG. 3)

  FIG. 3 of Patent Document 1 shows a light shielding film 41 made of a metal thin film such as aluminum (Al) provided on any one of a plurality of interlayer insulating films having a multilayer wiring structure. . The opening 42 of the light shielding film 41 is selectively provided so that photocharge is generated in the semiconductor substrate 1 immediately below the light receiving cathode region 11a constituting the photodiode D1.

  However, depending on the distance between the light shielding film 41 and the semiconductor substrate 1, sufficient light shielding characteristics of the charge storage region 12a located next to the light receiving cathode region 11a cannot be obtained, and light enters the charge storage region 12a. As a result, the amount of signal charge transferred to the charge readout region 13 may fluctuate.

  Further, due to capacitive coupling between the charge storage region (hereinafter also referred to as a charge holding region) and the wiring in the wiring layer, the potential change in the signal wiring or the control wiring in the wiring layer affects the potential in the charge holding region. Thus, the potential distribution may be disturbed, and transfer characteristics may vary among pixels.

  Some aspects of the present invention improve the light shielding characteristics of the charge holding region, reduce fluctuations in the signal charge amount due to light incident on the charge holding region, and between the charge holding region and the wiring of the wiring layer. The present invention relates to providing a solid-state imaging device in which variation in transfer characteristics due to the influence of the change in the potential of the wiring in the wiring layer on the potential of the charge holding region is improved by reducing capacitive coupling. Further, some aspects of the present invention relate to providing an electronic device or the like using such a solid-state imaging device.

  The solid-state imaging device according to the first aspect of the present invention includes a light receiving element, a charge holding region, and a floating diffusion region disposed on a semiconductor substrate, and a region between the light receiving element and the charge holding region on the semiconductor substrate. A first transfer gate having a gate electrode arranged through a gate insulating film; and a gate electrode arranged through a gate insulating film on a region between the charge holding region and the floating diffusion region in the semiconductor substrate. A second transfer gate; a wiring layer including wiring disposed on the semiconductor substrate via a plurality of interlayer insulating films; and a light shielding film disposed on the semiconductor substrate side of the wiring layer to shield the charge holding region Is provided.

  According to the first aspect of the present invention, the light shielding film is arranged closer to the semiconductor substrate than the wiring layer, thereby improving the light shielding characteristics of the charge holding region, and the amount of signal charge caused by light incident on the charge holding region. Variations can be reduced. In addition, capacitive coupling between the charge holding region and the wiring of the wiring layer can be reduced, and variation in transfer characteristics due to the influence of the change in the potential of the wiring in the wiring layer on the potential of the charge holding region can be improved.

  Here, the light shielding film may be electrically connected to the gate electrode of the first transfer gate. In that case, for example, when a high-level control signal is supplied to the gate electrode of the first transfer gate and the first transfer gate is turned on, the charge holding region is affected by the influence of the electric field formed by the light shielding film. Therefore, electrons having negative charges are easily transferred from the light receiving element to the charge holding region.

  Alternatively, the light shielding film may be electrically connected to the gate electrode of the second transfer gate. In that case, for example, when a high-level control signal is supplied to the gate electrode of the first transfer gate and the first transfer gate is turned on, a low-level signal is applied to the gate electrode of the second transfer gate. A control signal is supplied. Therefore, it is possible to stabilize the potential distribution of the charge holding region by reducing the influence of the change in the potential of the upper wiring layer on the light shielding film on the potential of the charge holding region.

  Alternatively, the light shielding film may be electrically connected to a wiring to which a power supply potential on the low potential side is supplied. In that case, since the potential of the light shielding film is always constant, it is possible to reduce the influence of the potential change of the wiring in the upper layer of the light shielding film on the potential of the charge retention region and stabilize the potential distribution of the charge retention region. it can.

  In the above, the solid-state imaging device includes four light receiving elements arranged in one row, four charge holding regions arranged corresponding to the four light receiving elements, four floating diffusion regions, and four first transfer gates. And four second transfer gates, and a light shielding layer that shields the four charge holding regions, and the four floating diffusion regions may be electrically connected to the gate electrode of one buffer transistor. . In that case, the four charge holding regions can be shielded by one light shielding layer.

  The solid-state imaging device may further include a wiring arranged at the same height as the light shielding film in the region where the logic circuit is arranged. In that case, the manufacturing process of the solid-state imaging device can be simplified by forming the light shielding film and the wiring of the logic circuit at the same time.

  Alternatively, the light shielding film may be disposed in a layer independent of the wiring layer in the region where the logic circuit is disposed. In that case, for example, by arranging a light shielding film at a position lower than the wiring of the logic circuit, the light shielding characteristics of the charge holding region are further improved, or the capacitance between the charge holding region and the wiring of the wiring layer Bonding can be further reduced.

  Further, the light shielding film may include a first layer containing aluminum or copper and a second layer containing titanium nitride disposed on the semiconductor substrate side of the first layer. Titanium nitride has a property that it is less likely to reflect light than aluminum, copper, or alloys thereof. Accordingly, by disposing the second layer containing titanium nitride on the semiconductor substrate side of the first layer, the light reflected by the main surface of the semiconductor substrate and then reflected again by the lower surface of the light shielding film and entering the charge holding region The amount of can be reduced.

  Here, it is desirable that the film thickness of the second layer be in the range of 50 nm to 80 nm. As a result, the second layer has a film thickness necessary and sufficient for exhibiting the properties of titanium nitride that hardly reflects light. The light-shielding film may further include a third layer that is disposed on the semiconductor substrate side of the second layer and contains titanium. In that case, the bonding property of the second layer containing titanium nitride to the base layer can be improved by the third layer containing titanium.

  An electronic apparatus according to a second aspect of the present invention includes any one of the solid-state imaging devices described above. According to the second aspect of the present invention, variation in the signal charge amount due to light incident on the charge holding region is reduced, and variation in transfer characteristics due to the influence of the change in the wiring potential of the wiring layer on the potential of the charge holding region. By using a solid-state imaging device with improved image quality, it is possible to provide an electronic device with improved image quality of image data obtained by imaging a subject.

The perspective view which shows the structural example of a CIS module. The block diagram which shows the structural example of the scanner apparatus using a CIS module. The block diagram which shows the structural example of an image sensor chip. FIG. 6 is a circuit diagram showing an equivalent circuit of a pixel portion and a readout circuit portion for one pixel. The circuit diagram which shows the example of the unit block in a line sensor. 1 is a plan view of a part of a solid-state imaging device according to a first embodiment of the present invention. Sectional drawing in VII-VII shown in FIG. Sectional drawing of a part of solid-state imaging device which concerns on the 2nd Embodiment of this invention. Sectional drawing of a part of solid-state imaging device which concerns on the 3rd Embodiment of this invention. The top view of a part of solid-state imaging device which concerns on the modification of the 1st Embodiment of this invention. The top view which shows the light shielding film arrange | positioned continuously over several unit blocks. The top view of a part of solid-state imaging device which concerns on the modification of the 2nd Embodiment of this invention. The top view of a part of solid-state imaging device which concerns on the modification of the 3rd Embodiment of this invention. The top view of a part of solid-state imaging device which concerns on the 4th Embodiment of this invention. Sectional drawing in XV-XV shown in FIG. The top view of a part of solid-state imaging device which concerns on the modification of the 4th Embodiment of this invention. Sectional drawing of the solid-state imaging device which concerns on the 5th Embodiment of this invention. Sectional drawing which shows the example of a light shielding film.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same referential mark is attached | subjected to the same component and the overlapping description is abbreviate | omitted.
<Electronic equipment>
In the following, a CIS scanner using a contact image sensor (CIS) module including a solid-state imaging device (image sensor chip) according to any embodiment of the present invention as an electronic apparatus according to an embodiment of the present invention. The apparatus will be described.

  FIG. 1 is a perspective view showing a configuration example of a CIS module, and FIG. 2 is a block diagram showing a configuration example of a scanner device using the CIS module shown in FIG. As shown in FIG. 1, the CIS module 10 includes a light guide 11 that irradiates light on the document 1, a lens array 12 that forms an image of reflected light from the document 1, and a photodiode that is disposed at the imaging position. And an image sensor 13 having a light receiving element.

  Referring to FIGS. 1 and 2, the CIS module 10 includes a light source 14 that generates light incident on an end of the light guide 11. In the case of a color scanner, the light source 14 includes, for example, red (R), green (G), and blue (B) LEDs. The three color LEDs are pulse-lit in a time division manner. The light guide 11 guides the light so that the light generated by the light source 14 is applied to the area of the document 1 along the main scanning direction A.

  The lens array 12 is composed of, for example, a rod lens array. The image sensor 13 has a plurality of pixels along the main scanning direction A, and moves in the sub scanning direction B together with the light guide 11 and the lens array 12.

  As shown in FIG. 2, the image sensor 13 may be configured by connecting a plurality of image sensor chips 20 in series. The CIS module 10 movable in the sub-scanning direction B is connected to a main substrate 16 fixed to the scanner device via a flexible wiring 15. On the main board 16, a system-on-chip (SoC) 17, an analog front end (AFE) 18, and a power supply circuit 19 are mounted.

  The system on chip 17 supplies a control signal, a clock signal, and the like to the CIS module 10. Pixel signals generated by the CIS module 10 are supplied to the analog front end 18. The analog front end 18 performs analog / digital conversion on the analog pixel signal and outputs digital pixel data to the system-on-chip 17.

  The power supply circuit 19 supplies a power supply voltage to the system-on-chip 17 and the analog front end 18 and supplies a power supply voltage, a reference voltage, and the like to the CIS module 10. Note that the analog front end 18, a part of the power supply circuit 19, or a light source driver may be mounted on the CIS module 10.

<Solid-state imaging device>
FIG. 3 is a block diagram illustrating a configuration example of an image sensor chip that is a solid-state imaging device according to any embodiment of the present invention. As shown in FIG. 3, the image sensor chip 20 includes a pixel unit 30, a readout circuit unit 40, and a control circuit unit 50, and may further include capacitors 61 to 64.

  In the pixel unit 30, light receiving elements (for example, photodiodes) are arranged in a plurality of pixels. The readout circuit unit 40 converts the signal charge output from the pixel unit 30 into a signal voltage and reads out pixel information. The control circuit unit 50 performs control for generating a pixel signal based on the output voltage of the readout circuit unit 40. For example, the control circuit unit 50 includes a correlated double sampling (CDS) circuit 51, an output circuit 52, and a logic circuit 53.

  The correlated double sampling circuit 51 performs correlated double sampling processing on the output voltage of the readout circuit unit 40. That is, the correlated double sampling circuit 51 samples the voltage immediately after the reset and the voltage after the exposure, and performs a difference process between them to cancel the reset noise and generate an output voltage corresponding to the light intensity. To do. The output circuit 52 generates and outputs a pixel signal based on the output voltage of the correlated double sampling circuit 51. A control signal, a clock signal, and the like are supplied to the logic circuit 53 from the system-on-chip 17 illustrated in FIG.

  The capacitor 61 is connected between the high-potential-side power supply potential wiring and the low-potential-side power supply potential wiring arranged in the first region AR1 of the image sensor chip 20, and stabilizes the power supply voltage. Further, the capacitors 62 to 64 are connected between the high-potential-side power supply potential wiring and the low-potential-side power supply potential wiring arranged in the second region AR2 of the image sensor chip 20, and supply the power supply voltage. Stabilize.

<Pixel part and readout circuit part>
FIG. 4 is a circuit diagram showing an equivalent circuit of a pixel portion and a readout circuit portion for one pixel. For example, a photodiode PD is disposed in one pixel of the pixel unit 30 illustrated in FIG. 3 as a light receiving element having a photoelectric conversion function. The photodiode PD generates and accumulates signal charges corresponding to the intensity of incident light.

  In order to read out the signal charge from the photodiode PD, the readout circuit section 40 shown in FIG. 3 includes a front transfer gate TG1, which is a first transfer gate, a charge holding capacitor C1, and a rear transfer gate, which is a second transfer gate. It includes TG2 and a charge retention capacitor C2. Further, the read circuit section 40 includes a transistor (also referred to as a buffer transistor in this application) QN1, a reset transistor QN2, and a selection transistor QN3 that constitute a read buffer amplifier. In the line sensor, when an analog shift register is provided in the final stage of the readout circuit unit 40, the selection transistor QN3 can be included in the analog shift register.

  Here, the pre-stage transfer gate TG1 constitutes a part of an N-channel MOS transistor having the cathode of the photodiode PD and the cathode of the storage diode (charge holding region CH) as the source and drain. Further, the storage diode constitutes a charge retention capacitor C1.

  Further, the post-transfer gate TG2 constitutes a part of an N-channel MOS transistor having the charge holding region CH and the N-type floating diffusion region (floating diffusion) FD disposed in the P-type semiconductor layer as the source and drain. ing. Further, the P-type semiconductor layer and the N-type floating diffusion region FD constitute a charge retention capacitor C2. In the present application, the semiconductor layer refers to a semiconductor substrate, a well formed in the semiconductor substrate, or an epitaxial layer formed on the semiconductor substrate.

  The photodiode PD, the front-stage transfer gate TG1, and the rear-stage transfer gate TG2 are connected in series between the low-potential-side power supply potential VSS line and the gate electrode of the buffer transistor QN1. The drain of the buffer transistor QN1 is connected to the wiring of the power supply potential VDD on the high potential side. In the following, it is assumed that the power supply potential VSS is the ground potential 0V.

  The reset transistor QN2 has a drain connected to the wiring of the power supply potential VDD, a source connected to the gate electrode of the buffer transistor QN1, and a gate electrode to which the reset signal RST is supplied. The selection transistor QN3 has a drain connected to the source of the buffer transistor QN1, a source connected to the output terminal of the readout circuit section 40, and a gate electrode to which the pixel selection signal SEL is supplied.

  The pre-stage transfer gate TG1 transfers the signal charge accumulated in the photodiode PD to the charge holding capacitor C1 when the control signal Tx1 is activated to a high level. The charge holding capacitor C1 holds the signal charge transferred by the previous transfer gate TG1. After the control signal Tx1 is deactivated to the low level, the control signal Tx2 is activated to the high level. The rear transfer gate TG2 transfers the signal charge held in the charge holding capacitor C1 to the charge holding capacitor C2 when the control signal Tx2 is activated to a high level. The charge holding capacitor C2 holds the signal charge transferred by the subsequent transfer gate TG2, and converts the signal charge into a signal voltage.

  The reset transistor QN2 resets the gate potential of the buffer transistor QN1 to an initial state potential (for example, the power supply potential VDD) when the reset signal RST is activated to a high level. When the reset is released, the buffer transistor QN1 outputs an output voltage corresponding to the signal voltage across the charge holding capacitor C2 from the source.

  The selection transistor QN3 selects the output voltage of the buffer transistor QN1 when the pixel selection signal SEL is activated to a high level. As a result, the output voltage of the buffer transistor QN1 is output to the output terminal of the read circuit section 40 via the selection transistor QN3 and becomes the output voltage Vs.

<Unit block of pixel portion and readout circuit portion>
FIG. 5 is a circuit diagram illustrating an example of a unit block of the pixel unit and the readout circuit unit in the line sensor. As shown in FIG. 5, four photodiodes PDa to PDd that are continuous in the main scanning direction A, and a readout circuit unit that reads out pixel information by converting signal charges transferred from the photodiodes PDa to PDd into signal voltages Constitutes one unit block 40A. For example, the number of unit blocks 40A provided in one line sensor is 216.

  The read circuit unit of the unit block 40A includes four front-stage transfer gates TG1a to TG1d, four rear-stage transfer gates TG2a to TG2d, one buffer transistor QN1, and one reset transistor QN2. That is, one buffer transistor QN1 and one reset transistor QN2 are shared by the four photodiodes PDa to PDd.

  Here, regardless of the resolution mode, the four pre-stage transfer gates TG1a to TG1d are simultaneously controlled to be in the on state. On the other hand, since each of the four photodiodes PDa to PDd constitutes one pixel, the four subsequent transfer gates TG2a to TG2d are controlled to be turned on at different timings. As a result, four output voltages corresponding to the signal charges of the four photodiodes PDa to PDd are output from the unit block 40A in a time division manner.

  FIG. 5 shows a control signal Tx1 commonly supplied to the four preceding transfer gates TG1a to TG1d and four control signals Tx2a to Tx2d supplied to the four succeeding transfer gates TG2a to TG2d, respectively. . As described above, since the four pre-stage transfer gates TG1a to TG1d are simultaneously turned on, the common control signal Tx1 is supplied.

  Here, the high-level potential may be different between the control signal Tx1 supplied to the preceding transfer gates TG1a to TG1d and the control signal Tx2a to Tx2d supplied to the succeeding transfer gates TG2a to TG2d, respectively. For example, the high level of the control signal Tx1 supplied to the pre-stage transfer gates TG1a to TG1d has a potential higher than the power supply potential VDD.

  That is, if the control signal Tx1 having a potential higher than the power supply potential VDD is supplied to the pre-stage transfer gates TG1a to TG1d, the pre-stage transfer gates TG1a to TG1d in the on state are saturated in charge transfer capability at an exposure intensity equal to or less than a specified value. The saturation level can be improved. Therefore, the signal charges accumulated in the photodiodes PDa to PDd can be transferred with high transfer capability, and an image with high contrast can be formed.

  On the other hand, as shown in FIG. 5, the control signals Tx2a to Tx2d are supplied from the CMOS logic circuits 70a to 70d to the subsequent transfer gates TG2a to TG2d, respectively. The CMOS logic circuits 70a to 70d are turned on in accordance with block selection signals Tx2 and Tx2r for selecting the unit block 40A, and supply timing signals Tx2a1 to Tx2d1 to the unit block 40A as control signals Tx2a to Tx2d. At this time, since the control signals Tx2a to Tx2d are generated without causing a voltage drop, the transfer capability of the subsequent transfer gates TG2a to TG2d can be increased.

  In FIG. 5, analog switches (transmission gates) composed of P-channel MOS transistors and N-channel MOS transistors are used as the CMOS logic circuits 70a to 70d. The configuration of the CMOS logic circuits 70a to 70d is as follows. It is not limited to. For example, as the CMOS logic circuits 70a to 70d, a circuit that does not cause a voltage drop, such as a clocked CMOS logic circuit or an AND gate circuit, can be used.

<First Embodiment>
FIG. 6 is a plan view of a part of the solid-state imaging device according to the first embodiment of the present invention, and FIG. 7 is a cross-sectional view taken along the line VII-VII shown in FIG. The solid-state imaging device according to the first embodiment is a line sensor in which a plurality of pixels are arranged in one row. FIG. 6 shows a configuration of a unit block of the pixel portion and the readout circuit portion shown in FIG.

As shown in FIGS. 6 and 7, this solid-state imaging device includes an N-type semiconductor substrate (Nsub) 100, a P well (P ⁻⁻ ) 110 formed in the semiconductor substrate 100, and a P well 110. An N-type impurity region (N ⁻ ) 121 formed, a charge holding region (CH) 122, and a floating diffusion region (FD) 123 are provided. The charge holding region 122 and the floating diffusion region 123 are high-concentration N-type impurity regions (N ⁺ ).

  As the semiconductor substrate 100, for example, a silicon (Si) substrate containing an N-type impurity such as phosphorus (P) or arsenic (As) is used. The P well 110 is formed, for example, by implanting P type impurity ions such as boron (B) into the semiconductor substrate 100 and performing thermal treatment to diffuse the impurities.

  The photodiode PDa has an anode composed of a P well 110 and a cathode composed of an N-type impurity region 121. A high-concentration P-type impurity region (pinning layer) may be disposed above the N-type impurity region 121 or the charge holding region 122. In the case where the pinning layer is provided, dark current generated in the N-type impurity region 121 or the charge holding region 122 can be reduced.

  As described above, the solid-state imaging device includes the light receiving element (photodiode PDa), the charge holding region 122, and the floating diffusion region 123 arranged on the semiconductor substrate 100. In addition, the solid-state imaging device includes a pre-stage transfer gate TG1a having a gate electrode 141 disposed via a gate insulating film on a region between the light receiving element and the charge holding region 122 in the semiconductor substrate 100, and a charge in the semiconductor substrate 100. A post-transfer gate TG2a having a gate electrode 142 disposed via a gate insulating film on a region between the holding region 122 and the floating diffusion region 123 is provided.

  The gate electrodes 141 and 142 are made of, for example, polysilicon doped with impurities and having conductivity. FIG. 6 also shows a buffer transistor QN1 and a reset transistor QN2.

  Furthermore, the solid-state imaging device is disposed on the semiconductor substrate 100 side of the wiring layer including wiring (signal wiring or control wiring) disposed on the semiconductor substrate 100 via a plurality of interlayer insulating films, A light-shielding film that shields the charge holding region 122 from light. That is, the light shielding film is disposed between the wiring of the wiring layer and the semiconductor substrate 100. Here, the interlayer insulating film may be two layers or three or more layers.

  In FIG. 7, as an example, an interlayer insulating film 150 disposed on the semiconductor substrate 100, a light shielding layer including a light shielding film 161 disposed on the interlayer insulating film 150, and an interlayer insulating film 150 and a light shielding layer are disposed. The interlayer insulating film 170 thus formed and wiring layers including wirings (signal wirings or control wirings) 181 to 184 disposed on the interlayer insulating film 170 are shown. The light shielding film 161 is disposed closer to the semiconductor substrate 100 than the wiring layer, and shields the charge holding region 122 from light.

The interlayer insulating films 150 and 170 are made of, for example, BPSG (Boron Phosphorus Silicon Glass) or silicon oxide film (SiO ₂ ). The light shielding film 161 and the wirings 181 to 184 include, for example, aluminum (Al) or copper (Cu).

  According to the above configuration, the light shielding film 161 is disposed closer to the semiconductor substrate 100 than the wiring layer, thereby improving the light shielding characteristics of the charge holding region 122 and reducing the amount of signal charge caused by light incident on the charge holding region 122. Variations can be reduced. In addition, capacitive coupling between the charge holding region 122 and the wirings 181 to 184 in the wiring layer is reduced, and variation in transfer characteristics due to the influence of the change in the wiring potential of the wiring layer on the potential of the charge holding region is improved. Can do.

  Further, the configuration of the photodiodes PDb to PDd and the like illustrated in FIG. 6 is the same as the configuration of the photodiode PDa and the like illustrated in FIG. Accordingly, the solid-state imaging device includes four light receiving elements (photodiodes PDa to PDd) arranged in a row and four charge holding regions arranged corresponding to the four light receiving elements in the unit block shown in FIG. 122, four floating diffusion regions 123, four front-stage transfer gates TG1a to TG1d, and four rear-stage transfer gates TG2a to TG2d.

  The four floating diffusion regions 123 are electrically connected to the gate electrode of one buffer transistor QN1. Further, the solid-state imaging device includes a light shielding layer that shields the four charge holding regions 122. In that case, the four charge holding regions 122 can be shielded from light by one light shielding layer. For example, the light shielding layer includes four light shielding films 161 that shield the four charge holding regions 122 from each other.

  In the contact hole formed in the interlayer insulating film 150, a plurality of contact plugs 151 and 152 containing, for example, tungsten (W), aluminum (Al), copper (Cu), or the like are disposed.

  In the first embodiment, the light shielding film 161 is electrically connected to the gate electrode 141 of the pre-stage transfer gate TG1a via the contact plug 151. In that case, when a high-level control signal is supplied to the gate electrode 141 of the previous-stage transfer gate TG1a and the previous-stage transfer gate TG1a is turned on, the charge holding region 122 is affected by the influence of the electric field formed by the light shielding film 161. Since the potential is increased, electrons having negative charges are easily transferred from the light receiving element (for example, the photodiode PDa) to the charge holding region 122.

  Note that the signal wiring 162 may be disposed in the light shielding layer. The signal wiring 162 electrically connects the floating diffusion region 123 and the gate electrode of the buffer transistor QN1 (FIG. 6) via the contact plug 152.

<Second Embodiment>
FIG. 8 is a partial cross-sectional view of a solid-state imaging device according to the second embodiment of the present invention. In the second embodiment, the light shielding film 161 is electrically connected to the gate electrode 142 of the post-transfer gate TG2a via the contact plug 153 disposed in the contact hole of the interlayer insulating film 150. Regarding other points, the second embodiment may be the same as the first embodiment.

  In that case, when a high-level control signal is supplied to the gate electrode 141 of the front-stage transfer gate TG1a and the front-stage transfer gate TG1a is turned on, a low-level control signal is applied to the gate electrode 142 of the rear-stage transfer gate TG2a. Supplied. Accordingly, the influence of the potential change of the wirings 181 to 184 on the upper layer of the light shielding film 161 on the potential of the charge holding region 122 can be reduced, and the potential distribution of the charge holding region 122 can be stabilized.

<Third Embodiment>
FIG. 9 is a partial cross-sectional view of a solid-state imaging apparatus according to the third embodiment of the present invention. In the third embodiment, the light shielding film 161 is electrically connected to the wiring to which the power supply potential VSS on the low potential side is supplied in the light shielding layer or the wiring layer. In other respects, the third embodiment may be the same as the first embodiment.

  In that case, since the potential of the light shielding film 161 is always constant, the influence of the potential change of the wirings 181 to 184 in the upper layer of the light shielding film 161 on the potential of the charge holding region 122 is reduced. The potential distribution can be stabilized.

<Modification of First Embodiment>
FIG. 10 is a plan view of a part of a solid-state imaging device according to a modification of the first embodiment of the present invention. FIG. 10 shows a specific arrangement example of the light shielding film 161 and the wirings 181 to 184 in addition to the components shown in FIG. Regarding other points, the modification of the first embodiment may be the same as that of the first embodiment.

  The light shielding film 161 disposed in the light shielding layer on the interlayer insulating film 150 (FIG. 7) is connected to the gates of the previous transfer gates TG1a to TG1d via the contact plugs 151a to 151d disposed in the contact holes of the interlayer insulating film 150. The electrode 141 is electrically connected. Accordingly, the plurality of charge holding regions 122 can be shielded from light by one light shielding film 161.

  Furthermore, as shown in FIG. 11, the light shielding film 161 may be continuously arranged across the plurality of unit blocks 40A. As a result, the charge holding regions 122 of the plurality of unit blocks 40 </ b> A can be shielded from light by one light shielding film 161. In that case, the light shielding film 161 is commonly connected to the gate electrodes 141 of the previous-stage transfer gates TG1a to TG1d in the plurality of unit blocks 40A.

  Further, the wirings 181 to 184 arranged in the wiring layer on the interlayer insulating film 170 (FIG. 7) are contact plugs 171a to 171d arranged in the contact holes of the interlayer insulating film 170 and the contact holes of the interlayer insulating film 150. Are electrically connected to the gate electrodes 142 of the rear-stage transfer gates TG2a to TG2d through four contact plugs (not shown) arranged in the, respectively. Thereby, the rear transfer gates TG2a to TG2d can be individually controlled.

<Modification of Second Embodiment>
FIG. 12 is a plan view of a part of a solid-state imaging device according to a modification of the second embodiment of the present invention. FIG. 12 shows a specific arrangement example of the light shielding films 161a to 161d and the wirings 180 to 184 in addition to the components shown in FIG. Regarding other points, the modification of the second embodiment may be the same as that of the second embodiment.

  The wiring 180 disposed in the wiring layer on the interlayer insulating film 170 (FIG. 8) is disposed in the contact plugs 170 a to 170 d disposed in the contact hole of the interlayer insulating film 170 and the contact hole of the interlayer insulating film 150. It is electrically connected to the gate electrodes 141 of the previous transfer gates TG1a to TG1d via four contact plugs (not shown).

  The wirings 181 to 184 arranged in the wiring layer on the interlayer insulating film 170 are shielded from light on the interlayer insulating film 150 (FIG. 8) via contact plugs 171a to 171d arranged in the contact holes of the interlayer insulating film 170. Each of the light shielding films 161a to 161d arranged in the layer is electrically connected.

  Further, the light shielding films 161a to 161d are electrically connected to the gate electrodes 142 of the rear transfer gates TG2a to TG2d through four contact plugs (not shown) disposed in the contact holes of the interlayer insulating film 150, respectively. Has been. Thereby, the rear transfer gates TG2a to TG2d can be individually controlled.

<Modification of Third Embodiment>
FIG. 13 is a plan view of a part of a solid-state imaging device according to a modification of the third embodiment of the present invention. FIG. 13 shows a specific arrangement example of the light shielding film 161 and the wirings 180 to 184 in addition to the components shown in FIG. Regarding other points, the modification of the third embodiment may be the same as that of the third embodiment.

  The wiring 180 disposed in the wiring layer on the interlayer insulating film 170 (FIG. 9) is disposed in the contact plugs 170 a to 170 d disposed in the contact hole of the interlayer insulating film 170 and the contact hole of the interlayer insulating film 150. It is electrically connected to the gate electrodes 141 of the previous transfer gates TG1a to TG1d via four contact plugs (not shown).

  The light-shielding film 161 disposed in the light-shielding layer on the interlayer insulating film 150 (FIG. 9) is electrically connected to the wiring to which the low-potential-side power supply potential VSS is supplied in the light-shielding layer or the wiring layer (FIG. 9). 9). Accordingly, the plurality of charge holding regions 122 can be shielded from light by one light shielding film 161.

  Furthermore, as shown in FIG. 11, the light shielding film 161 may be continuously arranged across the plurality of unit blocks 40A. As a result, the charge holding regions 122 of the plurality of unit blocks 40 </ b> A can be shielded from light by one light shielding film 161. In that case, the light shielding film 161 is commonly connected to the wiring to which the power supply potential on the low potential side is supplied in the plurality of unit blocks 40A.

  In addition, the wirings 181 to 184 arranged in the wiring layer on the interlayer insulating film 170 are arranged in the contact plugs 171 a to 171 d arranged in the contact hole of the interlayer insulating film 170 and the contact hole of the interlayer insulating film 150. The gate electrodes 142 of the rear transfer gates TG2a to TG2d are electrically connected to each other through four contact plugs (not shown). Thereby, the rear transfer gates TG2a to TG2d can be individually controlled.

<Fourth Embodiment>
FIG. 14 is a plan view of a part of a solid-state imaging device according to the fourth embodiment of the present invention, and FIG. 15 is a cross-sectional view taken along line XV-XV shown in FIG. The solid-state imaging device according to the fourth embodiment is an area sensor in which a plurality of pixels are arranged in a two-dimensional matrix. FIG. 14 shows a configuration of a pixel portion and a readout circuit portion for one pixel, and an equivalent circuit thereof is the same as the equivalent circuit shown in FIG.

  The area sensor has pixel portions and readout circuit portions arranged in a plurality of lines, and signal charges are simultaneously transferred from the light receiving elements of those lines to the respective charge holding regions CH (refer to FIG. 4 below). Transferred. This function is called a global shutter (electronic shutter).

  Thereafter, the signal charges held in the charge holding region CH of the sequentially selected lines are transferred to the floating diffusion region FD, the selection transistor QN3 is turned on, and the output voltage of the buffer transistor QN1 changes the selection transistor QN3. Via the output terminal of the readout circuit section.

As shown in FIGS. 14 and 15, this solid-state imaging device includes an N-type semiconductor substrate (Nsub) 100, a P well (P ⁻⁻ ) 110 formed in the semiconductor substrate 100, and a P well 110. N-type impurity regions 121 and 124 to 126 formed, a charge holding region (CH) 122, and a floating diffusion region (FD) 123 are provided. The photodiode PD has an anode composed of a P well 110 and a cathode composed of an N-type impurity region (N ⁻ ) 121.

  The floating diffusion region 123 shown in FIG. 14 constitutes the source of the reset transistor QN2. The N-type impurity region 124 constitutes the drain of the reset transistor QN2 and the drain of the buffer transistor QN1. The N-type impurity region 125 constitutes the source of the buffer transistor QN1 and the drain of the selection transistor QN3. The N-type impurity region 126 constitutes the source of the selection transistor QN3.

  On the region between the N-type impurity region 121 and the charge holding region 122 in the semiconductor substrate 100 in which the P well 110 is formed, the gate electrode 141 of the pre-stage transfer gate TG1 is disposed via the gate insulating film. Yes. On the region between the charge holding region 122 and the floating diffusion region 123 in the semiconductor substrate 100, the gate electrode 142 of the post-transfer gate TG2 is disposed via a gate insulating film.

  Similarly, on the region between the floating diffusion region 123 and the N-type impurity region 124, the gate electrode 143 of the reset transistor QN2 is disposed via a gate insulating film. On the region between the N-type impurity region 124 and the N-type impurity region 125, the gate electrode 144 of the buffer transistor QN1 is disposed via a gate insulating film. On the region between the N-type impurity region 125 and the N-type impurity region 126, the gate electrode 145 of the selection transistor QN3 is disposed via a gate insulating film. The gate electrodes 141 to 145 are made of, for example, polysilicon having conductivity doped with impurities.

  Further, for example, as shown in FIG. 15, the solid-state imaging device includes an interlayer insulating film 150 disposed on the semiconductor substrate 100, a light shielding layer including a light shielding film 161 disposed on the interlayer insulating film 150, and interlayer insulation. An interlayer insulating film 170 disposed on the film 150 and the light shielding layer, and a wiring layer including wirings 181 to 184 disposed on the interlayer insulating film 170 are provided. The light shielding film 161 is disposed closer to the semiconductor substrate 100 than the wiring layer, and shields the charge holding region 122 from light.

  In FIG. 15, as in the first embodiment, the light shielding film 161 is electrically connected to the gate electrode 141 of the pre-stage transfer gate TG1 via the contact plug 151 disposed in the contact hole of the interlayer insulating film 150. Has been. Alternatively, the light shielding film 161 may be electrically connected to the gate electrode 142 of the post-transfer gate TG2 as in the second embodiment, or the power supply potential on the low potential side as in the third embodiment. May be electrically connected to the wiring supplied.

<Modification of Fourth Embodiment>
FIG. 16 is a plan view of a part of a solid-state imaging device according to a modification of the fourth embodiment of the present invention. FIG. 16 shows a specific arrangement example of the light shielding film 161 in addition to the components shown in FIG. 14, and the layout of the gate electrodes 141 and 142 is changed. Regarding other points, the modification of the fourth embodiment may be the same as that of the fourth embodiment.

  In the example shown in FIG. 16, the light shielding film 161 disposed in the light shielding layer on the interlayer insulating film 150 (FIG. 15) is disposed so as to completely cover the charge retaining region 122 in plan view. Shield from light. In the present application, the “plan view” means that each part is seen through from a direction perpendicular to the main surface of the semiconductor substrate 100 (the upper surface in FIG. 15).

  Therefore, when the light shielding film 161 is electrically connected to the gate electrode 141 of the front transfer gate TG1 (FIG. 15) or the wiring to which the power supply potential on the low potential side is supplied, the rear transfer gate TG2 (FIG. 15). The gate electrode 142 is arranged so as to protrude outside the light shielding film 161 in plan view. Accordingly, the gate electrode 142 can be electrically connected to the upper wiring via the contact plug 153 disposed in the contact hole of the interlayer insulating film 150.

  On the other hand, when the light shielding film 161 is electrically connected to the gate electrode 142 of the rear transfer gate TG2 (FIG. 15) or the wiring to which the power supply potential on the low potential side is supplied, the front transfer gate TG1 (FIG. 15). The gate electrode 141 is disposed so as to protrude outside the light shielding film 161 in plan view. As a result, the gate electrode 141 can be electrically connected to the upper wiring via the contact plug 151 disposed in the contact hole of the interlayer insulating film 150.

<Fifth Embodiment>
Next, a solid-state imaging device according to a fifth embodiment of the present invention will be described.
FIG. 17 is a cross-sectional view of a solid-state imaging device according to the fifth embodiment of the present invention. The solid-state imaging device may be a line sensor or an area sensor. In the following, a case of a line sensor will be described as an example.

  FIG. 17 shows a first area AR1 in which a pixel portion and a readout circuit section are arranged, and a second area AR2 in which a logic circuit is arranged. The configurations of the pixel portion and the readout circuit portion in the first area AR1 shown in FIG. 17 are the same as the configurations of the pixel portion and the readout circuit portion shown in FIG. In the second region AR2, a P-channel MOS transistor QP4 and an N-channel MOS transistor QN4 used in the logic circuit are provided. For example, the transistors QP4 and QN4 constitute any of the CMOS logic circuits 70a to 70d shown in FIG.

An N well 111 and a P well 112 are formed in the semiconductor substrate 100 in the second region AR2. P-type impurity regions (P ⁺ ) 131 and 132 constituting the source and drain of the transistor QP4 are formed in the N well 111, and the source and drain of the transistor QN4 are constituted in the P well 112. N-type impurity regions (N ⁺ ) 127 and 128 are formed.

  In the second region AR2, a first wiring layer including wirings 163 to 166 is disposed on the interlayer insulating film 150, and a second wiring layer including wirings 185 to 188 is disposed on the interlayer insulating film 170. Wiring layers are arranged. The wirings 163 to 166 and 185 to 188 include, for example, aluminum (Al) or copper (Cu).

  As described above, the solid-state imaging device further includes the wirings 163 to 166 arranged at the same height as the light shielding film 161 in the second area AR2 where the logic circuit is arranged. In that case, the manufacturing process of the solid-state imaging device can be simplified by simultaneously forming the light shielding film 161 and the wirings 163 to 166 of the logic circuit. In the present application, “height” means the height from the main surface (the upper surface in the drawing) of the semiconductor substrate 100.

  On the other hand, the light shielding film 161 may be disposed in a layer independent of the wiring layer in the second region AR2 where the logic circuit is disposed. In that case, for example, by arranging the light shielding film 161 at a position lower than the wiring of the logic circuit, the light shielding characteristics of the charge holding region 122 are further improved, or the wirings 181 to 181 of the charge holding region 122 and the wiring layer are improved. Capacitive coupling with 184 can be further reduced.

<Example of light shielding film>
Next, examples of the light shielding film used in the first to fifth embodiments of the present invention will be described with reference to FIGS. FIG. 18 is a cross-sectional view showing an example of a light shielding film. In the first to fifth embodiments of the present invention, a light shielding film 161 as shown in FIG. 18 may be used.

  18 is a first layer 191 containing aluminum (Al) or copper (Cu) and a second layer containing titanium nitride (TiN) disposed on the semiconductor substrate 100 side of the first layer 191. Layer 192. Titanium nitride (TiN) has a property that it is less likely to reflect light than aluminum (Al), copper (Cu), or alloys thereof.

  Therefore, by disposing the second layer 192 containing titanium nitride (TiN) on the semiconductor substrate 100 side of the first layer 191, the light passes through the interlayer insulating films 170 and 150 and is reflected by the main surface of the semiconductor substrate 100. It is possible to reduce the amount of light that is reflected again later on the lower surface of the light shielding film 161 and is incident on the charge holding region 122. The film thickness of the second layer 192 is preferably in the range of 500 to 800 nm (50 to 80 nm). As a result, the second layer 192 has a necessary and sufficient film thickness to exhibit the properties of titanium nitride (TiN) that hardly reflects light.

  The light-shielding film 161 may further include a third layer 193 that is disposed on the semiconductor substrate 100 side of the second layer 192 and contains titanium (Ti). In that case, the bonding property of the second layer 192 containing titanium nitride (TiN) to the base layer can be improved by the third layer 193 containing titanium (Ti). The thickness of the third layer 193 is preferably in the range of 100 to 250 (10 nm to 25 nm). Thereby, the third layer 193 improves the bonding property of the second layer 192 to the base layer and hardly affects the light reflection characteristics.

  Further, the light-shielding film 161 may further include a fourth layer 194 that is disposed on the opposite side of the first layer 191 from the semiconductor substrate 100 and includes titanium nitride (TiN). By providing the fourth layer 194, it is possible to reduce reflected light when exposing the photoresist in the photolithography process in manufacturing the solid-state imaging device. The film thickness of the fourth layer 194 is preferably in the range of 500 to 800 mm (50 to 80 nm), similar to the film thickness of the second layer 192. Note that wirings arranged at the same height as the light shielding film 161 (for example, the wirings 162 to 166 shown in FIG. 17) may have the same configuration as the light shielding film 161.

  As described in the first to fifth embodiments, the fluctuation of the signal charge amount due to the light incident on the charge holding region 122 is reduced, and the potential change of the wirings 181 to 184 in the wiring layer is the potential of the charge holding region 122. By using a solid-state imaging device in which variation in transfer characteristics due to the influence on the image is improved, it is possible to provide an electronic apparatus in which the image quality of image data obtained by imaging a subject is improved.

  In addition to the scanner device, the solid-state imaging devices according to the first to fifth embodiments include, for example, a drive recorder, a digital movie, a digital still camera, a mobile terminal such as a mobile phone, a video phone, a crime prevention TV monitor, The present invention can be applied to an electronic device that images a subject and generates image data, such as a measurement device and a medical device.

  In the above-described embodiment, the case where an N-type impurity region or the like is formed in a P-type semiconductor layer has been described. However, the present invention is not limited to the above-described embodiment. For example, the present invention can also be applied to the case where a P-type impurity region or the like is formed in an N-type semiconductor layer. As described above, many modifications can be made within the technical idea of the present invention according to persons having ordinary knowledge in the technical field.

  DESCRIPTION OF SYMBOLS 1 ... Original, 10 ... CIS module, 11 ... Light guide, 12 ... Lens array, 13 ... Image sensor, 14 ... Light source, 15 ... Flexible wiring, 16 ... Main board, 17 ... System on chip, 18 ... Analog front end, DESCRIPTION OF SYMBOLS 19 ... Power supply circuit, 20 ... Image sensor chip, 30 ... Pixel part, 40 ... Reading circuit part, 40A ... Unit block, 50 ... Control circuit part, 51 ... Correlated double sampling circuit, 52 ... Output circuit, 53 ... Logic circuit , 61 to 64 ... capacitors, 70a to 70d ... CMOS logic circuit, 100 ... semiconductor substrate, 110, 112 ... P well, 111 ... N well, 121, 124 to 128 ... N-type impurity region, 122, CH ... charge retention Region 123 FD floating region 131-132 P-type impurity region 141-14 ... Gate electrode, 150, 170 ... Interlayer insulating film, 151, 151a to 151d, 152, 153, 170a to 170d, 171a to 171d ... Contact plug, 161, 161a to 161d ... Light shielding film, 162 ... Signal wiring, 163 to 166 , 180 to 188 ... wiring, 191 to 194 ... first to fourth layers of the light shielding film, PD ... photodiode, TG1, TG1a to TG1d ... front transfer gate, TG2, TG2a to TG2d ... post transfer gate, QN1 ... buffer Transistor, QN2 ... Reset transistor, QN3 ... Select transistor, QN4 ... N channel MOS transistor, QP4 ... P channel MOS transistor, C1, C2 ... Charge holding capacitance

Claims (11)

A light receiving element, a charge holding region, and a floating diffusion region disposed on a semiconductor substrate;
A first transfer gate having a gate electrode disposed via a gate insulating film on a region between the light receiving element and the charge holding region in the semiconductor substrate;
A second transfer gate having a gate electrode disposed through a gate insulating film on a region between the charge holding region and the floating diffusion region in the semiconductor substrate;
A wiring layer including wiring disposed on the semiconductor substrate via a plurality of interlayer insulating films;
A light-shielding film disposed on the semiconductor substrate side of the wiring layer and shielding the charge holding region;
A solid-state imaging device.   The solid-state imaging device according to claim 1, wherein the light shielding film is electrically connected to the gate electrode of the first transfer gate.   The solid-state imaging device according to claim 1, wherein the light shielding film is electrically connected to the gate electrode of the second transfer gate.   The solid-state imaging device according to claim 1, wherein the light shielding film is electrically connected to a wiring to which a power supply potential on a low potential side is supplied. Four light receiving elements arranged in one row;
Four charge holding regions, four floating diffusion regions, four first transfer gates, and four second transfer gates arranged corresponding to the four light receiving elements;
A light shielding layer that shields the four charge holding regions;
5. The solid-state imaging device according to claim 1, wherein the four floating diffusion regions are electrically connected to a gate electrode of one buffer transistor.   The solid-state imaging device according to claim 1, further comprising a wiring arranged at the same height as the light shielding film in a region where the logic circuit is arranged.   The solid-state imaging device according to claim 1, wherein the light shielding film is disposed in a layer independent of a wiring layer in a region where the logic circuit is disposed.   The said light shielding film has either the 1st layer containing aluminum or copper, and the 2nd layer which is arrange | positioned at the said semiconductor substrate side of the said 1st layer, and contains a titanium nitride. The solid-state imaging device according to 1.   The solid-state imaging device according to claim 8, wherein the film thickness of the second layer is in a range of 50 nm to 80 nm.   10. The solid-state imaging device according to claim 8, wherein the light shielding film further includes a third layer that is disposed on the semiconductor substrate side of the second layer and includes titanium.   An electronic apparatus comprising the solid-state imaging device according to claim 1.

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