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WO2022088942A1 - 显示面板、显示装置及显示面板的制造方法 - Google Patents

显示面板、显示装置及显示面板的制造方法 Download PDF

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Publication number
WO2022088942A1
WO2022088942A1 PCT/CN2021/115874 CN2021115874W WO2022088942A1 WO 2022088942 A1 WO2022088942 A1 WO 2022088942A1 CN 2021115874 W CN2021115874 W CN 2021115874W WO 2022088942 A1 WO2022088942 A1 WO 2022088942A1
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WO
WIPO (PCT)
Prior art keywords
layer
substrate
display
away
insulating layer
Prior art date
Application number
PCT/CN2021/115874
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English (en)
French (fr)
Inventor
文平
张顺
张元其
罗昶
王威
王裕
刘庭良
曾扬
张毅
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/786,391 priority Critical patent/US20230012152A1/en
Publication of WO2022088942A1 publication Critical patent/WO2022088942A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H10K59/179—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/82—Interconnections, e.g. terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H01L2224/05018—Shape in side view being a conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05562—On the entire exposed surface of the internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2902—Disposition
    • H01L2224/29026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H01L2224/29028—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body the layer connector being disposed on at least two separate bonding areas, e.g. bond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel, a display device, and a manufacturing method of the display panel.
  • a flexible multi-layer surface touch (Flexible Multi-Layer On Cell, abbreviated FMLOC) method is used to set the touch element on the finished film between the display substrate and the cover glass of the Thin Film Encapsulation (TFE) process.
  • the bonding area of the integrated circuit chip of the display substrate ie the IC bonding area
  • an organic material film layer such as a planarization layer (Planarization, PLN for short) or a pixel definition layer (Pixel Definition Layer, PDL for short).
  • a display panel comprising:
  • a display substrate having a display area and a non-display area surrounding the display area comprising a substrate and an integrated circuit (Integrated Circuit, IC for short) junction disposed on one side of the substrate and located in the non-display area , wherein the IC joint includes:
  • a first passivation layer located on the side of the substrate adjacent to the lead, covering the peripheral area of the lead, and exposing the central area of the lead;
  • a first spacer layer located on the side of the first passivation layer away from the substrate, and covering the first passivation layer and the edge where the first passivation layer is connected to the pin;
  • the first metal layer is located on the side of the first spacer layer away from the substrate, covers at least the central part of the pin, and is electrically connected to the pin.
  • the display panel further includes:
  • An IC chip having chip pins, the IC chip being located on a side of the first metal layer away from the substrate;
  • the conductive adhesive film is located between the chip pins of the IC chip and the first metal layer, and is electrically connected to the chip pins of the IC chip and the first metal layer.
  • the display panel further includes:
  • a touch control structure at least located in the display area of the display substrate
  • the display substrate further includes:
  • An encapsulation layer located between the plurality of light emitting elements and the touch control structure, is configured to encapsulate the display substrate.
  • the touch control structure includes:
  • a second spacer layer is located on the side of the encapsulation layer away from the substrate and covers the surface of the encapsulation layer.
  • the touch control structure further includes:
  • a first touch electrode layer which has a first touch electrode pattern, and is located on the side of the second spacer layer away from the substrate;
  • a touch insulating layer having a touch insulating pattern and located on a side of the first touch electrode layer away from the substrate;
  • the second touch electrode layer has a second touch electrode pattern and is located on the side of the touch insulating layer away from the substrate, and part of the second touch electrode pattern passes through the touch insulating layer.
  • the via hole is electrically connected to the first touch electrode pattern.
  • the touch control structure further includes:
  • the insulating protection layer has an insulating protection pattern, is located on the side of the second touch electrode layer away from the substrate, and is configured to perform insulation protection on the second touch electrode layer.
  • the second spacer layer and the first spacer layer are located in the same layer and have the same material.
  • the touch insulating layer and the first spacer layer are located on the same layer and have the same material, and the second touch electrode layer and the first metal layer are located on the same layer and have the same material.
  • the display substrate further includes:
  • a second insulating layer located between the first insulating layer and the first passivation layer
  • the pins include:
  • the first lead metal layer is located on the surface of the first insulating layer on the side away from the substrate, and is partially covered by the second insulating layer.
  • the display substrate further includes:
  • a third insulating layer located between the second insulating layer and the first passivation layer
  • the pins also include:
  • the second lead metal layer is located on the surface of the third insulating layer on the side away from the substrate, and is connected to the first lead metal layer through the via holes passing through the second insulating layer and the third insulating layer.
  • the second pin metal layer is also electrically connected to the first metal layer.
  • the display substrate further includes:
  • a thin film transistor device includes an active layer, a gate, a source and a drain, the active layer is located between the first insulating layer and the substrate, and the gate is located away from the first insulating layer
  • the surface on the side of the substrate, the source electrode and the drain electrode are located on the surface of the third insulating layer on the side away from the substrate, and pass through the first insulating layer and the second insulating layer. layers and vias of the third insulating layer are respectively electrically connected to the active layer;
  • a capacitor device comprising a first capacitor electrode plate and a second capacitor electrode plate, the first capacitor electrode plate is located on the surface of the first insulating layer away from the substrate, and the second capacitor electrode plate is located on the side of the first insulating layer away from the substrate the surface of the second insulating layer on the side away from the substrate;
  • the gate electrode, the first capacitor plate and the first lead metal layer are located in the same layer and have the same material, and the source electrode, the drain electrode and the second lead metal layer are located in the same layer. layer and the same material.
  • the display substrate further includes:
  • a second passivation layer located on a side of the third insulating layer away from the substrate and covering the source electrode and the drain electrode;
  • planarization layer located on the side of the second passivation layer away from the substrate
  • the plurality of light-emitting elements are located between the planarization layer and the encapsulation layer, and the second passivation layer and the first passivation layer are located in the same layer and have the same material.
  • a display device including the aforementioned display panel.
  • a method for manufacturing a display panel comprising:
  • a display substrate having a display area and a non-display area surrounding the display area, the display substrate including a substrate and an IC junction formed on one side of the substrate and located in the non-display area,
  • the step of forming the IC joint includes:
  • a first passivation layer is formed on the side of the substrate adjacent to the pin, and the first passivation layer covers the peripheral region of the pin and exposes the central region of the pin;
  • a first spacer layer is formed on the side of the first passivation layer away from the substrate, and the first spacer layer covers the first passivation layer and the first passivation layer and the lead the edges where the feet meet;
  • a first metal layer is formed on the side of the first spacer layer away from the substrate, and the first metal layer covers at least the central part of the pin and is electrically connected to the pin.
  • step of forming the first passivation layer between the step of forming the first passivation layer and the step of forming the first spacer layer, further comprising:
  • At least a portion of the planarization layer corresponding to the pins is removed.
  • FIG. 1 is a partial schematic diagram of an overall layout of a display substrate and an IC joint in an embodiment of a display panel according to the present disclosure
  • FIG. 2 is an AA cross-sectional structural diagram of an area where an IC joint is located in an embodiment of the display panel according to the present disclosure
  • FIG. 3 is a schematic cross-sectional structure diagram of a display area in an embodiment of a display panel according to the present disclosure
  • FIG. 4 is a schematic flowchart of forming an IC joint in an embodiment of a manufacturing method of a display panel according to the present disclosure
  • FIG. 5 is a schematic flowchart of forming a light-emitting element, an encapsulation layer and a touch control structure in an embodiment of a manufacturing method of a display panel according to the present disclosure.
  • first,” “second,” and similar words do not denote any order, quantity, or importance, but are merely used to distinguish the different parts.
  • “Comprising” or “comprising” and similar words mean that the element preceding the word covers the elements listed after the word, and does not exclude the possibility that other elements are also covered.
  • “Up”, “Down”, “Left”, “Right”, etc. are only used to represent the relative positional relationship, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
  • a specific device when a specific device is described as being located between the first device and the second device, there may or may not be an intervening device between the specific device and the first device or the second device.
  • the specific device When it is described that a specific device is connected to other devices, the specific device may be directly connected to the other device without intervening devices, or may not be directly connected to the other device but have intervening devices.
  • the bonding pins of the IC bonding region (IC bonding region) of the display substrate are covered by an organic material film layer (eg, a planarization layer).
  • an organic material film layer eg, a planarization layer. It is found through research that in the FMLOC process, when a spacer layer (ie, a barrier layer) is formed in the IC bonding area, the adhesion between the spacer layer and the organic material film layer is poor. Also, the edge portion of the organic material film layer not covered by the spacer layer is exposed. All of these make the organic material film easily absorb water in the water washing step in the FMLOC process. When subsequent tests are performed on the display substrate, such as the reliability test of high temperature and high humidity, the moisture absorbed in the organic material film layer is thermally expanded, which may cause the spacer layer and metal layer in the IC bonding area to peel off.
  • the spacer layer when the spacer layer is formed, the spacer layer is made to cover the edge portion of the organic material film layer, so as not to be exposed. It has been found through research that when this structure is adopted, the metal layer covered on the junction pins of the IC bonding area will also cover the spacer layer covered with the organic material film layer, so its edge area is not covered with the spacer layer and the organic material. The central area of the material film layer can reach a height difference of 1.2 ⁇ m. In this way, when the electrical connection between the metal layer and the pins of the IC chip is realized through the Anisotropic Conductive Film (ACF), the conductive particles in the edge region of the ACF corresponding to the metal layer are subjected to greater force and are easily pressed.
  • ACF Anisotropic Conductive Film
  • the crack spacer layer which makes the organic material film layer easy to absorb water through the cracks of the spacer layer in the water washing step in the FMLOC process.
  • subsequent tests are performed on the display substrate, such as the reliability test of high temperature and high humidity, the moisture absorbed in the organic material film layer is thermally expanded, which may cause the spacer layer and metal layer in the IC bonding area to peel off.
  • embodiments of the present disclosure provide a display panel, a display device, and a manufacturing method of the display panel, which can improve the problems such as peeling of the spacer layer and the metal layer in the IC bonding area.
  • FIG. 1 is a partial schematic diagram of an overall layout of a display substrate and an IC joint in an embodiment of a display panel according to the present disclosure.
  • FIG. 2 is a schematic AA cross-sectional structure diagram of a region where an IC joint is located in an embodiment of the display panel according to the present disclosure.
  • a display panel includes a display substrate 1 .
  • the display substrate 1 has a display area 10A and a non-display area 10B surrounding the display area 10A.
  • the display area 10A is used for displaying images
  • the non-display area 10B is used for arranging related circuits and related electronic components to support the display of the display area 10A.
  • the specific shape of the display area 10A is not limited, for example, a circle, an ellipse, a polygon, and the like.
  • the display area 10A is substantially polygonal, eg, substantially rectangular as shown in FIG. 1 .
  • the display area 10A is roughly polygonal in shape: after ignoring the rounded corners, beveled corners or process errors of the display area, the display area 10A has a polygonal shape.
  • the display substrate 1 includes a substrate 10 and an IC joint 20 disposed on one side of the substrate 10 and located in the non-display area 10B.
  • the IC bonding portion 20 is configured to connect pins of an IC chip that can provide drive signals, data signals, clock signals, etc. to display pixels in the display substrate, and detection signals, etc., to the display substrate.
  • the display substrate 1 is an Active Matrix Organic Light-Emitting Diode (AMOLED) display substrate or a Passive Matrix Organic Light-Emitting Diode (PMOLED) display substrate.
  • AMOLED Active Matrix Organic Light-Emitting Diode
  • PMOLED Passive Matrix Organic Light-Emitting Diode
  • the substrate 10 may be a flexible substrate (eg, polyimide material) or a rigid substrate (eg, glass or resin material).
  • the IC joint 20 includes: leads 21 , a first passivation layer (PVX) 22 , a first spacer layer 23 and a first metal layer 24 .
  • the first passivation layer 22 is located on the side of the substrate 10 adjacent to the lead 21, and covers the peripheral area of the lead 21, and exposes the central area of the lead 21.
  • the first passivation layer 22 may be formed of an inorganic material, for example, a compound of silicon such as silicon oxide SiOx, silicon nitride SiNx, or silicon oxynitride SiNO.
  • the first spacer layer 23 is located on the side of the first passivation layer 22 away from the substrate 10 , and covers the passivation layer 22 and the area where the first passivation layer 22 is connected to the pins 21 . edge.
  • the first spacer layer 23 can be made of insulating material, such as silicon nitride SiNx.
  • the first metal layer 24 is located on the side of the first spacer layer 23 away from the substrate 10 , covers at least the central portion of the lead 21 , and is electrically connected to the lead 21 .
  • the peripheral area of the lead 21 is covered by the first passivation layer 22 , which is different from that in the present embodiment.
  • the adhesion between the first spacer layer 23 is better than the adhesion between the organic material film layer and the spacer layer in the related art, it is not easy to peel off from the first passivation layer 22, and it can also prevent the organic material film layer from absorbing water vapor and causing damage.
  • the thermal expansion causes the spacer layer and the metal layer to peel off, further making the first spacer layer 23 and the first metal layer 24 in the IC joint more difficult to peel off.
  • the display panel further includes: an IC chip 4 and a conductive adhesive film 41 .
  • the IC chip 4 has chip pins 42 , and the IC chip 4 is located on the side of the first metal layer 24 away from the substrate 10 .
  • the conductive adhesive film 41 is located between the chip pins 42 of the IC chip 4 and the first metal layer 24 , and is electrically connected to the chip pins 42 of the IC chip 4 and the first metal layer 24 .
  • the conductive adhesive film 41 can be ACF.
  • the first spacer layer 23 is directly covered on the first passivation layer. Therefore, the height difference between the edge and the center of the first metal layer 24 formed on the first spacer layer 23 and the first metal layer 24 on the IC chip 4 is relatively small, which makes the conductive particles of the conductive adhesive film 41 corresponding to the edge position relatively stressed. Smaller, the first spacer layer 23 is not easily fractured.
  • the organic material film layer absorbs water vapor through the cracks of the spacer layer and expands due to heat, which causes the spacer layer and the metal layer to peel off, and further makes the first spacer layer 23 and the first metal layer in the IC joint part. 24 is less prone to peeling.
  • the display substrate further includes: a first insulating layer 12a and a second insulating layer 12b.
  • the first insulating layer 12 a is located between the first passivation layer 22 and the substrate 10 .
  • the second insulating layer 12b is located between the first insulating layer 12a and the first passivation layer 22 .
  • Materials of the first insulating layer (eg, the first gate insulating layer GI1) 12a and the second insulating layer (eg, the second gate insulating layer GI2) 12b may include silicon compounds or metal oxides, eg, silicon oxynitride SiNO, silicon oxide SiOx, silicon nitride SiNx, silicon oxycarbide SiCxOy, silicon nitride nitride SiCxNy, aluminum oxide AlOx, aluminum nitride AlNx, tantalum oxide TaOx, hafnium oxide HfOx, zirconium oxide ZrOx, titanium oxide TiOx, etc.
  • the first insulating layer 12a and the second insulating layer 12b may be a single layer or multiple layers.
  • the pins 21 in the IC bonding portion 20 may be formed simultaneously in the process of forming the display pixels in the display substrate 1 .
  • the lead 21 includes a first lead metal layer 21a.
  • the first lead metal layer 21a is located on the surface of the first insulating layer 12a away from the substrate 10, and is partially covered by the second insulating layer 12b.
  • the display substrate further includes a third insulating layer 12c.
  • the third insulating layer 12c is located between the second insulating layer 12b and the first passivation layer 22 .
  • the material of the third insulating layer (eg, the interlayer insulating layer ILD) 12c may include silicon compounds, metal oxides, and the like. Specifically, the silicon compounds and metal oxides listed above can be selected, which will not be repeated here.
  • the pin 21 further includes a second pin metal layer 21b.
  • the second lead metal layer 21b is located on the surface of the third insulating layer 12c on the side away from the substrate 10, and is connected to the first insulating layer 12c through a via hole passing through the second insulating layer 12b and the third insulating layer 12c.
  • the lead metal layer 21 a is electrically connected, and the second lead metal layer 21 b is also electrically connected to the first metal layer 24 .
  • FIG 3 is a schematic cross-sectional structure diagram of a display area in an embodiment of a display panel according to the present disclosure.
  • the display panel further includes a touch control structure 30 .
  • the touch control structure 30 is formed on the display substrate 1 using the aforementioned FMLOC process.
  • the touch control structure 30 is located at least in the display area 10A of the display substrate 1 .
  • the touch structure 30 is located in the display area 10A.
  • the touch structures 30 are located in the display area 10A and the non-display area 10B.
  • the organic material film layer in the IC bonding area in the related art is easily washed with water. Water absorbs during the process, and the IC joint in this embodiment uses the first passivation layer 22 to cover the peripheral area of the lead 21, which avoids the problem that the organic material easily absorbs water when the lead is covered with an organic material film.
  • the display substrate 1 further includes: a plurality of light emitting elements 15 and an encapsulation layer 19 .
  • a plurality of light emitting elements 15 are disposed on one side of the substrate 10 adjacent to the IC joint portion 20 and located in the display area 10A.
  • the display substrate 1 may further include a thin film transistor device 13 and a capacitor device 14 .
  • the thin film transistor device 13 is electrically connected to the light emitting elements 15 so as to control the light emitting elements 15 so that each light emitting element 15 emits light independently.
  • the thin film transistor device 13 may include an active layer 13a, a gate electrode 13b, a source electrode 13c and a drain electrode 13d.
  • the active layer 13a is located between the first insulating layer 12a and the substrate 10
  • the gate 13b is located on the surface of the first insulating layer 12a away from the substrate 10
  • the electrode 13c and the drain electrode 13d are located on the surface of the third insulating layer 12c away from the substrate 10, and pass through the first insulating layer 12a, the second insulating layer 12b and the third insulating layer 12b.
  • the via holes of the insulating layer 12c are respectively electrically connected to the active layer 13a.
  • the material of the active layer 13a may include inorganic semiconductor materials (eg, polycrystalline silicon or amorphous silicon, etc.), organic semiconductor materials, or oxide semiconductor materials.
  • the material of the gate electrode 13b may include metals, metal alloys, metal nitrides, conductive metal oxides or transparent conductive materials, such as silver, copper, aluminum alloy, aluminum nitride, tin oxide, indium tin oxide, and the like.
  • the material of the source electrode 13c and the drain electrode 13d may include metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc., for example, multilayer metals Mo-Al-Mo or Ti-Al-Ti.
  • the capacitor device 14 may include a first capacitor plate 14a and a second capacitor plate 14b, the first capacitor plate 14a is located on the surface of the first insulating layer 12a away from the substrate 10, the second capacitor plate 14a The capacitor plate 14b is located on the surface of the second insulating layer 12b on the side away from the substrate 10 .
  • the gate 13b, the first capacitor plate 14a and the first lead metal layer 21a are located in the same layer and made of the same material, which is beneficial to the gate 13b, the first capacitor plate 14a and the first lead metal
  • the layer 21a is formed by the same patterning process, thereby simplifying the process.
  • the source electrode 13c, the drain electrode 13d and the second lead metal layer 21b are located in the same layer and made of the same material, which is beneficial to the source electrode 13c, the drain electrode 13d and the second lead metal layer 21b through the same patterning process formed, thereby simplifying the process.
  • the structure of the same layer and the same material mentioned here and later can be a layer structure formed by using the same film forming process to form a film layer with a specific pattern, and then using the same mask to pattern the film layer through a patterning process.
  • one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous.
  • These particular graphics may also be at different heights or have different thicknesses.
  • a buffer layer 11 may also be provided between the first insulating layer 12 a and the substrate 10 .
  • the buffer layer 11 is used to prevent or reduce the diffusion of metal atoms or impurities from the substrate into the active layer of the transistor.
  • the buffer layer 11 may include inorganic materials such as silicon oxide SiOx, silicon nitride SiNx, or silicon oxynitride SiNO, and may be formed as a single layer or multiple layers.
  • the display substrate 1 further includes: a second passivation layer 16 and a planarization layer 17 .
  • the second passivation layer 16 is located on the side of the third insulating layer 12c away from the substrate 10 and covers the source electrode 13c and the drain electrode 13d.
  • the second passivation layer 16 and the first passivation layer 22 are located in the same layer and have the same material, which is beneficial to be formed by the same patterning process, thereby simplifying the process.
  • the planarization layer 17 is located on the side of the second passivation layer 16 away from the substrate 10 .
  • a plurality of light emitting elements 15 are located between the planarization layer 17 and the encapsulation layer 19 .
  • the material of the planarization layer can include organic insulating materials, such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane and other resin materials etc. or urethane, thermoplastic polyurethane and other elastic materials.
  • the planarization layer 17 may also be formed on the IC bonding region, for example, on the surface of the first passivation layer 22 on the side away from the substrate 10 .
  • the planarization layer including organic materials is easy to absorb water in the related art, at least the part of the planarization layer 17 corresponding to the pins 21 may be removed by etching and other processes.
  • the light emitting element 15 may be an OLED light emitting element.
  • the light-emitting element may include a first electrode layer 15a, an organic light-emitting layer 15b, and a second electrode layer 15c.
  • the first electrode layer 15 a is located between the planarization layer 17 and the pixel definition layer 18
  • the organic light emitting layer 15 b is located in the pixel opening defined by the pixel definition layer 18
  • the second electrode layer 15 c is located at a part of the organic light emitting layer 15 b away from the substrate 10 . side.
  • the first electrode layer 15a may be electrically connected to the drain electrode 13d through a via hole passing through the planarization layer 17 and the second passivation layer 16 .
  • the first electrode layer 15 a serves as an anode layer of the light-emitting element 15
  • the second electrode layer 15 c serves as a cathode of the light-emitting element 15
  • Both the first electrode layer 15a and the second electrode layer 15b can be made of materials such as metals, metal alloys, metal nitrides, conductive metal oxides or transparent conductive materials.
  • the organic light-emitting layer 15b may include small molecular organic materials or polymer molecular organic materials, such as fluorescent light-emitting materials or phosphorescent light-emitting materials, which may emit red light, green light, blue light or white light.
  • the touch control structure 30 includes a second spacer layer 31 .
  • the second spacer layer 31 is located on the side of the encapsulation layer 19 away from the substrate 10 and covers the surface of the encapsulation layer 19 .
  • the second spacer layer 31 and the first spacer layer 23 are located in the same layer and have the same material, which facilitates the formation of the second spacer layer 31 and the first spacer layer 23 through the same patterning process, thereby simplifying the process.
  • the touch structure 30 includes a first touch electrode layer 32 .
  • the first touch electrode layer 32 has a first touch electrode pattern (TSP Metal A, TMA for short), and is located on a side of the second spacer layer 31 away from the substrate 10 .
  • the material of the first touch electrode layer 32 may include metals, alloys, metal nitrides, conductive metal oxides, or transparent conductive materials, for example, multi-layer metals Mo-Al-Mo or Ti-Al-Ti.
  • the first touch electrode pattern can be used to form the lower channel of the bridge region, and can also be used for the upper and lower access of the touch driving electrodes TX located at the periphery and the left and right access of the touch sensing electrode RX signal wiring.
  • the touch driving electrodes TX and the touch sensing electrodes RX can be arranged horizontally and vertically, respectively, or other arrangements can be adopted as required.
  • the touch structure 30 further includes: a touch insulating layer 33 and a second touch electrode layer 34 .
  • the touch insulating layer 33 has a touch insulating pattern and is located on the side of the first touch electrode layer 32 away from the substrate 10 .
  • the material of the touch insulating layer 33 may include inorganic materials, such as silicon oxide SiOx, silicon nitride SiNx, or silicon oxynitride SiNO, which can serve as an interlayer dielectric layer to play an insulating role.
  • the touch insulating layer 33 and the first spacer layer 23 are located on the same layer and have the same material, which facilitates the formation of the touch insulating layer 33 and the first spacer layer 23 through the same patterning process, thereby simplifying the process.
  • the second touch electrode layer 34 has a second touch electrode pattern (TSP Metal B, TMB for short), and is located on the side of the touch insulating layer 33 away from the substrate 10, and part of the second touch electrodes The pattern is electrically connected to the first touch electrode pattern through via holes penetrating through the touch insulating layer 33 .
  • the second touch electrode pattern can be used to form the upper channel of the bridge area, and can also be used to form the metal mesh electrode outside the bridge area and the signal traces at the periphery.
  • the second touch electrode layer 34 and the first metal layer 24 are located in the same layer and have the same material, which facilitates that the second touch electrode layer 34 and the first metal layer 24 pass through the same patterning process formed, thereby simplifying the process.
  • the touch control structure 30 further includes an insulating protection layer 35 .
  • the insulating protection layer 35 has an insulating protection pattern and is located on the side of the second touch electrode layer 34 away from the substrate 10 , and is configured to perform insulation protection on the second touch electrode layer 34 .
  • the material of the insulating protection layer 35 may include inorganic insulating materials or organic insulating materials, such as polyimide.
  • the above-described display panel embodiments of the present disclosure can be applied to various types of display devices. Therefore, the present disclosure also provides a display device including the aforementioned display panel.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • FIG. 4 is a schematic flowchart of forming an IC joint in an embodiment of a manufacturing method of a display panel according to the present disclosure.
  • a method of manufacturing a display panel includes: forming a display substrate 1 having a display area 10A and a non-display area 10B surrounding the display area 10A, the The display substrate 1 includes a substrate 10 and an IC bonding portion 20 formed on one side of the substrate 10 and located in the non-display area 10B.
  • the steps of forming the IC bonding portion 20 may include steps 110 to 140 .
  • the substrate 10 is formed.
  • pins 21 are formed on one side of the substrate 10 .
  • a first passivation layer 22 is formed on the side of the substrate 10 adjacent to the pins 21 , and the first passivation layer 22 covers the peripheral area of the pins 21 and exposes all the pins 21 . the center area of the pin 21.
  • a first spacer layer 23 is formed on the side of the first passivation layer 22 away from the substrate 10, and the first spacer layer 23 covers the first passivation layer 22 and the first spacer layer 23.
  • the first passivation layer 22 is connected to the edge of the lead 21 .
  • a first metal layer 24 is formed on the side of the first spacer layer 23 away from the substrate 10, and the first metal layer 24 covers at least the central portion of the lead 21, and It is electrically connected to the pin 21 .
  • the peripheral area of the lead 21 is covered by the first passivation layer 22 , which is different from that in the present embodiment.
  • the adhesion between the first spacer layer 23 is better than the adhesion between the organic material film layer and the spacer layer in the related art, it is not easy to peel off from the first passivation layer 22, and it can also prevent the organic material film layer from absorbing water vapor and causing damage.
  • the thermal expansion causes the spacer layer and the metal layer to peel off, further making the first spacer layer 23 and the first metal layer 24 in the IC joint more difficult to peel off.
  • the method may further include: forming the first passivation layer 22 A planarization layer 17 is formed on the side away from the substrate 10 ; at least the portion of the planarization layer 17 corresponding to the pins 21 is removed.
  • the planarization layer material may be removed by means of laser or chemical etching.
  • the opening position of the mask of the planarization layer may be set so that the planarization layer does not cover the first passivation layer 22 and the pins 21 in the IC bonding area.
  • FIG. 5 is a schematic flowchart of forming a light-emitting element, an encapsulation layer and a touch control structure in an embodiment of a manufacturing method of a display panel according to the present disclosure.
  • the step of forming the display substrate 1 further includes step 210 and step 220 .
  • step 210 a plurality of light emitting elements 15 are formed on a side of the substrate 10 adjacent to the IC bonding portion 20 and at a position corresponding to the display area 10A.
  • step 220 an encapsulation layer 19 is formed on a side of the plurality of light-emitting elements 15 away from the substrate 10 to encapsulate the display substrate 1 .
  • the manufacturing method of the display panel further includes: forming a touch structure 30 on a side of the encapsulation layer 19 away from the substrate 10 .
  • the touch structure 30 may be formed by an FMLOC process.
  • the steps of forming the touch control structure 30 may include steps 230 to 270 .
  • a second spacer layer 31 is formed on the side of the encapsulation layer 19 away from the substrate 10 , and the second spacer layer 31 covers the surface of the encapsulation layer 19 .
  • a first touch electrode layer 32 having a first touch electrode pattern is formed on a side of the second spacer layer 31 away from the substrate 10 .
  • a touch insulating layer 33 having a touch insulating pattern is formed on a side of the first touch electrode layer 32 away from the substrate 10 .
  • a second touch electrode layer 34 having a second touch electrode pattern is formed on a side of the touch insulating layer 33 away from the substrate 10, and part of the second touch electrode pattern is formed. It is electrically connected to the first touch electrode pattern through via holes penetrating through the touch insulating layer 33 .
  • an insulating protection layer 35 having an insulating protection pattern is formed on a side of the second touch electrode layer 34 away from the substrate 10 , so as to perform insulation protection on the second touch electrode layer 34 .
  • the second spacer layer 31 and the first spacer layer 23 are formed by the same patterning process, and the second touch electrode layer 34 and the first metal layer 24 are formed by the same patterning process. This helps to simplify the process. In other embodiments, the touch insulating layer 33 and the first spacer layer 23 are formed through the same patterning process, which is beneficial to simplify the process.
  • a photomask process can be used to form the first touch electrode pattern, the second touch electrode pattern, the touch insulating pattern and the insulating protection pattern, respectively.
  • these patterns can also be formed by a chemical vapor deposition (Chemical Vapor Deposition, CVD for short) process.

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Abstract

本公开涉及一种显示面板、显示装置及显示面板的制造方法。显示面板包括：显示基板，具有显示区和围绕所述显示区的非显示区，所述显示基板包括衬底和设置在衬底一侧且位于所述非显示区的集成电路接合部，其中，所述集成电路接合部包括：引脚；第一钝化层，位于所述衬底邻近引脚的一侧，并覆盖在所述引脚的周边区域，并露出所述引脚的中心区域；第一间隔层，位于所述第一钝化层远离所述衬底的一侧，并覆盖所述第一钝化层和所述第一钝化层与所述引脚相接的边缘；和第一金属层，位于所述第一间隔层远离所述衬底的一侧，至少覆盖所述引脚的中心部位，并与所述引脚电连接。

Description

显示面板、显示装置及显示面板的制造方法
相关申请的交叉引用
本申请是以CN申请号为202011194836.1，申请日为2020年10月30日的申请为基础，并主张其优先权，该CN申请的公开内容在此作为整体引入本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板、显示装置及显示面板的制造方法。
背景技术
在有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示装置的一些相关技术中，采用柔性多层表面式触控(Flexible Multi-Layer On Cell，简称FMLOC)方式将触控元件设置在完成薄膜封装(Thin Film Encapsulation，简称TFE)工艺的显示基板与盖板玻璃之间。该显示基板的集成电路芯片的接合区域(即IC bonding区域)的焊盘由有机材料膜层，例如平坦化层(Planarization，简称PLN)或像素定义层(Pixel Definition Layer，简称PDL)进行包覆。
发明内容
在本公开的一个方面，提供一种显示面板，包括：
显示基板，具有显示区和围绕所述显示区的非显示区，所述显示基板包括衬底和设置在衬底一侧且位于所述非显示区的集成电路(Integrated Circuit，简称IC)接合部，其中，所述IC接合部包括：
引脚；
第一钝化层，位于所述衬底邻近引脚的一侧，并覆盖在所述引脚的周边区域，并露出所述引脚的中心区域；
第一间隔层，位于所述第一钝化层远离所述衬底的一侧，并覆盖所述第一钝化层和所述第一钝化层与所述引脚相接的边缘；和
第一金属层，位于所述第一间隔层远离所述衬底的一侧，至少覆盖所述引脚的中心部位，并与所述引脚电连接。
在一些实施例中，所述显示面板还包括：
IC芯片，具有芯片管脚，所述IC芯片位于所述第一金属层远离所述衬底的一侧；和
导电胶膜，位于所述IC芯片的芯片管脚与所述第一金属层之间，且与所述IC芯片的芯片管脚与所述第一金属层均电连接。
在一些实施例中，所述显示面板还包括：
触控结构，至少位于所述显示基板的显示区；
其中，所述显示基板还包括：
多个发光元件，设置在所述衬底邻近所述IC接合部的一侧，且位于所述显示区；和
封装层，位于所述多个发光元件与所述触控结构之间，被配置为对所述显示基板进行封装。
在一些实施例中，所述触控结构包括：
第二间隔层，位于所述封装层远离所述衬底的一侧，且覆盖在所述封装层的表面。
在一些实施例中，所述触控结构还包括：
第一触控电极层，具有第一触控电极图案，且位于所述第二间隔层远离所述衬底的一侧；
触控绝缘层，具有触控绝缘图案，且位于所述第一触控电极层远离所述衬底的一侧；和
第二触控电极层，具有第二触控电极图案，且位于所述触控绝缘层远离所述衬底的一侧，部分所述第二触控电极图案通过贯穿所述触控绝缘层的过孔与所述第一触控电极图案电连接。
在一些实施例中，所述触控结构还包括：
绝缘保护层，具有绝缘保护图案，且位于所述第二触控电极层远离所述衬底的一侧，被配置为对所述第二触控电极层进行绝缘保护。
在一些实施例中，所述第二间隔层与所述第一间隔层位于同层且材料相同。
在一些实施例中，所述触控绝缘层与所述第一间隔层位于同层且材料相同，所述第二触控电极层与所述第一金属层位于同层且材料相同。
在一些实施例中，所述显示基板还包括：
第一绝缘层，位于所述第一钝化层与所述衬底之间；和
第二绝缘层，位于所述第一绝缘层与所述第一钝化层之间，
其中，所述引脚包括：
第一引脚金属层，位于所述第一绝缘层远离所述衬底一侧的表面上，且部分地由所述第二绝缘层覆盖。
在一些实施例中，所述显示基板还包括：
第三绝缘层，位于所述第二绝缘层与所述第一钝化层之间，
其中，所述引脚还包括：
第二引脚金属层，位于所述第三绝缘层远离所述衬底一侧的表面上，通过贯穿所述第二绝缘层和第三绝缘层的过孔与所述第一引脚金属层电连接，所述第二引脚金属层还与所述第一金属层电连接。
在一些实施例中，所述显示基板还包括：
薄膜晶体管器件，包括有源层、栅极、源极和漏极，所述有源层位于所述第一绝缘层与所述衬底之间，所述栅极位于所述第一绝缘层远离所述衬底一侧的表面，所述源极和所述漏极位于所述第三绝缘层远离所述衬底一侧的表面，并通过贯穿所述第一绝缘层、所述第二绝缘层和所述第三绝缘层的过孔分别与所述有源层电连接；和
电容器件，包括第一电容极板和第二电容极板，所述第一电容极板位于所述第一绝缘层远离所述衬底一侧的表面，所述第二电容极板位于所述第二绝缘层远离所述衬底一侧的表面；
其中，所述栅极、所述第一电容极板和所述第一引脚金属层位于同层且材料相同，所述源极、所述漏极和所述第二引脚金属层位于同层且材料相同。
在一些实施例中，所述显示基板还包括：
第二钝化层，位于所述第三绝缘层远离所述衬底的一侧，且覆盖所述源极和所述漏极；和
平坦化层，位于所述第二钝化层远离所述衬底的一侧，
其中，所述多个发光元件位于所述平坦化层与所述封装层之间，所述第二钝化层与所述第一钝化层位于同层且材料相同。
在本公开的另一个方面，提供一种显示装置，包括前述的显示面板。
在本公开的又一个方面，提供一种显示面板的制造方法，包括：
形成具有显示区和围绕所述显示区的非显示区的显示基板，所述显示基板包括衬底和形成在衬底一侧且位于所述非显示区的IC接合部，
其中，形成所述IC接合部的步骤包括：
在所述衬底一侧形成引脚；
在所述衬底邻近引脚的一侧形成第一钝化层，并使所述第一钝化层覆盖在所述引脚的周边区域，并露出所述引脚的中心区域；
在所述第一钝化层远离所述衬底的一侧形成第一间隔层，并使所述第一间隔层覆盖所述第一钝化层和所述第一钝化层与所述引脚相接的边缘；和
在所述第一间隔层远离所述衬底的一侧形成第一金属层，并使所述第一金属层至少覆盖所述引脚的中心部位，并与所述引脚电连接。
在一些实施例中，在形成所述第一钝化层的步骤和形成所述第一间隔层的步骤之间，还包括：
在所述第一钝化层远离所述衬底的一侧形成平坦化层；
去除所述平坦化层至少对应于所述引脚的部分。
附图说明
构成说明书的一部分的附图描述了本公开的实施例，并且连同说明书一起用于解释本公开的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本公开，其中：
图1是根据本公开显示面板的一实施例中显示基板的整体布局及IC接合部的局部示意图；
图2是根据本公开显示面板的一实施例中IC接合部所在区域的AA截面结构示意图；
图3是根据本公开显示面板的一实施例中显示区的截面结构示意图；
图4是根据本公开显示面板的制造方法的一实施例中形成IC接合部的流程示意图；
图5是根据本公开显示面板的制造方法的一实施例中形成发光元件、封装层和触控结构的流程示意图。
应当明白，附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。此外，相同或类似的参考标号表示相同或类似的构件。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。对示例性实施例的描述仅仅是说明性的，决不作为对本公开及其应用或使用的任何限制。本公开可以以许多不同的形式实现，不限于这里所述的实施例。提供这些实施例是为了使本公开透彻且完整，并且向本领域技术人员充分表达本公开的范围。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、材料的组分、数字表达式和数值应被解释为仅仅是示例性的，而不是作为限制。
本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的部分。“包括”或者“包含”等类似的词语意指在该词前的要素涵盖在该词后列举的要素，并不排除也涵盖其他要素的可能。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开中，当描述到特定器件位于第一器件和第二器件之间时，在该特定器件与第一器件或第二器件之间可以存在居间器件，也可以不存在居间器件。当描述到特定器件连接其它器件时，该特定器件可以与所述其它器件直接连接而不具有居间器件，也可以不与所述其它器件直接连接而具有居间器件。
本公开使用的所有术语(包括技术术语或者科学术语)与本公开所属领域的普通技术人员理解的含义相同，除非另外特别定义。还应当理解，在诸如通用字典中定义的术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。
在有些相关技术中，显示基板的IC接合区域(IC bonding区域)的接合部引脚由有机材料膜层(例如平坦化层)进行包覆。经研究发现，在FMLOC工艺中，在IC接合区域形成间隔层(即barrier层)时，间隔层与有机材料膜层的粘附力较差。而且，有机材料膜层未被间隔层包覆的边缘部分裸露。这都使得有机材料膜层容易在FMLOC工艺中的水洗步骤中吸水。而当后续显示基板进行有关测试，例如高温高湿的信赖性测试时，有机材料膜层内吸收的水分受热膨胀，可能导致IC接合区域的间隔层以及金属层等剥落。
在另一些相关技术中，在形成间隔层时，使间隔层包覆有机材料膜层的边缘部分，不使其裸露。经研究发现，在采用这种结构时，IC接合区域的接合部引脚上覆盖的 金属层也会覆盖在包覆有机材料膜层的间隔层上，因此其边缘区域与未覆盖间隔层和有机材料膜层的中心区域可达到1.2μm的高度差。这样在通过异向导电胶膜(Anisotropic Conductive Film，简称ACF)实现金属层与IC芯片的管脚之间的电连接时，ACF对应于金属层的边缘区域的导电粒子受力较大，容易压裂间隔层，这使得有机材料膜层容易在FMLOC工艺中的水洗步骤中经过间隔层的裂缝吸水。而当后续显示基板进行有关测试，例如高温高湿的信赖性测试时，有机材料膜层内吸收的水分受热膨胀，可能导致IC接合区域的间隔层以及金属层等剥落。
有鉴于此，本公开实施例提供一种显示面板、显示装置及显示面板的制造方法，能够改善IC接合区域的间隔层以及金属层剥落等不良情形。
图1是根据本公开显示面板的一实施例中显示基板的整体布局及IC接合部的局部示意图。图2是根据本公开显示面板的一实施例中IC接合部所在区域的AA截面结构示意图。
参考图1，在一些实施例中，显示面板包括显示基板1。显示基板1具有显示区10A和围绕所述显示区10A的非显示区10B。显示区10A用于显示图像，非显示区10B用于布置相关电路和相关电子元件，以支持显示区10A的显示。
显示区10A的具体形状不限，例如呈圆形、椭圆形或者多边形等等。参考图1，在一些实施例中，显示区10A大致呈多边形，例如大致呈图1所示的矩形。这里显示区10A大致呈多边形可以理解为：在忽略显示区域的圆倒角、斜倒角或者工艺误差后，显示区10A的形状为多边形。
在图1中，所述显示基板1包括衬底10和设置在衬底10一侧且位于所述非显示区10B的IC接合部20。IC接合部20被配置为连接可向显示基板中的显示像素提供驱动信号、数据信号和时钟信号等，以及向显示基板提供检测信号等的IC芯片的管脚。
在一些实施例中，显示基板1为主动矩阵有机发光二极管(Active Matrix Organic Light-Emitting Diode，AMOLED)显示基板或被动矩阵有机发光二极管(Passive Matrix Organic Light-Emitting Diode，PMOLED)显示基板。例如，在显示基板10为AMOLED显示基板时，其衬底10可以为柔性衬底(例如聚酰亚胺材料)或者硬质衬底(例如玻璃或树脂材料)。
在图2中，IC接合部20包括：引脚21、第一钝化层(PVX)22、第一间隔层23和第一金属层24。第一钝化层22位于所述衬底10邻近引脚21的一侧，并覆盖在所 述引脚21的周边区域，并露出所述引脚21的中心区域。第一钝化层22可采用无机材料形成，例如氧化硅SiOx、氮化硅SiNx或氮氧化硅SiNO等硅的化合物。
第一间隔层23位于所述第一钝化层22远离所述衬底10的一侧，并覆盖所述钝化层22和所述第一钝化层22与所述引脚21相接的边缘。第一间隔层23可采用绝缘材料制成，例如氮化硅SiNx。第一金属层24位于所述第一间隔层23远离所述衬底10的一侧，至少覆盖所述引脚21的中心部位，并与所述引脚21电连接。
相比于相关技术中IC接合区域采用通过平坦化层等有机材料膜层包覆引脚的周边区域的结构，本实施例通过第一钝化层22包覆引脚21的周边区域，其与第一间隔层23之间粘附力优于相关技术中有机材料膜层与间隔层的粘附力，不容易从第一钝化层22上剥落，而且还可避免有机材料膜层吸收水汽并受热膨胀，而导致间隔层和金属层剥落的情形，进一步使得IC接合部中的第一间隔层23和第一金属层24更不容易剥落。
参考图2，在一些实施例中，显示面板还包括：IC芯片4和导电胶膜41。IC芯片4具有芯片管脚42，所述IC芯片4位于所述第一金属层24远离所述衬底10的一侧。导电胶膜41位于所述IC芯片4的芯片管脚42与所述第一金属层24之间，且与所述IC芯片4的芯片管脚42与所述第一金属层24均电连接。导电胶膜41可采用ACF。
相比于相关技术中采用间隔层包覆有机材料膜层的边缘部分，并采用ACF连接金属层与IC芯片的管脚的结构，本实施例中第一间隔层23直接包覆在第一钝化层22，因此形成在第一间隔层23和IC芯片4上的第一金属层24的边缘和中心的高度差相对较小，这使得导电胶膜41对应于边缘位置的导电粒子受力相对较小，不容易压裂第一间隔层23。另一方面，也可避免有机材料膜层经间隔层的裂缝吸收水汽并受热膨胀，而导致间隔层和金属层剥落的情形，进一步使得IC接合部中的第一间隔层23和第一金属层24更不容易剥落。
在图2中，显示基板还包括：第一绝缘层12a和第二绝缘层12b。第一绝缘层12a位于所述第一钝化层22与所述衬底10之间。第二绝缘层12b位于所述第一绝缘层12a与所述第一钝化层22之间。
第一绝缘层(例如第一栅绝缘层GI1)12a和第二绝缘层(例如第二栅绝缘层GI2)12b的材料均可包括硅化合物或金属氧化物，例如，氮氧化硅SiNO、氧化硅SiOx、氮化硅SiNx、碳氧化硅SiCxOy、碳化氮硅SiCxNy、氧化铝AlOx、氮化铝AlNx、氧 化钽TaOx、氧化铪HfOx、氧化锆ZrOx、氧化钛TiOx等。第一绝缘层12a和第二绝缘层12b可以为单层或多层。
IC接合部20中的引脚21可在形成显示基板1中的显示像素过程中同步形成。参考图2，在一些实施例中，引脚21包括第一引脚金属层21a。第一引脚金属层21a位于所述第一绝缘层12a远离所述衬底10一侧的表面上，且部分地由所述第二绝缘层12b覆盖。
参考图2，在一些实施例中，显示基板还包括第三绝缘层12c。第三绝缘层12c位于所述第二绝缘层12b与所述第一钝化层22之间。第三绝缘层(例如层间绝缘层ILD)12c的材料可包括硅化合物、金属氧化物等。具体可以选择上文所列举的硅化合物和金属氧化物，这里不再赘述。
在图2中，引脚21还包括第二引脚金属层21b。第二引脚金属层21b位于所述第三绝缘层12c远离所述衬底10一侧的表面上，通过贯穿所述第二绝缘层12b和第三绝缘层12c的过孔与所述第一引脚金属层21a电连接，所述第二引脚金属层21b还与所述第一金属层24电连接。
图3是根据本公开显示面板的一实施例中显示区的截面结构示意图。
参考图3，在一些实施例中，显示面板还包括触控结构30。触控结构30采用前述的FMLOC工艺形成在显示基板1上。触控结构30至少位于所述显示基板1的显示区10A。在一些实施例中，触控结构30位于显示区10A。在另一些实施例中，触控结构30位于显示区10A和非显示区10B。
对于采用FMLOC工艺形成的触控结构30来说，由于其工艺中的每道光掩模(Photo Mask)工艺之前需要对显示基板进行水洗，相关技术中IC接合区域中的有机材料膜层容易在水洗过程中吸水，而本实施例中的IC接合部由于采用第一钝化层22包覆引脚21的周边区域，避免了采用有机材料膜层包覆引脚时有机材料容易吸水的问题。
在图3中，显示基板1还包括：多个发光元件15和封装层19。多个发光元件15设置在所述衬底10邻近所述IC接合部20的一侧，且位于所述显示区10A。对于AMOLED显示基板来说，显示基板1还可包括薄膜晶体管器件13和电容器件14。薄膜晶体管器件13与发光元件15电连接，以便向控制发光元件15，以使各个发光元件15独立发光。
薄膜晶体管器件13可包括有源层13a、栅极13b、源极13c和漏极13d。所述有 源层13a位于所述第一绝缘层12a与所述衬底10之间，所述栅极13b位于所述第一绝缘层12a远离所述衬底10一侧的表面，所述源极13c和所述漏极13d位于所述第三绝缘层12c远离所述衬底10一侧的表面，并通过贯穿所述第一绝缘层12a、所述第二绝缘层12b和所述第三绝缘层12c的过孔分别与所述有源层13a电连接。
有源层13a的材料可包括无机半导体材料(例如多晶硅或非晶硅等)、有机半导体材料或氧化物半导体材料。栅极13b的材料可包括金属、金属合金、金属氮化物、导电金属氧化物或透明导电材料等，例如银、铜、铝合金、氮化铝、氧化锡、氧化铟锡等。源极13c和漏极13d的材料可以包括金属、合金、金属氮化物、导电金属氧化物或透明导电材料等，例如，多层金属Mo-Al-Mo或Ti-Al-Ti。
电容器件14可包括第一电容极板14a和第二电容极板14b，所述第一电容极板14a位于所述第一绝缘层12a远离所述衬底10一侧的表面，所述第二电容极板14b位于所述第二绝缘层12b远离所述衬底10一侧的表面。
在一些实施例中，栅极13b、第一电容极板14a和第一引脚金属层21a位于同层且材料相同，这样有利于栅极13b、第一电容极板14a和第一引脚金属层21a通过同一构图工艺形成，从而简化工艺。在一些实施例中，源极13c、漏极13d和第二引脚金属层21b位于同层且材料相同，这样有利于源极13c、漏极13d和第二引脚金属层21b通过同一构图工艺形成，从而简化工艺。
这里和后面提到的同层同材料的结构可以为采用同一成膜工艺形成具有特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。这些特定图形还可能处于不同的高度或者具有不同的厚度。
在图2和图3中，在第一绝缘层12a与衬底10之间还可设置缓冲层11。缓冲层11用于防止或减少金属原子或杂质从衬底扩散到晶体管的有源层中。缓冲层11可包括氧化硅SiOx、氮化硅SiNx或氮氧化硅SiNO等无机材料，并可形成为单层或多层。
参考图3，在一些实施例中，显示基板1还包括：第二钝化层16和平坦化层17。第二钝化层16位于所述第三绝缘层12c远离所述衬底10的一侧，且覆盖所述源极13c和所述漏极13d。在一些实施例中，第二钝化层16与所述第一钝化层22位于同层且材料相同，有利于通过同一构图工艺形成，从而简化工艺。
平坦化层17位于所述第二钝化层16远离所述衬底10的一侧。多个发光元件15 位于所述平坦化层17与所述封装层19之间。平坦化层的材料可以包括有机绝缘材料制成，例如聚酰亚胺、环氧树脂、压克力、聚酯、光致抗蚀剂、聚丙烯酸酯、聚酰胺、硅氧烷等树脂类材料等或氨基甲酸乙酯、热塑性聚氨酯等弹性材料。
在形成平坦化层17时，平坦化层17也可形成在IC接合区域，例如形成在第一钝化层22远离衬底10一侧的表面上。为了避免相关技术中包括有机材料的平坦化层容易吸水的问题，可通过刻蚀等工艺将平坦化层17至少对应于所述引脚21的部分去除。
参考图3，发光元件15可以为OLED发光元件。该发光元件可包括第一电极层15a、有机发光层15b和第二电极层15c。第一电极层15a位于平坦化层17和像素定义层18之间，有机发光层15b位于像素定义层18所界定的像素开口内，第二电极层15c位于有机发光层15b远离衬底10的一侧。第一电极层15a可通过贯穿平坦化层17和第二钝化层16的过孔与漏极13d电连接。
在一些实施例中，第一电极层15a作为发光元件15的阳极层，第二电极层15c作为发光元件15的阴极。第一电极层15a和第二电极层15b均可以采用金属、金属合金、金属氮化物、导电金属氧化物或透明导电材料等材料制成。有机发光层15b可以包括小分子有机材料或聚合物分子有机材料，例如荧光发光材料或磷光发光材料，可以发出红光、绿光、蓝光或白光。
参考图3，在一些实施例中，触控结构30包括第二间隔层31。第二间隔层31位于所述封装层19远离所述衬底10的一侧，且覆盖在所述封装层19的表面。在一些实施例中，第二间隔层31与所述第一间隔层23位于同层且材料相同，这样有利于第二间隔层31与第一间隔层23通过同一构图工艺形成，从而简化工艺。
参考图3，在一些实施例中，触控结构30包括第一触控电极层32。第一触控电极层32具有第一触控电极图案(TSP Metal A，简称TMA)，且位于所述第二间隔层31远离所述衬底10的一侧。第一触控电极层32的材料可包括金属、合金、金属氮化物、导电金属氧化物或透明导电材料等，例如，多层金属Mo-Al-Mo或Ti-Al-Ti。
第一触控电极图案可用于形成桥接区域的下层通道，还可用于位于周边的触控驱动电极TX的上下接入与触控感应电极RX信号走线的左右接入。在另一些实施例中，触控驱动电极TX和触控感应电极RX可分别横向和纵向，或者根据需要采用其他布置方式。
在图3中，触控结构30还包括：触控绝缘层33和第二触控电极层34。触控绝缘 层33具有触控绝缘图案，且位于所述第一触控电极层32远离所述衬底10的一侧。触控绝缘层33的材料可包括无机材料，例如氧化硅SiOx、氮化硅SiNx或氮氧化硅SiNO，可作为层间介质层起到绝缘作用。在一些实施例中，触控绝缘层33与所述第一间隔层23位于同层且材料相同，这样有利于触控绝缘层33与第一间隔层23通过同一构图工艺形成，从而简化工艺。
第二触控电极层34具有第二触控电极图案(TSP Metal B，简称TMB)，且位于所述触控绝缘层33远离所述衬底10的一侧，部分所述第二触控电极图案通过贯穿所述触控绝缘层33的过孔与所述第一触控电极图案电连接。第二触控电极图案可用于形成桥接区域的上层通道，还可用于形成桥接区域之外的金属网电极以及位于周边的信号走线。在一些实施例中，第二触控电极层34与所述第一金属层24位于同层且材料相同，这样有利于第二触控电极层34与所述第一金属层24通过同一构图工艺形成，从而简化工艺。
参考图3，在一些实施例中，触控结构30还包括绝缘保护层35。绝缘保护层35具有绝缘保护图案，且位于所述第二触控电极层34远离所述衬底10的一侧，被配置为对所述第二触控电极层34进行绝缘保护。绝缘保护层35的材料可包括无机绝缘材料或有机绝缘材料，例如聚酰亚胺。
本公开的上述显示面板实施例可适用于各类显示装置。因此，本公开还提供了一种显示装置，包括前述的显示面板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
图4是根据本公开显示面板的制造方法的一实施例中形成IC接合部的流程示意图。
参考图4和本公开的前述显示面板实施例，在一些实施例中，显示面板的制造方法包括：形成具有显示区10A和围绕所述显示区10A的非显示区10B的显示基板1，所述显示基板1包括衬底10和形成在衬底10一侧且位于所述非显示区10B的IC接合部20。在形成显示基板1的过程中，形成所述IC接合部20的步骤可包括步骤110到步骤140。
在步骤110之前，先形成衬底10。在步骤110中，在所述衬底10一侧形成引脚21。在步骤120中，在所述衬底10邻近引脚21的一侧形成第一钝化层22，并使所述第一钝化层22覆盖在所述引脚21的周边区域，并露出所述引脚21的中心区域。
在步骤130中，在所述第一钝化层22远离所述衬底10的一侧形成第一间隔层23， 并使所述第一间隔层23覆盖所述第一钝化层22和所述第一钝化层22与所述引脚21相接的边缘。在步骤140中，在所述第一间隔层23远离所述衬底10的一侧形成第一金属层24，并使所述第一金属层24至少覆盖所述引脚21的中心部位，并与所述引脚21电连接。
相比于相关技术中IC接合区域采用通过平坦化层等有机材料膜层包覆引脚的周边区域的结构，本实施例通过第一钝化层22包覆引脚21的周边区域，其与第一间隔层23之间粘附力优于相关技术中有机材料膜层与间隔层的粘附力，不容易从第一钝化层22上剥落，而且还可避免有机材料膜层吸收水汽并受热膨胀，而导致间隔层和金属层剥落的情形，进一步使得IC接合部中的第一间隔层23和第一金属层24更不容易剥落。
在一些实施例中，在图4中形成所述第一钝化层22的步骤120和形成所述第一间隔层23的步骤130之间，还可包括：在所述第一钝化层22远离所述衬底10的一侧形成平坦化层17；去除所述平坦化层17至少对应于所述引脚21的部分。在去除平坦化层时，可通过激光或化学刻蚀的方式去除平坦化层材料。在另一些实施例中，还可在步骤120之后，通过设置平坦化层的掩膜版的开口位置使得平坦化层不覆盖IC接合区域中的第一钝化层22和引脚21。
图5是根据本公开显示面板的制造方法的一实施例中形成发光元件、封装层和触控结构的流程示意图。
参考图5，在一些实施例中，形成所述显示基板1的步骤还包括步骤210和步骤220。在步骤210中，在所述衬底10邻近所述IC接合部20的一侧且对应于所述显示区10A的位置形成多个发光元件15。在步骤220中，在所述多个发光元件15远离所述衬底10的一侧形成封装层19，以对所述显示基板1进行封装。
在一些实施例中，显示面板的制造方法还包括：在所述封装层19远离所述衬底10的一侧形成触控结构30。触控结构30可通过FMLOC工艺形成。参考图5，形成所述触控结构30的步骤可包括步骤230到步骤270。在步骤230中，在所述封装层19远离所述衬底10的一侧形成第二间隔层31，并使所述第二间隔层31覆盖在所述封装层19的表面。
在步骤240中，在所述第二间隔层31远离所述衬底10的一侧形成具有第一触控电极图案的第一触控电极层32。在步骤250中，在所述第一触控电极层32远离所述衬底10的一侧形成具有触控绝缘图案的触控绝缘层33。
在步骤260中，在所述触控绝缘层33远离所述衬底10的一侧形成具有第二触控电极图案的第二触控电极层34，并使部分所述第二触控电极图案通过贯穿所述触控绝缘层33的过孔与所述第一触控电极图案电连接。在步骤270中，在所述第二触控电极层34远离所述衬底10的一侧形成具有绝缘保护图案的绝缘保护层35，以便对所述第二触控电极层34进行绝缘保护。
在上述实施例中，所述第二间隔层31与所述第一间隔层23通过同一构图工艺形成，所述第二触控电极层34与所述第一金属层24通过同一构图工艺形成。这样有利于简化工艺。在另一些实施例中，触控绝缘层33与所述第一间隔层23通过同一构图工艺形成，这样有利于简化工艺。
上述步骤240到步骤270中均可采用光掩模(Photo Mask)工艺分别形成第一触控电极图案、第二触控电极图案、触控绝缘图案和绝缘保护图案。在另一些实施例中，这些图案也可采用化学气相沉积(Chemical Vapor Deposition，简称CVD)工艺形成。
本说明书中多个实施例采用递进的方式描述，各实施例的重点有所不同，而各个实施例之间相同或相似的部分相互参见即可。对于方法实施例而言，由于其整体以及涉及的步骤与显示面板实施例中的内容存在对应关系，因此描述的比较简单，相关之处参见显示面板实施例的部分说明即可。
至此，已经详细描述了本公开的各实施例。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本公开的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本公开的范围。本领域的技术人员应该理解，可在不脱离本公开的范围和精神的情况下，对以上实施例进行修改或者对部分技术特征进行等同替换。本公开的范围由所附权利要求来限定。

Claims (15)

  1. 一种显示面板，包括：
    显示基板，具有显示区和围绕所述显示区的非显示区，所述显示基板包括衬底和设置在衬底一侧且位于所述非显示区的集成电路接合部，其中，所述集成电路接合部包括：
    引脚；
    第一钝化层，位于所述衬底邻近引脚的一侧，并覆盖在所述引脚的周边区域，并露出所述引脚的中心区域；
    第一间隔层，位于所述第一钝化层远离所述衬底的一侧，并覆盖所述第一钝化层和所述第一钝化层与所述引脚相接的边缘；和
    第一金属层，位于所述第一间隔层远离所述衬底的一侧，至少覆盖所述引脚的中心部位，并与所述引脚电连接。
  2. 根据权利要求1所述的显示面板，还包括：
    集成电路芯片，具有芯片管脚，所述集成电路芯片位于所述第一金属层远离所述衬底的一侧；和
    导电胶膜，位于所述集成电路芯片的芯片管脚与所述第一金属层之间，且与所述集成电路芯片的芯片管脚与所述第一金属层均电连接。
  3. 根据权利要求1或2所述的显示面板，还包括：
    触控结构，至少位于所述显示基板的显示区；
    其中，所述显示基板还包括：
    多个发光元件，设置在所述衬底邻近所述集成电路接合部的一侧，且位于所述显示区；和
    封装层，位于所述多个发光元件与所述触控结构之间，被配置为对所述显示基板进行封装。
  4. 根据权利要求3所述的显示面板，其中，所述触控结构包括：
    第二间隔层，位于所述封装层远离所述衬底的一侧，且覆盖在所述封装层的表面。
  5. 根据权利要求3所述的显示面板，其中，所述触控结构还包括：
    第一触控电极层，具有第一触控电极图案，且位于所述第二间隔层远离所述衬底的一侧；
    触控绝缘层，具有触控绝缘图案，且位于所述第一触控电极层远离所述衬底的一侧；和
    第二触控电极层，具有第二触控电极图案，且位于所述触控绝缘层远离所述衬底的一侧，部分所述第二触控电极图案通过贯穿所述触控绝缘层的过孔与所述第一触控电极图案电连接。
  6. 根据权利要求5所述的显示面板，其中，所述触控结构还包括：
    绝缘保护层，具有绝缘保护图案，且位于所述第二触控电极层远离所述衬底的一侧，被配置为对所述第二触控电极层进行绝缘保护。
  7. 根据权利要求4所述的显示面板，其中，所述第二间隔层与所述第一间隔层位于同层且材料相同。
  8. 根据权利要求5所述的显示面板，其中，所述触控绝缘层与所述第一间隔层位于同层且材料相同，所述第二触控电极层与所述第一金属层位于同层且材料相同。
  9. 根据权利要求3所述的显示面板，其中，所述显示基板还包括：
    第一绝缘层，位于所述第一钝化层与所述衬底之间；和
    第二绝缘层，位于所述第一绝缘层与所述第一钝化层之间，
    其中，所述引脚包括：
    第一引脚金属层，位于所述第一绝缘层远离所述衬底一侧的表面上，且部分地由所述第二绝缘层覆盖。
  10. 根据权利要求9所述的显示面板，其中，所述显示基板还包括：
    第三绝缘层，位于所述第二绝缘层与所述第一钝化层之间，
    其中，所述引脚还包括：
    第二引脚金属层，位于所述第三绝缘层远离所述衬底一侧的表面上，通过贯穿所述第二绝缘层和第三绝缘层的过孔与所述第一引脚金属层电连接，所述第二引脚金属层还与所述第一金属层电连接。
  11. 根据权利要求10所述的显示面板，其中，所述显示基板还包括：
    薄膜晶体管器件，包括有源层、栅极、源极和漏极，所述有源层位于所述第一绝缘层与所述衬底之间，所述栅极位于所述第一绝缘层远离所述衬底一侧的表面，所述源极和所述漏极位于所述第三绝缘层远离所述衬底一侧的表面，并通过贯穿所述第一绝缘层、所述第二绝缘层和所述第三绝缘层的过孔分别与所述有源层电连接；和
    电容器件，包括第一电容极板和第二电容极板，所述第一电容极板位于所述第一 绝缘层远离所述衬底一侧的表面，所述第二电容极板位于所述第二绝缘层远离所述衬底一侧的表面；
    其中，所述栅极、所述第一电容极板和所述第一引脚金属层位于同层且材料相同，所述源极、所述漏极和所述第二引脚金属层位于同层且材料相同。
  12. 根据权利要求11所述的显示面板，其中，所述显示基板还包括：
    第二钝化层，位于所述第三绝缘层远离所述衬底的一侧，且覆盖所述源极和所述漏极；和
    平坦化层，位于所述第二钝化层远离所述衬底的一侧，
    其中，所述多个发光元件位于所述平坦化层与所述封装层之间，所述第二钝化层与所述第一钝化层位于同层且材料相同。
  13. 一种显示装置，包括：
    权利要求1～12任一所述的显示面板。
  14. 一种显示面板的制造方法，包括：
    形成具有显示区和围绕所述显示区的非显示区的显示基板，所述显示基板包括衬底和形成在衬底一侧且位于所述非显示区的集成电路接合部，
    其中，形成所述集成电路接合部的步骤包括：
    在所述衬底一侧形成引脚；
    在所述衬底邻近引脚的一侧形成第一钝化层，并使所述第一钝化层覆盖在所述引脚的周边区域，并露出所述引脚的中心区域；
    在所述第一钝化层远离所述衬底的一侧形成第一间隔层，并使所述第一间隔层覆盖所述第一钝化层和所述第一钝化层与所述引脚相接的边缘；和
    在所述第一间隔层远离所述衬底的一侧形成第一金属层，并使所述第一金属层至少覆盖所述引脚的中心部位，并与所述引脚电连接。
  15. 根据权利要求14所述的显示面板的制造方法，其中，在形成所述第一钝化层的步骤和形成所述第一间隔层的步骤之间，还包括：
    在所述第一钝化层远离所述衬底的一侧形成平坦化层；
    去除所述平坦化层至少对应于所述引脚的部分。
PCT/CN2021/115874 2020-10-30 2021-09-01 显示面板、显示装置及显示面板的制造方法 WO2022088942A1 (zh)

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CN109309101A (zh) * 2018-10-25 2019-02-05 昆山国显光电有限公司 显示面板及显示装置
CN111524908A (zh) * 2020-04-28 2020-08-11 京东方科技集团股份有限公司 显示面板及显示装置
CN111755463A (zh) * 2020-06-24 2020-10-09 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
CN111785757A (zh) * 2020-07-14 2020-10-16 京东方科技集团股份有限公司 显示装置、显示面板及其制造方法
CN113053923A (zh) * 2021-03-15 2021-06-29 武汉华星光电半导体显示技术有限公司 显示面板和显示装置

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