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WO2021238467A1 - 显示装置 - Google Patents

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Publication number
WO2021238467A1
WO2021238467A1 PCT/CN2021/086799 CN2021086799W WO2021238467A1 WO 2021238467 A1 WO2021238467 A1 WO 2021238467A1 CN 2021086799 W CN2021086799 W CN 2021086799W WO 2021238467 A1 WO2021238467 A1 WO 2021238467A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
sub
spacer
pixels
array substrate
Prior art date
Application number
PCT/CN2021/086799
Other languages
English (en)
French (fr)
Inventor
王孟杰
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/765,429 priority Critical patent/US20220365384A1/en
Publication of WO2021238467A1 publication Critical patent/WO2021238467A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13398—Spacer materials; Spacer properties
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13396—Spacers having different sizes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making

Definitions

  • the present disclosure relates to the field of display technology, and more particularly to a display device.
  • liquid crystal display technology has been successfully applied to display products such as notebook computers, monitors, and televisions. With the increase in the possession of liquid crystal display products, people have also put forward higher requirements for the display quality of liquid crystal products.
  • a display device includes an array substrate and a counter substrate arranged opposite to the array substrate.
  • the array substrate includes a first substrate and a plurality of sub-pixels arranged on the first substrate and arranged in an array.
  • the counter substrate includes a second substrate and a plurality of first spacers arranged on a side of the second substrate close to the array substrate. Wherein, the orthographic projection of the first spacer on the array substrate is located in the area where the area between two adjacent rows of sub-pixels and the area between two adjacent rows of sub-pixels intersect.
  • the opposite substrate further includes a plurality of second spacers. There is no overlap between the orthographic projection of the second spacer on the second substrate and the orthographic projection of the first spacer on the second substrate; the plurality of second spacers are arranged in Multiple rows, each row of second spacers are arranged along the column direction of the plurality of sub-pixels; the orthographic projection of each row of the second spacers on the array substrate is located in the column area where one row of sub-pixels is located Inside.
  • the plurality of second spacers and the plurality of first spacers are arranged in the same layer.
  • the size of the first spacer and the size of the second spacer are the same or substantially the same.
  • the area of the surface of the first spacer away from the second substrate and the area of the second spacer away from the second substrate is greater than 10,000 ⁇ m 2 .
  • the counter substrate further includes a plurality of filter patterns arranged on a side of the first spacer close to the second substrate.
  • An orthographic projection of a filter pattern on the array substrate covers a row of sub-pixels, and an orthographic projection of a first spacer on the second substrate is located within a range of a filter pattern.
  • the filter pattern In a direction perpendicular to the extension of the filter pattern, the filter pattern has a protruding portion where the first spacer is located.
  • the edge of the orthographic projection of the first spacer on the second substrate is located inside the edge of the protruding part of the filter pattern.
  • the orthographic projection of the protruding part on the second substrate is equal to the orthographic projection of the second spacer on the second substrate.
  • the projections have no overlap.
  • the filter pattern adjacent to the convex portion has a concave portion.
  • the protruding part extends into the recessed part.
  • the array substrate further includes a plurality of gate lines disposed on the first substrate. At least one gate line is located between two adjacent rows of sub-pixels.
  • the orthographic projection of the first spacer on the array substrate and the grid line have an overlapping area.
  • the counter substrate includes a plurality of second spacers, the orthographic projection of the second spacers on the array substrate and the grid line have an overlapping area.
  • the gate line has a convex portion.
  • the orthographic projection of the second spacers on the array substrate is located in the area where the protruding part of the grid line is located.
  • the protruding portion of the gate line protrudes toward a side away from a row of sub-pixels coupled to the gate line.
  • two gate lines are arranged between two adjacent rows of sub-pixels.
  • a gate line to which one sub-pixel is coupled is located on one of the opposite sides of the row of sub-pixels in the column direction;
  • the gate line to which another sub-pixel is coupled is located on the other side of the row of sub-pixels on the opposite sides in the column direction.
  • the counter substrate when the counter substrate includes a plurality of second spacers, in the area between two adjacent rows of sub-pixels, one of the two adjacent second spacers is the first
  • the orthographic projection of two spacers on the array substrate has an overlapping area with one of the two grid lines; the other of the two adjacent second spacers is in the The orthographic projection on the array substrate has an overlapping area with the other of the two grid lines.
  • the array substrate further includes a plurality of data lines disposed on the first substrate. Two adjacent columns of sub-pixels are coupled to one data line.
  • the array substrate further includes a plurality of common signals arranged on the first substrate.
  • the plurality of common signal lines and the plurality of data lines are arranged in the same layer and extend in the same direction.
  • a common signal line is located between two adjacent columns of sub-pixels; along the row direction of the sub-pixel arrangement, a common signal line is located between two adjacent data lines; the first spacer is located on the array substrate There is an overlap area between the orthographic projection and the common signal line.
  • the array substrate further includes thin film transistors arranged in the sub-pixels.
  • the thin film transistors in two adjacent sub-pixels in a row of sub-pixels are respectively located on opposite sides of the row of sub-pixels in the column direction.
  • the thin film transistor on one side is coupled to a gate line provided on the same side as the thin film transistor on the one side; the thin film transistor on the other side is coupled with the thin film transistor on the other side.
  • the thin film transistor on the other side is coupled to a gate line provided on the same side.
  • the orthographic projection of the second spacers on the array substrate does not overlap with the thin film transistor.
  • the orthographic projection of one second spacer on the array substrate overlaps with one thin film transistor.
  • the array substrate further includes a plurality of first electrodes disposed on the first substrate.
  • a first electrode is located in a sub-pixel; the first electrode is coupled to the thin film transistor.
  • the counter substrate further includes a second electrode provided on the second substrate. The second electrode is located on a side of the first spacer close to the second substrate.
  • the array substrate further includes a first electrode and a second electrode disposed on the first substrate and located in the sub-pixel.
  • the first electrode is a surface electrode
  • the second electrode is a slit electrode.
  • the first electrode is closer to the first substrate than the second electrode.
  • One of the first electrode and the second electrode is coupled to the thin film transistor.
  • FIG. 1 is a structural diagram of a display panel according to some embodiments
  • FIG. 2 is a cross-sectional view of the display panel in FIG. 1 along the direction A-A';
  • FIG. 3 is another structural diagram of a display panel according to some embodiments.
  • FIG. 4 is a cross-sectional view of the display panel in FIG. 3 along the direction B-B';
  • Fig. 5 is a cross-sectional view of the display panel in Fig. 3 along the direction C-C';
  • FIG. 6 is another structural diagram of a display panel according to some embodiments.
  • FIG. 7 is another structural diagram of a display panel according to some embodiments.
  • FIG. 8 is still another structural diagram of a display panel according to some embodiments.
  • FIG. 9 is a structural diagram of a display device according to some embodiments.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features.
  • plural means two or more.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • the exemplary embodiments are described herein with reference to cross-sectional views and/or plan views as idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Therefore, variations in the shape with respect to the drawings due to, for example, manufacturing technology and/or tolerances can be envisaged. Therefore, the exemplary embodiments should not be construed as being limited to the shape of the area shown herein, but include shape deviations due to, for example, manufacturing.
  • the etched area shown as a rectangle will generally have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the area of the device, and are not intended to limit the scope of the exemplary embodiments.
  • Pogo test Perform a pressing test on the display panel (Pogo test), that is, to fix the display panel on the press test platform, press the display panel with the indenter of the pressing test device (for example, the pressure is 50kgf), and then remove the indenter after holding for a period of time , Light up the display panel to confirm the pressing phenomenon.
  • the support area of the spacers is insufficient, which makes the display panel's compression resistance weaker, which causes the display panel to fail after the press test.
  • a dark spot appears at the pressing position, and the dark spot does not disappear for a long time or disappears slowly, which seriously affects the quality of the display panel.
  • An embodiment of the present disclosure provides a display device 200. As shown in FIG. 9, the display device 200 includes a display panel 100.
  • the display panel 100 includes an array substrate 10 and a counter substrate 20.
  • the array substrate 10 and the counter substrate 20 are disposed opposite to each other.
  • the display panel 100 further includes a liquid crystal layer 30 disposed between the array substrate 10 and the counter substrate 20.
  • the array substrate 10 includes a first substrate 101 and a plurality of sub-pixels P disposed on the first substrate 101.
  • the multiple sub-pixels P are arranged in an array.
  • the sub-pixels P arranged in a row along the horizontal direction X are called sub-pixels in the same row
  • the sub-pixels P arranged in a row along the vertical direction Y are called sub-pixels in the same column.
  • the counter substrate 20 includes a second substrate 201 and a plurality of first spacers 210 provided on the second substrate 201.
  • the orthographic projection of the first spacer 210 on the array substrate 10 is located in the area where the area between two adjacent rows of sub-pixels and the area between two adjacent rows of sub-pixels intersect.
  • the first spacer 210 can support the display panel 100, compared to the area between two adjacent rows of sub-pixels and the adjacent two rows. If there is no spacer in the area where the sub-pixels intersect with each other, the pressure resistance of the display panel 100 can be improved.
  • the orthographic projection of the first spacers 210 on the array substrate 10 is located in two adjacent rows.
  • the area between the pixels and the area between two adjacent columns of sub-pixels are in the area where they intersect each other, so that when the display panel 100 is pressed, the first spacer 210 can support the display panel 100.
  • the support of the spacers on the display panel 100 is increased.
  • the area increases the support strength of the display panel 100 and the pressure resistance capability of the display panel 100, thereby preventing the display panel 100 from being poorly pressed and improving the pressure resistance capability of the display device 200.
  • the counter substrate 20 further includes a plurality of second spacers 220.
  • the orthographic projection of the second spacer 220 on the second substrate 201 and the orthographic projection of the first spacer 210 on the second substrate 201 do not overlap.
  • the plurality of second spacers 220 are arranged in a plurality of rows, and each column of the second spacers 220 is arranged along the column direction in which the plurality of sub-pixels P are arranged.
  • the orthographic projection of each column of second spacers 220 on the array substrate 10 is located in a column area where a column of sub-pixels is located.
  • the column area where a column of sub-pixels is located may include the area where each sub-pixel in a column of sub-pixels is located and the area between every two adjacent rows of sub-pixels. Refer to the M area in FIG. 1.
  • the orthographic projection of the second spacer 220 on the array substrate 10 is located between two sub-pixels in the same column and in two adjacent rows.
  • the first spacer 210 and the second spacer 220 can jointly support the display panel 100, so that the supporting area of the display panel 100 is increased, and the display is improved.
  • the support strength of the panel 100 improves the compression resistance of the display panel 100, thereby preventing the display panel 100 from being pressed poorly.
  • the first spacer 210 and the second spacer 220 are both auxiliary spacers.
  • the auxiliary spacers (including the first spacer 210 and the second spacer 220) in the embodiments of the present disclosure
  • the distribution density is 50% higher than that of the original auxiliary spacer (only the second spacer 220 is included, and the first spacer 210 is not included).
  • the supporting area of the auxiliary spacer (including the first spacer 210 and the second spacer 220) is compared with that of the original auxiliary spacer.
  • the supporting area of the spacer (only the second spacer 220 is included, and the first spacer 210 is not included) is increased by 50%.
  • the distance between the first spacer 210 and the second spacer 220 adjacent to the first spacer 210 is greater than Deviation of process capability in actual production process. In this way, it is possible to avoid affecting the film-forming effect of the first spacer 210 and the second spacer 220 due to actual process errors, thereby avoiding affecting the supporting ability of the first spacer 210 and the second spacer 220, and avoiding The stress resistance of the display panel 100 is affected.
  • the plurality of second spacers 220 and the plurality of first spacers 210 are arranged in the same layer.
  • the material of the plurality of second spacers 220 is the same as the material of the plurality of first spacers 210.
  • the second spacer 220 and the first spacer 210 are formed simultaneously, thereby saving the process.
  • the size of the first spacer 210 and the size of the second spacer 220 are the same or substantially the same.
  • the distance between the surface of the first spacer 210 close to the array substrate 10 and the surface close to the second substrate 201 is the same as the distance between the surface close to the array substrate 10 and the surface close to the second spacer 220
  • the distance between the surfaces of the second substrate 201 is equal or approximately equal.
  • the area of the surface of the first spacer 210 away from the second substrate 201 and the area of the second spacer 220 away from the second substrate 201 are equal to each other.
  • the sum of the areas of the side surfaces is greater than 10000 ⁇ m 2 . In this way, the support strength of the display panel 100 can be increased, so as to avoid black spots or mura defects on the display panel 100.
  • the shape of the orthographic projection of the first spacer 210 on the array substrate 10 and the shape of the orthographic projection of the second spacer 220 on the array substrate 10 may be the same or different. For example, all of them may be circular or hexagonal.
  • the area of the orthographic projection of the first spacer 210 on the array substrate 10 and the area of the orthographic projection of the second spacer 220 on the array substrate 10 may be equal or not equal.
  • the counter substrate 20 further includes a plurality of filter patterns 202 disposed on the side of the first spacer 210 close to the second substrate 201.
  • the plurality of filter patterns 202 includes a red filter pattern, a blue filter pattern, and a green filter pattern.
  • the light emitted from the red filter pattern is red light
  • the light emitted from the blue filter pattern is blue light
  • the light emitted from the green filter pattern is green light.
  • An orthographic projection of a filter pattern 202 on the array substrate 10 covers a row of sub-pixels.
  • the orthographic projection of a first spacer 210 on the second substrate 201 is located within a range where a filter pattern 202 is located.
  • the filter pattern 202 In the extending direction perpendicular to the filter pattern 202 (ie, in the horizontal direction X in FIG. 3), the filter pattern 202 has a protruding portion T1 at the position where the first spacer 210 is located.
  • the edge of the orthographic projection of the first spacer 210 on the second substrate 201 is located inside the edge of the protruding portion T1 of the filter pattern 202.
  • the orthographic projection of the protruding portion T1 on the second substrate 201 and the orthographic projection of the second spacer 220 on the second substrate 201 do not overlap .
  • the bottom of the first spacer 210 is located on the same filter pattern 202, and will not straddle two adjacent filter patterns 202, because the same filter pattern 202 is compared with different filter patterns 202.
  • the thickness uniformity of the film layer is good, that is, the thickness uniformity of the convex portion T1 of the filter pattern 202 where the first spacer 210 is located is good. Therefore, the thickness of the first spacer 210 is close to the second substrate 201.
  • the surface of the side is flat, and during the pressing process of the display panel 100, the force of the first spacer 210 is uniform, so as to prevent the first spacer 210 from being damaged (for example, cracks).
  • the distance between the edges close to the protruding part T1 is greater than the deviation of the process capability in the actual production process. In this way, it is possible to avoid process errors that cause the orthographic projection of the first spacer 210 on the second substrate 201 to exceed the inner side of the edge of the protruding portion T1 of the filter pattern 202, and affect the first spacer 210 close to the second substrate.
  • the problem of the flatness of the surface on the side of the substrate 201 avoids affecting the supporting ability of the first spacer 210 and the compressive resistance of the display panel 100.
  • the filter pattern 202 adjacent to the convex portion T1 has a concave portion T2.
  • the protruding portion T1 extends into the recessed portion T2.
  • the protruding portion T1 may be in contact with the adjacent edge of the recessed portion T2 without a gap between the two. In the actual production process, the protruding portion T1 may overlap the adjacent edge of the recessed portion T2, or the protruding portion T1 and the adjacent edge of the recessed portion T2 may have a small gap or almost no gap.
  • the orthographic projection of the first spacer 210 on the first substrate 101 does not overlap with the overlapped area.
  • the orthographic projection of the first spacer 210 on the first substrate 101 does not overlap with the area where the gap exists. It can be understood that in the orthographic projection of the protruding portion T1 on the array substrate 10, it is close to an edge of the recessed portion T2 and coincides with an edge of the protruding portion T1 in the orthographic projection of the recessed portion T2 on the array substrate 10. .
  • the orthographic projection of the protruding portion T1 of one filter pattern 202 on the second substrate 201 does not overlap with the orthographic projection of the other filter pattern 202 on the second substrate 201.
  • the orthographic projection of the recessed portion T2 of one filter pattern 202 on the second substrate 201 has no overlap with the orthographic projection of the other filter pattern 202 on the second substrate 201.
  • the adjacent filter pattern 202 has a concave part T2, which will not cover the convex part T1, and will not affect the film uniformity of the convex part T1, so that the convex
  • the thickness at each position in the exit portion T1 is uniform.
  • the surface of the first spacer 210 close to the second substrate 201 is flat.
  • the force of the first spacer 210 is uniform, thereby avoiding the first spacer 210.
  • the cushion 210 is damaged.
  • the array substrate 10 further includes a plurality of gate lines GL disposed on the first substrate 101. At least one gate line GL is located between two adjacent rows of sub-pixels.
  • the orthographic projection of the first spacer 210 on the array substrate 10 has an overlapping area with the gate line GL.
  • the orthographic projection of the second spacers 220 on the array substrate 10 has an overlapping area with the gate line GL.
  • a metal material is used as the material of the gate line GL.
  • the first spacer 210 and the second spacer 220 are supported by the gate line GL on the side close to the array substrate 10, thereby improving the first spacer.
  • the supporting effect of the object 210 and the second spacer 220 is improved.
  • the position of the second spacer 220 can design the position of the second spacer 220 according to the size of the space between the gate line GL and the adjacent sub-pixels under the condition of ensuring the normal display of the display panel 100. For example, along the extending direction of the gate line GL, two adjacent second spacers 220 are arranged in a staggered manner.
  • the gate line GL has a convex portion.
  • the orthographic projection of the second spacers 220 on the array substrate 10 is located in the area where the protruding part of the gate line GL is located.
  • the second spacer 220 may be supported by the protruding part of the gate line GL, so that the contact surface of the second spacer 220 and the array substrate 10 is uniformly stressed. Therefore, damage to the second spacer 220 is avoided.
  • the protruding part of the gate line GL protrudes toward the side away from the row of sub-pixels coupled to the gate line GL. In this way, it can be avoided that the distance between the gate line GL and the sub-pixel P is too small to affect the size of the light-emitting area of the sub-pixel, thereby avoiding affecting the aperture ratio of the display panel 100.
  • two gate lines GL are arranged between two adjacent rows of sub-pixels.
  • the gate line GL to which one sub-pixel is coupled is located on one side of the row of sub-pixels on opposite sides in the column direction.
  • the gate line GL to which another sub-pixel is coupled is located on the other side of the row of sub-pixels on the opposite sides in the column direction.
  • a row of sub-pixels is coupled to two gate lines GL.
  • the odd-numbered columns of sub-pixels of a row of sub-pixels are coupled to one gate line GL, and the even-numbered columns of sub-pixels are coupled to another gate line GL.
  • the counter substrate 20 when the counter substrate 20 includes a plurality of second spacers 220, in the area between two adjacent rows of sub-pixels, two adjacent second spacers
  • the orthographic projection of a second spacer 220 in the spacer 220 on the array substrate 10 has an overlapping area with one of the two gate lines GL.
  • the orthographic projection of the other second spacer 220 of the two adjacent second spacers 220 on the array substrate 10 has an overlapping area with the other of the two gate lines GL.
  • the two gate lines GL in the region between the two adjacent rows of sub-pixels are respectively coupled to the two adjacent rows of sub-pixels.
  • the orthographic projection of two adjacent second spacers 220 on the array substrate 10 may also have an overlapping area with one of the two gate lines GL, but no intersection with the other gate line GL. Stacked area.
  • the array substrate 10 further includes a plurality of data lines DL disposed on the first substrate 101. Two adjacent columns of sub-pixels are coupled to one data line DL.
  • two adjacent columns of sub-pixels are divided into one group, and a data line DL is arranged between the two adjacent groups of sub-pixels.
  • the array substrate 10 further includes a plurality of common signal lines CL provided on the first substrate 101.
  • the extending directions of the plurality of common signal lines CL and the plurality of data lines DL are the same.
  • a common signal line CL is located between two adjacent columns of sub-pixels.
  • the common signal line CL is configured to transmit a common voltage signal to the sub-pixels.
  • one common signal line CL is located between two adjacent data lines DL.
  • the orthographic projection of the first spacer 210 on the array substrate 10 has an overlap area with the common signal line CL.
  • two adjacent columns of sub-pixels are divided into a group, a data line DL is arranged between two adjacent groups of sub-pixels, and a common signal line CL is arranged between two columns of sub-pixels in each group of sub-pixels.
  • the orthographic projection of the first spacer 210 on the array substrate 10 overlaps with the intersection area of the common signal line CL and the gate line GL.
  • the array substrate 10 further includes a thin film transistor (TFT) disposed in the sub-pixel P.
  • TFT thin film transistor
  • the TFTs in two adjacent sub-pixels in a row of sub-pixels are respectively located on opposite sides of the row of sub-pixels in the column direction.
  • the TFT located on one side is coupled to a gate line GL provided on the same side as the TFT on the side.
  • the TFT on the other side is coupled to a gate line GL provided on the same side as the TFT on the other side.
  • the orthographic projection of the second spacers 220 on the array substrate 10 does not overlap with the TFT.
  • the orthographic projection of a second spacer 220 on the array substrate 10 overlaps with a TFT.
  • the opposite substrate 20 also includes a main spacer, according to the main spacer and the second spacer 220 (ie auxiliary spacer The height difference of) and the position of the main spacer are designed for the position of the second spacer 220, which is not limited here.
  • the array substrate 10 further includes a plurality of first electrodes 110 disposed on the first substrate 101.
  • One first electrode 110 is located in one sub-pixel P.
  • the first electrode 110 is coupled to the TFT.
  • the first electrode 110 is a pixel electrode.
  • the counter substrate 20 further includes a second electrode 120 provided on the second substrate 201.
  • the second electrode 120 is located on the side of the first spacer 210 close to the second substrate 201.
  • the second electrode 120 is a common electrode.
  • the second electrode 120 is located on a side of the filter pattern 202 away from the first substrate 201.
  • the second electrode 120 is coupled with the common signal lines CL (not shown in the figure).
  • the array substrate 10 further includes a first electrode 110 and a second electrode 120 disposed on the first substrate 101 and located in the sub-pixel P.
  • the first electrode 110 is a surface electrode
  • the second electrode 120 is a slit electrode
  • the first electrode 110 is closer to the first substrate 101 than the second electrode 120.
  • One of the first electrode 110 and the second electrode 120 is coupled to the TFT. That is, the first electrode 110 is coupled to the TFT, and at this time, the first electrode 110 is a pixel electrode; or, the second electrode 120 is coupled to the TFT, and at this time, the second electrode 120 is a common electrode.
  • the array substrate 10 includes a plurality of common signal lines CL
  • the second electrode 120 is coupled to the common signal line CL; or, if the second electrode 120 is coupled to the common signal line CL.
  • the first electrode 110 is coupled to the common signal line CL.
  • the array substrate 10 further includes a plurality of common signal lines CL provided on the first substrate 101.
  • the plurality of common signal lines CL and the plurality of gate lines DL are arranged in the same layer and have the same material.
  • a common signal line CL is located in the area where a row of sub-pixels is located.
  • the orthographic projection of the common signal line CL on the first substrate 101 does not overlap with the TFT.
  • the common signal line CL has a plurality of bending line segments, and any two adjacent bending line segments are coupled by a conductive pattern at the edges that are close to each other.
  • the conductive pattern is in the same layer as the common electrode line CL, and the conductive pattern is on the first substrate.
  • the orthographic projection on 101 overlaps with the data line DL.
  • a bending line segment is located in the area where two adjacent sub-pixels in a row of sub-pixels are located, and a bending line segment includes five sub-line segments coupled in sequence, wherein the middle sub-line segment is located on the first substrate 101.
  • the edges on opposite sides in the extending direction of the gate line GL are respectively located in the sub-pixels, and the middle part is located in the gap area between the two sub-pixels.
  • the counter substrate 20 further includes a third spacer provided on the second substrate 201.
  • the third spacer serves as the main spacer and supports the display panel 100 during the process of pressing the display panel 100.
  • the supporting area of the display panel 100 by the third spacer is smaller than the supporting area of the display panel 100 by the first spacer 210 and the second spacer 220 as a whole.
  • the orthographic projection of the third spacer on the array substrate 10 does not overlap with the orthographic projection of the first spacer 210 on the array substrate 10 and the orthographic projection of the second spacer 220 on the array substrate 10.
  • the height of the third spacer is greater than or approximately equal to the height of the second spacer 220.
  • the orthographic projection of the first spacer 210 on the array substrate 10 may be located between the orthographic projection of the second spacer 220 on the array substrate 10 and the orthographic projection of the third spacer on the array substrate 10 .
  • the orthographic projection of the third spacer on the array substrate 10 overlaps the TFT or is located between two sub-pixels in two adjacent rows and overlaps the gate line GL, and a plurality of third spacers are in the array
  • the orthographic projections on the substrate 10 are uniformly distributed.
  • the array substrate 10 includes a plurality of sub-pixel groups, each sub-pixel group includes a plurality of sub-pixels P, each sub-pixel group includes the same number of sub-pixels P, and a third spacer is in the array
  • the orthographic projection on the substrate 10 is located in a sub-pixel group.
  • the orthographic projection of the second spacers 220 on the array substrate 10 does not overlap with the TFTs, and the counter substrate 20 includes the second spacers 220.
  • the height difference between the third spacer and the second spacer 220 that is, the auxiliary spacer
  • the orthographic projection of the third spacer on the array substrate 10 overlaps the TFT.
  • the third spacer that is, the main spacer
  • the second spacer 220 that is, the auxiliary spacer
  • the third spacer is positioned directly on the array substrate 10.
  • the counter substrate 20 when the counter substrate 20 includes a plurality of second spacers 220, and the orthographic projection of one second spacer 220 on the array substrate 10 overlaps with one TFT, the counter substrate 20 includes the first In the case of three spacers (that is, the main spacer), and the height difference between the third spacer and the second spacer 220 (that is, the auxiliary spacer) is large (for example, the height difference is greater than 0.5 ⁇ m), the first The orthographic projection of the three spacers on the array substrate 10 overlaps with the TFT.
  • the third spacer that is, the main spacer
  • the height difference between the third spacer and the second spacer 220 that is, the auxiliary spacer
  • the support capacity of the third spacer will be Insufficient, resulting in a reduction in the pressure resistance of the display panel 100.
  • the display device 200 further includes a driver IC (Driver IC).
  • the driving IC is bound to the array substrate 10 in the display panel 100 and coupled to the data line DL.
  • the driving IC is configured to transmit a data signal to the data line DL.
  • the above-mentioned display device 200 may be any device that displays images, whether in motion (for example, video) or fixed (for example, still images), and regardless of text or images. More specifically, it is expected that the described embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, and personal data assistants (PDAs).
  • PDAs personal data assistants
  • Handheld or portable computers GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, TV monitors, flat panel displays, computer monitors, car monitors (e.g., Odometer display, etc.), navigator, cockpit controller and/or display, camera view display (for example, the display of a rear-view camera in a vehicle), electronic photos, electronic billboards or signs, projectors, building structures, packaging And aesthetic structure (for example, a display of the image of a piece of jewelry), etc.

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Abstract

一种显示装置（200），包括阵列基板（10）和与阵列基板（10）相对设置的对置基板（20）。阵列基板（10）包括第一衬底（101）和和设置于第一衬底（101）上且呈阵列排布的多个亚像素（P）。对置基板（20）包括第二衬底（201）和设置于第二衬底（201）靠近阵列基板（10）一侧的多个第一隔垫物（210）。其中，第一隔垫物（210）在阵列基板（10）上的正投影，位于相邻两行亚像素（P）之间的区域与相邻两列亚像素（P）之间的区域相交叉的区域内。

Description

显示装置
本申请要求于2020年05月29日提交的、申请号为202020950733.2的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示装置。
背景技术
近年来，随着显示技术的进步，用户观感体验的要求越来越高。其中，液晶显示技术已经成功应用于笔记本电脑、显示屏、电视等显示产品中。随着液晶显示产品的拥有量的增大，人们对液晶产品的显示品质也提出了更高的要求。
发明内容
提供一种显示装置。所述显示装置包括阵列基板和与所述阵列基板相对设置的对置基板。所述阵列基板包括第一衬底和和设置于所述第一衬底上且呈阵列排布的多个亚像素。所述对置基板包括第二衬底和设置于所述第二衬底靠近所述阵列基板一侧的多个第一隔垫物。其中，第一隔垫物在所述阵列基板上的正投影，位于相邻两行亚像素之间的区域与相邻两列亚像素之间的区域相交叉的区域内。
在一些实施例中，所述对置基板还包括多个第二隔垫物。第二隔垫物在所述第二衬底上的正投影与所述第一隔垫物在所述第二衬底上的正投影无交叠；所述多个第二隔垫物排列成多列，每列第二隔垫物沿所述多个亚像素排列的列方向排列；每列所述第二隔垫物在所述阵列基板上的正投影，位于一列亚像素所在的列区域内。
在一些实施例中，所述多个第二隔垫物与所述多个第一隔垫物同层设置。
在一些实施例中，在垂直于所述第二衬底的方向上，所述第一隔垫物的尺寸和所述第二隔垫物的尺寸相同或大致相同。
在一些实施例中，在所述阵列基板的1mm 2的单位面积内，第一隔垫物远离所述第二衬底一侧的表面的面积和第二隔垫物远离所述第二衬底一侧的表面的面积之和大于10000μm 2。
在一些实施例中，所述对置基板还包括设置于所述第一隔垫物靠近所述第二衬底一侧的多个滤光图案。一个滤光图案在所述阵列基板上的正投影覆盖一列亚像素，一个第一隔垫物在所述第二衬底上的正投影位于一个滤光图案所在范围内。在垂直于所述滤光图案的延伸方向上，在所述第一隔垫物所 在位置处，所述滤光图案具有凸出部分。所述第一隔垫物在所述第二衬底上的正投影的边缘，位于所述滤光图案的凸出部分的边缘的内侧。在所述对置基板包括第二隔垫物的情况下，所述凸出部分在所述第二衬底上的正投影与所述第二隔垫物在所述第二衬底上的正投影无交叠。
在一些实施例中，所述多个滤光图案中，与所述凸出部分相邻的滤光图案具有凹陷部分。所述凸出部分延伸至所述凹陷部分内。
在一些实施例中，所述阵列基板还包括设置于所述第一衬底上的多条栅线。至少一条栅线位于相邻两行亚像素之间。所述第一隔垫物在所述阵列基板上的正投影与栅线有交叠区域。在所述对置基板包括多个第二隔垫物的情况下，所述第二隔垫物在所述阵列基板上的正投影与栅线有交叠区域。
在一些实施例中，沿亚像素排列的列方向，所述栅线具有凸出部分。在所述对置基板包括多个第二隔垫物的情况下，所述第二隔垫物在所述阵列基板上的正投影，位于所述栅线的凸出部分所在区域内。
在一些实施例中，沿亚像素排列的列方向，所述栅线的凸出部分朝向远离与该栅线耦接的一行亚像素的一侧凸出。
在一些实施例中，相邻两行亚像素之间设置有两条栅线。沿亚像素排列的列方向，一行亚像素中的相邻两个亚像素中，一个亚像素所耦接的栅线，位于该行亚像素在所述列方向上相对两侧中的一侧；另一个亚像素所耦接的栅线，位于该行亚像素在所述列方向上相对两侧中的另一侧。
在一些实施例中，在所述对置基板包括多个第二隔垫物的情况下，在相邻两行亚像素之间的区域内，相邻两个第二隔垫物中的一个第二隔垫物在所述阵列基板上的正投影，与所述两条栅线中的一条栅线有交叠区域；相邻两个第二隔垫物中的另一个第二隔垫物在所述阵列基板上的正投影，与所述两条栅线中的另一条栅线有交叠区域。
在一些实施例中，所述阵列基板还包括设置于所述第一衬底上的多条数据线。相邻两列亚像素与一条数据线耦接。
在一些实施例中，所述阵列基板还包括设置于所述第一衬底上的多条公共信号。所述多条公共信号线与所述多条数据线同层设置且延伸方向相同。一条公共信号线位于相邻两列亚像素之间；沿亚像素排列的行方向，一条公共信号线位于相邻两条数据线之间；所述第一隔垫物在所述阵列基板上的正投影与所述公共信号线有交叠区域。
在一些实施例中，所述阵列基板还包括设置于所述亚像素内的薄膜晶体管。沿亚像素排列的列方向，一行亚像素中的相邻两个亚像素中的薄膜晶体 管，分别位于该行亚像素在所述列方向上相对的两侧。在一行亚像素在所述列方向上相对的两侧中，位于一侧的薄膜晶体管和与该一侧的薄膜晶体管同侧设置的一条栅线耦接；位于另一侧的薄膜晶体管和与该另一侧的薄膜晶体管同侧设置的一条栅线耦接。
在一些实施例中，在所述对置基板包括多个第二隔垫物的情况下，所述第二隔垫物在所述阵列基板上的正投影与所述薄膜晶体管无交叠。
在一些实施例中，在所述对置基板包括多个第二隔垫物的情况下，一个第二隔垫物在所述阵列基板上的正投影与一个薄膜晶体管重叠。
在一些实施例中，所述阵列基板还包括设置于第一衬底上的多个第一电极。一个第一电极位于一个亚像素内；所述第一电极和所述薄膜晶体管耦接。所述对置基板还包括设置于所述第二衬底上的第二电极。所述第二电极位于所述第一隔垫物靠近所述第二衬底的一侧。
在一些实施例中，所述阵列基板还包括设置于所述第一衬底上、且位于所述亚像素内的第一电极和第二电极。所述第一电极为面电极，所述第二电极为狭缝电极。所述第一电极相对于所述第二电极更靠近所述第一衬底。所述第一电极和所述第二电极中的一者与所述薄膜晶体管耦接。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示面板的一种结构图；
图2为图1中的显示面板沿A-A’方向的剖视图；
图3为根据一些实施例的显示面板的另一种结构图；
图4为图3中的显示面板沿B-B’方向的剖视图；
图5为图3中的显示面板沿C-C’方向的剖视图；
图6为根据一些实施例的显示面板的又一种结构图；
图7为根据一些实施例的显示面板的又一种结构图；
图8为根据一些实施例的显示面板的又一种结构图；
图9为根据一些实施例的显示装置的一种结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起 的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
对显示面板进行按压测试(Pogo测试)，即为将显示面板固定于按压测试的平台上，用按压测试设备的压头对显示面板进行按压(例如压力为50kgf)，保持一段时间后撤去压头，点亮显示面板确认按压现象。发明人发现由于一些显示面板的分辨率较低，PPI(Pixels Per Inch)较低，导致隔垫物的支撑面积不足，使得显示面板的抗压能力较弱，导致显示面板在按压测试后会在按压位置处出现黑斑，且黑斑长时间不消失或消失缓慢，严重影响显示面板的品质。
本公开的实施例提供一种显示装置200，如图9所示，显示装置200包括显示面板100。
如图1和图2所示，显示面板100包括阵列基板10和对置基板20。阵列基板10与对置基板20相对设置。
其中，显示面板100还包括设置于阵列基板10和对置基板20之间的液晶层30。
阵列基板10包括第一衬底101和设置于第一衬底101上的多个亚像素P。多个亚像素P呈阵列排布。
示例性地，如图1所示，沿水平方向X排列成一排的亚像素P称为同一行亚像素，沿竖直方向Y排列成一排的亚像素P称为同一列亚像素。
对置基板20包括第二衬底201和设置于第二衬底201上的多个第一隔垫物210。
其中，第一隔垫物210在阵列基板10上的正投影，位于相邻两行亚像素之间的区域与相邻两列亚像素之间的区域相交叉的区域内。
在此情况下，在对显示面板100进行按压的过程中，第一隔垫物210可以对显示面板100起到支撑作用，相比于在相邻两行亚像素之间的区域与相邻两列亚像素之间的区域向相交叉的区域内无隔垫物的情况，可以提高显示面板100的抗压能力。
因此，本公开的实施例中的显示面板100，通过对置基板20中的多个第一隔垫物210，第一隔垫物210在阵列基板10上的正投影，位于相邻两行亚像素之间的区域与相邻两列亚像素之间的区域向相交叉的区域内，使得在显示面板100进行按压的情况下，第一隔垫物210可以对显示面板100起到支撑作用，相比于在相邻两行亚像素之间的区域与相邻两列亚像素之间的区域 向相交叉的区域内无隔垫物的情况，增大了隔垫物对显示面板100的支撑面积，提高了显示面板100的支撑强度，提升了显示面板100的抗压能力，从而避免显示面板100发生按压不良，提高显示装置200的抗压能力。
在一些实施例中，如图1和图2所示，对置基板20还包括多个第二隔垫物220。
第二隔垫物220在第二衬底201上的正投影与第一隔垫物210在第二衬底201上的正投影无交叠。
多个第二隔垫物220排列成多列，每列第二隔垫物沿多个亚像素P排列的列方向排列。每列第二隔垫物220在阵列基板10上的正投影，位于一列亚像素所在的列区域内。
需要说明的是，一列亚像素所在的列区域可以包括一列亚像素中的每个亚像素所在区域和每相邻两行亚像素之间的区域，可以参考图1中的M区域。
示例性地，第二隔垫物220在阵列基板10上的正投影，位于处于同一列且处于相邻两行的两个亚像素之间。
在此情况下，在显示面板100进行按压的情况下，第一隔垫物210和第二隔垫物220可以共同对显示面板100进行支撑，使得显示面板100的支撑面积增大，提高了显示面板100的支撑强度，提升了显示面板100的抗压能力，从而避免显示面板100发生按压不良。
第一隔垫物210和第二隔垫物220均为辅隔垫物，示例性地，本公开实施例中辅隔垫物(包括第一隔垫物210和第二隔垫物220)的分布密度相比于原来辅隔垫物(仅包括第二隔垫物220，不包括第一隔垫物210)的分布密度提升50％。在第一隔垫物210和第二隔垫物220的支撑面积相等的情况下，辅隔垫物(包括第一隔垫物210和第二隔垫物220)的支撑面积相比于原来辅隔垫物(仅包括第二隔垫物220，不包括第一隔垫物210)的支撑面积提升50％。
需要说明的是，在平行于第二衬底201所在平面方向上，第一隔垫物210和与该第一隔垫物210相邻的第二隔垫物220，相互靠近的边缘的间距大于实际生产过程中的工艺能力偏差。这样，可以避免影响因实际工艺误差而影响第一隔垫物210和第二隔垫物220的成膜效果，从而避免影响第一隔垫物210和第二隔垫物220的支撑能力，避免影响显示面板100的抗压能力。
在一些实施例中，多个第二隔垫物220和多个第一隔垫物210同层设置。
多个第二隔垫物220的材料和多个第一隔垫物210的材料相同。
在此情况下，第二隔垫物220和第一隔垫物210同步形成，从而节省工序。
在一些实施例中，在垂直于第二衬底201的方向上，第一隔垫物210的尺寸和第二隔垫物220的尺寸相同或大致相同。
可以理解的是，第一隔垫物210中的靠近阵列基板10的表面和靠近第二衬底201的表面之间的距离，与第二隔垫物220中的靠近阵列基板10的表面和靠近第二衬底201的表面之间的距离相等或大致相等。
在一些实施例中，在阵列基板10的1mm 2的单位面积内，第一隔垫物210远离第二衬底201一侧的表面的面积和第二隔垫物220远离第二衬底201一侧的表面的面积之和大于10000μm 2。这样一来，可以使得显示面板100的支撑强度增加，从而避免显示面板100出现黑斑或者Mura不良。
需要说明的是，第一隔垫物210在阵列基板10上的正投影的形状和第二隔垫物220在阵列基板10上的正投影的形状可以相同，也可以不相同。例如，可以均为圆形或者六边形等。
其中，第一隔垫物210在阵列基板10上的正投影的面积和第二隔垫物220在阵列基板10上的正投影的面积可以相等，也可以不相等。
在一些实施例中，如图3和图4所示，对置基板20还包括设置于第一隔垫物210靠近第二衬底201一侧的多个滤光图案202。
示例性地，多个滤光图案202包括红色滤光图案、蓝色滤光图案和绿色滤光图案。其中，由红色滤光图案出射的光为红色光，由蓝色滤光图案出射的光为蓝色光，由绿色滤光图案出射的光为绿色光。
一个滤光图案202在阵列基板10上的正投影覆盖一列亚像素。
一个第一隔垫物210在第二衬底201上的正投影位于一个滤光图案202所在范围内。
在垂直于滤光图案202的延伸方向上(即在图3中的水平方向X上)，在第一隔垫物210所在位置处，滤光图案202具有凸出部分T1。第一隔垫物210在第二衬底201上的正投影的边缘，位于滤光图案202的凸出部分T1的边缘的内侧。
在对置基板20包括第二隔垫物220的情况下，凸出部分T1在第二衬底201上的正投影与第二隔垫物220在第二衬底201上的正投影无交叠。
在此情况下，第一隔垫物210的底部位于同一滤光图案202上，而不会跨在相邻的两个滤光图案202上，由于同一滤光图案202相比不同滤光图案202的膜层厚度均匀性好，即第一隔垫物210所在的滤光图案202的凸出部分T1的厚度均匀性较好，因此，第一隔垫物210中的靠近第二衬底201一侧的表面平坦，在显示面板100按压的过程中，第一隔垫物210的受力均匀，从 而避免第一隔垫物210损坏(例如出现裂纹)。
需要说明的是，在平行于第二衬底201所在平面方向上，第一隔垫物210与其所在的凸出部分T1相互靠近的边缘的间距、靠近凸出部分T1的第二隔垫物220与凸出部分T1相互靠近的边缘的间距均大于实际生产过程中的工艺能力偏差。这样，可以避免工艺误差导致第一隔垫物210在第二衬底201上的正投影超出滤光图案202的凸出部分T1的边缘的内侧，影响第一隔垫物210中的靠近第二衬底201一侧的表面平坦性的问题，从而避免影响第一隔垫物210的支撑能力，避免影响显示面板100的抗压能力。
在一些实施例中，如图3所示，多个滤光图案202中，与凸出部分T1相邻的滤光图案202具有凹陷部分T2。凸出部分T1延伸至凹陷部分T2内。
需要说明的是，凸出部分T1可以与凹陷部分T2的相靠近的边缘接触且两者之间无间隙。在实际生产工艺中，凸出部分T1可以与凹陷部分T2的相靠近的边缘搭接，或者，凸出部分T1可以与凹陷部分T2的相靠近的边缘存在较小的间隙或者近似无间隙。
其中，在凸出部分T1与凹陷部分T2的相靠近的边缘搭接的情况下，第一隔垫物210在第一衬底101上的正投影与搭接的区域无交叠。在凸出部分T1可以与凹陷部分T2的相靠近的边缘存在间隙的情况下，第一隔垫物210在第一衬底101上的正投影与存在间隙的区域无交叠。可以理解的是，凸出部分T1在阵列基板10上的正投影中，靠近凹陷部分T2的一边缘，与凹陷部分T2在阵列基板10上的正投影中，靠近凸出部分T1的一边缘重合。
在此情况下，一个滤光图案202的凸出部分T1在第二衬底201上的正投影与其他滤光图案202在第二衬底201上的正投影无交叠。一个滤光图案202的凹陷部分T2在第二衬底201上的正投影与其他滤光图案202在第二衬底201上的正投影无交叠。
这样，在滤光图案202的凸出部分T1位置处，相邻滤光图案202具有凹陷部分T2，不会覆盖该凸出部分T1，不会影响凸出部分T1的膜层均匀性，使得凸出部分T1中的各个位置处的厚度均匀。在此情况下，第一隔垫物210中的靠近第二衬底201一侧的表面平坦，在显示面板100按压的过程中，第一隔垫物210的受力均匀，从而避免第一隔垫物210损坏。
在一些实施例中，如图1和图2所示，阵列基板10还包括设置于第一衬底101上的多条栅线GL。至少一条栅线GL位于相邻两行亚像素之间。
第一隔垫物210在阵列基板10上的正投影与栅线GL有交叠区域。
在对置基板20包括多个第二隔垫物220的情况下，第二隔垫物220在阵 列基板10上的正投影与栅线GL有交叠区域。
示例性地，栅线GL的材料采用金属材料。
在此情况下，在对显示面板100按压的过程中，第一隔垫物210和第二隔垫物220在靠近阵列基板10的一侧会受到栅线GL的支撑，从而提高第一隔垫物210和第二隔垫物220的支撑效果。
需要说明的是，领域内技术人员可以在保证显示面板100正常显示的条件下，根据栅线GL与相邻亚像素的空间大小，对第二隔垫物220的位置进行设计。例如，沿栅线GL的延伸方向，相邻两个第二隔垫物220错位排列。
在一些实施例中，如图1所示，沿亚像素排列的列方向(即图1中的竖直方向Y)，栅线GL具有凸出部分。
在对置基板20包括多个第二隔垫物220的情况下，第二隔垫物220在阵列基板10上的正投影，位于栅线GL的凸出部分所在区域内。
在此情况下，在按压显示面板100的过程中，第二隔垫物220可以受到栅线GL的凸出部分的支撑，使得第二隔垫物220与阵列基板10的接触面受力均匀，从而避免第二隔垫物220损坏。
需要说明的是，领域内技术人员可以根据栅线GL所在区域的空间大小，设计栅线GL的凸出部分的凸出方向。
在一些实施例中，如图1所示，沿亚像素排列的列方向，栅线GL的凸出部分朝向远离与该栅线GL耦接的一行亚像素的一侧凸出。这样，可以避免栅线GL与亚像素P的间距过小而影响亚像素的出光区域的大小，从而避免影响显示面板100的开口率。
在一些实施例中，如图1所示，相邻两行亚像素之间设置有两条栅线GL。
沿亚像素排列的列方向，一行亚像素中的相邻两个亚像素中，一个亚像素所耦接的栅线GL，位于该行亚像素在列方向上相对两侧中的一侧。另一个亚像素所耦接的栅线GL，位于该行亚像素在列方向上相对两侧中的另一侧。
可以理解的是，一行亚像素与两根栅线GL耦接。例如，一行亚像素的奇数列亚像素与一根栅线GL耦接，偶数列亚像素与另一根栅线GL耦接。
在一些实施例中，如图1所示，在对置基板20包括多个第二隔垫物220的情况下，在相邻两行亚像素之间的区域内，相邻两个第二隔垫物220中的一个第二隔垫物220在阵列基板10上的正投影，与两条栅线GL中的一条栅线GL有交叠区域。相邻两个第二隔垫物220中的另一个第二隔垫物220在阵列基板10上的正投影，与两条栅线GL中的另一条栅线GL有交叠区域。
可以理解的是，在相邻两行亚像素之间的区域内的两条栅线GL分别与该 相邻两行亚像素耦接。
需要说明的是，领域内的技术人员可以根据实际情况，考虑栅线GL所在空间大小，对第二隔垫物220的位置进行设置。
示例性地，相邻两个第二隔垫物220在阵列基板10上的正投影，也可以与两条栅线GL中的一条栅线GL有交叠区域，与另一条栅线GL无交叠区域。
在一些实施例中，如图1所示，阵列基板10还包括设置于第一衬底101上的多条数据线DL。相邻两列亚像素与一条数据线DL耦接。
示例性地，将相邻两列亚像素划分为一组，相邻两组亚像素之间设置一条数据线DL。
在一些实施例中，如图1所示，阵列基板10还包括设置于第一衬底101上的多条公共信号线CL。多条公共信号线CL与多条数据线DL的延伸方向相同。一条公共信号线CL位于相邻两列亚像素之间。公共信号线CL被配置为向亚像素传输公共电压信号。
沿亚像素P排列的行方向，一条公共信号线CL位于相邻两条数据线DL之间。
如图1和图2所示，第一隔垫物210在阵列基板10上的正投影与公共信号线CL有交叠区域。
示例性地，将相邻两列亚像素划分为一组，相邻两组亚像素之间设置一条数据线DL，每组亚像素中的两列亚像素之间设置有一条公共信号线CL。
第一隔垫物210在阵列基板10上的正投影，与公共信号线CL和栅线GL的交叉区域有交叠。
在一些实施例中，如图1所示，阵列基板10还包括设置于亚像素P内的薄膜晶体管(Thin Film Transistor，TFT)。
沿亚像素P排列的列方向，一行亚像素中的相邻两个亚像素中的TFT，分别位于该行亚像素在所述列方向上相对的两侧。
在一行亚像素P在列方向上相对的两侧中，位于一侧的TFT和与该一侧的TFT同侧设置的一条栅线GL耦接。位于另一侧的TFT和与该另一侧的TFT同侧设置的一条栅线GL耦接。
示例性地，如图1所示，在对置基板20包括多个第二隔垫物220的情况下，第二隔垫物220在阵列基板10上的正投影与TFT无交叠。或者，如图6所示，一个第二隔垫物220在阵列基板10上的正投影与一个TFT重叠。
需要说明的是，领域内的技术人员可以根据实际情况，例如，在对置基板20还包括主隔垫物的情况下，根据主隔垫物与第二隔垫物220(即辅助隔 垫物)的高度差以及主隔垫物的位置，对第二隔垫物220所在位置进行设计，在此不做限定。
在一些实施例中，如图3所示，阵列基板10还包括设置于第一衬底101上的多个第一电极110。一个第一电极110位于一个亚像素P内。第一电极110和TFT耦接。
其中，第一电极110为像素电极。
如图5所示，对置基板20还包括设置于第二衬底201上的第二电极120。第二电极120位于第一隔垫物210靠近第二衬底201的一侧。
其中，第二电极120为公共电极。
可以理解的是，在对置基板20包括多个滤光图案202的情况下，第二电极120位于滤光图案202远离第衬底201的一侧。
在阵列基板10包括多条公共信号线CL的情况下，第二电极120与公共信号线CL耦接(图中未示出)。
在一些实施例中，如图7所示，阵列基板10还包括设置于第一衬底101上、且位于亚像素P内的第一电极110和第二电极120。
第一电极110为面电极，第二电极120为狭缝电极.
第一电极110相对于第二电极120更靠近第一衬底101。
第一电极110和第二电极120中的一者与TFT耦接。即，第一电极110与TFT耦接，此时，第一电极110为像素电极；或者，第二电极120与TFT耦接，此时，第二电极120为公共电极。
可以理解的是，在阵列基板10包括多条公共信号线CL的情况下，若第一电极110与TFT耦接，则第二电极120与公共信号线CL耦接；或者，若第二电极120与TFT耦接，则第一电极110与公共信号线CL耦接。
另外，在一些实施例中，如图8所示，阵列基板10还包括设置于第一衬底101上的多条公共信号线CL。
多条公共信号线CL与多条栅线DL同层设置且材料相同。
一条公共信号线CL位于一行亚像素所在区域内。公共信号线CL在第一衬底101上的正投影与TFT无交叠。
公共信号线CL具有多个弯折线段，任意相邻两个弯折线段在相互靠近的边缘处通过导电图案耦接，该导电图案与公共电极线CL同层，且导电图案在第一衬底101上的正投影与数据线DL有重叠。一个弯折线段位于一行亚像素中的相邻两个亚像素所在区域内，且一个弯折线段包括依次耦接的五个子线段，其中，最中间的子线段在第一衬底101上的正投影，在栅线GL的延伸方 向上的相对两侧的边缘分别位于亚像素内，中间部分位于两个亚像素的间隙区域内。
此外，在一些实施例中，对置基板20还包括设置于第二衬底201上的第三隔垫物。
其中，第三隔垫物作为主隔垫物，在按压显示面板100的过程中对显示面板100进行支撑。第三隔垫物对显示面板100的支撑面积，小于第一隔垫物210和第二隔垫物220整体对显示面板100的支撑面积。
第三隔垫物在阵列基板10上的正投影，位于与第一隔垫物210在阵列基板10上的正投影和第二隔垫物220在阵列基板10上的正投影均无交叠。
在第二衬底201的厚度方向上，第三隔垫物的高度大于或近似等于第二隔垫物220的高度。
示例性地，第一隔垫物210在阵列基板10上的正投影可以位于第二隔垫物220在阵列基板10上的正投影和第三隔垫物在阵列基板10上的正投影之间。
第三隔垫物在阵列基板10上的正投影与TFT有交叠或者处于相邻两行的两个亚像素之间且与栅线GL有交叠，且多个第三隔垫物在阵列基板10上的正投影均匀分布。
需要说明的是，领域内技术人员可以根据实际需要，对第三隔垫物的分布密度和设置位置进行设计。示例性地，阵列基板10包括多个亚像素组，每个亚像素组包括多个亚像素P，每个亚像素组所包括的亚像素P的个数相同，一个第三隔垫物在阵列基板10上的正投影位于一个亚像素组内。
示例性地，在对置基板20包括多个第二隔垫物220的情况下，第二隔垫物220在阵列基板10上的正投影与TFT无交叠，则在对置基板20包括第三隔垫物(即主隔垫物)，且第三隔垫物和第二隔垫物220(即辅助隔垫物)的高度差较小(例如高度差约为0.1μm)的情况下，第三隔垫物在阵列基板10上的正投影与TFT有交叠。这样，可以避免在第三隔垫物(即主隔垫物)和第二隔垫物220(即辅助隔垫物)的高度差较小，且第三隔垫物在阵列基板10上的正投影与TFT有交叠的情况下，若第二隔垫物220在阵列基板10上的正投影与TFT有交叠，则在按压显示面板100的过程中，第二隔垫物220出现过支撑，导致显示面板100出现显示不良(例如显示亮度不均)。
示例性地，在对置基板20包括多个第二隔垫物220的情况下，一个第二隔垫物220在阵列基板10上的正投影与一个TFT重叠，则在对置基板20包括第三隔垫物(即主隔垫物)，且第三隔垫物和第二隔垫物220(即辅助隔垫 物)的高度差较大(例如高度差大于0.5μm)的情况下，第三隔垫物在阵列基板10上的正投影与TFT有交叠。这样，可以避免在在对置基板20包括第三隔垫物(即主隔垫物)，且第三隔垫物和第二隔垫物220(即辅助隔垫物)的高度差较大(例如高度差大于0.5μm)的情况下，若第三隔垫物在阵列基板10上的正投影与栅线GL有交叠，则在按压显示面板100的过程中，第三隔垫物支撑能力不足，导致显示面板100抗压能力降低。
此外，如图9所示，显示装置200还包括驱动IC(Driver IC)。驱动IC与显示面板100中的阵列基板10绑定，并与数据线DL耦接。
驱动IC被配置为向数据线DL传输数据信号。
示例性地，上述的显示装置200可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种显示装置，包括：
    阵列基板，所述阵列基板包括第一衬底和设置于所述第一衬底上且呈阵列排布的多个亚像素；
    对置基板，所述对置基板与所述阵列基板相对设置；所述对置基板包括第二衬底和设置于所述第二衬底靠近所述阵列基板一侧的多个第一隔垫物；
    其中，第一隔垫物在所述阵列基板上的正投影，位于相邻两行亚像素之间的区域与相邻两列亚像素之间的区域相交叉的区域内。
  2. 根据权利要求1所述的显示装置，其中，所述对置基板还包括：多个第二隔垫物；
    第二隔垫物在所述第二衬底上的正投影与所述第一隔垫物在所述第二衬底上的正投影无交叠；
    所述多个第二隔垫物排列成多列，每列第二隔垫物沿所述多个亚像素排列的列方向排列；每列所述第二隔垫物在所述阵列基板上的正投影，位于一列亚像素所在的列区域内。
  3. 根据权利要求2所述的显示装置，其中，所述多个第二隔垫物与所述多个第一隔垫物同层设置。
  4. 根据权利要求2或3所述的显示装置，其中，在垂直于所述第二衬底的方向上，所述第一隔垫物的尺寸和所述第二隔垫物的尺寸相同或大致相同。
  5. 根据权利要求2～4所述的显示装置，其中，在所述阵列基板的1mm 2的单位面积内，第一隔垫物远离所述第二衬底一侧的表面的面积和第二隔垫物远离所述第二衬底一侧的表面的面积之和大于10000μm 2。
  6. 根据权利要求1～5中任一项所述的显示装置，其中，所述对置基板还包括：
    设置于所述第一隔垫物靠近所述第二衬底一侧的多个滤光图案；一个滤光图案在所述阵列基板上的正投影覆盖一列亚像素；
    一个第一隔垫物在所述第二衬底上的正投影位于一个滤光图案所在范围内；
    在垂直于所述滤光图案的延伸方向上，在所述第一隔垫物所在位置处，所述滤光图案具有凸出部分；所述第一隔垫物在所述第二衬底上的正投影的边缘，位于所述滤光图案的凸出部分的边缘的内侧；
    在所述对置基板包括第二隔垫物的情况下，所述凸出部分在所述第二衬底上的正投影与所述第二隔垫物在所述第二衬底上的正投影无交叠。
  7. 根据权利要求6所述的显示装置，其中，所述多个滤光图案中，与所述凸出部分相邻的滤光图案具有凹陷部分；
    所述凸出部分延伸至所述凹陷部分内。
  8. 根据权利要求1～7中任一项所述的显示装置，其中，所述阵列基板还包括：
    设置于所述第一衬底上的多条栅线；
    至少一条栅线位于相邻两行亚像素之间；
    所述第一隔垫物在所述阵列基板上的正投影与栅线有交叠区域；
    在所述对置基板包括多个第二隔垫物的情况下，所述第二隔垫物在所述阵列基板上的正投影与栅线有交叠区域。
  9. 根据权利要求8所述的显示装置，其中，沿亚像素排列的列方向，所述栅线具有凸出部分；
    在所述对置基板包括多个第二隔垫物的情况下，所述第二隔垫物在所述阵列基板上的正投影，位于所述栅线的凸出部分所在区域内。
  10. 根据权利要求9所述的显示装置，其中，沿亚像素排列的列方向，所述栅线的凸出部分朝向远离与该栅线耦接的一行亚像素的一侧凸出。
  11. 根据权利要求8～10中任一项所述的显示装置，其中，相邻两行亚像素之间设置有两条栅线；
    沿亚像素排列的列方向，一行亚像素中的相邻两个亚像素中，一个亚像素所耦接的栅线，位于该行亚像素在所述列方向上相对两侧中的一侧；另一个亚像素所耦接的栅线，位于该行亚像素在所述列方向上相对两侧中的另一侧。
  12. 根据权利要求11所述的显示装置，其中，在所述对置基板包括多个第二隔垫物的情况下，在相邻两行亚像素之间的区域内，相邻两个第二隔垫物中的一个第二隔垫物在所述阵列基板上的正投影，与所述两条栅线中的一条栅线有交叠区域；相邻两个第二隔垫物中的另一个第二隔垫物在所述阵列基板上的正投影，与所述两条栅线中的另一条栅线有交叠区域。
  13. 根据权利要求11或12所述的显示装置，其中，所述阵列基板还包括：
    设置于所述第一衬底上的多条数据线；
    相邻两列亚像素与一条数据线耦接。
  14. 根据权利要求13所述的显示装置，其中，所述阵列基板还包括：
    设置于所述第一衬底上的多条公共信号线；
    所述多条公共信号线与所述多条数据线同层设置且延伸方向相同；
    一条公共信号线位于相邻两列亚像素之间；
    沿亚像素排列的行方向，一条公共信号线位于相邻两条数据线之间；
    所述第一隔垫物在所述阵列基板上的正投影与所述公共信号线有交叠区域。
  15. 根据权利要求11所述的显示装置，其中，所述阵列基板还包括：
    设置于所述亚像素内的薄膜晶体管；
    沿亚像素排列的列方向，一行亚像素中的相邻两个亚像素中的薄膜晶体管，分别位于该行亚像素在所述列方向上相对的两侧；
    在一行亚像素在所述列方向上相对的两侧中，位于一侧的薄膜晶体管和与该一侧的薄膜晶体管同侧设置的一条栅线耦接；位于另一侧的薄膜晶体管和与该另一侧的薄膜晶体管同侧设置的一条栅线耦接。
  16. 根据权利要求15所述的显示装置，其中，在所述对置基板包括多个第二隔垫物的情况下，所述第二隔垫物在所述阵列基板上的正投影与所述薄膜晶体管无交叠。
  17. 根据权利要求15所述的显示装置，其中，在所述对置基板包括多个第二隔垫物的情况下，一个第二隔垫物在所述阵列基板上的正投影与一个薄膜晶体管重叠。
  18. 根据权利要求15～17中任一项所述的显示装置，其中，所述阵列基板还包括设置于第一衬底上的多个第一电极；一个第一电极位于一个亚像素内；所述第一电极和所述薄膜晶体管耦接；
    所述对置基板还包括设置于所述第二衬底上的第二电极；所述第二电极位于所述第一隔垫物靠近所述第二衬底的一侧。
  19. 根据权利要求15～17中任一项所述的显示装置，其中，所述阵列基板还包括设置于所述第一衬底上、且位于所述亚像素内的第一电极和第二电极；
    所述第一电极为面电极，所述第二电极为狭缝电极；所述第一电极相对于所述第二电极更靠近所述第一衬底；
    所述第一电极和所述第二电极中的一者与所述薄膜晶体管耦接。
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CN211928360U (zh) * 2020-05-29 2020-11-13 北京京东方显示技术有限公司 显示装置

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