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WO2021203475A1 - 像素补偿驱动电路及其驱动方法、显示装置 - Google Patents

像素补偿驱动电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2021203475A1
WO2021203475A1 PCT/CN2020/085850 CN2020085850W WO2021203475A1 WO 2021203475 A1 WO2021203475 A1 WO 2021203475A1 CN 2020085850 W CN2020085850 W CN 2020085850W WO 2021203475 A1 WO2021203475 A1 WO 2021203475A1
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WO
WIPO (PCT)
Prior art keywords
transistor
scan signal
terminal
switch
driving
Prior art date
Application number
PCT/CN2020/085850
Other languages
English (en)
French (fr)
Inventor
吴珍
王振岭
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/764,639 priority Critical patent/US11355065B2/en
Publication of WO2021203475A1 publication Critical patent/WO2021203475A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technology, and in particular to a pixel compensation driving circuit, a driving method thereof, and a display device.
  • An organic light emitting diode (OLED) display device is a display device that uses organic light-emitting materials to inject and recombine and emit light under the drive of an electric field. It has self-luminescence, wide viewing angle, high contrast, and low power consumption. Advantages such as electricity and high response speed.
  • the present invention provides a pixel compensation driving circuit, a driving method thereof, and a display device, so as to solve the technical problem of uneven display of the existing OLED display device.
  • the present invention provides a pixel compensation driving circuit
  • the pixel compensation driving circuit includes: a driving transistor DT, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a storage capacitor, A light-emitting element, a first switch S1, a second switch S2, and a compensation unit;
  • the control terminal of the driving transistor DT is connected to the first node G, the first terminal of the driving transistor DT is connected to the second node S, and the second terminal of the driving transistor DT is connected to the third node Q;
  • the control terminal of the first transistor T1 is connected to the first scan signal Scan1, the first terminal of the first transistor T1 is connected to the data line and the first terminal of the compensation unit, and the second terminal of the first transistor T1 Connect to the first node G;
  • the control terminal of the second transistor T2 is connected to the second scan signal Scan2, the first terminal of the second transistor T2 is connected to the second node S, and the second terminal of the second transistor T2 is connected to the first switch S1 The first end of and the first end of the second switch S2;
  • the control terminal of the third transistor T3 is connected to the third scan signal Scan3, the first terminal of the third transistor T3 is connected to the negative power supply voltage VSS, and the second terminal of the third transistor T3 is connected to the second node S;
  • the control terminal of the fourth transistor T4 is connected to the fourth scan signal Scan4, the first terminal of the fourth transistor T4 is connected to the third node Q, and the second terminal of the fourth transistor T4 is connected to the positive power supply voltage VDD;
  • the first end of the storage capacitor is connected to a first node G, and the second end of the storage capacitor is connected to a second node S;
  • the first end of the light-emitting element is connected to the positive power supply voltage VDD, and the second end of the light-emitting element is connected to the third node Q;
  • the second terminal of the first switch S1 is connected to the initialization voltage Vi;
  • the second end of the second switch S2 is connected to the second end of the compensation unit
  • the compensation unit is used for detecting and storing the initial threshold voltage of the driving transistor DT, so that the pixel compensation driving circuit can superimpose the data voltage output by the data line and the initial threshold voltage according to the superimposed data voltage, The actual threshold voltage of the driving transistor DT is compensated.
  • the pixel compensation driving circuit further detects and stores the mobility of the driving transistor DT according to the superimposed data voltage.
  • the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are N-type thin film transistors.
  • the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors Or amorphous silicon thin film transistors.
  • the light-emitting element is an organic light-emitting diode.
  • the first end of the light-emitting element is an anode end
  • the second end of the light-emitting element is a cathode end
  • the first scan signal Scan1, the second scan signal Scan2, the third scan signal Scan3, and the fourth scan signal Scan4 are provided by a timing controller.
  • the present invention provides a pixel compensation driving method for driving a pixel compensation driving circuit.
  • the pixel compensation driving circuit includes a driving transistor DT, a first transistor T1, a second transistor T2, a third transistor T3, and a second transistor.
  • Four transistors T4 a storage capacitor, a light-emitting element, a first switch S1, a second switch S2, and a compensation unit;
  • the control terminal of the driving transistor DT is connected to the first node G, the first terminal of the driving transistor DT is connected to the second node S, and the second terminal of the driving transistor DT is connected to the third node Q;
  • the control terminal of the first transistor T1 is connected to the first scan signal Scan1, the first terminal of the first transistor T1 is connected to the data line and the first terminal of the compensation unit, and the second terminal of the first transistor T1 Connect to the first node G;
  • the control terminal of the second transistor T2 is connected to the second scan signal Scan2, the first terminal of the second transistor T2 is connected to the second node S, and the second terminal of the second transistor T2 is connected to the first switch S1 The first end of and the first end of the second switch S2;
  • the control terminal of the third transistor T3 is connected to the third scan signal Scan3, the first terminal of the third transistor T3 is connected to the negative power supply voltage VSS, and the second terminal of the third transistor T3 is connected to the second node S;
  • the control terminal of the fourth transistor T4 is connected to the fourth scan signal Scan4, the first terminal of the fourth transistor T4 is connected to the third node Q, and the second terminal of the fourth transistor T4 is connected to the positive power supply voltage VDD;
  • the first end of the storage capacitor is connected to a first node G, and the second end of the storage capacitor is connected to a second node S;
  • the first end of the light-emitting element is connected to the positive power supply voltage VDD, and the second end of the light-emitting element is connected to the third node Q;
  • the second terminal of the first switch S1 is connected to the initialization voltage Vi;
  • the second end of the second switch S2 is connected to the second end of the compensation unit
  • the pixel compensation driving method includes the following steps:
  • Step S1 during the shutdown period, the compensation unit detects and stores the initial threshold voltage of the driving transistor DT;
  • Step S2 During the booting period, the pixel compensation driving circuit controls the actual threshold value of the driving transistor DT in each frame time according to the superimposed data voltage obtained by superimposing the initial threshold voltage and the data voltage output by the data line. The voltage is compensated.
  • the pixel compensation driving method further includes:
  • Step S3 During the booting period, the pixel compensation driving circuit detects and stores the mobility of the driving transistor DT in each frame time according to the superimposed data voltage.
  • the step S2 includes a reset phase, a detection phase, a voltage writing phase, and a light-emitting phase;
  • the first scan signal Scan1, the second scan signal Scan2, and the fourth scan signal Scan4 provide a high level
  • the third scan signal Scan3 provides a low level
  • the first scan signal Scan3 provides a low level.
  • a switch S1 is closed, and the second switch S2 is open; the driving transistor DT, the first transistor T1, the second transistor T2, and the fourth transistor T4 are open, and the third transistor T3 is closed,
  • the second terminal of the second transistor T2 is connected to the initialization voltage Vi, and the first terminal of the first transistor T1 is connected to the reference voltage;
  • the first scan signal Scan1 and the fourth scan signal Scan4 provide a high level
  • the second scan signal Scan2 and the third scan signal Scan3 provide a low level
  • the first scan signal Scan1 and the fourth scan signal Scan4 provide a low level.
  • the switch S1 and the second switch S2 are turned off; the driving transistor DT, the first transistor T1, and the fourth transistor T4 are turned on, the second transistor T2 and the third transistor T3 are turned off, and the The first terminal of the first transistor T1 is connected to the reference voltage;
  • the first scan signal Scan1 and the third scan signal Scan3 provide a high level
  • the second scan signal Scan2 and the fourth scan signal Scan4 provide a low level
  • the first scan signal Scan1 and the third scan signal Scan4 provide a low level.
  • a switch S1 and the second switch S2 are turned off; the driving transistor DT, the first transistor T1 and the third transistor T3 are turned on, the second transistor T2 and the fourth transistor T4 are turned off, so The first end of the first transistor T1 is connected to the superimposed data voltage; and
  • the third scan signal Scan3 provides a high level
  • the first scan signal Scan1, the second scan signal Scan2, and the fourth scan signal Scan4 provide a low level
  • the first switch S1 and the second switch S2 are turned off
  • the driving transistor DT and the third transistor T3 are turned on
  • the first transistor T1, the second transistor T2, and the fourth transistor T4 are turned off
  • the first transistor T1 is turned off.
  • the first terminal of a transistor T1 is connected to the reference voltage.
  • the step S3 includes a first mobility detection phase, a second mobility detection phase, and a third mobility detection phase;
  • the first scan signal Scan1, the second scan signal Scan2, and the third scan signal Scan3 provide a high level
  • the fourth scan signal Scan4 provides a low level.
  • Level the first switch S1 is closed, the second switch S2 is open; the driving transistor DT, the first transistor T1, the second transistor T2, and the third transistor T3 are open, and the The four transistors T4 are turned off, the second terminal of the second transistor T2 is connected to the initialization voltage Vi, and the first terminal of the first transistor T1 is connected to the superimposed data voltage;
  • the second scan signal Scan2 and the third scan signal Scan3 provide a high level
  • the first scan signal Scan1 and the fourth scan signal Scan4 provide a low level.
  • Level the first switch S1 and the second switch S2 are turned off; the driving transistor DT, the second transistor T2, and the third transistor T3 are turned on, and the first transistor T1 and the fourth transistor T3 are turned on.
  • the transistor T4 is turned off, and the first terminal of the first transistor T1 is connected to the reference voltage; and
  • the second scan signal Scan2 and the third scan signal Scan3 provide a high level
  • the first scan signal Scan1 and the fourth scan signal Scan4 provide a low level.
  • Level the first switch S1 is open, the second switch S2 is closed; the driving transistor DT, the second transistor T2, and the third transistor T3 are open, and the first transistor T1 and the second transistor T3 are open.
  • the four transistor T4 is turned off, the second terminal of the second transistor T2 is connected to the second terminal of the compensation unit, and the first terminal of the first transistor T1 is connected to a reference voltage.
  • the step S1 includes a first initial threshold voltage detection phase and a second initial threshold voltage detection phase
  • the first scan signal Scan1, the second scan signal Scan2, and the third scan signal Scan3 provide a high level
  • the fourth scan signal Scan4 provides a low level.
  • Level the first switch S1 is closed and the second switch S2 is open; the driving transistor DT, the first transistor T1, the second transistor T2, and the third transistor T3 are open, and the The fourth transistor T4 is turned off, the second terminal of the second transistor T2 is connected to the initialization voltage Vi, and the first terminal of the first transistor T1 is connected to the data voltage; and
  • the first scan signal Scan1, the second scan signal Scan2, and the third scan signal Scan3 provide a high level
  • the fourth scan signal Scan4 provides a low level.
  • Level the first switch S1 is open, and the second switch S2 is closed; the driving transistor DT, the first transistor T1, the second transistor T2, and the third transistor T3 are open, and the The fourth transistor T4 is turned off, the second terminal of the second transistor T2 is connected to the second terminal of the compensation unit, and the first terminal of the first transistor T1 is connected to the data voltage.
  • the present invention provides a display device, the display device includes a pixel compensation driving circuit, the pixel compensation driving circuit includes: a driving transistor DT, a first transistor T1, a second transistor T2, a third transistor T3, A fourth transistor T4, a storage capacitor, a light-emitting element, a first switch S1, a second switch S2, and a compensation unit;
  • the control terminal of the driving transistor DT is connected to the first node G, the first terminal of the driving transistor DT is connected to the second node S, and the second terminal of the driving transistor DT is connected to the third node Q;
  • the control terminal of the first transistor T1 is connected to the first scan signal Scan1, the first terminal of the first transistor T1 is connected to the data line and the first terminal of the compensation unit, and the second terminal of the first transistor T1 Connect to the first node G;
  • the control terminal of the second transistor T2 is connected to the second scan signal Scan2, the first terminal of the second transistor T2 is connected to the second node S, and the second terminal of the second transistor T2 is connected to the first switch S1 The first end of and the first end of the second switch S2;
  • the control terminal of the third transistor T3 is connected to the third scan signal Scan3, the first terminal of the third transistor T3 is connected to the negative power supply voltage VSS, and the second terminal of the third transistor T3 is connected to the second node S;
  • the control terminal of the fourth transistor T4 is connected to the fourth scan signal Scan4, the first terminal of the fourth transistor T4 is connected to the third node Q, and the second terminal of the fourth transistor T4 is connected to the positive power supply voltage VDD;
  • the first end of the storage capacitor is connected to a first node G, and the second end of the storage capacitor is connected to a second node S;
  • the first end of the light-emitting element is connected to the positive power supply voltage VDD, and the second end of the light-emitting element is connected to the third node Q;
  • the second terminal of the first switch S1 is connected to the initialization voltage Vi;
  • the second end of the second switch S2 is connected to the second end of the compensation unit
  • the compensation unit is used for detecting and storing the initial threshold voltage of the driving transistor DT, so that the pixel compensation driving circuit can superimpose the data voltage output by the data line and the initial threshold voltage according to the superimposed data voltage, The actual threshold voltage of the driving transistor DT is compensated.
  • the pixel compensation driving circuit further detects and stores the mobility of the driving transistor DT according to the superimposed data voltage.
  • the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are N-type thin film transistors.
  • the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors Or amorphous silicon thin film transistors.
  • the light-emitting element is an organic light-emitting diode.
  • the first end of the light-emitting element is an anode end
  • the second end of the light-emitting element is a cathode end
  • the first scan signal Scan1, the second scan signal Scan2, the third scan signal Scan3, and the fourth scan signal Scan4 are provided by a timing controller.
  • the display device is an active matrix organic light emitting diode display device.
  • the pixel compensation driving circuit includes a driving transistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a storage capacitor, a light-emitting element, a first switch, a second switch, and a compensation unit.
  • the pixel compensation driving circuit Detecting and storing the initial threshold voltage of the driving transistor during each shutdown period of the display device, so that the pixel compensation driving circuit will superimpose the initial threshold voltage and the data voltage output by the data line during the next startup period of the display device to obtain the superimposed data voltage,
  • the actual threshold voltage of the driving transistor is compensated, and finally the current flowing through the light-emitting element is independent of the actual threshold voltage of the driving transistor, thereby eliminating the problem of uneven display of the display device caused by the drift of the actual threshold voltage of the driving transistor, and improving the picture The display effect.
  • FIG. 1 is a diagram of a pixel compensation driving circuit provided by an embodiment of the present invention.
  • FIG. 2 is a flowchart of a pixel compensation driving method provided by an embodiment of the present invention.
  • FIG. 3 is a timing diagram of driving signals of a pixel compensation driving circuit provided by an embodiment of the present invention.
  • FIG. 4 is a circuit diagram of the pixel compensation driving circuit in the reset phase provided by the embodiment of the present invention.
  • FIG. 5 is a circuit diagram of the pixel compensation driving circuit in the detection phase according to an embodiment of the present invention.
  • FIG. 6 is a circuit diagram of the pixel compensation driving circuit in the voltage writing stage provided by an embodiment of the present invention.
  • FIG. 7 is a circuit diagram of a pixel compensation driving circuit provided by an embodiment of the present invention in a light-emitting phase.
  • FIG. 1 is a diagram of a pixel compensation driving circuit provided by an embodiment of the present invention.
  • the pixel compensation driving circuit adopts a 5T1C structure and includes: a driving transistor DT, a first The transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the storage capacitor Cst, the light emitting element, the first switch S1, the second switch S2, and the compensation unit.
  • the control terminal of the driving transistor DT is connected to the first node G, the first terminal of the driving transistor DT is connected to the second node S, and the second terminal of the driving transistor DT is connected to the third node Q.
  • the control terminal of the first transistor T1 is connected to the first scan signal Scan1, the first terminal of the first transistor T1 is connected to the data line and the first terminal of the compensation unit, and the second terminal of the first transistor T1 is connected to the first node G.
  • the control terminal of the second transistor T2 is connected to the second scan signal Scan2, the first terminal of the second transistor T2 is connected to the second node S, and the second terminal of the second transistor T2 is connected to the first terminal of the first switch S1 and the second switch The first end of S2.
  • the control terminal of the third transistor T3 is connected to the third scan signal Scan3, the first terminal of the third transistor T3 is connected to the negative power supply voltage VSS, and the second terminal of the third transistor T3 is connected to the second node S.
  • the control terminal of the fourth transistor T4 is connected to the fourth scan signal Scan4, the first terminal of the fourth transistor T4 is connected to the third node Q, and the second terminal of the fourth transistor T4 is connected to the positive power supply voltage VDD.
  • the first end of the storage capacitor Cst is connected to the first node G, and the second end of the storage capacitor Cst is connected to the second node S.
  • the first end of the light-emitting element is connected to the positive power supply voltage VDD, and the second end of the light-emitting element is connected to the third node Q.
  • the second terminal of the first switch S1 is connected to the initialization voltage Vi.
  • the second end of the second switch S2 is connected to the second end of the compensation unit.
  • the compensation unit is used to detect and store the initial threshold voltage of the driving transistor DT, so that the pixel compensation driving circuit compensates the actual threshold voltage of the driving transistor DT according to the superimposed data voltage obtained by superimposing the initial threshold voltage and the data voltage output by the data line .
  • the pixel compensation driving circuit also detects and stores the mobility of the driving transistor DT according to the superimposed data voltage.
  • control terminal, first terminal, and second terminal of the transistor in the embodiment of the present invention are the gate, source, and drain of the transistor, respectively, and the first terminal and the second terminal can be interchanged.
  • the light-emitting element is an organic light-emitting diode, and the first end of the light-emitting element is the anode end, and the second end is the cathode end.
  • the compensation unit may include an analog-to-digital converter, a current comparator, a controller, a memory, and a digital-to-analog converter connected in sequence, and the input terminal of the analog-to-digital converter is connected to the second terminal of the second switch S2, and the output of the digital-to-analog converter The terminal is connected to the first terminal of the first transistor T1.
  • the analog-to-digital converter is used to digitize the initial threshold voltage of the driving transistor DT output by the second terminal of the second transistor T2
  • the memory is used to store the digitized initial threshold voltage
  • the digital-to-analog converter is used to simulate the digitized initial threshold voltage. Then, input to the first terminal of the first transistor T1.
  • the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are N-type thin film transistors.
  • the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 in the embodiment of the present invention all use the same type of thin film transistors, so as to avoid different types of thin film transistors.
  • the difference between the transistors has an adverse effect on the pixel compensation drive circuit.
  • the first scan signal Scan1, the second scan signal Scan2, the third scan signal Scan3, and the fourth scan signal Scan4 are all provided by an external timing controller.
  • the embodiment of the present invention also provides a pixel compensation driving method for driving the aforementioned pixel compensation driving circuit. It is understandable that the display device including the above pixel compensation driving circuit includes a cycle period composed of a plurality of shutdown periods and a plurality of startup periods.
  • FIG. 2 is a flowchart of a pixel compensation driving method according to an embodiment of the present invention, as shown in FIG. 2. As shown, the pixel compensation driving method includes the following steps:
  • step S1 during the shutdown period, the compensation unit detects and stores the initial threshold voltage of the driving transistor DT.
  • Step S2 During the start-up period, the pixel compensation driving circuit compensates the actual threshold voltage of the driving transistor DT in each frame time according to the superimposed data voltage obtained by superimposing the initial threshold voltage and the data voltage output by the data line.
  • the pixel compensation driving method further includes:
  • step S3 during the startup period, the pixel compensation driving circuit detects and stores the mobility of the driving transistor DT in each frame time according to the superimposed data voltage.
  • step S2 in each frame time, the pixel compensation driving circuit compensates for the actual threshold voltage of the driving transistor DT according to the superimposed data voltage obtained by superimposing the initial threshold voltage and the data voltage output by the data line, including resetting. Phase, detection phase, voltage writing phase and light-emitting phase.
  • FIG. 3 is a timing diagram of driving signals of the pixel compensation driving circuit provided by an embodiment of the present invention.
  • FIG. 4 is a circuit diagram of the pixel compensation driving circuit provided by an embodiment of the present invention in the reset phase.
  • the first scan signal Scan1, the second scan signal Scan2, and the fourth scan signal Scan4 provide a high level
  • the third scan signal Scan3 provides a low level
  • the first switch S1 is closed
  • the second switch S2 is open.
  • the driving transistor DT, the first transistor T1, the second transistor T2, and the fourth transistor T4 are turned on, the third transistor T3 is turned off, the second terminal of the second transistor T2 is connected to the initialization voltage Vi, and the first terminal of the first transistor T1 is connected to Reference voltage Vref.
  • the first node G is written in the reference voltage Vref
  • the second node S is written in the initialization voltage Vi.
  • the first scan signal Scan1 and the fourth scan signal Scan4 provide high voltage
  • the second scan signal Scan2 and the third scan signal Scan3 provide a low level, the first switch S1 and the second switch S2 are turned off; the driving transistor DT, the first transistor T1 and the fourth transistor T4 are turned on, and the second transistor T2 and The third transistor T3 is turned off, and the first terminal of the first transistor T1 is connected to the reference voltage Vref.
  • the first node G is written with the reference voltage Vref
  • the positive power supply voltage VDD charges the second node S
  • the voltage of the second node S rises to Vref-Vth, where Vth is the actual threshold voltage of the driving transistor DT during power-on.
  • FIGS. 3 and 6 are a circuit diagram of the pixel compensation driving circuit provided by an embodiment of the present invention in the voltage writing phase.
  • the first scan signal Scan1 and the third scan signal Scan3 are provided High level
  • the second scan signal Scan2 and the fourth scan signal Scan4 provide low level
  • the first switch S1 and the second switch S2 are turned off
  • the driving transistor DT, the first transistor T1 and the third transistor T3 are turned on
  • the second transistor T2 and the fourth transistor T4 are turned off, and the first end of the first transistor T1 is connected to the superimposed data voltage Vdata+Vth0.
  • the first node G writes Vdata+Vth0
  • the voltage of the second node S remains Vref-Vth
  • the voltage between the control terminal and the first terminal of the driving transistor DT is between the first node G and the second node S
  • the voltage difference between Vgs Vdata-Vref+Vth+Vth0, where Vdata is the data voltage output by the data line, and Vth0 is the initial threshold voltage of the driving transistor DT during the shutdown period.
  • FIG. 7 is a circuit diagram of the pixel compensation driving circuit provided by an embodiment of the present invention in the light-emitting phase.
  • the third scan signal Scan3 provides a high level
  • the first scan signal Scan1 The second scan signal Scan2 and the fourth scan signal Scan4 provide a low level, the first switch S1 and the second switch S2 are turned off; the driving transistor DT and the third transistor T3 are turned on, and the first transistor T1, the second transistor T2, and the fourth transistor are turned on.
  • the transistor T4 is turned off, and the first terminal of the first transistor T1 is connected to the reference voltage Vref.
  • k is the mobility of the driving transistor DT.
  • the pixel compensation driving circuit provided by the embodiment of the present invention can effectively compensate the actual threshold voltage Vth of the driving transistor DT in real time, and finally make the current flowing through the light-emitting element independent of the actual threshold voltage Vth of the driving transistor DT.
  • the problem of uneven display of the display device caused by the drift of the actual threshold voltage Vth of the driving transistor DT is eliminated, and the display effect of the picture is improved.
  • this compensation method is an internal compensation method, the compensation speed is fast.
  • the pixel compensation driving circuit detects and stores the mobility of the driving transistor DT according to the superimposed data voltage.
  • the working process includes a first mobility detection stage and a second mobility detection stage. Phase and the third mobility detection phase.
  • the first scan signal Scan1, the second scan signal Scan2, and the third scan signal Scan3 provide a high level
  • the fourth scan signal Scan4 provides a low level
  • the first switch S1 is closed
  • the second The switch S2 is turned off;
  • the driving transistor DT, the first transistor T1, the second transistor T2, and the third transistor T3 are turned on
  • the fourth transistor T4 is turned off, the second terminal of the second transistor T2 is connected to the initialization voltage Vi
  • the first transistor T1 The first terminal is connected to the superimposed data voltage Vdata+Vth0.
  • the first node G is written with the superimposed data voltage Vdata+Vth0
  • the second node S is written with the initialization voltage Vi.
  • the second scan signal Scan2 and the third scan signal Scan3 provide a high level
  • the first scan signal Scan1 and the fourth scan signal Scan4 provide a low level
  • the first switch S1 and the second switch S2 is turned off
  • the driving transistor DT, the second transistor T2, and the third transistor T3 are turned on
  • the first transistor T1 and the fourth transistor T4 are turned off, and the first terminal of the first transistor T1 is connected to the reference voltage Vref.
  • the second scan signal Scan2 and the third scan signal Scan3 provide a high level
  • the first scan signal Scan1 and the fourth scan signal Scan4 provide a low level
  • the first switch S1 is turned off, and the The second switch S2 is closed
  • the driving transistor DT, the second transistor T2 and the third transistor T3 are open
  • the first transistor T1 and the fourth transistor T4 are closed
  • the second end of the second transistor T2 is connected to the second end of the compensation unit
  • the first transistor The first terminal of T1 is connected to the reference voltage Vref.
  • the compensation unit obtains the charging voltage output by the second transistor T2, obtains and stores the mobility of the driving transistor DT according to the charging voltage.
  • the working process of the compensation unit detecting and storing the initial threshold voltage of the driving transistor DT in step S1 includes a first initial threshold voltage detection phase and a second initial threshold voltage detection phase.
  • the first scan signal Scan1, the second scan signal Scan2, and the third scan signal Scan3 provide a high level
  • the fourth scan signal Scan4 provides a low level
  • the first switch S1 is closed
  • the The second switch S2 is turned off;
  • the driving transistor DT, the first transistor T1, the second transistor T2, and the third transistor T3 are turned on, the fourth transistor T4 is turned off, the second terminal of the second transistor T2 is connected to the initialization voltage Vi, and the first transistor T1
  • the data voltage Vdata is connected to the first terminal of the.
  • the first scan signal Scan1, the second scan signal Scan2, and the third scan signal Scan3 provide a high level
  • the fourth scan signal Scan4 provides a low level
  • the first switch S1 is turned off.
  • the second switch S2 is closed; the driving transistor DT, the first transistor T1, the second transistor T2, and the third transistor T3 are turned on, the fourth transistor T4 is turned off, and the second end of the second transistor T2 is connected to the second end of the compensation unit.
  • the first terminal of the transistor T1 is connected to the data voltage Vdata.
  • the compensation unit obtains and stores the initial threshold voltage Vth0 of the driving transistor DT.
  • the embodiment of the present invention also provides a display device.
  • the display device includes a pixel compensation driving circuit.
  • the pixel compensation driving circuit adopts a 5T1C structure and includes: a driving transistor DT, a first transistor T1, a second transistor T2, The third transistor T3, the fourth transistor T4, the storage capacitor Cst, the light emitting element, the first switch S1, the second switch S2, and the compensation unit.
  • the control terminal of the driving transistor DT is connected to the first node G, the first terminal of the driving transistor DT is connected to the second node S, and the second terminal of the driving transistor DT is connected to the third node Q.
  • the control terminal of the first transistor T1 is connected to the first scan signal Scan1, the first terminal of the first transistor T1 is connected to the data line and the first terminal of the compensation unit, and the second terminal of the first transistor T1 is connected to the first node G.
  • the control terminal of the second transistor T2 is connected to the second scan signal Scan2, the first terminal of the second transistor T2 is connected to the second node S, and the second terminal of the second transistor T2 is connected to the first terminal of the first switch S1 and the second switch The first end of S2.
  • the control terminal of the third transistor T3 is connected to the third scan signal Scan3, the first terminal of the third transistor T3 is connected to the negative power supply voltage VSS, and the second terminal of the third transistor T3 is connected to the second node S.
  • the control terminal of the fourth transistor T4 is connected to the fourth scan signal Scan4, the first terminal of the fourth transistor T4 is connected to the third node Q, and the second terminal of the fourth transistor T4 is connected to the positive power supply voltage VDD.
  • the first end of the storage capacitor Cst is connected to the first node G, and the second end of the storage capacitor Cst is connected to the second node S.
  • the first end of the light-emitting element is connected to the positive power supply voltage VDD, and the second end of the light-emitting element is connected to the third node Q.
  • the second terminal of the first switch S1 is connected to the initialization voltage Vi.
  • the second end of the second switch S2 is connected to the second end of the compensation unit.
  • the compensation unit is used to detect and store the initial threshold voltage of the driving transistor DT, so that the pixel compensation driving circuit compensates the actual threshold voltage of the driving transistor DT according to the superimposed data voltage obtained by superimposing the initial threshold voltage and the data voltage output by the data line .
  • the pixel compensation driving circuit also detects and stores the mobility of the driving transistor DT according to the superimposed data voltage.
  • control terminal, first terminal, and second terminal of the transistor in the embodiment of the present invention are the gate, source, and drain of the transistor, respectively, and the first terminal and the second terminal can be interchanged.
  • the light-emitting element is an organic light-emitting diode, and the first end of the light-emitting element is the anode end, and the second end is the cathode end.
  • the compensation unit may include an analog-to-digital converter, a current comparator, a controller, a memory, and a digital-to-analog converter connected in sequence, and the input terminal of the analog-to-digital converter is connected to the second terminal of the second switch S2, and the output of the digital-to-analog converter The terminal is connected to the first terminal of the first transistor T1.
  • the analog-to-digital converter is used to digitize the initial threshold voltage of the driving transistor DT output by the second terminal of the second transistor T2
  • the memory is used to store the digitized initial threshold voltage
  • the digital-to-analog converter is used to simulate the digitized initial threshold voltage. Then, input to the first terminal of the first transistor T1.
  • the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are N-type thin film transistors.
  • the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 in the embodiment of the present invention all use the same type of thin film transistors, so as to avoid different types of thin film transistors.
  • the difference between the transistors has an adverse effect on the pixel compensation drive circuit.
  • the first scan signal Scan1, the second scan signal Scan2, the third scan signal Scan3, and the fourth scan signal Scan4 are all provided by an external timing controller.
  • the display device may be an Active-Matrix Organic Light-Emitting Diode (Active-Matrix Organic Light-Emitting Diode).
  • Active-Matrix Organic Light-Emitting Diode Active-Matrix Organic Light-Emitting Diode
  • AMOLED Active-Matrix Organic Light-Emitting Diode

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Abstract

一种像素补偿驱动电路及其驱动方法、显示装置。像素补偿驱动电路包括驱动晶体管（DT）、第一晶体管（T1）、第二晶体管（T2）、第三晶体管（T3）、第四晶体管（T4）、存储电容（Cst）、发光元件、第一开关（S1）、第二开关（S2）和补偿单元。补偿单元用于侦测并存储驱动晶体管（DT）的初始阈值电压，以使像素补偿驱动电路根据初始阈值电压与数据线输出的数据电压叠加得到的叠加数据电压，对驱动晶体管（DT）的实际阈值电压进行补偿。像素补偿驱动电路还根据叠加数据电压，侦测并存储驱动晶体管(DT)的迁移率。使流经发光元件的电流与驱动晶体管(DT)的实际阈值电压无关，从而消除驱动晶体管(DT)的实际阈值电压发生漂移导致显示装置出现显示不均的问题。

Description

像素补偿驱动电路及其驱动方法、显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种像素补偿驱动电路及其驱动方法、显示装置。
 背景技术
有机发光二极管(organic light emitting diode，OLED)显示装置，是一种利用有机发光材料在电场驱动下发生载流子注入和复合而发光的显示装置，具有自发光、广视角、高对比度、低耗电和高反应速度等优点。
然而，由于制造工艺的限制，现有的OLED显示装置中的每个像素的驱动晶体管的电气特性存在一定差异，并且，驱动晶体管在工作过程中不稳定，易受温度和光照等因素的影响而发生特性漂移，驱动晶体管在空间上的电气特性差异和时间上的特性漂移均会造成驱动晶体管的阈值电压发生漂移，导致OLED显示装置出现显示不均的问题。
 技术问题
本发明提供一种像素补偿驱动电路及其驱动方法、显示装置，以解决现有的OLED显示装置显示不均的技术问题。
 技术解决方案
第一方面，本发明提供了一种像素补偿驱动电路，所述像素补偿驱动电路包括：驱动晶体管DT、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、存储电容、发光元件、第一开关S1、第二开关S2和补偿单元；
所述驱动晶体管DT的控制端连接第一节点G，所述驱动晶体管DT的第一端连接第二节点S，所述驱动晶体管DT的第二端连接第三节点Q；
所述第一晶体管T1的控制端接入第一扫描信号Scan1，所述第一晶体管T1的第一端连接数据线和所述补偿单元的第一端，所述第一晶体管T1的第二端连接第一节点G；
所述第二晶体管T2的控制端接入第二扫描信号Scan2，所述第二晶体管T2的第一端连接第二节点S，所述第二晶体管T2的第二端连接所述第一开关S1的第一端和所述第二开关S2的第一端；
所述第三晶体管T3的控制端接入第三扫描信号Scan3，所述第三晶体管T3的第一端接入电源负电压VSS，所述第三晶体管T3的第二端连接第二节点S；
所述第四晶体管T4的控制端接入第四扫描信号Scan4，所述第四晶体管T4的第一端连接第三节点Q，所述第四晶体管T4的第二端接入电源正电压VDD；
所述存储电容的第一端连接第一节点G，所述存储电容的第二端连接第二节点S；
所述发光元件的第一端接入电源正电压VDD，所述发光元件的第二端连接第三节点Q；
所述第一开关S1的第二端接入初始化电压Vi；
所述第二开关S2的第二端连接所述补偿单元的第二端；
所述补偿单元用于侦测并存储所述驱动晶体管DT的初始阈值电压，以使所述像素补偿驱动电路根据所述初始阈值电压与所述数据线输出的数据电压叠加得到的叠加数据电压，对所述驱动晶体管DT的实际阈值电压进行补偿。
在一些实施例中，所述像素补偿驱动电路还根据所述叠加数据电压，侦测并存储所述驱动晶体管DT的迁移率。
在一些实施例中，所述驱动晶体管DT、所述第一晶体管T1、所述第二晶体管T2、所述第三晶体管T3和所述第四晶体管T4为N型薄膜晶体管。
在一些实施例中，所述驱动晶体管DT、所述第一晶体管T1、所述第二晶体管T2、所述第三晶体管T3和所述第四晶体管T4为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
在一些实施例中，所述发光元件为有机发光二极管。
在一些实施例中，所述发光元件的第一端为阳极端，所述发光元件的第二端为阴极端。
在一些实施例中，所述第一扫描信号Scan1、所述第二扫描信号Scan2、所述第三扫描信号Scan3和所述第四扫描信号Scan4由时序控制器提供。
第二方面，本发明提供了一种像素补偿驱动方法，用于驱动像素补偿驱动电路，所述像素补偿驱动电路包括驱动晶体管DT、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、存储电容、发光元件、第一开关S1、第二开关S2和补偿单元；
所述驱动晶体管DT的控制端连接第一节点G，所述驱动晶体管DT的第一端连接第二节点S，所述驱动晶体管DT的第二端连接第三节点Q；
所述第一晶体管T1的控制端接入第一扫描信号Scan1，所述第一晶体管T1的第一端连接数据线和所述补偿单元的第一端，所述第一晶体管T1的第二端连接第一节点G；
所述第二晶体管T2的控制端接入第二扫描信号Scan2，所述第二晶体管T2的第一端连接第二节点S，所述第二晶体管T2的第二端连接所述第一开关S1的第一端和所述第二开关S2的第一端；
所述第三晶体管T3的控制端接入第三扫描信号Scan3，所述第三晶体管T3的第一端接入电源负电压VSS，所述第三晶体管T3的第二端连接第二节点S；
所述第四晶体管T4的控制端接入第四扫描信号Scan4，所述第四晶体管T4的第一端连接第三节点Q，所述第四晶体管T4的第二端接入电源正电压VDD；
所述存储电容的第一端连接第一节点G，所述存储电容的第二端连接第二节点S；
所述发光元件的第一端接入电源正电压VDD，所述发光元件的第二端连接第三节点Q；
所述第一开关S1的第二端接入初始化电压Vi；
所述第二开关S2的第二端连接所述补偿单元的第二端；
所述像素补偿驱动方法包括以下步骤：
步骤S1，在关机期间，所述补偿单元侦测并存储所述驱动晶体管DT的初始阈值电压；
步骤S2，在开机期间，所述像素补偿驱动电路根据所述初始阈值电压与所述数据线输出的数据电压叠加得到的叠加数据电压，在每一帧时间内对所述驱动晶体管DT的实际阈值电压进行补偿。
在一些实施例中，在所述步骤S2之后，所述像素补偿驱动方法还包括：
步骤S3，在开机期间，所述像素补偿驱动电路根据所述叠加数据电压，在每一帧时间内侦测并存储所述驱动晶体管DT的迁移率。
在一些实施例中，所述步骤S2包括复位阶段、侦测阶段、电压写入阶段和发光阶段；
在所述复位阶段中，所述第一扫描信号Scan1、所述第二扫描信号Scan2和所述第四扫描信号Scan4提供高电平，所述第三扫描信号Scan3提供低电平，所述第一开关S1闭合，所述第二开关S2断开；所述驱动晶体管DT、所述第一晶体管T1、所述第二晶体管T2和所述第四晶体管T4打开，所述第三晶体管T3关闭，所述第二晶体管T2的第二端接入初始化电压Vi，所述第一晶体管T1的第一端接入参考电压；
在所述侦测阶段中，所述第一扫描信号Scan1和所述第四扫描信号Scan4提供高电平，所述第二扫描信号Scan2和第三扫描信号Scan3提供低电平，所述第一开关S1和所述第二开关S2断开；所述驱动晶体管DT、所述第一晶体管T1和所述第四晶体管T4打开，所述第二晶体管T2和所述第三晶体管T3关闭，所述第一晶体管T1的第一端接入参考电压；
在所述电压写入阶段中，所述第一扫描信号Scan1和所述第三扫描信号Scan3提供高电平，所述第二扫描信号Scan2和第四扫描信号Scan4提供低电平，所述第一开关S1和所述第二开关S2断开；所述驱动晶体管DT、所述第一晶体管T1和所述第三晶体管T3打开，所述第二晶体管T2和所述第四晶体管T4关闭，所述第一晶体管T1的第一端接入所述叠加数据电压；以及
在所述发光阶段中，所述第三扫描信号Scan3提供高电平，所述第一扫描信号Scan1、所述第二扫描信号Scan2和第四扫描信号Scan4提供低电平，所述第一开关S1和所述第二开关S2断开；所述驱动晶体管DT和所述第三晶体管T3打开，所述第一晶体管T1、所述第二晶体管T2和所述第四晶体管T4关闭，所述第一晶体管T1的第一端接入参考电压。
在一些实施例中，所述步骤S3包括第一迁移率侦测阶段、第二迁移率侦测阶段和第三迁移率侦测阶段；
在所述第一迁移率侦测阶段中，所述第一扫描信号Scan1、所述第二扫描信号Scan2和所述第三扫描信号Scan3提供高电平，所述第四扫描信号Scan4提供低电平，所述第一开关S1闭合，所述第二开关S2断开；所述驱动晶体管DT、所述第一晶体管T1、所述第二晶体管T2和所述第三晶体管T3打开，所述第四晶体管T4关闭，所述第二晶体管T2的第二端接入初始化电压Vi，所述第一晶体管T1的第一端接入所述叠加数据电压；
在所述第二迁移率侦测阶段中，所述第二扫描信号Scan2和所述第三扫描信号Scan3提供高电平，所述第一扫描信号Scan1和所述第四扫描信号Scan4提供低电平，所述第一开关S1和所述第二开关S2断开；所述驱动晶体管DT、所述第二晶体管T2和所述第三晶体管T3打开，所述第一晶体管T1和所述第四晶体管T4关闭，所述第一晶体管T1的第一端接入参考电压；以及
在所述第三迁移率侦测阶段中，所述第二扫描信号Scan2和所述第三扫描信号Scan3提供高电平，所述第一扫描信号Scan1和所述第四扫描信号Scan4提供低电平，所述第一开关S1断开，所述第二开关S2闭合；所述驱动晶体管DT、所述第二晶体管T2和所述第三晶体管T3打开，所述第一晶体管T1和所述第四晶体管T4关闭，所述第二晶体管T2的第二端连接所述补偿单元的第二端，所述第一晶体管T1的第一端接入参考电压。
在一些实施例中，所述步骤S1包括第一初始阈值电压侦测阶段和第二初始阈值电压侦测阶段；
在所述第一初始阈值电压侦测阶段中，所述第一扫描信号Scan1、所述第二扫描信号Scan2和所述第三扫描信号Scan3提供高电平，所述第四扫描信号Scan4提供低电平，所述第一开关S1闭合，所述第二开关S2断开；所述驱动晶体管DT、所述第一晶体管T1、所述第二晶体管T2和所述第三晶体管T3打开，所述第四晶体管T4关闭，所述第二晶体管T2的第二端接入初始化电压Vi，所述第一晶体管T1的第一端接入所述数据电压；以及
在所述第二初始阈值电压侦测阶段中，所述第一扫描信号Scan1、所述第二扫描信号Scan2和所述第三扫描信号Scan3提供高电平，所述第四扫描信号Scan4提供低电平，所述第一开关S1断开，所述第二开关S2闭合；所述驱动晶体管DT、所述第一晶体管T1、所述第二晶体管T2和所述第三晶体管T3打开，所述第四晶体管T4关闭，所述第二晶体管T2的第二端连接所述补偿单元的第二端，所述第一晶体管T1的第一端接入所述数据电压。
第三方面，本发明提供了一种显示装置，所述显示装置包括像素补偿驱动电路，所述像素补偿驱动电路包括：驱动晶体管DT、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、存储电容、发光元件、第一开关S1、第二开关S2和补偿单元；
所述驱动晶体管DT的控制端连接第一节点G，所述驱动晶体管DT的第一端连接第二节点S，所述驱动晶体管DT的第二端连接第三节点Q；
所述第一晶体管T1的控制端接入第一扫描信号Scan1，所述第一晶体管T1的第一端连接数据线和所述补偿单元的第一端，所述第一晶体管T1的第二端连接第一节点G；
所述第二晶体管T2的控制端接入第二扫描信号Scan2，所述第二晶体管T2的第一端连接第二节点S，所述第二晶体管T2的第二端连接所述第一开关S1的第一端和所述第二开关S2的第一端；
所述第三晶体管T3的控制端接入第三扫描信号Scan3，所述第三晶体管T3的第一端接入电源负电压VSS，所述第三晶体管T3的第二端连接第二节点S；
所述第四晶体管T4的控制端接入第四扫描信号Scan4，所述第四晶体管T4的第一端连接第三节点Q，所述第四晶体管T4的第二端接入电源正电压VDD；
所述存储电容的第一端连接第一节点G，所述存储电容的第二端连接第二节点S；
所述发光元件的第一端接入电源正电压VDD，所述发光元件的第二端连接第三节点Q；
所述第一开关S1的第二端接入初始化电压Vi；
所述第二开关S2的第二端连接所述补偿单元的第二端；
所述补偿单元用于侦测并存储所述驱动晶体管DT的初始阈值电压，以使所述像素补偿驱动电路根据所述初始阈值电压与所述数据线输出的数据电压叠加得到的叠加数据电压，对所述驱动晶体管DT的实际阈值电压进行补偿。
在一些实施例中，所述像素补偿驱动电路还根据所述叠加数据电压，侦测并存储所述驱动晶体管DT的迁移率。
在一些实施例中，所述驱动晶体管DT、所述第一晶体管T1、所述第二晶体管T2、所述第三晶体管T3和所述第四晶体管T4为N型薄膜晶体管。
在一些实施例中，所述驱动晶体管DT、所述第一晶体管T1、所述第二晶体管T2、所述第三晶体管T3和所述第四晶体管T4为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
在一些实施例中，所述发光元件为有机发光二极管。
在一些实施例中，所述发光元件的第一端为阳极端，所述发光元件的第二端为阴极端。
在一些实施例中，所述第一扫描信号Scan1、所述第二扫描信号Scan2、所述第三扫描信号Scan3和所述第四扫描信号Scan4由时序控制器提供。
在一些实施例中，所述显示装置为有源矩阵有机发光二极管显示装置。
 有益效果
本发明提供的像素补偿驱动电路包括驱动晶体管、第一晶体管、第二晶体管、第三晶体管、第四晶体管、存储电容、发光元件、第一开关、第二开关和补偿单元，其中，补偿单元用于在显示装置每一次关机期间侦测并存储驱动晶体管的初始阈值电压，以使像素补偿驱动电路在显示装置下一次开机期间根据初始阈值电压与数据线输出的数据电压叠加得到的叠加数据电压，对驱动晶体管的实际阈值电压进行补偿，最终使流经发光元件的电流与驱动晶体管的实际阈值电压无关，从而消除驱动晶体管的实际阈值电压发生漂移导致显示装置出现显示不均的问题，改善了画面的显示效果。
 附图说明
图1为本发明的实施例提供的像素补偿驱动电路图。
图2为本发明的实施例提供的像素补偿驱动方法流程图。
图3为本发明的实施例提供的像素补偿驱动电路的驱动信号时序图。
图4为本发明的实施例提供的像素补偿驱动电路在复位阶段中的电路图。
图5为本发明的实施例提供的像素补偿驱动电路在侦测阶段中的电路图。
图6为本发明的实施例提供的像素补偿驱动电路在电压写入阶段中的电路图。
图7为本发明的实施例提供的像素补偿驱动电路在发光阶段中的电路图。
 本发明的实施方式
为使本发明的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本发明进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。
本发明的实施例提供一种像素补偿驱动电路，图1为本发明的实施例提供的像素补偿驱动电路图，如图1所示，像素补偿驱动电路采用5T1C结构，包括：驱动晶体管DT、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、存储电容Cst、发光元件、第一开关S1、第二开关S2和补偿单元。
驱动晶体管DT的控制端连接第一节点G，驱动晶体管DT的第一端连接第二节点S，驱动晶体管DT的第二端连接第三节点Q。第一晶体管T1的控制端接入第一扫描信号Scan1，第一晶体管T1的第一端连接数据线和补偿单元的第一端，第一晶体管T1的第二端连接第一节点G。第二晶体管T2的控制端接入第二扫描信号Scan2，第二晶体管T2的第一端连接第二节点S，第二晶体管T2的第二端连接第一开关S1的第一端和第二开关S2的第一端。第三晶体管T3的控制端接入第三扫描信号Scan3，第三晶体管T3的第一端接入电源负电压VSS，第三晶体管T3的第二端连接第二节点S。第四晶体管T4的控制端接入第四扫描信号Scan4，第四晶体管T4的第一端连接第三节点Q，第四晶体管T4的第二端接入电源正电压VDD。存储电容Cst的第一端连接第一节点G，存储电容Cst的第二端连接第二节点S。发光元件的第一端接入电源正电压VDD，发光元件的第二端连接第三节点Q。第一开关S1的第二端接入初始化电压Vi。第二开关S2的第二端连接补偿单元的第二端。
补偿单元用于侦测并存储驱动晶体管DT的初始阈值电压，以使像素补偿驱动电路根据初始阈值电压与数据线输出的数据电压叠加得到的叠加数据电压，对驱动晶体管DT的实际阈值电压进行补偿。
像素补偿驱动电路还根据叠加数据电压，侦测并存储驱动晶体管DT的迁移率。
需要说明的是，本发明的实施例中的晶体管的控制端、第一端和第二端分别为晶体管的栅极、源极和漏极，且第一端和第二端可以互换。
发光元件为有机发光二极管，发光元件的第一端为阳极端，第二端为阴极端。
补偿单元可以包括依次连接的模数转换器、电流比较器、控制器、存储器和数模转换器，且模数转换器的输入端连接第二开关S2的第二端，数模转换器的输出端连接第一晶体管T1的第一端。其中，模数转换器用于将第二晶体管T2的第二端输出的驱动晶体管DT的初始阈值电压数字化，存储器用于存储数字化的初始阈值电压，数模转换器用于将数字化的初始阈值电压模拟化后，输入至第一晶体管T1的第一端。
驱动晶体管DT、第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4为N型薄膜晶体管。
驱动晶体管DT、第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
需要说明的是，本发明的实施例中的驱动晶体管DT、第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4均采用同一种类型的薄膜晶体管，以避免不同类型的薄膜晶体管之间的差异性对像素补偿驱动电路的不利影响。
第一扫描信号Scan1、第二扫描信号Scan2、第三扫描信号Scan3和第四扫描信号Scan4均由外部的时序控制器提供。
本发明的实施例还提供一种像素补偿驱动方法，用于驱动上述像素补偿驱动电路。可以理解的是，包含上述像素补偿驱动电路的显示装置包括由多个关机期间和多个开机期间组成的循环周期，图2为本发明的实施例提供的像素补偿驱动方法流程图，如图2所示，像素补偿驱动方法包括以下步骤：
步骤S1，在关机期间，补偿单元侦测并存储驱动晶体管DT的初始阈值电压。
步骤S2，在开机期间，像素补偿驱动电路根据初始阈值电压与数据线输出的数据电压叠加得到的叠加数据电压，在每一帧时间内对驱动晶体管DT的实际阈值电压进行补偿。
在步骤S2之后，像素补偿驱动方法还包括：
步骤S3，在开机期间，像素补偿驱动电路根据叠加数据电压，在每一帧时间内侦测并存储驱动晶体管DT的迁移率。
具体的，步骤S2中在每一帧时间内，像素补偿驱动电路根据初始阈值电压与数据线输出的数据电压叠加得到的叠加数据电压，对驱动晶体管DT的实际阈值电压进行补偿的工作过程包括复位阶段、侦测阶段、电压写入阶段和发光阶段。
图3为本发明的实施例提供的像素补偿驱动电路的驱动信号时序图，图4为本发明的实施例提供的像素补偿驱动电路在复位阶段中的电路图，结合图3和图4，在复位阶段t1中，第一扫描信号Scan1、第二扫描信号Scan2和第四扫描信号Scan4提供高电平，第三扫描信号Scan3提供低电平，第一开关S1闭合，第二开关S2断开。驱动晶体管DT、第一晶体管T1、第二晶体管T2和第四晶体管T4打开，第三晶体管T3关闭，第二晶体管T2的第二端接入初始化电压Vi，第一晶体管T1的第一端接入参考电压Vref。此时，第一节点G写入参考电压Vref，第二节点S写入初始化电压Vi。
图5为本发明的实施例提供的像素补偿驱动电路在侦测阶段中的电路图，结合图3和图5，在侦测阶段t2中，第一扫描信号Scan1和第四扫描信号Scan4提供高电平，第二扫描信号Scan2和第三扫描信号Scan3提供低电平，第一开关S1和第二开关S2断开；驱动晶体管DT、第一晶体管T1和第四晶体管T4打开，第二晶体管T2和第三晶体管T3关闭，第一晶体管T1的第一端接入参考电压Vref。此时，第一节点G写入参考电压Vref，电源正电压VDD对第二节点S充电，第二节点S的电压抬升为Vref-Vth，其中，Vth为开机期间驱动晶体管DT的实际阈值电压。
图6为本发明的实施例提供的像素补偿驱动电路在电压写入阶段中的电路图，结合图3和图6，在电压写入阶段t3中，第一扫描信号Scan1和第三扫描信号Scan3提供高电平，第二扫描信号Scan2和第四扫描信号Scan4提供低电平，第一开关S1和第二开关S2断开；驱动晶体管DT、第一晶体管T1和第三晶体管T3打开，第二晶体管T2和第四晶体管T4关闭，第一晶体管T1的第一端接入叠加数据电压Vdata+Vth0。此时，第一节点G写入Vdata+Vth0，第二节点S的电压保持为Vref-Vth，驱动晶体管DT的控制端与第一端之间的电压为第一节点G与第二节点S之间的电压差，为Vgs=Vdata-Vref+Vth+Vth0，其中，Vdata为数据线输出的数据电压，Vth0为关机期间驱动晶体管DT的初始阈值电压。
图7为本发明的实施例提供的像素补偿驱动电路在发光阶段中的电路图，结合图3和图7，在发光阶段t4中，第三扫描信号Scan3提供高电平，第一扫描信号Scan1、第二扫描信号Scan2和第四扫描信号Scan4提供低电平，第一开关S1和第二开关S2断开；驱动晶体管DT和第三晶体管T3打开，第一晶体管T1、第二晶体管T2和第四晶体管T4关闭，第一晶体管T1的第一端接入参考电压Vref。此时，驱动晶体管DT驱动发光元件发光，流经发光元件的电流为：I=k(Vgs–Vth) 2=k(Vdata-Vref+Vth0) 2。其中，k为驱动晶体管DT的迁移率。
由此可见，本发明的实施例提供的像素补偿驱动电路，能够有效的实时补偿驱动晶体管DT的实际阈值电压Vth，最终使流经发光元件的电流与驱动晶体管DT的实际阈值电压Vth无关，从而消除驱动晶体管DT的实际阈值电压Vth发生漂移导致显示装置出现显示不均的问题，改善了画面的显示效果。并且该种补偿方式由于是内部补偿方式，因此补偿速度快。
具体的，步骤S3中在每一帧时间内，像素补偿驱动电路根据叠加数据电压，侦测并存储驱动晶体管DT的迁移率的工作过程包括第一迁移率侦测阶段、第二迁移率侦测阶段和第三迁移率侦测阶段。
在第一迁移率侦测阶段中，第一扫描信号Scan1、第二扫描信号Scan2和第三扫描信号Scan3提供高电平，第四扫描信号Scan4提供低电平，第一开关S1闭合，第二开关S2断开；驱动晶体管DT、第一晶体管T1、第二晶体管T2和第三晶体管T3打开，第四晶体管T4关闭，第二晶体管T2的第二端接入初始化电压Vi，第一晶体管T1的第一端接入叠加数据电压Vdata+Vth0。此时，第一节点G写入叠加数据电压Vdata+Vth0，第二节点S写入初始化电压Vi。
在第二迁移率侦测阶段中，第二扫描信号Scan2和第三扫描信号Scan3提供高电平，第一扫描信号Scan1和第四扫描信号Scan4提供低电平，第一开关S1和第二开关S2断开；驱动晶体管DT、第二晶体管T2和第三晶体管T3打开，第一晶体管T1和第四晶体管T4关闭，第一晶体管T1的第一端接入参考电压Vref。
在第三迁移率侦测阶段中，第二扫描信号Scan2和第三扫描信号Scan3提供高电平，第一扫描信号Scan1和第四扫描信号Scan4提供低电平，第一开关S1断开，第二开关S2闭合；驱动晶体管DT、第二晶体管T2和第三晶体管T3打开，第一晶体管T1和第四晶体管T4关闭，第二晶体管T2的第二端连接补偿单元的第二端，第一晶体管T1的第一端接入参考电压Vref。此时，补偿单元获取第二晶体管T2输出的充电电压，根据充电电压获取驱动晶体管DT的迁移率并进行存储。
步骤S1中补偿单元侦测并存储驱动晶体管DT的初始阈值电压的工作过程包括第一初始阈值电压侦测阶段和第二初始阈值电压侦测阶段。
在第一初始阈值电压侦测阶段中，第一扫描信号Scan1、第二扫描信号Scan2和第三扫描信号Scan3提供高电平，第四扫描信号Scan4提供低电平，第一开关S1闭合，第二开关S2断开；驱动晶体管DT、第一晶体管T1、第二晶体管T2和第三晶体管T3打开，第四晶体管T4关闭，第二晶体管T2的第二端接入初始化电压Vi，第一晶体管T1的第一端接入数据电压Vdata。
在第二初始阈值电压侦测阶段中，第一扫描信号Scan1、第二扫描信号Scan2和第三扫描信号Scan3提供高电平，第四扫描信号Scan4提供低电平，第一开关S1断开，第二开关S2闭合；驱动晶体管DT、第一晶体管T1、第二晶体管T2和第三晶体管T3打开，第四晶体管T4关闭，第二晶体管T2的第二端连接补偿单元的第二端，第一晶体管T1的第一端接入数据电压Vdata。此时，补偿单元获取驱动晶体管DT的初始阈值电压Vth0并进行存储。
本发明的实施例还提供一种显示装置，显示装置包括像素补偿驱动电路，如图1所示，像素补偿驱动电路采用5T1C结构，包括：驱动晶体管DT、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、存储电容Cst、发光元件、第一开关S1、第二开关S2和补偿单元。
驱动晶体管DT的控制端连接第一节点G，驱动晶体管DT的第一端连接第二节点S，驱动晶体管DT的第二端连接第三节点Q。第一晶体管T1的控制端接入第一扫描信号Scan1，第一晶体管T1的第一端连接数据线和补偿单元的第一端，第一晶体管T1的第二端连接第一节点G。第二晶体管T2的控制端接入第二扫描信号Scan2，第二晶体管T2的第一端连接第二节点S，第二晶体管T2的第二端连接第一开关S1的第一端和第二开关S2的第一端。第三晶体管T3的控制端接入第三扫描信号Scan3，第三晶体管T3的第一端接入电源负电压VSS，第三晶体管T3的第二端连接第二节点S。第四晶体管T4的控制端接入第四扫描信号Scan4，第四晶体管T4的第一端连接第三节点Q，第四晶体管T4的第二端接入电源正电压VDD。存储电容Cst的第一端连接第一节点G，存储电容Cst的第二端连接第二节点S。发光元件的第一端接入电源正电压VDD，发光元件的第二端连接第三节点Q。第一开关S1的第二端接入初始化电压Vi。第二开关S2的第二端连接补偿单元的第二端。
补偿单元用于侦测并存储驱动晶体管DT的初始阈值电压，以使像素补偿驱动电路根据初始阈值电压与数据线输出的数据电压叠加得到的叠加数据电压，对驱动晶体管DT的实际阈值电压进行补偿。
像素补偿驱动电路还根据叠加数据电压，侦测并存储驱动晶体管DT的迁移率。
需要说明的是，本发明的实施例中的晶体管的控制端、第一端和第二端分别为晶体管的栅极、源极和漏极，且第一端和第二端可以互换。
发光元件为有机发光二极管，发光元件的第一端为阳极端，第二端为阴极端。
补偿单元可以包括依次连接的模数转换器、电流比较器、控制器、存储器和数模转换器，且模数转换器的输入端连接第二开关S2的第二端，数模转换器的输出端连接第一晶体管T1的第一端。其中，模数转换器用于将第二晶体管T2的第二端输出的驱动晶体管DT的初始阈值电压数字化，存储器用于存储数字化的初始阈值电压，数模转换器用于将数字化的初始阈值电压模拟化后，输入至第一晶体管T1的第一端。
驱动晶体管DT、第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4为N型薄膜晶体管。
驱动晶体管DT、第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
需要说明的是，本发明的实施例中的驱动晶体管DT、第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4均采用同一种类型的薄膜晶体管，以避免不同类型的薄膜晶体管之间的差异性对像素补偿驱动电路的不利影响。
第一扫描信号Scan1、第二扫描信号Scan2、第三扫描信号Scan3和第四扫描信号Scan4均由外部的时序控制器提供。
另外，显示装置可以为有源矩阵有机发光二极管（Active-Matrix Organic Light-Emitting Diode，AMOLED）显示装置，具体为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，对本领域普通技术人员来说，可以根据本发明的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本发明所附的权利要求的保护范围。

Claims (20)

  1. 一种像素补偿驱动电路，其中，所述像素补偿驱动电路包括：驱动晶体管(DT)、第一晶体管(T1)、第二晶体管(T2)、第三晶体管(T3)、第四晶体管(T4)、存储电容、发光元件、第一开关(S1)、第二开关(S2)和补偿单元；
    所述驱动晶体管(DT)的控制端连接第一节点(G)，所述驱动晶体管(DT)的第一端连接第二节点(S)，所述驱动晶体管(DT)的第二端连接第三节点(Q)；
    所述第一晶体管(T1)的控制端接入第一扫描信号(Scan1)，所述第一晶体管(T1)的第一端连接数据线和所述补偿单元的第一端，所述第一晶体管(T1)的第二端连接第一节点(G)；
    所述第二晶体管(T2)的控制端接入第二扫描信号(Scan2)，所述第二晶体管(T2)的第一端连接第二节点(S)，所述第二晶体管(T2)的第二端连接所述第一开关(S1)的第一端和所述第二开关(S2)的第一端；
    所述第三晶体管(T3)的控制端接入第三扫描信号(Scan3)，所述第三晶体管(T3)的第一端接入电源负电压(VSS)，所述第三晶体管(T3)的第二端连接第二节点(S)；
    所述第四晶体管(T4)的控制端接入第四扫描信号(Scan4)，所述第四晶体管(T4)的第一端连接第三节点(Q)，所述第四晶体管(T4)的第二端接入电源正电压(VDD)；
    所述存储电容的第一端连接第一节点(G)，所述存储电容的第二端连接第二节点(S)；
    所述发光元件的第一端接入电源正电压(VDD)，所述发光元件的第二端连接第三节点(Q)；
    所述第一开关(S1)的第二端接入初始化电压(Vi)；
    所述第二开关(S2)的第二端连接所述补偿单元的第二端；
    所述补偿单元用于侦测并存储所述驱动晶体管(DT)的初始阈值电压，以使所述像素补偿驱动电路根据所述初始阈值电压与所述数据线输出的数据电压叠加得到的叠加数据电压，对所述驱动晶体管(DT)的实际阈值电压进行补偿。
  2. 如权利要求1所述的像素补偿驱动电路，其中，所述像素补偿驱动电路还根据所述叠加数据电压，侦测并存储所述驱动晶体管(DT)的迁移率。
  3. 如权利要求1所述的像素补偿驱动电路，其中，所述驱动晶体管(DT)、所述第一晶体管(T1)、所述第二晶体管(T2)、所述第三晶体管(T3)和所述第四晶体管(T4)为N型薄膜晶体管。
  4. 如权利要求1所述的像素补偿驱动电路，其中，所述驱动晶体管(DT)、所述第一晶体管(T1)、所述第二晶体管(T2)、所述第三晶体管(T3)和所述第四晶体管(T4)为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
  5. 如权利要求1所述的像素补偿驱动电路，其中，所述发光元件为有机发光二极管。
  6. 如权利要求1所述的像素补偿驱动电路，其中，所述发光元件的第一端为阳极端，所述发光元件的第二端为阴极端。
  7. 如权利要求1所述的像素补偿驱动电路，其中，所述第一扫描信号(Scan1)、所述第二扫描信号(Scan2)、所述第三扫描信号(Scan3)和所述第四扫描信号(Scan4)由时序控制器提供。
  8. 一种像素补偿驱动方法，用于驱动像素补偿驱动电路，其中，所述像素补偿驱动电路包括驱动晶体管(DT)、第一晶体管(T1)、第二晶体管(T2)、第三晶体管(T3)、第四晶体管(T4)、存储电容、发光元件、第一开关(S1)、第二开关(S2)和补偿单元；
    所述驱动晶体管(DT)的控制端连接第一节点(G)，所述驱动晶体管(DT)的第一端连接第二节点(S)，所述驱动晶体管(DT)的第二端连接第三节点(Q)；
    所述第一晶体管(T1)的控制端接入第一扫描信号(Scan1)，所述第一晶体管(T1)的第一端连接数据线和所述补偿单元的第一端，所述第一晶体管(T1)的第二端连接第一节点(G)；
    所述第二晶体管(T2)的控制端接入第二扫描信号(Scan2)，所述第二晶体管(T2)的第一端连接第二节点(S)，所述第二晶体管(T2)的第二端连接所述第一开关(S1)的第一端和所述第二开关(S2)的第一端；
    所述第三晶体管(T3)的控制端接入第三扫描信号(Scan3)，所述第三晶体管(T3)的第一端接入电源负电压(VSS)，所述第三晶体管(T3)的第二端连接第二节点(S)；
    所述第四晶体管(T4)的控制端接入第四扫描信号(Scan4)，所述第四晶体管(T4)的第一端连接第三节点(Q)，所述第四晶体管(T4)的第二端接入电源正电压(VDD)；
    所述存储电容的第一端连接第一节点(G)，所述存储电容的第二端连接第二节点(S)；
    所述发光元件的第一端接入电源正电压(VDD)，所述发光元件的第二端连接第三节点(Q)；
    所述第一开关(S1)的第二端接入初始化电压(Vi)；
    所述第二开关(S2)的第二端连接所述补偿单元的第二端；
    所述像素补偿驱动方法包括以下步骤：
    步骤S1，在关机期间，所述补偿单元侦测并存储所述驱动晶体管(DT)的初始阈值电压；
    步骤S2，在开机期间，所述像素补偿驱动电路根据所述初始阈值电压与所述数据线输出的数据电压叠加得到的叠加数据电压，在每一帧时间内对所述驱动晶体管(DT)的实际阈值电压进行补偿。
  9. 如权利要求8所述的像素补偿驱动方法，其中，在所述步骤S2之后，所述像素补偿驱动方法还包括：
    步骤S3，在开机期间，所述像素补偿驱动电路根据所述叠加数据电压，在每一帧时间内侦测并存储所述驱动晶体管(DT)的迁移率。
  10. 如权利要求8所述的像素补偿驱动方法，其中，所述步骤S2包括复位阶段、侦测阶段、电压写入阶段和发光阶段；
    在所述复位阶段中，所述第一扫描信号(Scan1)、所述第二扫描信号(Scan2)和所述第四扫描信号(Scan4)提供高电平，所述第三扫描信号(Scan3)提供低电平，所述第一开关(S1)闭合，所述第二开关(S2)断开；所述驱动晶体管(DT)、所述第一晶体管(T1)、所述第二晶体管(T2)和所述第四晶体管(T4)打开，所述第三晶体管(T3)关闭，所述第二晶体管(T2)的第二端接入初始化电压(Vi)，所述第一晶体管(T1)的第一端接入参考电压；
    在所述侦测阶段中，所述第一扫描信号(Scan1)和所述第四扫描信号(Scan4)提供高电平，所述第二扫描信号(Scan2)和第三扫描信号(Scan3)提供低电平，所述第一开关(S1)和所述第二开关(S2)断开；所述驱动晶体管(DT)、所述第一晶体管(T1)和所述第四晶体管(T4)打开，所述第二晶体管(T2)和所述第三晶体管(T3)关闭，所述第一晶体管(T1)的第一端接入参考电压；
    在所述电压写入阶段中，所述第一扫描信号(Scan1)和所述第三扫描信号(Scan3)提供高电平，所述第二扫描信号(Scan2)和第四扫描信号(Scan4)提供低电平，所述第一开关(S1)和所述第二开关(S2)断开；所述驱动晶体管(DT)、所述第一晶体管(T1)和所述第三晶体管(T3)打开，所述第二晶体管(T2)和所述第四晶体管(T4)关闭，所述第一晶体管(T1)的第一端接入所述叠加数据电压；以及
    在所述发光阶段中，所述第三扫描信号(Scan3)提供高电平，所述第一扫描信号(Scan1)、所述第二扫描信号(Scan2)和第四扫描信号(Scan4)提供低电平，所述第一开关(S1)和所述第二开关(S2)断开；所述驱动晶体管(DT)和所述第三晶体管(T3)打开，所述第一晶体管(T1)、所述第二晶体管(T2)和所述第四晶体管(T4)关闭，所述第一晶体管(T1)的第一端接入参考电压。
  11. 如权利要求9所述的像素补偿驱动方法，其中，所述步骤S3包括第一迁移率侦测阶段、第二迁移率侦测阶段和第三迁移率侦测阶段；
    在所述第一迁移率侦测阶段中，所述第一扫描信号(Scan1)、所述第二扫描信号(Scan2)和所述第三扫描信号(Scan3)提供高电平，所述第四扫描信号(Scan4)提供低电平，所述第一开关(S1)闭合，所述第二开关(S2)断开；所述驱动晶体管(DT)、所述第一晶体管(T1)、所述第二晶体管(T2)和所述第三晶体管(T3)打开，所述第四晶体管(T4)关闭，所述第二晶体管(T2)的第二端接入初始化电压(Vi)，所述第一晶体管(T1)的第一端接入所述叠加数据电压；
    在所述第二迁移率侦测阶段中，所述第二扫描信号(Scan2)和所述第三扫描信号(Scan3)提供高电平，所述第一扫描信号(Scan1)和所述第四扫描信号(Scan4)提供低电平，所述第一开关(S1)和所述第二开关(S2)断开；所述驱动晶体管(DT)、所述第二晶体管(T2)和所述第三晶体管(T3)打开，所述第一晶体管(T1)和所述第四晶体管(T4)关闭，所述第一晶体管(T1)的第一端接入参考电压；以及
    在所述第三迁移率侦测阶段中，所述第二扫描信号(Scan2)和所述第三扫描信号(Scan3)提供高电平，所述第一扫描信号(Scan1)和所述第四扫描信号(Scan4)提供低电平，所述第一开关(S1)断开，所述第二开关(S2)闭合；所述驱动晶体管(DT)、所述第二晶体管(T2)和所述第三晶体管(T3)打开，所述第一晶体管(T1)和所述第四晶体管(T4)关闭，所述第二晶体管(T2)的第二端连接所述补偿单元的第二端，所述第一晶体管(T1)的第一端接入参考电压。
  12. 如权利要求8所述的像素补偿驱动方法，其中，所述步骤S1包括第一初始阈值电压侦测阶段和第二初始阈值电压侦测阶段；
    在所述第一初始阈值电压侦测阶段中，所述第一扫描信号(Scan1)、所述第二扫描信号(Scan2)和所述第三扫描信号(Scan3)提供高电平，所述第四扫描信号(Scan4)提供低电平，所述第一开关(S1)闭合，所述第二开关(S2)断开；所述驱动晶体管(DT)、所述第一晶体管(T1)、所述第二晶体管(T2)和所述第三晶体管(T3)打开，所述第四晶体管(T4)关闭，所述第二晶体管(T2)的第二端接入初始化电压(Vi)，所述第一晶体管(T1)的第一端接入所述数据电压；以及
    在所述第二初始阈值电压侦测阶段中，所述第一扫描信号(Scan1)、所述第二扫描信号(Scan2)和所述第三扫描信号(Scan3)提供高电平，所述第四扫描信号(Scan4)提供低电平，所述第一开关(S1)断开，所述第二开关(S2)闭合；所述驱动晶体管(DT)、所述第一晶体管(T1)、所述第二晶体管(T2)和所述第三晶体管(T3)打开，所述第四晶体管(T4)关闭，所述第二晶体管(T2)的第二端连接所述补偿单元的第二端，所述第一晶体管(T1)的第一端接入所述数据电压。
  13. 一种显示装置，其中，所述显示装置包括像素补偿驱动电路，所述像素补偿驱动电路包括：驱动晶体管(DT)、第一晶体管(T1)、第二晶体管(T2)、第三晶体管(T3)、第四晶体管(T4)、存储电容、发光元件、第一开关(S1)、第二开关(S2)和补偿单元；
    所述驱动晶体管(DT)的控制端连接第一节点(G)，所述驱动晶体管(DT)的第一端连接第二节点(S)，所述驱动晶体管(DT)的第二端连接第三节点(Q)；
    所述第一晶体管(T1)的控制端接入第一扫描信号(Scan1)，所述第一晶体管(T1)的第一端连接数据线和所述补偿单元的第一端，所述第一晶体管(T1)的第二端连接第一节点(G)；
    所述第二晶体管(T2)的控制端接入第二扫描信号(Scan2)，所述第二晶体管(T2)的第一端连接第二节点(S)，所述第二晶体管(T2)的第二端连接所述第一开关(S1)的第一端和所述第二开关(S2)的第一端；
    所述第三晶体管(T3)的控制端接入第三扫描信号(Scan3)，所述第三晶体管(T3)的第一端接入电源负电压(VSS)，所述第三晶体管(T3)的第二端连接第二节点(S)；
    所述第四晶体管(T4)的控制端接入第四扫描信号(Scan4)，所述第四晶体管(T4)的第一端连接第三节点(Q)，所述第四晶体管(T4)的第二端接入电源正电压(VDD)；
    所述存储电容的第一端连接第一节点(G)，所述存储电容的第二端连接第二节点(S)；
    所述发光元件的第一端接入电源正电压(VDD)，所述发光元件的第二端连接第三节点(Q)；
    所述第一开关(S1)的第二端接入初始化电压(Vi)；
    所述第二开关(S2)的第二端连接所述补偿单元的第二端；
    所述补偿单元用于侦测并存储所述驱动晶体管(DT)的初始阈值电压，以使所述像素补偿驱动电路根据所述初始阈值电压与所述数据线输出的数据电压叠加得到的叠加数据电压，对所述驱动晶体管(DT)的实际阈值电压进行补偿。
  14. 如权利要求13所述的显示装置，其中，所述像素补偿驱动电路还根据所述叠加数据电压，侦测并存储所述驱动晶体管(DT)的迁移率。
  15. 如权利要求13所述的显示装置，其中，所述驱动晶体管(DT)、所述第一晶体管(T1)、所述第二晶体管(T2)、所述第三晶体管(T3)和所述第四晶体管(T4)为N型薄膜晶体管。
  16. 如权利要求13所述的显示装置，其中，所述驱动晶体管(DT)、所述第一晶体管(T1)、所述第二晶体管(T2)、所述第三晶体管(T3)和所述第四晶体管(T4)为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
  17. 如权利要求13所述的显示装置，其中，所述发光元件为有机发光二极管。
  18. 如权利要求13所述的显示装置，其中，所述发光元件的第一端为阳极端，所述发光元件的第二端为阴极端。
  19. 如权利要求13所述的显示装置，其中，所述第一扫描信号(Scan1)、所述第二扫描信号(Scan2)、所述第三扫描信号(Scan3)和所述第四扫描信号(Scan4)由时序控制器提供。
  20. 如权利要求13所述的显示装置，其中，所述显示装置为有源矩阵有机发光二极管显示装置。
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