Nothing Special   »   [go: up one dir, main page]

WO2021184426A1 - 阵列基板及液晶显示面板 - Google Patents

阵列基板及液晶显示面板 Download PDF

Info

Publication number
WO2021184426A1
WO2021184426A1 PCT/CN2020/082913 CN2020082913W WO2021184426A1 WO 2021184426 A1 WO2021184426 A1 WO 2021184426A1 CN 2020082913 W CN2020082913 W CN 2020082913W WO 2021184426 A1 WO2021184426 A1 WO 2021184426A1
Authority
WO
WIPO (PCT)
Prior art keywords
spacer
thin film
array substrate
film transistor
layer
Prior art date
Application number
PCT/CN2020/082913
Other languages
English (en)
French (fr)
Inventor
张子翔
Original Assignee
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US16/765,171 priority Critical patent/US20210286208A1/en
Publication of WO2021184426A1 publication Critical patent/WO2021184426A1/zh

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present invention relates to the field of display technology, and in particular to an array substrate and a liquid crystal display panel.
  • LCD Liquid Crystal Display
  • the common display devices such as LCD TVs, mobile phones, computer monitors, notebook computers, etc., all have liquid crystal display technology.
  • the structure of a liquid crystal display panel generally includes a backlight module, a thin film transistor array substrate (Thin Film Transistor Array Substrate), a color filter substrate (Color Filter Substrate), and a substrate disposed between the thin film transistor array substrate and the color filter substrate.
  • Liquid crystal layer Crystal Layer A gap spacer is also arranged between the array substrate and the color filter substrate to support the accommodating space of the liquid crystal layer and prevent the array substrate and the color filter substrate from infinitely approaching and squeeze the liquid crystal layer.
  • COA (Color filter On Array) array substrate is to directly fabricate the color resist layer originally set on the color filter substrate on the array substrate. This structure can eliminate the influence of the alignment accuracy of the color resist layer on the display panel, so it is widely used .
  • the gap spacer in order to prevent the gap spacer from affecting the aperture ratio of the COA array substrate, the gap spacer is disposed on the upper layer of the thin film transistor of the array substrate, and is blocked by the black matrix in the liquid crystal display panel. During the entire life cycle of the panel, the gap spacer has been subjected to a large or small squeezing force, and this squeezing force finally acts on the thin film transistor. When the thin film transistor is squeezed by the gap spacer for a long time, the electrical performance will be abnormal, which will eventually cause the display of the liquid crystal display panel to be abnormal.
  • the gap spacer provided on the upper layer of the thin film transistor on the array substrate will exert a pressing force on the thin film transistor, and the thin film transistor will experience abnormal electrical performance when subjected to the pressure of the gap spacer for a long time, and Eventually, the display of the liquid crystal display panel is abnormal.
  • the present application provides an array substrate, which includes:
  • a thin film transistor layer disposed on the base substrate, and the thin film transistor layer includes a plurality of thin film transistors
  • the color resist layer is arranged on the base substrate and covers the thin film transistor layer, the color resist layer is provided with an opening, and the opening and the thin film transistor are staggered in a vertical direction;
  • the first spacer is arranged on the color resist layer, and the first spacer and the thin film transistor are staggered in the vertical direction.
  • the base substrate is a glass substrate or a polyimide substrate.
  • the thin film transistor layer further includes a plurality of scan lines and a plurality of data lines that are electrically connected to the thin film transistor, and the scan lines and the data lines respectively provide the thin film transistors. Scan signal and data signal.
  • the pixel electrode layer includes a plurality of pixel electrodes, and three of the openings are provided between two adjacent pixel electrodes along the extending direction of the data line.
  • the first spacer is arranged between two adjacent pixel electrodes and between two adjacent openings.
  • the pixel electrode layer includes a plurality of pixel electrodes, and two openings are provided between two adjacent pixel electrodes along a direction in which the data line extends.
  • the first spacer is arranged in a blank area between two adjacent pixel electrodes except for the opening and the area where the thin film transistor is located.
  • the first spacer partially covers the opening.
  • the first spacer and the opening are staggered in the vertical direction.
  • the color resist layer includes a plurality of openings, and the first spacer is disposed between two adjacent openings.
  • the outermost layer of the color resist layer is provided with a passivation layer, and the first spacer is provided on the passivation layer.
  • the array substrate further includes a second spacer, the second spacer is disposed on the color resist layer, and the height of the second spacer is smaller than that of the first spacer. The height of the septum.
  • the second spacer is arranged corresponding to the thin film transistor in the vertical direction, or is staggered from the thin film transistor in the vertical direction.
  • the color resist layer includes a red resist, a green resist, and a blue resist, respectively corresponding to the red pixel area, the green pixel area, and the blue pixel area of the array substrate.
  • the first spacer The second spacer is disposed on the blue resistor, and the second spacer is disposed on the red resistor and/or the green resistor.
  • the application also provides a liquid crystal display panel, which includes:
  • An upper substrate disposed opposite to the array substrate, the upper substrate including a black matrix arranged in an array;
  • a liquid crystal layer arranged between the array substrate and the upper substrate.
  • the present application also provides a liquid crystal display panel, including: an array substrate, an upper substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the upper substrate;
  • the array substrate includes: a base substrate; a thin film transistor layer disposed on the base substrate, the thin film transistor layer includes a plurality of thin film transistors; a color resist layer is disposed on the base substrate and covers all In the thin film transistor layer, an opening is provided on the color resist layer, and the opening and the thin film transistor are staggered in the vertical direction; the pixel electrode layer is provided on the color resist layer, and the pixel electrode layer includes multiple A pixel electrode, the pixel electrode is electrically connected to the thin film transistor through the opening; a first spacer is disposed on the color resist layer, the first spacer is connected to the thin film transistor and the The openings are staggered in the vertical direction;
  • the upper substrate includes a black matrix arranged in an array.
  • the array substrate further includes a second spacer disposed on the color resist layer, the height of the second spacer is smaller than the height of the first spacer, The second spacer is arranged corresponding to the thin film transistor in the vertical direction, or is staggered from the thin film transistor in the vertical direction.
  • the first spacer and the second spacer are arranged up and down corresponding to the black matrix.
  • the first spacers and the thin film transistors on the array substrate are staggered in the vertical direction, thereby avoiding the long-term compression of the first spacers.
  • the function of the thin film transistor is abnormal, which is beneficial to maintain the performance stability of the liquid crystal display panel and improve the user experience.
  • FIG. 1 is a schematic diagram of a partial structure of an implementation manner of an array substrate provided by an embodiment of the present application
  • Fig. 2 is a cross-sectional view of the array substrate shown in Fig. 1 taken along the line A-A';
  • FIG. 3 is a schematic diagram of a partial structure of another implementation of an array substrate provided by an embodiment of the present application.
  • FIG. 4 is a cross-sectional view of the array substrate shown in FIG. 3 taken along the line A-A';
  • FIG. 5 is a schematic structural diagram of a liquid crystal display panel provided by an embodiment of the present application.
  • An embodiment of the present application provides an array substrate, the array substrate includes a first spacer for supporting, and the first spacer and the thin film transistor on the array substrate are staggered in the vertical direction,
  • the downward force generated by the first spacers due to supporting the upper substrate of the liquid crystal display panel will not act on the thin film transistor, thereby avoiding
  • the function of the thin film transistor is abnormal due to being squeezed for a long time, which is beneficial to improve the display quality of the liquid crystal display panel.
  • FIG. 1 is a partial structural diagram of an implementation of an array substrate provided by an embodiment of the present application
  • Figure 2 is a section of the array substrate shown in Figure 1 along the line AA' Sectional view.
  • the array substrate 10 provided in the present application includes a base substrate 11, a thin film transistor layer 12, a color resist layer 13 and a pixel electrode layer 14. It should be noted that, in order to clearly show the structure of the array substrate 10, FIG. 1 only shows a partial structural diagram of the array substrate 10. The structural features of the array substrate 10 are periodic and regular.
  • FIG. 2 is for those shown in FIG. 1
  • the array substrate is a schematic cross-sectional structure diagram formed by rotary sectioning, which is intended to show the key structure position characteristics.
  • the base substrate 11 serves as the base layer of the array substrate 10 and plays a role of carrying and supporting various components on the array substrate 10.
  • the base substrate 11 may be a rigid substrate such as a glass substrate, or a flexible substrate such as a polyimide substrate.
  • the thin film transistor layer 12 is disposed on the base substrate 11.
  • a buffer layer is further provided between the base substrate 11 and the thin film transistor layer 12, and the buffer layer It may be a laminated structure of organic layer-inorganic layer-organic layer.
  • the thin film transistor layer 12 includes a plurality of thin film transistors 121, and a scan line 122 and a data line 123 electrically connected to the thin film transistor 121.
  • the thin film transistor 121 includes a gate layer 1211, a gate insulating layer 1212, an active layer 1213, and a source and drain layer 1214.
  • the gate layer 1211 is disposed on the base substrate 11
  • the gate insulating layer 1212 is disposed on the base substrate 11, and covers the gate layer 1211
  • the active layer 1213 It is disposed on the gate insulating layer 1212
  • the source and drain layer 1214 is disposed on the active layer.
  • the scan line 122 and the gate layer 1211 are located in the same layer and electrically connected.
  • the data line 123 and the source-drain layer 1214 are located in the same layer and are connected to the source electrode in the source-drain layer 1214. Electrical connection. It should be understood that the scan line 122 is used to provide a scan signal to the thin film transistor 121 to control the on and off of the source and drain of the thin film transistor 121; the data line 123 is used to provide The transistor 121 provides control signals to control the functions of the array substrate 10.
  • the thin film transistor 121 further includes a first passivation layer 1215 disposed on an outer layer thereof, and the first passivation layer 1215 completely covers the active layer 1213 and the source/drain layer 1214.
  • the first passivation layer 1215 may be made of an inorganic insulating material, such as silicon nitride or the like.
  • the color resist layer 13 is disposed on the base substrate 11 and covers the thin film transistor layer 12.
  • the color resist layer 13 is provided with an opening 133, and the opening 133 and the thin film transistor 121 are staggered in the vertical direction.
  • the vertical direction refers to the thickness direction of the array substrate 10; the arrangement of the opening 133 and the thin film transistor 121 staggered in the treatment direction refers to: the opening 133 is in the substrate.
  • the vertical projection on the base substrate 11 and the vertical projection of the thin film transistor 121 on the base substrate 11 do not overlap with each other or overlap only at the edges.
  • the pixel electrode layer 14 is provided on the color resist layer 13, specifically, the outermost layer of the color resist layer 13 is provided with a second passivation layer 132, and the pixel electrode layer 14 is provided on the second passivation layer.
  • the second passivation layer 132 is made of an inorganic insulating material, such as silicon nitride or the like.
  • the pixel electrode layer 14 includes a plurality of pixel electrodes 141, and the pixel electrodes 141 are electrically connected to the thin film transistor layer 12 through the opening 133.
  • the second passivation layer 132 extends along the opening 133 to the thin film transistor layer 12, and a via hole is formed at a position where it is connected to the source and drain 1214 of the thin film transistor 121,
  • the pixel electrode 141 is electrically connected to the source and drain 1214 through the opening 133 and the via hole, so that the pixel electrode 141 can receive the data signal transmitted by the thin film transistor 121.
  • the array substrate 10 further includes a first spacer 15 disposed on the color resist layer 13, specifically, the first spacer 15 is disposed on the second passivation layer 132.
  • the first spacer 15 and the thin film transistor 121 are staggered in the vertical direction, in other words, along the thickness direction of the array substrate 10, the first spacer 15 is on the base substrate 11
  • the vertical projection area of the thin film transistor 121 does not overlap with the vertical projection area of the thin film transistor 121 on the base substrate 11 or only overlaps at the edge portion.
  • the first spacer 15 is used to support the upper substrate of the liquid crystal display panel, so during the entire life cycle of the liquid crystal display panel Inside, the first spacer 15 has been subjected to a larger or smaller squeezing force, and this squeezing force finally acts on the array substrate 10.
  • the embodiment of the present application uses the first spacer 15
  • the staggered arrangement with the thin film transistor 121 can prevent the thin film transistor 121 from being squeezed, thereby ensuring the performance stability of the thin film transistor 121.
  • the array substrate 10 includes a plurality of pixel electrodes 141, and each pixel electrode 141 corresponds to a pixel area.
  • Three of the openings 133 are arranged between two adjacent pixel electrodes 141 along the extending direction of the data line 123, and the first spacer 15 is arranged between the two adjacent pixel electrodes 141, And arranged between two adjacent openings 133, the first spacer 15 and the opening 133 are staggered in the vertical direction, that is, the first spacer 15 and the opening 133 are arranged in a vertical direction.
  • the vertical projections on the base substrate 11 do not overlap.
  • the first spacer 15 partially covers at least one of the openings 133, that is, the vertical projection of the first spacer 15 and the at least one opening 133 on the base substrate 11 Partially coincide. It should be understood that the above position setting of the first spacer 15 can ensure that when the array substrate 10 is used in a display panel, the first spacer 15 is covered by the black matrix on the upper substrate, and at the same time Prevent the first spacer 15 from squeezing the thin film transistor 121.
  • the array substrate 10 further includes a second spacer 16 disposed on the color resist layer 13, and the height of the second spacer 16 is smaller than the height of the first spacer 15.
  • the second spacer 16 may be arranged corresponding to the thin film transistor 121 in the vertical direction, or may be staggered from the thin film transistor 121 in the vertical direction. It should be understood that the second spacer 16 plays a role of auxiliary support. When the array substrate 10 is applied to a liquid crystal display panel, only when the liquid crystal display panel is subjected to a relatively large squeezing effect, the Only the second spacer 16 plays a supporting role.
  • the color resist layer 13 includes a plurality of color resists 131, and each of the color resists 131 corresponds to a pixel area.
  • the color resistors 131 can be divided into blue resistors 131a, red resistors 131b and green resistors (not shown in the figure), respectively corresponding to the red pixel area, the green pixel area and the blue pixel area of the array substrate 10.
  • the first spacer 15 is disposed on the upper layer of the blue barrier 131a
  • the second spacer 16 is disposed on the upper layer of the red barrier 131b and/or the green barrier.
  • FIGS. 3 and 4 are schematic diagrams of another embodiment of the array substrate 10 provided by the embodiment of the present application.
  • the difference from the embodiment of the array substrate 10 shown in FIGS. 1 and 2 lies in the following aspects:
  • Two openings 133 are provided between two adjacent pixel electrodes 141 in the direction in which the line 123 extends, and the first spacer 15 is provided except for the area where the opening 133 and the thin film transistor 121 are located.
  • the blank area between the two adjacent pixel electrodes 141, and the first spacer 15 is staggered from the opening 133 and the thin film transistor 121 in the vertical direction.
  • the first spacer 15 may partially cover the opening 133.
  • the above position setting of the first spacer 15 can ensure that when the array substrate 10 is used in a display panel, the first spacer 15 is covered by the black matrix on the upper substrate, and at the same time Prevent the first spacer 15 from squeezing the thin film transistor 121.
  • the array substrate provided by the embodiment of the present application includes a first spacer for supporting, and the first spacer and the thin film transistor on the array substrate are staggered in the vertical direction.
  • the downward force generated by the first spacer will not act on the thin film transistor, thereby preventing the thin film transistor from being squeezed for a long time.
  • Abnormal functions help to improve the display quality of the liquid crystal display panel.
  • the embodiment of the present application also provides a liquid crystal display panel. As shown in FIG.
  • the upper substrate 30 is provided with a black matrix 31 arranged in an array, the first spacer 15 and the second spacer 16 are arranged up and down corresponding to the black matrix 31, and the first spacer The object 15 and the second spacer 16 are used to support the upper substrate 30.
  • the black matrix 31 is used to cover the opaque metal coverage area on the array substrate 10, especially the area between two adjacent pixel electrodes 141 ( 1), including the thin film transistor 121, the data line 123 and the scan line 122 located between the pixel electrode 141 region, so the first spacer 15 and the second spacer 16 are also The black matrix 31 covers.
  • the first spacer and the thin film transistor on the array substrate are staggered in the vertical direction, thereby avoiding the first spacer.
  • the long-term squeezing of the thin film transistor causes its function to be abnormal, which is beneficial to maintaining the performance stability of the liquid crystal display panel and improving the user experience.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)

Abstract

一种阵列基板（10）及液晶显示面板，液晶显示面板包括阵列基板（10）。阵列基板（10）包括衬底基板（11）、设置于衬底基板（11）上的薄膜晶体管层（12）和色阻层（13）、设置于色阻层（13）上的像素电极层（14）和第一隔垫物（13），其中，第一隔垫物（13）与薄膜晶体管层（12）上的薄膜晶体管（12）在竖直方向上错开设置。

Description

阵列基板及液晶显示面板   技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及液晶显示面板。
 背景技术
液晶显示器（Liquid Crystal Display, LCD）具有机身薄、省电、无辐射等众多优点，在显示装备领域得到广泛应用。目前常见的显示设备中，如液晶电视、移动电话、计算机显示器、笔记本电脑等，均存在液晶显示技术的身影。
液晶显示面板的结构一般包括背光模组（Backlight module）、薄膜晶体管阵列基板（Thin Film Transistor Array Substrate）、彩膜基板（Color Filter Substrate）、以及设置于薄膜晶体管阵列基板和彩膜基板之间的液晶层（Liquid Crystal Layer）。在阵列基板和彩膜基板之间还设置有间隙隔垫物，用于支撑起液晶层的容置空间，防止阵列基板和彩膜基板无限接近而挤压液晶层。COA（Color filter On Array）阵列基板是将原设置于彩膜基板上的色阻层直接制作在阵列基板上，这种结构可以消除色阻层对位精度对显示面板的影响，因此得到广泛应用。在现有技术中，为了避免间隙隔垫物对COA阵列基板开口率产生影响，会将间隙隔垫物设置于阵列基板的薄膜晶体管上层，并被液晶显示面板中的黑色矩阵遮挡，而在显示面板的整个寿命周期中，间隙隔垫物一直受到或大或小的挤压力作用，这种挤压力最终作用在薄膜晶体管上。薄膜晶体管长期受到间隙隔垫物的挤压作用会出现电性能异常的现象，并最终导致液晶显示面板的显示异常。
 技术问题
在现有技术中，设置于阵列基板的薄膜晶体管上层的间隙隔垫物会对薄膜晶体管产生挤压力作用，薄膜晶体管长期受到间隙隔垫物的挤压作用会出现电性能异常的现象，并最终导致液晶显示面板的显示异常。
 技术解决方案
为了解决上述技术问题，本申请提供的解决方案如下：
本申请提供一种阵列基板，其包括：
衬底基板；
薄膜晶体管层，设置于所述衬底基板上，所述薄膜晶体管层包括多个薄膜晶体管；
色阻层，设置于所述衬底基板上，并覆盖所述薄膜晶体管层，所述色阻层上设置开口，所述开口与所述薄膜晶体管在竖直方向上错开设置；
像素电极层，设置于所述色阻层上，所述像素电极层通过所述开口与所述薄膜晶体管电性连接；以及
第一隔垫物，设置于所述色阻层上，所述第一隔垫物与所述薄膜晶体管在竖直方向上错开设置。
在本申请的阵列基板中，所述衬底基板为玻璃基板或聚酰亚胺基板。
在本申请的阵列基板中，所述薄膜晶体管层还包括与所述薄膜晶体管电性连接的多条扫描线和多条数据线，所述扫描线和所述数据线分别为所述薄膜晶体管提供扫描信号和数据信号。
在本申请的阵列基板中，所述像素电极层包括多个像素电极，沿所述数据线延伸方向相邻的两个所述像素电极之间设置三个所述开口。
在本申请的阵列基板中，所述第一隔垫物设置于相邻两个所述像素电极之间，并设置于相邻两个所述开口之间。
在本申请的阵列基板中，所述像素电极层包括多个像素电极，沿所述数据线延伸的方向相邻的两个所述像素电极之间设置两个所述开口。
在本申请的阵列基板中，所述第一隔垫物设置于除所述开口和所述薄膜晶体管所在区域之外的相邻两个所述像素电极之间的空白区域。
在本申请的阵列基板中，所述第一隔垫物部分覆盖所述开口。
在本申请的阵列基板中，所述第一隔垫物与所述开口在竖直方向上错开设置。
在本申请的阵列基板中，所述色阻层包括多个开口，所述第一隔垫物设置于相邻两个所述开口之间。
在本申请的阵列基板中，所述色阻层的最外层设置有钝化层，所述第一隔垫物设置于所述钝化层上。
在本申请的阵列基板中，所述阵列基板还包括第二隔垫物，所述第二隔垫物设置于所述色阻层上，所述第二隔垫物的高度小于所述第一隔垫物的高度。
在本申请的阵列基板中，所述第二隔垫物与所述薄膜晶体管沿竖直方向对应设置，或与所述薄膜晶体管沿竖直方向错开设置。
在本申请的阵列基板中，所述色阻层包括红色阻、绿色阻和蓝色阻，分别对应所述阵列基板的红像素区、绿像素区和蓝像素区，所述第一隔垫物设置于所述蓝色阻上，所述第二隔垫物设置于所述红色阻和/或所述绿色阻上。
本申请还提供一种液晶显示面板，其包括：
如上所述的阵列基板；
与所述阵列基板相对设置的上基板，所述上基板包括阵列排布的黑色矩阵；以及
设置于所述阵列基板与所述上基板之间的液晶层。
本申请还提供一种液晶显示面板，包括：阵列基板、与所述阵列基板相对设置的上基板、以及设置于所述阵列基板与所述上基板之间的液晶层；
所述阵列基板包括：衬底基板；薄膜晶体管层，设置于所述衬底基板上，所述薄膜晶体管层包括多个薄膜晶体管；色阻层，设置于所述衬底基板上，并覆盖所述薄膜晶体管层，所述色阻层上设置开口，所述开口与所述薄膜晶体管在竖直方向上错开设置；像素电极层，设置于所述色阻层上，所述像素电极层包括多个像素电极，所述像素电极通过所述开口与所述薄膜晶体管电性连接；第一隔垫物，设置于所述色阻层上，所述第一隔垫物与所述薄膜晶体管及所述开口在竖直方向上错开设置；
所述上基板包括阵列排布的黑色矩阵。
在本申请的液晶显示面板中，所述阵列基板还包括设置于所述色阻层上的第二隔垫物，所述第二隔垫物的高度小于所述第一隔垫物的高度，所述第二隔垫物与所述薄膜晶体管沿竖直方向对应设置，或与所述薄膜晶体管沿竖直方向错开设置。
在本申请的液晶显示面板中，所述第一隔垫物及所述第二隔垫物与所述黑色矩阵上下对应设置。
 有益效果
本申请提供的阵列基板及液晶显示面板，通过将所述第一隔垫物与所述阵列基板上的薄膜晶体管在竖直方向上错开设置，避免了所述第一隔垫物长期挤压所述薄膜晶体管而导致其功能异常，有利于维持所述液晶显示面板的性能稳定性，提升用户使用体验。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的阵列基板的一种实施方式的局部结构示意图；
图2是图1所示的阵列基板沿A-A’线剖切的截面图；
图3是本申请实施例提供的阵列基板的另一种实施方式的局部结构示意图；
图4是图3所示的阵列基板沿A-A’线剖切的截面图；
图5是本申请实施例提供的液晶显示面板的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请实施例提供了一种阵列基板，所述阵列基板包括起支撑作用的第一隔垫物，所述第一隔垫物与所述阵列基板上的薄膜晶体管在竖直方向上错开设置，当所述阵列基板应用于液晶显示面板中时，所述第一隔垫物因支撑所述液晶显示面板的上基板而产生的向下的作用力不会作用于所述薄膜晶体管上，从而避免了所述薄膜晶体管因长期受挤压而导致其功能异常，有利于提高所述液晶显示面板的显示质量。
如图1和图2所示，其中图1是本申请实施例提供的阵列基板的一种实施方式的局部结构示意图，图2是图1所示的阵列基板沿A-A’线剖切的截面图。本申请提供的阵列基板10包括衬底基板11、薄膜晶体管层12、色阻层13以及像素电极层14。需要说明的是，为了清楚显示所述阵列基板10的结构，图1仅示出了该阵列基板10的局部结构示意图，所述阵列基板10的结构特征具有周期性和规律性，本领域技术人员可以根据本申请实施例的示图及文字描述很容易得出所述阵列基板10的完整结构特征；另外，为了清楚说明本实施例中的关键结构的特征，图2是针对图1所示的阵列基板采用旋转剖切形成的截面结构示意图，旨在示出关键结构位置特征。
所述衬底基板11作为所述阵列基板10的基底层，起到承载和支撑所述阵列基板10上的各个组成元件的作用。可选地，所述衬底基板11可以是玻璃基板等硬质基板，或聚酰亚胺基板等柔性基板。
所述薄膜晶体管层12设置于所述衬底基板11上。可选地，为了优化所述衬底基板11与所述薄膜晶体管层12之间的结合关系，所述衬底基板11与所述薄膜晶体管层12之间还设置有缓冲层，所述缓冲层可以是有机层-无机层-有机层的叠层结构。
所述薄膜晶体管层12包括多个薄膜晶体管121，以及与所述薄膜晶体管121电性连接的扫描线122和数据线123。具体地，所述薄膜晶体管121包括栅极层1211、栅极绝缘层1212、有源层1213以及源漏极层1214。其中，所述栅极层1211设置于所述衬底基板11上，所述栅极绝缘层1212设置于所述衬底基板11上，并覆盖所述栅极层1211，所述有源层1213设置于所述栅极绝缘层1212上，所述源漏极层1214设置于所述有源层上。所述扫描线122与所述栅极层1211位于同一层并电性连接，所述数据线123与所述源漏极层1214位于同一层，并与所述源漏极层1214中的源极电性连接。应当理解的是，所述扫描线122用于向所述薄膜晶体管121提供扫描信号以控制所述薄膜晶体管121中的源极和漏极的通断；所述数据线123用于向所述薄膜晶体管121提供控制信号，以控制所述阵列基板10的功能。
可选地，所述薄膜晶体管121还包括设置于其外层的第一钝化层1215，所述第一钝化层1215完全覆盖所述有源层1213和所述源漏极层1214。所述第一钝化层1215可以由无机绝缘材料制作而成，例如可以是氮化硅等。
所述色阻层13设置于所述衬底基板11上，并覆盖所述薄膜晶体管层12。所述色阻层13上设有开口133，所述开口133与所述薄膜晶体管121在竖直方向上错开设置。需要说明的是，所述竖直方向是指所述阵列基板10的厚度方向；所述开口133与所述薄膜晶体管121在所述处置方向上错开设置是指：所述开口133在所述衬底基板11上的垂直投影，与所述薄膜晶体管121在所述衬底基板11上的垂直投影彼此不重合或仅边缘部分重合。
所述像素电极层14设置于所述色阻层13上，具体地，所述色阻层13的最外层设置有第二钝化层132，所述像素电极层14设置于所述第二钝化层132上。可选地，所述第二钝化层132由无机绝缘材料制作而成，例如可以是氮化硅等。
所述像素电极层14包括多个像素电极141，所述像素电极141通过所述开口133与所述薄膜晶体管层12电性连接。具体地，所述第二钝化层132沿所述开口133延伸至所述薄膜晶体管层12上，并在与所述薄膜晶体管121的所述源漏极1214相接处的位置形成过孔，所述像素电极141通过所述开口133和所述过孔与所述源漏极1214电性连接，从而使所述像素电极141可以接收由所述薄膜晶体管121传递的数据信号。
所述阵列基板10还包括设置于所述色阻层13上的第一隔垫物15，具体地，所述第一隔垫物15设置于所述第二钝化层132上。所述第一隔垫物15与所述薄膜晶体管121在竖直方向上错开设置，换言之，沿所述阵列基板10的厚度方向，所述第一隔垫物15在所述衬底基板11上的垂直投影区，与所述薄膜晶体管121在所述衬底基板11上的垂直投影区不重合或仅在边缘部分重合。应当理解的是，在将所述阵列基板10应用于液晶显示面板中时，所述第一隔垫物15用于支撑所述液晶显示面板的上基板，因此在该液晶显示面板的整个寿命周期内，所述第一隔垫物15一直承受或大或小的挤压力，这种挤压力最终作用在所述阵列基板10上，本申请实施例通过将所述第一隔垫物15与所述薄膜晶体管121错开设置，可以使所述薄膜晶体管121免受挤压，从而保证了所述薄膜晶体管121的性能稳定性。
所述阵列基板10包括多个像素电极141，每一个所述像素电极141对应一个像素区。沿所述数据线123延伸方向相邻的两个所述像素电极141之间设置三个所述开口133，所述第一隔垫物15设置于所述相邻两个像素电极141之间，并设置于相邻两个所述开口133之间，所述第一隔垫物15与所述开口133在竖直方向上错开设置，即所述第一隔垫物15与所述开口133在所述衬底基板11上的垂直投影不重合。另外，可选地，所述第一隔垫物15部分覆盖至少一个所述开口133，即所述第一隔垫物15与至少一个所述开口133在所述衬底基板11上的垂直投影部分重合。应当理解的是，所述第一隔垫物15的上述位置设置可以保证所述阵列基板10应用于显示面板中时，所述第一隔垫物15被位于上基板上的黑色矩阵遮盖，同时避免所述第一隔垫物15挤压所述薄膜晶体管121。
可选地，所述阵列基板10还包括设置于所述色阻层13上的第二隔垫物16，所述第二隔垫物16的高度小于所述第一隔垫物15的高度。所述第二隔垫物16可以与所述薄膜晶体管121沿竖直方向对应设置，或与所述薄膜晶体管121沿竖直方向错开设置。应当理解的是，所述第二隔垫物16起辅助支撑作用，当所述阵列基板10应用于液晶显示面板中时，只有当所述液晶显示面板受到较大的挤压作用时，所述第二隔垫物16才发挥支撑作用。
可选地，所述色阻层13包括多个色阻131，每一个所述色阻131对应一个像素区。所述色阻131可以分为蓝色阻131a、红色阻131b以及绿色阻（图中未示出），分别对应所述阵列基板10的红像素区、绿像素区和蓝像素区。所述第一隔垫物15设置于所述蓝色阻131a的上层，所述第二隔垫物16设置于所述红色阻131b和/或所述绿色阻的上层。
图3和图4是本申请实施例提供的阵列基板10的另一种实施方式示意图，与图1和图2所示的阵列基板10的实施方式的不同之处在于以下方面：沿所述数据线123延伸的方向相邻的两个所述像素电极141之间设置两个所述开口133，所述第一隔垫物15设置于除所述开口133和所述薄膜晶体管121所在区域之外的所述相邻两个像素电极141之间的空白区域，并且所述第一隔垫物15与所述开口133和所述薄膜晶体管121在竖直方向上均错开设置，可选地，所述第一隔垫物15可以部分覆盖所述开口133。应当理解的是，所述第一隔垫物15的上述位置设置可以保证所述阵列基板10应用于显示面板中时，所述第一隔垫物15被位于上基板上的黑色矩阵遮盖，同时避免所述第一隔垫物15挤压所述薄膜晶体管121。
综上所述，本申请实施例提供的阵列基板包括起支撑作用的第一隔垫物，所述第一隔垫物与所述阵列基板上的薄膜晶体管在竖直方向上错开设置，当所述阵列基板应用于液晶显示面板中时，所述第一隔垫物产生的向下的作用力不会作用于所述薄膜晶体管上，从而避免了所述薄膜晶体管因长期受挤压而导致其功能异常，有利于提高所述液晶显示面板的显示质量。
本申请实施例还提供了一种液晶显示面板，如图5所示，所述液晶显示面板包括上述实施例提供的阵列基板10，以及与所述阵列基板10相对设置的上基板30、设置于所述阵列基板10与所述上基板30之间的液晶层20。其中所述上基板30上设置有阵列排布的黑色矩阵31，所述第一隔垫物15和所述第二隔垫物16与所述黑色矩阵31上下对应设置，所述第一隔垫物15和所述第二隔垫物16用于支撑所述上基板30。应当理解的是，在所述液晶显示面板中，所述黑色矩阵31用于遮盖所述阵列基板10上的不透明的金属覆盖区，尤其是相邻两个所述像素电极141之间的区域（参考图1所示），包括位于所述像素电极141区域之间的薄膜晶体管121、数据线123和扫描线122，因此所述第一隔垫物15和所述第二隔垫物16同样被所述黑色矩阵31遮盖。
综上所述，本申请实施例提供的液晶显示面板，通过将所述第一隔垫物与所述阵列基板上的薄膜晶体管在竖直方向上错开设置，避免了所述第一隔垫物长期挤压所述薄膜晶体管而导致其功能异常，有利于维持所述液晶显示面板的性能稳定性，提升用户体验。
需要说明的是，虽然本发明以具体实施例揭露如上，但上述实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种阵列基板，其包括：
    衬底基板；
    薄膜晶体管层，设置于所述衬底基板上，所述薄膜晶体管层包括多个薄膜晶体管；
    色阻层，设置于所述衬底基板上，并覆盖所述薄膜晶体管层，所述色阻层上设置开口，所述开口与所述薄膜晶体管在竖直方向上错开设置；
    像素电极层，设置于所述色阻层上，所述像素电极层通过所述开口与所述薄膜晶体管电性连接；以及
    第一隔垫物，设置于所述色阻层上，所述第一隔垫物与所述薄膜晶体管在竖直方向上错开设置。
  2. 根据权利要求1所述的阵列基板，其中，所述衬底基板为玻璃基板或聚酰亚胺基板。
  3. 根据权利要求1所述的阵列基板，其中，所述薄膜晶体管层还包括与所述薄膜晶体管电性连接的多条扫描线和多条数据线，所述扫描线和所述数据线分别为所述薄膜晶体管提供扫描信号和数据信号。
  4. 根据权利要求3所述的阵列基板，其中，所述像素电极层包括多个像素电极，沿所述数据线延伸方向相邻的两个所述像素电极之间设置三个所述开口。
  5. 根据权利要求4所述的阵列基板，其中，所述第一隔垫物设置于相邻两个所述像素电极之间，并设置于相邻两个所述开口之间。
  6. 根据权利要求3所述的阵列基板，其中，所述像素电极层包括多个像素电极，沿所述数据线延伸的方向相邻的两个所述像素电极之间设置两个所述开口。
  7. 根据权利要求6所述的阵列基板，其中，所述第一隔垫物设置于除所述开口和所述薄膜晶体管所在区域之外的相邻两个所述像素电极之间的空白区域。
  8. 根据权利要求1所述的阵列基板，其中，所述第一隔垫物部分覆盖所述开口。
  9. 根据权利要求1所述的阵列基板，其中，所述第一隔垫物与所述开口在竖直方向上错开设置。
  10. 根据权利要求9所述的阵列基板，其中，所述色阻层包括多个开口，所述第一隔垫物设置于相邻两个所述开口之间。
  11. 根据权利要求1所述的阵列基板，其中，所述色阻层的最外层设置有钝化层，所述第一隔垫物设置于所述钝化层上。
  12. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括第二隔垫物，所述第二隔垫物设置于所述色阻层上，所述第二隔垫物的高度小于所述第一隔垫物的高度。
  13. 根据权利要求12所述的阵列基板，其中，所述第二隔垫物与所述薄膜晶体管沿竖直方向对应设置，或与所述薄膜晶体管沿竖直方向错开设置。
  14. 根据权利要求12所述的阵列基板，其中，所述色阻层包括红色阻、绿色阻和蓝色阻，分别对应所述阵列基板的红像素区、绿像素区和蓝像素区，所述第一隔垫物设置于所述蓝色阻上，所述第二隔垫物设置于所述红色阻和/或所述绿色阻上。
  15. 一种液晶显示面板，其包括：
    权利要求1所述的阵列基板；
    与所述阵列基板相对设置的上基板，所述上基板包括阵列排布的黑色矩阵；以及
    设置于所述阵列基板与所述上基板之间的液晶层。
  16. 一种液晶显示面板，包括：阵列基板、与所述阵列基板相对设置的上基板、以及设置于所述阵列基板与所述上基板之间的液晶层；
    所述阵列基板包括：衬底基板；薄膜晶体管层，设置于所述衬底基板上，所述薄膜晶体管层包括多个薄膜晶体管；色阻层，设置于所述衬底基板上，并覆盖所述薄膜晶体管层，所述色阻层上设置开口，所述开口与所述薄膜晶体管在竖直方向上错开设置；像素电极层，设置于所述色阻层上，所述像素电极层包括多个像素电极，所述像素电极通过所述开口与所述薄膜晶体管电性连接；第一隔垫物，设置于所述色阻层上，所述第一隔垫物与所述薄膜晶体管及所述开口在竖直方向上错开设置；
    所述上基板包括阵列排布的黑色矩阵。
  17. 根据权利要求16所述的液晶显示面板，其中，所述阵列基板还包括设置于所述色阻层上的第二隔垫物，所述第二隔垫物的高度小于所述第一隔垫物的高度，所述第二隔垫物与所述薄膜晶体管沿竖直方向对应设置，或与所述薄膜晶体管沿竖直方向错开设置。
  18. 根据权利要求17所述的液晶显示面板，其中，所述第一隔垫物及所述第二隔垫物与所述黑色矩阵上下对应设置。
PCT/CN2020/082913 2020-03-16 2020-04-02 阵列基板及液晶显示面板 WO2021184426A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/765,171 US20210286208A1 (en) 2020-03-16 2020-04-02 Array substrate and liquid crystal display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010179661.0A CN111208677A (zh) 2020-03-16 2020-03-16 阵列基板及液晶显示面板
CN202010179661.0 2020-03-16

Publications (1)

Publication Number Publication Date
WO2021184426A1 true WO2021184426A1 (zh) 2021-09-23

Family

ID=70789968

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/082913 WO2021184426A1 (zh) 2020-03-16 2020-04-02 阵列基板及液晶显示面板

Country Status (2)

Country Link
CN (1) CN111208677A (zh)
WO (1) WO2021184426A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114967212A (zh) * 2022-05-24 2022-08-30 苏州华星光电技术有限公司 彩膜基板及液晶显示面板
CN115268155A (zh) * 2022-06-01 2022-11-01 京东方科技集团股份有限公司 显示基板及其制备方法、显示面板及显示装置

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112068370B (zh) * 2020-09-09 2021-10-08 深圳市华星光电半导体显示技术有限公司 阵列基板及其制造方法
CN113064304B (zh) * 2021-03-29 2022-09-20 京东方科技集团股份有限公司 液晶显示面板及其制作方法、液晶显示装置
CN113253520B (zh) * 2021-04-30 2023-01-24 滁州惠科光电科技有限公司 一种显示面板及显示设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105372881A (zh) * 2015-12-01 2016-03-02 武汉华星光电技术有限公司 液晶显示面板
CN106094361A (zh) * 2016-08-22 2016-11-09 深圳市华星光电技术有限公司 液晶显示面板
CN205750219U (zh) * 2016-06-21 2016-11-30 厦门天马微电子有限公司 一种液晶显示装置
CN107229152A (zh) * 2017-07-04 2017-10-03 深圳市华星光电技术有限公司 液晶显示面板的制作方法及液晶显示面板
CN107526224A (zh) * 2016-06-16 2017-12-29 三星显示有限公司 显示装置
US20190204649A1 (en) * 2015-08-11 2019-07-04 Samsung Display Co., Ltd. Liquid crystal display and method for manufacturing the same

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05232479A (ja) * 1992-02-21 1993-09-10 Sanyo Electric Co Ltd 液晶表示装置
CN1262874C (zh) * 2002-09-16 2006-07-05 Nec液晶技术株式会社 有源寻址液晶显示器及其制造方法
KR100895306B1 (ko) * 2002-11-14 2009-05-07 삼성전자주식회사 액정 표시 장치용 기판
KR100682358B1 (ko) * 2003-11-10 2007-02-15 엘지.필립스 엘시디 주식회사 액정 표시 패널 및 제조 방법
KR20080050851A (ko) * 2006-12-04 2008-06-10 삼성전자주식회사 액정표시패널
KR20100025806A (ko) * 2008-08-28 2010-03-10 엘지디스플레이 주식회사 발광 표시 패널 및 그의 제조 방법
CN101762916B (zh) * 2008-12-25 2011-07-20 北京京东方光电科技有限公司 阵列基板和液晶面板及其制造方法
CN102566145B (zh) * 2010-12-07 2015-05-20 北京京东方光电科技有限公司 液晶面板及液晶面板、阵列基板和彩膜基板的制造方法
CN103744230A (zh) * 2013-12-31 2014-04-23 南京中电熊猫液晶显示科技有限公司 一种液晶显示面板及其制作方法
CN109870855A (zh) * 2019-04-09 2019-06-11 京东方科技集团股份有限公司 一种阵列基板、液晶显示面板及液晶显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190204649A1 (en) * 2015-08-11 2019-07-04 Samsung Display Co., Ltd. Liquid crystal display and method for manufacturing the same
CN105372881A (zh) * 2015-12-01 2016-03-02 武汉华星光电技术有限公司 液晶显示面板
CN107526224A (zh) * 2016-06-16 2017-12-29 三星显示有限公司 显示装置
CN205750219U (zh) * 2016-06-21 2016-11-30 厦门天马微电子有限公司 一种液晶显示装置
CN106094361A (zh) * 2016-08-22 2016-11-09 深圳市华星光电技术有限公司 液晶显示面板
CN107229152A (zh) * 2017-07-04 2017-10-03 深圳市华星光电技术有限公司 液晶显示面板的制作方法及液晶显示面板

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114967212A (zh) * 2022-05-24 2022-08-30 苏州华星光电技术有限公司 彩膜基板及液晶显示面板
CN114967212B (zh) * 2022-05-24 2024-03-19 苏州华星光电技术有限公司 彩膜基板及液晶显示面板
CN115268155A (zh) * 2022-06-01 2022-11-01 京东方科技集团股份有限公司 显示基板及其制备方法、显示面板及显示装置
CN115268155B (zh) * 2022-06-01 2023-10-27 京东方科技集团股份有限公司 显示基板及其制备方法、显示面板及显示装置

Also Published As

Publication number Publication date
CN111208677A (zh) 2020-05-29

Similar Documents

Publication Publication Date Title
WO2021184426A1 (zh) 阵列基板及液晶显示面板
US11694646B2 (en) Display panel having opening in first electrode and display device thereof
US11199750B2 (en) Display panel having black matrix comprising extension portions
WO2018196233A1 (zh) 液晶显示面板及其液晶显示装置
US20080291376A1 (en) Liquid crystal panel having low-resistance common electrode layer
JP2018527623A (ja) Ｖａ型ｃｏａ液晶表示パネル
WO2021184506A1 (zh) 液晶显示面板
EP3567422B1 (en) Array substrate and display device
US8194225B2 (en) Array substrate for LCD device
US20170139247A1 (en) Thin Film Transistor Array Substrate, Manufacturing for the Same, and Liquid Crystal Display Panel Having the Same
WO2019095459A1 (zh) 阵列基板、液晶显示面板及液晶显示设备
WO2020073415A1 (zh) 显示面板的制程和显示面板
WO2018195893A1 (zh) 液晶显示面板及其制造方法与应用的显示装置
WO2020107723A1 (zh) 一种阵列基板及显示面板
WO2021103159A1 (zh) 一种显示面板及显示装置
WO2020228168A1 (zh) 阵列基板及其制作方法
WO2017031815A1 (zh) Coa型液晶显示面板
JP3208909B2 (ja) 液晶表示装置
WO2022236798A1 (zh) 显示基板、显示面板及显示装置
WO2019051971A1 (zh) 阵列基板及显示面板
US11977301B2 (en) Liquid crystal display panel and electronic paper
WO2019100423A1 (zh) 一种液晶显示面板以及液晶显示装置
JP2004004526A (ja) 液晶表示装置
JP2023524181A (ja) ディスプレイパネル及び表示装置
KR101480841B1 (ko) 액정표시장치

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20925993

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20925993

Country of ref document: EP

Kind code of ref document: A1