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WO2021093687A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2021093687A1
WO2021093687A1 PCT/CN2020/127235 CN2020127235W WO2021093687A1 WO 2021093687 A1 WO2021093687 A1 WO 2021093687A1 CN 2020127235 W CN2020127235 W CN 2020127235W WO 2021093687 A1 WO2021093687 A1 WO 2021093687A1
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WIPO (PCT)
Prior art keywords
electrode
gate
drain
sub
transistor
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PCT/CN2020/127235
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English (en)
French (fr)
Inventor
袁粲
李永谦
袁志东
李蒙
程雪连
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Priority to US17/614,301 priority Critical patent/US20220262886A1/en
Publication of WO2021093687A1 publication Critical patent/WO2021093687A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/828—Transparent cathodes, e.g. comprising thin metal layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a preparation method thereof, and a display device.
  • Self-luminous display substrates such as Organic Light-Emitting Diode (OLED) display substrates have the advantages of self-luminescence, lightness and thinness, low power consumption, good color reproduction, responsiveness, and wide viewing angle, and have been more and more widely used. It has become one of the mainstreams in the current market in display devices such as mobile phones, notebook computers, and televisions.
  • OLED Organic Light-Emitting Diode
  • inventions of the present disclosure provide a display substrate.
  • the display substrate includes a substrate, and a pixel driving circuit and a bottom emission type light emitting device arranged in a display area on the substrate and located in each sub-pixel.
  • the light emitting device includes a first electrode electrically connected to the pixel driving circuit.
  • the pixel driving circuit includes a first storage capacitor, and the first storage capacitor includes a first storage electrode and a second storage electrode that are arranged oppositely.
  • the first electrode is multiplexed as the first storage electrode. Both the second storage electrode and the first electrode are transparent electrodes.
  • the display substrate further includes a power cord.
  • the pixel driving circuit further includes a first transistor.
  • the first transistor includes a first gate, a first semiconductor active pattern, a first source, and a first drain.
  • the first transistor is a driving transistor.
  • the first source electrode is electrically connected to the power line, and the first drain electrode is electrically connected to the first electrode.
  • the first semiconductor active pattern includes a first channel region, a first source region, and a first drain region, and the conductivity of the first source region and the first drain region is greater than that of the first drain region.
  • the conductivity of the channel region, and the first source is in contact with the first source region, and the first drain is in contact with the first drain region.
  • the second storage electrode is a semiconductor pattern that has undergone a conductive treatment, wherein the second storage electrode is the same layer and the same material as the first source region and the first drain region.
  • the display substrate further includes: gate lines and data lines.
  • the pixel driving circuit further includes a second transistor including a second gate, a second semiconductor active pattern, a second source, and a second drain. A part of the gate line is multiplexed as the second gate.
  • the second source electrode is electrically connected to the data line.
  • the second drain is electrically connected to the second storage electrode and the first gate.
  • the display substrate further includes: a first connection electrode.
  • the first connection electrode and the second drain are an integral structure, and the first connection electrode is electrically connected to the second storage electrode and the first gate through a first via hole, respectively.
  • the second drain and the first gate are spaced in a first direction.
  • the first gate extends in the second direction.
  • the first direction and the second direction are perpendicular or substantially perpendicular.
  • the first connection electrode extends along the first direction.
  • the size in the second direction of the portion of the first connection electrode that is electrically connected to the second drain is smaller than the portion of the first connection electrode that is electrically connected to the first gate. The size in the second direction.
  • the second semiconductor active pattern includes a second channel region, a second source region, and a second drain region.
  • the second source is in contact with the second source region
  • the second drain is in contact with the second drain region.
  • the second storage electrode and the second drain region have an integral structure.
  • the second storage electrode and the first gate are electrically connected through a second via hole.
  • the second drain and the first gate are spaced in a first direction.
  • the first gate extends in the second direction.
  • the first direction and the second direction are perpendicular or substantially perpendicular.
  • the second storage electrode includes an extension portion extending along the first direction and electrically connected to the second drain region. The size in the second direction of the portion of the extension portion that is electrically connected to the second drain region is smaller than the size in the second direction of the portion of the extension portion that is electrically connected to the first gate. size.
  • the pixel driving circuit when the pixel driving circuit includes a second transistor, the pixel driving circuit further includes a third transistor.
  • the third transistor includes a third gate, a third semiconductor active pattern, a third source, and a third drain.
  • the first transistor and the third transistor are located on both sides of the first storage capacitor along the first direction.
  • the display substrate further includes a second connection electrode and a sensing signal line.
  • the third source electrode is electrically connected to the first drain electrode through the second connecting electrode, and the third source electrode, the second connecting electrode and the first drain electrode are an integral structure.
  • the third drain is electrically connected to the sensing signal line.
  • the second connection electrode is electrically connected to the first electrode through a third via hole.
  • the third gate of the third transistor located in any row of sub-pixels is multiplexed by a portion of the gate line corresponding to the adjacent row of sub-pixels closest to the third transistor constitute.
  • the first transistor is a top-gate thin film transistor.
  • the display substrate further includes: a first metal pattern disposed on a side of the first semiconductor active pattern close to the substrate. Along the thickness direction of the substrate, the orthographic projection of the first semiconductor active pattern on the substrate is located within the orthographic projection of the first metal pattern on the substrate.
  • the display substrate further includes a second metal pattern. Along the thickness direction of the substrate, the second metal pattern and the orthographic projection of the second connection electrode on the substrate at least partially overlap.
  • the first metal pattern and the second metal pattern are an integral structure.
  • the second metal pattern is electrically connected to the second connection electrode through a fourth via hole.
  • the pixel driving circuit further includes a second storage capacitor composed of at least a part of each of the second storage electrode and the second metal pattern.
  • the first transistor, the second transistor, and the third transistor are all top-gate thin film transistors.
  • the display substrate further includes a data line
  • the power line, the sensing signal line, and the data line are arranged in parallel and in the same layer.
  • every two adjacent sub-pixels constitute a group, and two data lines are arranged between the two sub-pixels in each group.
  • One side of the sub-pixels of each group is provided with a power line, and the opposite side is provided with a sensing signal line, and the power line and the sensing signal line are spaced apart.
  • the pixel driving circuit in the two sub-pixels located on one side of the power line and close to the power line, and the pixel driving circuit located on the other side of the power line and close to the power line are both connected to the power line.
  • the pixel driving circuit in the two sub-pixels located on one side of the sensing signal line and close to the sensing signal line, and the pixel driving circuit located on the sensing signal line are both connected to the sensing signal line.
  • the display substrate further includes: a first auxiliary electrode provided for any one of the power lines, and a second auxiliary electrode provided for any one of the sensing signal lines.
  • the orthographic projection of the first auxiliary electrode on the substrate is located within the orthographic projection of the power line on the substrate.
  • the first auxiliary electrode and the power line are electrically connected through a plurality of fifth via holes.
  • the orthographic projection of the second auxiliary electrode on the substrate is located within the orthographic projection of the sensing signal line on the substrate.
  • the second auxiliary electrode and the sensing signal line are electrically connected through a plurality of sixth via holes.
  • the first auxiliary electrode, the second auxiliary electrode and the first gate electrode have the same layer and the same material.
  • the first electrode includes a first sub-electrode and a second sub-electrode that are disposed oppositely and electrically connected, and the second sub-electrode is disposed on a side of the first sub-electrode far away from the substrate. side.
  • the display substrate further includes: a filter unit and a flat layer stacked between the first sub-electrode and the second sub-electrode; the flat layer is located near the second sub-electrode of the filter unit. One side of the electrode.
  • embodiments of the present disclosure provide a display device including the display substrate described in any of the above embodiments.
  • inventions of the present disclosure provide a method for preparing a display substrate.
  • the preparation method includes:
  • a pixel driving circuit located in each sub-pixel is formed in the display area on the substrate.
  • the pixel driving circuit includes a first storage capacitor, and the first storage capacitor includes a first storage electrode and a second storage electrode that are arranged oppositely. Both the first storage electrode and the second storage electrode are transparent electrodes.
  • a bottom emission type light emitting device located on the side of the pixel driving circuit away from the substrate is formed.
  • the light emitting device includes a first electrode.
  • the first electrode is multiplexed by the first storage electrode.
  • the pixel driving circuit further includes a first transistor including a first gate, a first semiconductor active pattern, a first source, and a first drain.
  • the first transistor is a driving transistor.
  • Forming the pixel driving circuit further includes: simultaneously forming the second storage electrode in the process of forming the first semiconductor active pattern.
  • the display substrate further includes gate lines and data lines.
  • the pixel driving circuit further includes a second transistor including a second gate, a second semiconductor active pattern, a second source, and a second drain.
  • the manufacturing method of the display substrate further includes: synchronously forming the gate line and the first gate.
  • the second source electrode is electrically connected to the data line
  • the second drain electrode is electrically connected to the first gate electrode and the second storage electrode.
  • the manufacturing method of the display substrate further includes: synchronously forming the second semiconductor active pattern and the first semiconductor active pattern; synchronously forming the second source electrode, the second drain electrode, The data line, the first source electrode, and the first drain electrode.
  • the display substrate further includes a power line and a sensing signal line.
  • the first source electrode is electrically connected to the power line, and the first drain electrode is electrically connected to the first electrode.
  • the pixel driving circuit further includes a third transistor; the third transistor includes a third gate, a third semiconductor active pattern, a third source, and a third drain.
  • the third source electrode is electrically connected to the first drain electrode through a second connecting electrode, and the third source electrode, the second connecting electrode and the first drain electrode are an integral structure.
  • the third drain is electrically connected to the sensing signal line.
  • the third gate of the third transistor located in any row of sub-pixels is formed by multiplexing a part of the gate line corresponding to the adjacent row of sub-pixels closest to the third transistor.
  • the manufacturing method of the display substrate further includes: synchronously forming the third semiconductor active pattern and the first semiconductor active pattern; synchronously forming the third source electrode, the third drain electrode, and the power source Line and the sensing signal line.
  • the manufacturing method of the display substrate further includes: before forming the pixel driving circuit, synchronously forming a first metal pattern and a second metal pattern on the substrate, so that the After the pixel driving circuit, the first semiconductor active pattern is formed on the side of the first metal pattern away from the substrate, and the second connecting electrode is formed on the second metal pattern away from the substrate.
  • the orthographic projection of the first semiconductor active pattern on the substrate is within the orthographic projection of the first metal pattern on the substrate, and the second metal pattern At least partially overlapping with the orthographic projection of the second connection electrode on the substrate.
  • the first metal pattern and the second metal pattern are an integral structure, and the second metal pattern is electrically connected to the second connection electrode through a fourth via hole.
  • the second metal pattern is electrically connected to the third source electrode.
  • FIG. 1 is a schematic diagram of a partial area of a display substrate according to some embodiments of the present disclosure
  • Fig. 2a is a schematic structural diagram of a bottom emission type light emitting device in some embodiments of the present disclosure
  • Fig. 2b is a schematic structural diagram of another bottom-emitting light-emitting device in some embodiments of the present disclosure.
  • FIG. 3 is an equivalent circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a sub-pixel S in the display substrate shown in FIG. 1;
  • FIG. 5 is a schematic cross-sectional view of a sub-pixel S shown in FIG. 4 in the AA' direction;
  • FIG. 6 is a schematic cross-sectional view of a sub-pixel S shown in FIG. 4 in the BB' direction;
  • FIG. 7 is a schematic cross-sectional view of the sub-pixel S shown in FIG. 4 in the CC' direction;
  • FIG. 8 is a schematic cross-sectional view of a sub-pixel S shown in FIG. 4 in the DD' direction;
  • FIG. 9a is a schematic cross-sectional view of a sub-pixel S shown in FIG. 4 in the EE' direction;
  • FIG. 9b is another schematic cross-sectional view of the sub-pixel S shown in FIG. 4 in the EE' direction;
  • FIG. 10 is a schematic cross-sectional view of a sub-pixel S shown in FIG. 4 in the FF' direction;
  • FIG. 11 is a schematic structural diagram of another sub-pixel S in a display substrate shown in FIG. 1;
  • FIG. 12 is a schematic cross-sectional view of a sub-pixel S shown in FIG. 11 in the GG' direction;
  • FIG. 13 is a schematic cross-sectional view of a sub-pixel S shown in FIG. 11 in the direction HH';
  • FIG. 14 is a schematic diagram showing the structure of a partial area of another display substrate according to some embodiments of the present disclosure.
  • FIG. 15 is a schematic structural diagram of a sub-pixel S in a display substrate shown in FIG. 14;
  • 16 is a schematic cross-sectional view of a sub-pixel S shown in FIG. 15 in the II' direction;
  • FIG. 17a is a schematic cross-sectional view of a sub-pixel S shown in FIG. 15 in the JJ' direction;
  • FIG. 17b is another schematic cross-sectional view of the sub-pixel S shown in FIG. 15 in the JJ' direction;
  • FIG. 18 is a schematic cross-sectional view of a sub-pixel S shown in FIG. 15 in the KK' direction;
  • FIG. 19 is a schematic diagram of a structure of the R region in the display substrate shown in FIG. 14;
  • FIG. 20 is a schematic diagram of a part of the structure in the R region shown in FIG. 19;
  • FIG. 21 is a schematic flowchart of a method for preparing a display substrate according to some embodiments of the present disclosure.
  • FIG. 22 is a schematic structural diagram of a display device according to some embodiments of the present disclosure.
  • the expressions of "electrical connection” and “contact” and their extensions may be used.
  • the terms “electrically connected” or “contact” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • the term “if” is optionally interpreted as meaning “when” or “when” or “in response to determination” or “in response to detection.”
  • the phrase “if it is determined" or “if [the stated condition or event] is detected” is optionally interpreted to mean “when determining" or “in response to determining" Or “when [stated condition or event] is detected” or “in response to detecting [stated condition or event]”.
  • each sub-pixel of the self-luminous display substrate is provided with a pixel drive circuit and a light-emitting device electrically connected to the pixel drive circuit.
  • the storage capacitor and the light-emitting device in the pixel driving circuit are located in different areas of the sub-pixel, which causes a cross-line at the electrical connection between the storage capacitor and the light-emitting device, thereby increasing the risk of crosstalk.
  • the storage capacitor needs to occupy a larger area of the sub-pixel.
  • the pixel driving circuit is located on the light-emitting side of the light-emitting device, and the storage capacitor occupies a larger area of the sub-pixel, which easily leads to a smaller aperture ratio of the sub-pixel, resulting in a smaller light-emitting area of the light-emitting device. Therefore, when the display brightness is the same, the smaller the light-emitting area of the light-emitting device, the greater the current density it needs, which tends to accelerate the aging speed of the light-emitting device and affect the life of the light-emitting device. However, if the facing area of the storage capacitor is set to be small, the capacitance of the storage capacitor is likely to be small, and the problem of uneven display image quality of the display substrate may occur.
  • the display substrate 1 has a display area AA, and a plurality of sub-pixels S are arranged in the display area AA of the display substrate 1.
  • the display substrate 1 includes a substrate 10, and a pixel driving circuit and a bottom emission type light emitting device 110 arranged in a display area AA on the substrate 10 and located in each sub-pixel S.
  • the pixel driving circuit includes a first storage capacitor 120.
  • the first storage capacitor 120 includes a first storage electrode 121 and a second storage electrode 122 disposed oppositely.
  • the light emitting device 110 includes a first electrode 111 electrically connected to the first storage capacitor 120 in the pixel driving circuit.
  • the first electrode 111 is multiplexed as the first storage electrode 121, and both the first electrode 111 and the second storage electrode 122 are transparent electrodes.
  • the pixel driving circuit is located on the light emitting side of the light emitting device 110. Therefore, those skilled in the art should understand that when the first electrode 111 is multiplexed as the first storage electrode 121, the second storage The electrode 122 is located on the side of the first storage electrode 121 close to the substrate 10.
  • FIG. 1 only schematically shows the distribution and structure of the sub-pixels S in a partial area of the display substrate 1, and the structure of the light-emitting device 110 is also only partially shown.
  • the light-emitting device 110 includes a first electrode 111 and a second electrode 112, and a light-emitting layer 113 located between the first electrode 111 and the second electrode 112.
  • the first electrode 111 is an anode and the second electrode 112 is a cathode; or, the first electrode 111 is a cathode and the second electrode 112 is an anode.
  • the light-emitting device 110 when the first electrode 111 is an anode and the second electrode 112 is a cathode, the light-emitting device 110 is upright. When the first electrode 111 is a cathode and the second electrode 112 is an anode, the light-emitting device 110 is inverted.
  • the light-emitting device 110 when the first electrode 111 is an anode and the second electrode 112 is a cathode, the light-emitting device 110 further includes a hole transport between the light-emitting layer 113 and the first electrode 111.
  • the layer 114 and the electron transport layer 115 located between the light-emitting layer 113 and the second electrode 112.
  • a hole injection layer may be provided between the hole transport layer 114 and the first electrode 111
  • an electron injection layer may be provided between the electron transport layer 115 and the second electrode 112.
  • the light-emitting device 110 when the first electrode 111 is a cathode and the second electrode 112 is an anode, the light-emitting device 110 further includes a hole transport layer 114, which is located between the light-emitting layer 113 and the second electrode 112, The electron transport layer 115 located between the light-emitting layer 113 and the first electrode 111, of course, a hole injection layer can also be provided between the hole transport layer 114 and the second electrode 112, and the electron transport layer 115 and the first electrode An electron injection layer is provided between 111.
  • the light-emitting layer 113 is an organic light-emitting layer or a quantum dot light-emitting layer.
  • the material of the first electrode 111 is indium tin oxide (ITO), and the material of the second electrode 112 is silver (Ag). But it is not limited to this.
  • the pixel driving circuit involved in the subsequent embodiments of the present disclosure is described with the light-emitting device 110 as an upright light-emitting device.
  • the display substrate 1 is usually provided with a pixel defining layer.
  • the light emitting device 110 is formed in the corresponding opening of the pixel defining layer, and the light emitting area of the sub-pixel S can be defined by the opening area of the pixel defining layer.
  • the material of the pixel defining layer can be a light-transmitting resin material.
  • the first electrode 111 of the light emitting device 110 is reused as the first storage electrode 121, and both the first electrode 111 and the second storage electrode 122 are set as transparent electrodes.
  • the first storage capacitor 120 is arranged in an area directly opposite to the light emitting device 110, that is, in the light emitting area of the light emitting device 110 and does not affect the light emitting effect of the light emitting device 110.
  • the first electrode 111 of the light-emitting device 110 is reused as the first storage electrode 121 of the first storage capacitor 120, which can avoid cross-line generation when the light-emitting device 110 and the first storage capacitor 120 are electrically connected, thereby avoiding crosstalk. risk.
  • the first storage capacitor 120 may not occupy the area of the sub-pixel S. In this way, when the area of the sub-pixel S is constant, the light-emitting device 110 may occupy the sub-pixel S. In this way, the aperture ratio of the sub-pixel S is increased.
  • both the first electrode 111 and the second storage electrode 122 are transparent electrodes, so that the area of the second storage electrode 122 can be set as large as possible, thereby effectively increasing the capacitance of the first storage capacitor 120 to avoid displaying
  • the substrate 1 has a problem of uneven display quality.
  • the display substrate 1 in the embodiment of the present disclosure is applied to an 8K high pixel density (Pixels Per Inch, PPI) display substrate, compared with the average aperture ratio of sub-pixels in the related art of about 12%, the display substrate The average aperture ratio of the pixels in Central Asia can be increased to about 17%, which effectively increases by about 40%.
  • the capacitance value of the storage capacitor in the related art that is about 0.13 pF
  • the capacitance value of the storage capacitor (ie, the first storage capacitor 120) in the display substrate can be increased to 0.17 pF, thereby effectively increasing by 30%.
  • the structure of the pixel drive circuit can be selected and set according to actual needs, for example, the 3T1C pixel circuit shown in FIG. 3; that is, the pixel circuit can be composed of three transistors T and a storage capacitor C, where the three transistors are respectively It is the first transistor T1, the second transistor T2, and the third transistor T3; the storage capacitor C is the first storage capacitor 120 in some of the foregoing embodiments.
  • the pixel driving circuit may also be a structure including other numbers of transistors or other numbers of storage capacitors, which is not limited in the embodiments of the present disclosure.
  • a pixel circuit with a 3T1C pixel driving circuit is taken as an example for description.
  • the structure of the pixel driving circuit in a single sub-pixel S is shown in FIGS. 3 and 4, and the pixel driving circuit further includes a first transistor T1, and the first transistor T1 is a driving transistor.
  • the first transistor T1 includes a first gate 131, a first semiconductor active pattern 132, a first source 133 and a first drain 134.
  • the first source electrode 133 is electrically connected to the power line 14, and the first drain electrode 134 is electrically connected to the first electrode 121.
  • the first semiconductor active pattern 132 includes a first channel region 1320, a first source region 1321, and a first drain region 1322, and the conductivity of the first source region 1321 and the first drain region 1322 is greater than that of the first channel
  • the region 1320 is conductive, the first source 133 is in contact with the first source region 1321, and the first drain 134 is in contact with the first drain region 1322.
  • the second storage electrode 122 may be obtained by conducting a semiconductor pattern, that is, the second storage electrode 122 may be a semiconductor pattern that has undergone a conductorization process. Based on this, the second storage electrode 122 and the first source region 1321 and the first drain region 1322 have the same layer and the same material.
  • the semiconductor layer may be separately conductive in different regions by ion implantation to form the second storage electrode 122 and the first source region 1321 and the first drain electrode in the first semiconductor active pattern 132 District 1322. There is a gap between the first source region 1321 and the first drain region 1322, and the portion of the semiconductor layer existing in the gap is the first channel region 1321 in the first semiconductor active pattern 132.
  • the ions implanted into the semiconductor layer may be boron ions or phosphorus ions.
  • the first transistor T1 in FIGS. 4 and 5 is illustrated by using a top-gate thin film transistor as an example.
  • the first semiconductor active pattern 132 is disposed on the first gate.
  • the first semiconductor active pattern 132 and the first gate electrode 131 are separated by the first gate insulating pattern 135, and both the first source electrode 133 and the first drain electrode 134 and the first gate electrode 131 is isolated by the interlayer insulating layer 20.
  • the first gate insulating pattern 135 and the first gate 131 are formed synchronously. Based on this, the first source electrode 133 and the first drain electrode 134 respectively contact the first semiconductor active pattern 132 through the via hole penetrating the interlayer insulating layer 20.
  • the simultaneous formation refers to the formation by the same patterning process, such as a mask process. All the "synchronization formation” involved in the embodiments of the present disclosure can be understood in this way, but it is not limited to this.
  • the first source electrode 133 and the first drain electrode 134 pass through the interlayer insulation, respectively.
  • the via holes of the two layers of the layer 20 and the gate insulating layer are in contact with the first semiconductor active pattern 132.
  • the semiconductor pattern is fabricated at the same time as the first semiconductor active pattern 132 of the first transistor T1 is fabricated, and the second storage electrode 122 is obtained by conducting the semiconductor pattern. On the basis of adding a patterning process, the second storage electrode 122 is formed.
  • the pixel driving circuit further includes a second transistor T2, and the second transistor T2 includes a second gate 151, a second semiconductor active The pattern 152, the second source electrode 153, and the second drain electrode 154.
  • the second transistor T2 in FIGS. 4 and 7 is illustrated by using a top-gate thin film transistor as an example.
  • the second semiconductor active pattern 152 is disposed on the second gate 151 close to the substrate.
  • the second semiconductor active pattern 152 and the second gate electrode 151 are isolated by the second gate insulating pattern 155, and the second source electrode 153 and the second drain electrode 154 are separated from the second gate electrode 151 by the interlayer The insulating layer 20 is isolated.
  • the second gate insulating pattern 155 is formed synchronously with the second gate electrode 151. Based on this, the second source electrode 153 and the second drain electrode 154 respectively contact the second semiconductor active pattern 152 through the via hole penetrating the interlayer insulating layer 20. In addition, similar to the first transistor T1, when the gate insulating layer between the second semiconductor active pattern 152 and the second gate 151 is not patterned, the second source electrode 153 and the second drain electrode 154 respectively pass through The via hole penetrating the two layers of the interlayer insulating layer 20 and the gate insulating layer is in contact with the second semiconductor active pattern 152.
  • a part of the gate line 16 is multiplexed as the second gate 151, which can effectively reduce the area occupied by the pixel driving circuit in the sub-pixel S and improve the sub-pixel Opening rate.
  • the second source electrode 153 is electrically connected to the data line 17.
  • the second drain electrode 154, the second storage electrode 122, and the first gate electrode 151 are electrically connected.
  • the display substrate 1 further includes a first connection electrode 156.
  • the second drain electrode 154 is electrically connected to the first connection electrode 156, and the two are in an integral structure.
  • the first connection electrode 156 is electrically connected to the second storage electrode 122 and the first gate 131 through the first via 1311.
  • the second drain electrode 154 and the first gate electrode 131 are spaced in the first direction (for example, the Y direction).
  • the first gate 131 extends in the second direction (for example, the X direction).
  • the first direction and the second direction are perpendicular or substantially perpendicular. That is to say, the angle between the first direction and the second direction is 90° or about 90°, for example, slightly less than 90° or slightly greater than 90°.
  • the first connection electrode 156 extends in the first direction.
  • the size of the portion of the first connection electrode 156 that is electrically connected to the second drain electrode 154 in the second direction is smaller than the size of the portion of the first connection electrode 156 that is electrically connected to the first gate 131 in the second direction. In this way, it is beneficial to reduce the area occupied by the pixel driving circuit in the sub-pixel S, so as to increase the aperture ratio of the sub-pixel.
  • the structure of the second semiconductor active pattern 152 is similar to that of the first semiconductor active pattern 132, and the two are formed simultaneously.
  • the second semiconductor active pattern 152 includes a second channel region 1520, a second source region 1521, and a second drain region 1522.
  • the second source 153 is in contact with the second source region 1521
  • the second drain 154 is in contact with the second drain region 1522.
  • the second storage electrode 122 is in contact with the second drain region 1522 in the second semiconductor active pattern 152, and the second storage electrode 122 and the second drain region 1522 are integrated.
  • the second storage electrode 122 and the first gate 131 are electrically connected through the second via 1322.
  • the second drain electrode 154 and the first gate electrode 131 are spaced in the first direction (ie, the Y direction).
  • the first gate 131 extends in the second direction (ie, the X direction).
  • the first direction and the second direction are perpendicular or substantially perpendicular. That is to say, the angle between the first direction and the second direction is 90° or about 90°, for example, slightly less than 90° or slightly greater than 90°.
  • the second storage electrode 122 includes an extension portion 1220 that extends along the first direction and is electrically connected to the second drain region 1522.
  • the size of the portion of the extension portion 1220 that is electrically connected to the second drain region 1522 in the second direction is smaller than the size of the portion of the extension portion 1220 that is electrically connected to the first gate 131 in the second direction. In this way, it is beneficial to reduce the area occupied by the pixel driving circuit in the sub-pixel S, so as to increase the aperture ratio of the sub-pixel.
  • the second transistor T2 in FIG. 11 and FIG. 12 is illustrated by taking a top-gate thin film transistor as an example.
  • the second semiconductor active pattern 152 is disposed on the side of the second gate 151 close to the substrate 10, and the second gate 151 and the second semiconductor active pattern 152 pass through the unpatterned second gate insulating layer. 157 isolation, and the second source 153 and the second drain 154 are isolated from the second gate 151 by the interlayer insulating layer 20.
  • the second source electrode 153 and the second drain electrode 154 are in contact with the second semiconductor active pattern 152 through via holes penetrating through the two layers of the interlayer insulating layer 20 and the second gate insulating layer 157, respectively.
  • the first source 133 of the first transistor T1 is electrically connected to the power line 14, and the first drain 134 is electrically connected to the first electrode 111.
  • the power supply line 14 is used to supply power to the pixel driving circuit.
  • the pixel driving circuit when the pixel driving circuit includes a second transistor T2, the pixel driving circuit further includes a third transistor T3.
  • the third transistor T3 includes a third gate 181, a third semiconductor active pattern 182, a third source 183 and a third drain 184.
  • the third transistor T3 in FIG. 4 and FIG. 10 is illustrated by taking a top-gate thin film transistor as an example.
  • the third semiconductor active pattern 182 is disposed on the side of the third gate 181 close to the substrate 10, the third semiconductor active pattern 182 and the third gate 181 are isolated by the third gate insulating pattern 185, The three source electrode 183 and the third drain electrode 184 are separated from the third gate electrode 181 by the interlayer insulating layer 20.
  • the third gate insulating pattern 185 is formed synchronously with the third gate electrode 181.
  • the third source electrode 183 and the third drain electrode 184 respectively contact the third semiconductor active pattern 182 through the via hole penetrating the interlayer insulating layer 20.
  • the third source electrode 183 and the third drain electrode 184 respectively pass through The via hole penetrating the two layers of the interlayer insulating layer 20 and the gate insulating layer is in contact with the third semiconductor active pattern 182.
  • the structure of the third semiconductor active pattern 182 is similar to that of the second semiconductor active pattern 152, and will not be described in detail here.
  • the first transistor T1 and the third transistor T3 are located on both sides of the first storage capacitor 120 along the first direction (ie, the Y direction).
  • the display substrate 1 further includes a second connection electrode 186.
  • the third source electrode 183 is electrically connected to the first drain electrode 134 through the second connecting electrode 186, and the third source electrode 183, the second connecting electrode 186 and the first drain electrode 134 are integrated.
  • the display substrate 1 further includes a sensing signal line 19.
  • the third drain electrode 184 is electrically connected to the sensing signal line 19.
  • FIG. 9 a and FIG. 10 that the second connection electrode 186 is electrically connected to the first electrode 111 through the third via 1811. That is, the second connection electrode 186 is used to realize electrical connection between the first electrode 111, the second drain electrode 134 and the third source electrode 183.
  • the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a first storage capacitor 120, its equivalent circuit diagram is shown in FIG. 3. Based on this, the parameter of the first transistor T1 can be sensed through the sensing signal line 19, and then the threshold voltage of the first transistor T1 can be compensated externally.
  • the materials of the second drain electrode 154, the third drain electrode 184, the gate line 16, the data line 17, the power line 14, and the sensing signal line 19 may be selected from copper (Cu), aluminum (Al), molybdenum (Mo), At least one of elementary metals of titanium (Ti), chromium (Cr), and tungsten (W) and metal alloys composed of these elements.
  • the materials of the first gate insulating pattern 136, the second gate insulating pattern 155, the third gate insulating pattern 185, and the interlayer insulating layer 157 may be selected from inorganic oxides such as silicon nitride (SiNx) and silicon dioxide (SiO2). One or more of them, and the first gate insulating pattern 136, the second gate insulating pattern 155, the third gate insulating pattern 185, and the interlayer insulating layer 157 may adopt a single-layer structure or a multilayer laminated structure.
  • the semiconductor material in the first semiconductor active pattern 132, the second semiconductor active pattern 152, and the third semiconductor active pattern 182 may be selected from transparent semiconductor oxides, such as indium zinc oxide (IGZO).
  • the third gate 181 of the third transistor T3 in any row of sub-pixels S is multiplexed by a part of the gate line 16 corresponding to the adjacent row of sub-pixels closest to the third transistor T3. constitute. Therefore, it is beneficial to reduce the area occupied by the pixel driving circuit in the sub-pixel S in the case where a plurality of sub-pixels S are arranged in an array, so as to increase the aperture ratio of the sub-pixels.
  • the display substrate 1 further includes: a side of the first semiconductor active pattern 132 close to the substrate 10 The first metal pattern 1313.
  • the orthographic projection of the first semiconductor active pattern 131 on the substrate 10 is within the orthographic projection of the first metal pattern 1313 on the substrate 10.
  • the first semiconductor active pattern 132 and the first metal pattern 1313 are separated by an insulating layer 1314.
  • the display substrate 1 further includes a second metal pattern 1851.
  • the orthographic projection of the second metal pattern 1851 and the second connection electrode 186 on the substrate 10 at least partially overlap.
  • the first metal pattern 1313 and the second metal pattern 1851 are an integral structure.
  • the second metal pattern 1851 is electrically connected to the second connection electrode 186 through the fourth via 1852. Since the second connection electrode 186 is electrically connected to the first electrode 111 through the third via 1811, the second metal pattern 1851 and the first electrode 111 are also electrically connected.
  • the storage capacitor C in the pixel driving circuit includes a first storage capacitor 120 and a second storage capacitor 123 connected in parallel with the first storage capacitor 120.
  • the second storage capacitor 123 may be composed of at least a part of each of the second storage electrode 122 and the second metal pattern 1851. That is, the two electrodes of the second storage capacitor 123 may be formed by multiplexing at least a part of the second storage electrode 122 and at least a part of the second metal pattern 1851.
  • the first metal pattern 1313 can prevent external light from being incident on the first semiconductor active pattern 132, thereby preventing external light from adversely affecting the performance of the first transistor T1.
  • the second storage electrode 122 and the second metal pattern 1851 can be used to form the second storage capacitor 123 connected in parallel with the first storage capacitor 120, so that the storage capacitor C of the pixel driving circuit includes the first storage capacitor.
  • a storage capacitor 120 and a second storage capacitor 123 can increase the capacitance of the storage capacitor C in the pixel driving circuit, and further avoid the problem of uneven image quality of the display substrate 1.
  • the second metal pattern 1851 overlaps the orthographic projection of the second connection electrode 186 on the substrate 10, which can also prevent the second metal pattern 1851 from affecting the aperture ratio of the sub-pixel S.
  • the first transistor T1, the second transistor T2, and the third transistor T3 are all top-gate thin film transistors, which facilitates the completion of the pixel driving circuit on the substrate.
  • the power line 14, the sensing signal line 19 and the data line 17 are arranged in parallel and in the same layer, which is beneficial to simplify the wiring design of each signal line in the display substrate 1.
  • every two adjacent sub-pixels S is a group, and two data lines 17 are arranged between the two sub-pixels S in each group.
  • a power line 14 is provided on one side of each group of sub-pixels, and a sensing signal line 19 is provided on the opposite side, and the power line 14 and the sensing signal line 19 are spaced apart.
  • the pixel driving circuit in the two sub-pixels located on one side of the power line 14 and close to the power line 14 and the two sub-pixels located on the other side of the power line 14 and close to the power line 14 are all connected to the power line 14.
  • the pixel driving circuit in the two sub-pixels located on one side of the sensing signal 19 and close to the sensing signal line 19 and the pixel driving circuit located on the other side of the sensing signal line 19 and close to the sensing signal
  • the pixel driving circuits in the two sub-pixels of the signal line 19 are both connected to the sensing signal line 19.
  • the total number of power lines 14 and sensing signal lines 19 can be reduced, thereby simplifying the manufacturing process of the display substrate 1.
  • the display substrate 1 further includes: a first auxiliary electrode 141 provided for any power line 14.
  • the orthographic projection of the first auxiliary electrode 141 on the substrate 10 is located within the orthographic projection of the power line 14 on the substrate 10.
  • the first auxiliary electrode 141 and the power line 14 are electrically connected through a plurality of fifth via holes 1411, that is, the first auxiliary electrode 141 is connected in parallel with the power line 14. In this way, it is beneficial to reduce the equivalent resistance of the power line 14, thereby reducing the loss of the signal transmitted by the power line 14.
  • the display substrate 1 further includes: a second auxiliary electrode 191 provided for any one of the sensing signal lines 19.
  • the orthographic projection of the second auxiliary electrode 191 on the substrate 10 is located within the orthographic projection of the sensing signal line 19 on the substrate 10.
  • the second auxiliary electrode 191 and the sensing signal line 19 are electrically connected through a plurality of sixth via holes 1911, that is, the second auxiliary electrode 191 is connected in parallel with the sensing signal line 19. In this way, it is beneficial to reduce the equivalent resistance of the sensing signal line 19, thereby reducing the loss of the signal transmitted by the sensing signal line 19.
  • the first auxiliary electrode 141, the second auxiliary electrode 191 and the first gate 131 have the same layer and the same material. Based on this, the first auxiliary electrode 141 and the second auxiliary electrode 191 can be fabricated at the same time as the first gate 131 is fabricated, thereby simplifying the fabrication process of the display substrate 1.
  • the display substrate 1 further includes a filter unit disposed in each sub-pixel S, so as to realize the color display of the display substrate 1 by using the filter unit.
  • the first electrode 111 includes a first sub-electrode 1111 and a second sub-electrode 1112 that are electrically connected, and the second sub-electrode 1112 is disposed at The side of the first sub-electrode 1111 away from the substrate 10.
  • the display substrate 1 further includes: a filter unit 30 and a flat layer 40 stacked between the first sub-electrode 1111 and the second sub-electrode 1112; the flat layer 40 is located on the side of the filter unit 30 close to the second sub-electrode 1112 .
  • the second sub-electrode 1112 is formed on the surface of the flat layer 40 away from the filter unit 30, which helps to ensure that the light-emitting layer 113 formed on the second sub-electrode 1112 has a good flatness, thereby ensuring that the display substrate 1 emits light uniformly.
  • the filter unit 30 is a color filter film.
  • the embodiment of the present disclosure provides a method for preparing the display substrate 1.
  • the preparation method of the display substrate 1 includes: S10 to S20.
  • the pixel driving circuit includes a first storage capacitor 120.
  • the first storage capacitor 120 includes a first storage electrode 121 and a second storage electrode 122 disposed oppositely. Both the first storage electrode 121 and the second storage electrode 122 are transparent electrodes.
  • the structure of the pixel driving circuit is as shown in some of the foregoing embodiments, and will not be described in detail here.
  • each sub-pixel S on the substrate 10 a bottom-emitting light-emitting device located on the side of the pixel driving circuit away from the substrate 10 is formed.
  • the light emitting device 110 includes a first electrode 111.
  • the first electrode 111 is formed by multiplexing the first storage electrode 121.
  • the beneficial effects that can be achieved by the manufacturing method of the display substrate 1 provided by the embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the display substrate 1 provided by the above-mentioned embodiments, and will not be repeated here.
  • the pixel driving circuit further includes a first transistor T1.
  • the first transistor T1 includes a first gate 131, a first semiconductor active pattern 132, a first source 133, and a first drain 134.
  • the first transistor T1 is a driving transistor.
  • forming the pixel driving circuit further includes: in the process of forming the first semiconductor active pattern 132, simultaneously forming the second storage electrode 122. Therefore, the manufacturing process of the pixel driving circuit can be simplified.
  • the display substrate 1 further includes gate lines 16 and data lines 17.
  • the pixel driving circuit also includes a second transistor T2.
  • the second transistor T2 includes a second gate 151, a second semiconductor active pattern 152, a second source 153, and a second drain 154.
  • the structure of the second semiconductor active pattern 152 is as shown in some of the foregoing embodiments.
  • Each sub-pixel S corresponds to a gate line 16, and a part of the gate line 16 can be multiplexed as the second gate 151.
  • the manufacturing method of the display substrate 1 further includes: simultaneously forming the gate line 16 and the first gate 131 in the process of performing S10. Therefore, the manufacturing process of the display substrate can be simplified.
  • the second source electrode 153 is electrically connected to the data line 17, and the second drain electrode 154 is electrically connected to the first gate electrode 131 and the second storage electrode 122.
  • the manufacturing method of the display substrate 1 further includes: in the process of performing S10, synchronously forming the second semiconductor active pattern 152 and the first semiconductor active pattern 132; and synchronously forming the second source 153 and the second drain.
  • the electrode 154, the data line 17, the first source electrode 133, and the first drain electrode 134 Therefore, the manufacturing process of the display substrate can be simplified.
  • the display substrate 1 further includes a power line 14 and a sensing signal line 19.
  • the first source electrode 133 is electrically connected to the power line 14, and the first drain electrode 134 is electrically connected to the first electrode 111.
  • the pixel driving circuit further includes: a third transistor T3.
  • the third transistor T3 includes a third gate 181, a third semiconductor active pattern 182, a third source 183, and a third drain 184.
  • the third source electrode 183 is electrically connected to the first drain electrode 134 through the second connecting electrode 186, and the third source electrode 183, the second connecting electrode 186 and the first drain electrode 134 are integrated.
  • the third drain electrode 184 is electrically connected to the sensing signal line 19.
  • the third gate 181 of the third transistor T3 located in any row of sub-pixels S can be multiplexed by a portion of the gate line 16 corresponding to the adjacent row of sub-pixels S closest to the third transistor T3.
  • the manufacturing method of the display substrate 1 further includes: in the process of performing S10, synchronously forming the third semiconductor active pattern 182 and the first semiconductor active pattern 132; and synchronously forming the third source 183 and the third drain. Pole 184, power line 14, and sensing signal line 19. Therefore, the manufacturing process of the display substrate can be further simplified.
  • the preparation method of the display substrate 1 further includes: before performing S10 , The first metal pattern 1313 and the second metal pattern 1851 are simultaneously formed on the substrate 10, so that after S10 is performed, the first semiconductor active pattern 132 is formed on the side of the first metal pattern 1313 away from the substrate 10.
  • the second connection electrode 186 is formed on the side of the second metal pattern 1851 away from the substrate 10.
  • first metal pattern 1313 and the second metal pattern 1851 are as described in the previous embodiments, and will not be described in detail here.
  • the orthographic projection of the first semiconductor active pattern 132 on the substrate 10 is within the orthographic projection of the first metal pattern 1313 on the substrate 10
  • the second metal pattern 1851 and the second metal pattern 1851 are The orthographic projections of the connection electrodes 186 on the substrate 10 at least partially overlap.
  • the first metal pattern 1313 and the second metal pattern 1851 are an integral structure, and the second metal pattern 1851 is electrically connected to the second connection electrode 186 through the fourth via 1852.
  • the second metal pattern 1851 is electrically connected to the third source electrode 183.
  • the embodiment of the present disclosure provides a display device.
  • the display device 1000 includes the display substrate 1 described in any of the foregoing embodiments.
  • the beneficial effects that can be achieved by the display device 1000 provided by the embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the display substrate 1 provided by the above-mentioned embodiments, and will not be repeated here.
  • the display device 1000 is an OLED display panel, an OLED display, an OLED television, a mobile phone, a tablet computer, a notebook computer, an electronic paper, a digital photo frame, or a navigator and other products or components with display functions.

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Abstract

本公开实施例提供一种显示基板及其制备方法、显示装置，不仅能够避免亚像素中的发光器件和存储电容电连接时产生跨线，以避免了串扰风险；还能够提高显示基板的像素开口率，以及增大像素驱动电路中存储电容的电容量。所述显示基板包括：衬底，设置于所述衬底上显示区内且位于每个亚像素中的像素驱动电路和底发光型发光器件；所述发光器件包括与所述像素驱动电路连接的第一电极；所述像素驱动电路包括第一存储电容，所述第一存储电容包括相对设置的第一存储电极和第二存储电极；所述第一电极复用为所述第一存储电极；所述第二存储电极和所述第一电极均为透明电极。

Description

显示基板及其制备方法、显示装置
本申请要求于2019年11月13日提交中国专利局、申请号为201911108797.6、申请名称为“显示面板及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其制备方法、显示装置。
背景技术
自发光显示基板例如有机发光二极管(Organic Light-Emitting Diode，OLED)显示基板具有自发光、轻薄、功耗低、色彩还原度好、反应灵敏以及广视角等优点，已经被越来越广泛的应用在手机、笔记本电脑以及电视等显示装置中，成为目前市场的主流之一。
发明内容
一方面，本公开实施例提供一种显示基板。所述显示基板包括：衬底，以及设置于所述衬底上的显示区内且位于每个亚像素中的像素驱动电路和底发光型发光器件。所述发光器件包括与所述像素驱动电路电连接的第一电极。所述像素驱动电路包括第一存储电容，所述第一存储电容包括相对设置的第一存储电极和第二存储电极。所述第一电极复用为所述第一存储电极。所述第二存储电极和所述第一电极均为透明电极。
在一些实施例中，所述显示基板还包括电源线。所述像素驱动电路还包括第一晶体管。所述第一晶体管包括第一栅极、第一半导体有源图案、第一源极和第一漏极。所述第一晶体管为驱动晶体管。所述第一源极与电源线电连接，所述第一漏极与所述第一电极电连接。所述第一半导体有源图案包括第一沟道区、第一源极区和第一漏极区，所述第一源极区和所述第一漏极区的导电性大于所述第一沟道区的导电性，且所述第一源极与所述第一源极区接触，所述第一漏极与所述第一漏极区接触。所述第二存储电极为经过导体化处理后的半导体图案，其中，所述第二存储电极与所述第一源极区和所述第一漏极区同层同材料。
在一些实施例中，所述显示基板还包括：栅线和数据线。所述像素驱动电路还包括第二晶体管，所述第二晶体管包括第二栅极、第二半导体有源图案、第二源极和第二漏极。所述栅线中的一部分复用为所述第二栅极。所述第二源极与所述数据线电连接。所述第二漏极与所述第二存储电极、所述第一栅极电连接。
在一些实施例中，所述显示基板还包括：第一连接电极。所述第一连接电极与所述第二漏极为一体结构，且所述第一连接电极通过第一过孔与所述第二存储电极、所述第一栅极分别电连接。
可选的，所述第二漏极与所述第一栅极在第一方向上具有间隔。所述第一栅极沿第二方向延伸。所述第一方向和所述第二方向垂直或大致垂直。所述第一连接电极沿 所述第一方向延伸。所述第一连接电极的与所述第二漏极电连接的部分在所述第二方向上的尺寸、小于所述第一连接电极的与所述第一栅极电连接的部分在所述第二方向上的尺寸。
在一些实施例中，所述第二半导体有源图案包括第二沟道区、第二源极区和第二漏极区。所述第二源极与所述第二源极区接触，所述第二漏极与所述第二漏极区接触。所述第二存储电极与所述第二漏极区为一体结构。所述第二存储电极与所述第一栅极通过第二过孔电连接。
可选的，所述第二漏极与所述第一栅极在第一方向上具有间隔。所述第一栅极沿第二方向延伸。所述第一方向和所述第二方向垂直或大致垂直。所述第二存储电极包括：沿所述第一方向延伸、且与所述第二漏极区电连接的延伸部。所述延伸部的与所述第二漏极区电连接的部分在第二方向上的尺寸、小于所述延伸部的与所述第一栅极电连接的部分在所述第二方向上的尺寸。
在一些实施例中，在所述像素驱动电路包括第二晶体管的情况下，所述像素驱动电路还包括第三晶体管。所述第三晶体管包括第三栅极、第三半导体有源图案、第三源极和第三漏极。所述第一晶体管和所述第三晶体管位于所述第一存储电容的沿第一方向的两侧。所述显示基板还包括第二连接电极和感测信号线。所述第三源极通过所述第二连接电极与所述第一漏极电连接，且所述第三源极、所述第二连接电极和所述第一漏极为一体结构。所述第三漏极与所述感测信号线电连接。所述第二连接电极通过第三过孔与所述第一电极电连接。
在一些实施例中，位于任一行亚像素中的所述第三晶体管的所述第三栅极，由距离所述第三晶体管最近的相邻行亚像素对应的所述栅线的一部分复用构成。
在此基础上，可选的，所述第一晶体管为顶栅型薄膜晶体管。
所述显示基板还包括：设置于所述第一半导体有源图案的靠近所述衬底一侧的第一金属图案。沿所述衬底的厚度方向，所述第一半导体有源图案在所述衬底上的正投影位于所述第一金属图案在所述衬底上的正投影内。
所述显示基板还包括第二金属图案。沿所述衬底的厚度方向，所述第二金属图案与所述第二连接电极在所述衬底上的正投影至少部分重叠。
所述第一金属图案和所述第二金属图案为一体结构。所述第二金属图案通过第四过孔与所述第二连接电极电连接。所述像素驱动电路还包括第二存储电容，所述第二存储电容由所述第二存储电极和所述第二金属图案中每者的至少一部分构成。
可选的，所述第一晶体管、所述第二晶体管和所述第三晶体管均为顶栅型薄膜晶体管。
可选的，在所述显示基板还包括数据线的情况下，所述电源线、所述感测信号线以及所述数据线平行且同层设置。
每行所述亚像素中，每相邻的两个所述亚像素为一组，每组的两个所述亚像素之间设置有两根所述数据线。每组所述亚像素的一侧设置有一根所述电源线，相对的另一侧设置有一根所述感测信号线，且所述电源线和所述感测信号线间隔设置。
针对每行所述亚像素，位于所述电源线的一侧且靠近所述电源线的两个所述亚像素中的所述像素驱动电路、以及位于所述电源线的另一侧且靠近所述电源线的两个所 述亚像素中的所述像素驱动电路，均与所述电源线连接。
针对每行所述亚像素，位于所述感测信号线的一侧且靠近所述感测信号线的两个所述亚像素中的所述像素驱动电路、以及位于所述感测信号线的另一侧且靠近所述感测信号线的两个所述亚像素中的所述像素驱动电路，均与所述感测信号线连接。
在此基础上，可选的，所述显示基板，还包括：针对任一根所述电源线设置的第一辅助电极，以及针对任一根所述感测信号线设置的第二辅助电极。
沿所述衬底的厚度方向，所述第一辅助电极在所述衬底上的正投影位于所述电源线在所述衬底上的正投影内。所述第一辅助电极与所述电源线通过多个第五过孔电连接。
沿所述衬底的厚度方向，所述第二辅助电极在所述衬底上的正投影位于所述感测信号线在所述衬底上的正投影内。所述第二辅助电极与所述感测信号线通过多个第六过孔电连接。
所述第一辅助电极、所述第二辅助电极与所述第一栅极同层同材料。
在一些实施例中，所述第一电极包括相对设置且电连接的第一子电极和第二子电极，所述第二子电极设置于所述第一子电极的远离所述衬底的一侧。所述显示基板还包括：层叠设置于所述第一子电极和所述第二子电极之间的滤光单元和平坦层；所述平坦层位于所述滤光单元的靠近所述第二子电极的一侧。
另一方面，本公开实施例提供一种显示装置，包括上述任一些实施例所述的显示基板。
又一方面，本公开实施例提供一种显示基板的制备方法。所述制备方法，包括：
在衬底上的显示区内形成位于每个亚像素中的像素驱动电路。所述像素驱动电路包括第一存储电容，所述第一存储电容包括相对设置的第一存储电极和第二存储电极。所述第一存储电极和所述第二存储电极均为透明电极。
在所述衬底上的每个所述亚像素中，形成位于所述像素驱动电路的远离所述衬底一侧的底发光型发光器件。所述发光器件包括第一电极。所述第一电极由所述第一存储电极复用构成。
在一些实施例中，所述像素驱动电路还包括第一晶体管，所述第一晶体管包括第一栅极、第一半导体有源图案、第一源极和第一漏极。所述第一晶体管为驱动晶体管。
形成所述像素驱动电路，还包括：在形成所述第一半导体有源图案的过程中，同步形成所述第二存储电极。
在一些实施例中，所述显示基板还包括栅线和数据线。所述像素驱动电路还包括第二晶体管，所述第二晶体管包括第二栅极、第二半导体有源图案、第二源极和第二漏极。
所述栅线的一部分复用为所述第二栅极。相应的，所述显示基板的制备方法，还包括：同步形成所述栅线和所述第一栅极。
所述第二源极与所述数据线电连接，所述第二漏极与所述第一栅极、所述第二存储电极电连接。相应的，所述显示基板的制备方法，还包括：同步形成所述第二半导体有源图案与所述第一半导体有源图案；同步形成所述第二源极、所述第二漏极、所述数据线、所述第一源极以及所述第一漏极。
在一些实施例中，所述显示基板还包括电源线和感测信号线。所述第一源极与所述电源线电连接，所述第一漏极与所述第一电极电连接。所述像素驱动电路还包括：第三晶体管；所述第三晶体管包括第三栅极、第三半导体有源图案、第三源极和第三漏极。所述第三源极通过第二连接电极与所述第一漏极电连接，且所述第三源极、所述第二连接电极和所述第一漏极为一体结构。所述第三漏极与感测信号线电连接。位于任一行亚像素中的所述第三晶体管的所述第三栅极，由距离所述第三晶体管最近的相邻行亚像素对应的所述栅线的一部分复用构成。
所述显示基板的制备方法，还包括：同步形成所述第三半导体有源图案与所述第一半导体有源图案；同步形成所述第三源极、所述第三漏极、所述电源线以及所述感测信号线。
在一些实施例中，所述显示基板的制备方法，还包括：在形成所述像素驱动电路之前，在所述衬底上同步形成第一金属图案和第二金属图案，以使得在形成所述像素驱动电路之后，所述第一半导体有源图案形成于所述第一金属图案的远离所述衬底的一侧，所述第二连接电极形成于所述第二金属图案的远离所述衬底的一侧。沿所述衬底的厚度方向，所述第一半导体有源图案在所述衬底上的正投影位于所述第一金属图案在所述衬底上的正投影内，所述第二金属图案与所述第二连接电极在所述衬底上的正投影至少部分重叠。所述第一金属图案和所述第二金属图案为一体结构，且所述第二金属图案通过第四过孔与所述第二连接电极电连接。所述第二金属图案与所述第三源极电连接。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为根据本公开一些实施例中的一种显示基板的部分区域的结构示意图；
图2a为根据本公开一些实施例中的一种底发光型发光器件的结构示意图；
图2b为根据本公开一些实施例中的另一种底发光型发光器件的结构示意图；
图3为根据本公开一些实施例中的一种像素驱动电路的等效电路图；
图4为图1所示的一种显示基板中一种亚像素S的结构示意图；
图5为图4所示的一种亚像素S在AA'向的剖面示意图；
图6为图4所示的一种亚像素S在BB'向的剖面示意图；
图7为图4所示的一种亚像素S在CC'向的剖面示意图；
图8为图4所示的一种亚像素S在DD'向的剖面示意图；
图9a为图4所示的一种亚像素S在EE'向的一种剖面示意图；
图9b为图4所示的一种亚像素S在EE'向的另一种剖面示意图；
图10为图4所示的一种亚像素S在FF'向的剖面示意图；
图11为图1所示的一种显示基板中另一种亚像素S的结构示意图；
图12为图11所示的一种亚像素S在GG'向的剖面示意图；
图13为图11所示的一种亚像素S在HH'向的剖面示意图；
图14为根据本公开一些实施例中的另一种显示基板的部分区域的结构示意图；
图15为图14所示的一种显示基板中一种亚像素S的结构示意图；
图16为图15所示的一种亚像素S在II'向的一种剖面示意图；
图17a为图15所示的一种亚像素S在JJ'向的一种剖面示意图；
图17b为图15所示的一种亚像素S在JJ'向的另一种剖面示意图；
图18为图15所示的一种亚像素S在KK'向的一种剖面示意图；
图19为图14所示的一种显示基板中R区域的一种结构示意图；
图20为图19所示的一种R区域中部分结构的示意图；
图21为根据本公开一些实施例中的一种显示基板的制备方法的流程示意图；
图22为根据本公开一些实施例中的一种显示装置的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”等序数仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“电连接”和“接触”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“电连接”或“接触”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
相关技术中，自发光显示基板的每个亚像素中均设置有像素驱动电路、以及与像素驱动电路电连接的发光器件。在单个亚像素的面积有限的情况下，像素驱动电路中的存储电容与发光器件分别位于亚像素的不同区域，导致存储电容与发光器件的电连接处会产生跨线，从而增加了串扰风险。在此基础上，若存储电容的正对面积设置的较大，则存储电容需要占用亚像素的面积也较大。这样对于底发光型的显示基板，像素驱动电路位于发光器件的出光侧，存储电容占用亚像素的面积较大容易导致亚像素的开口率较小，导致发光器件的发光面积较小。由此，在显示亮度相同的情况下，发光器件的发光面积越小，其需要的电流密度就越大，从而容易加快发光器件的老化速度，影响发光器件的寿命。而若将存储电容的正对面积设置的较小，则容易导致存储电容的电容量较小，进而出现显示基板显示画质不均的问题。
请参阅图1～图3，本公开一些实施例提供一种显示基板1。显示基板1具有显示区AA，显示基板1的显示区AA内设置有多个亚像素S。显示基板1包括：衬底10，以及设置于衬底10上显示区AA内且位于每个亚像素S中的像素驱动电路和底发光型发光器件110。像素驱动电路包括第一存储电容120。第一存储电容120包括相对设置的第一存储电极121和第二存储电极122。发光器件110包括与像素驱动电路中的第一存储电容120电连接的第一电极111。
在本公开实施例中，第一电极111复用为第一存储电极121，第一电极111与第二存储电极122均采用透明电极。
由于发光器件110为底发光型，即像素驱动电路位于发光器件110的出光侧，因而，本领域技术人员应该明白，在第一电极111复用为第一存储电极121的情况下，第二存储电极122位于第一存储电极121的靠近衬底10一侧。
需要说明的是，图1仅示意出显示基板1部分区域内亚像素S的分布及结构，其中，发光器件110的结构也仅作了部分示意。
可选的，如图2a和图2b所示，该发光器件110包括第一电极111和第二电极112，以及位于第一电极111和第二电极112之间的发光层113。
可选的，第一电极111为阳极，第二电极112为阴极；或者，第一电极111为阴极，第二电极112为阳极。
可以理解的是，在第一电极111为阳极，第二电极112为阴极的情况下，该发光器件110为正置。在第一电极111为阴极，第二电极112为阳极的情况下，该发光器件110为倒置。
在此基础上，如图2a所示，在第一电极111为阳极，第二电极112为阴极的情况下，该发光器件110还包括位于发光层113和第一电极111之间的空穴传输层114、位于发光层113和第二电极112之间的电子传输层115。当然，根据需要在一些实施例中，还可以在空穴传输层114和第一电极111之间设置空穴注入层，可以在电子传输层115和第二电极112之间设置电子注入层。
或者，如图2b所示，在第一电极111为阴极，第二电极112为阳极的情况下，该发光器件110还包括位于发光层113和第二电极112之间的空穴传输层114、位于发光层113和第一电极111之间的电子传输层115，当然，还可以在空穴传输层114和第二电极112之间设置空穴注入层，可以在电子传输层115和第一电极111之间设置电子注入层。
在此基础上，可选的，发光层113为有机发光层或者量子点发光层。
可选的，第一电极111的材料采用氧化铟锡(ITO)，第二电极112的材料采用金属银(Ag)。但并不仅限于此。
需要说明的是，本公开实施例后续涉及的像素驱动电路，以发光器件110为正置发光器件进行说明。此外，显示基板1中通常设置有像素界定层。发光器件110形成于像素界定层的对应开口内，可以利用像素界定层的开口面积限定亚像素S的发光面积。像素界定层的材料可以采用透光树脂材料。
在本公开实施例提供的显示基板1中，通过将发光器件110的第一电极111复用作第一存储电极121，并将第一电极111和第二存储电极122均设置为透明电极，可使第一存储电容120设置在发光器件110正对的区域，也即位于发光器件110的发光区且不影响发光器件110的出光效果。如此，一方面，发光器件110的第一电极111复用作第一存储电容120的第一存储电极121，可以避免发光器件110和第一存储电容120电连接时产生跨线，从而避免出现串扰风险。另一方面，在保证显示基板1正常显示的情况下，第一存储电容120可以不占用亚像素S的面积，这样在亚像素S的面积一定的情况下，可以使发光器件110占用亚像素S中较多的面积，从而提高亚像素S的开口率。再一方面，第一电极111与第二存储电极122均为透明电极，可以使得第二存储电极122的面积设置的尽可能的大，从而有效增加第一存储电容120的电容量，以避免显示基板1出现显示画质不均的问题。
当将本公开实施例中的显示基板1应用在8K高像素密度(Pixels Per Inch，PPI)的显示基板中之后，与相关技术中亚像素的平均开口率约为12％相比，该显示基板中亚像素的平均开口率可以提升至约17％左右，从而有效提升了约40％。此外，与相关技术中存储电容的电容值约为0.13pF相比，该显示基板中存储电容(即第一存储电容120)的电容值可以提升至0.17pF，从而有效提升了30％。
像素驱动电路的结构可以根据实际需求选择设置，例如采用图3中所示的3T1C的像素电路；也即，该像素电路可以由三个晶体管T和一个存储电容C构成，其中，三个晶体管分别为第一晶体管T1、第二晶体管T2和第三晶体管T3；存储电容C即为前述一些实施例中的第一存储电容120。当然，像素驱动电路还可以为包括其他数量的晶体管或其他数量的存储电容的结构，本公开实施例对此不作限定。
以下一些实施例以像素驱动电路为3T1C的像素电路为例进行说明。
可选的，单个亚像素S中像素驱动电路的结构如图3和图4所示，像素驱动电路还包括第一晶体管T1，第一晶体管T1为驱动晶体管。如图5所示，第一晶体管T1包括第一栅极131、第一半导体有源图案132、第一源极133和第一漏极134。
请结合图3～图5理解，第一源极133与电源线14电连接，第一漏极134与第一电极121电连接。
第一半导体有源图案132包括第一沟道区1320、第一源极区1321和第一漏极区1322，第一源极区1321和第一漏极区1322的导电性大于第一沟道区1320的导电性，且第一源极133与第一源极区1321接触，第一漏极134与第一漏极区1322接触。
第二存储电极122可以通过对半导体图案进行导体化得到，也即第二存储电极122可以为经过导体化处理后的半导体图案。基于此，第二存储电极122与第一源极区1321、第一漏极区1322同层同材料。
示例的，可以对半导体层采用离子注入的方式在其不同区域分别进行导体化，以形成第二存储电极122、以及第一半导体有源图案132中的第一源极区1321和第一漏极区1322。第一源极区1321和第一漏极区1322之间具有间隔，存在于该间隔内的半导体层的部分为第一半导体有源图案132中的第一沟道区1321。对半导体层注入的离子可以为硼离子或磷离子。
需要说明的是，图4和图5中的第一晶体管T1以顶栅型薄膜晶体管为例进行示意，在此情况下，如图5所示，第一半导体有源图案132设置于第一栅极131的靠近衬底10一侧，第一半导体有源图案132与第一栅极131通过第一栅绝缘图案135隔离，第一源极133和第一漏极134二者与第一栅极131之间通过层间绝缘层20隔离。
可选的，如图5所示，第一栅绝缘图案135与第一栅极131同步形成。基于此，第一源极133和第一漏极134分别通过贯穿层间绝缘层20的过孔与第一半导体有源图案132接触。
此处，同步形成是指采用同一次构图工艺制作形成，例如光掩膜(Mask)工艺。本公开实施例中涉及的全部的“同步形成”，均可照此理解，但并不仅限于此。
可以理解的是，在位于第一半导体有源图案132与第一栅极131之间的栅绝缘层未图案化的情况下，第一源极133和第一漏极134分别通过贯穿层间绝缘层20和栅绝缘层两层的过孔与第一半导体有源图案132接触。
请参阅图6，本公开实施例中，在制作第一晶体管T1的第一半导体有源图案132的同时制作半导体图案，并通过对半导体图案导体化得到上述第二存储电极122，可以在不额外增加构图工艺的基础上，形成第二存储电极122。
在此基础上，可选的，如图4、图7、图11和图12所示，像素驱动电路还包括第二晶体管T2，第二晶体管T2包括第二栅极151、第二半导体有源图案152、第二源极153和第二漏极154。
需要说明的是，图4和图7中的第二晶体管T2以顶栅型薄膜晶体管为例进行示意，在此情况下，第二半导体有源图案152设置于第二栅极151的靠近衬底10一侧，第二半导体有源图案152与第二栅极151通过第二栅绝缘图案155隔离，第二源极153和第二漏极154二者与第二栅极151之间通过层间绝缘层20隔离。
如图7所示，第二栅绝缘图案155与第二栅极151同步形成。基于此，第二源极153和第二漏极154分别通过贯穿层间绝缘层20的过孔与第二半导体有源图案152接触。此外，与第一晶体管T1类似，在位于第二半导体有源图案152与第二栅极151之间的栅绝缘层未图案化的情况下，第二源极153和第二漏极154分别通过贯穿层间绝缘层20和栅绝缘层两层的过孔与第二半导体有源图案152接触。
在一些实施例中，如图4和图11所示，栅线16中的一部分复用为第二栅极151， 可以有效减小像素驱动电路在亚像素S中占用的面积，提高亚像素的开口率。此外，第二源极153与数据线17电连接。第二漏极154、第二存储电极122和第一栅极151电连接。
在一种可能的实施方式中，如图4和图8所示，显示基板1还包括第一连接电极156。第二漏极154与第一连接电极156电连接，且二者为一体结构。第一连接电极156通过第一过孔1311与第二存储电极122、第一栅极131电连接。
可选的，如图4所示，第二漏极154与第一栅极131在第一方向(例如Y方向)上具有间隔。第一栅极131沿第二方向(例如X方向)延伸。此处，第一方向和第二方向垂直或大致垂直。这也就是说，第一方向和第二方向之间的夹角为90°或在90°左右，例如略小于90°或略大于90°。在此基础上，第一连接电极156沿第一方向延伸。第一连接电极156的与第二漏极154电连接的部分在第二方向上的尺寸、小于第一连接电极156的与第一栅极131电连接的部分在第二方向上的尺寸。如此，有利于减小像素驱动电路在亚像素S中占用的面积，以提高亚像素的开口率。
在另一种可能的实施方式中，如图11和图12所示，第二半导体有源图案152的结构与第一半导体有源图案132相似，二者同步形成。第二半导体有源图案152包括第二沟道区1520、第二源极区1521和第二漏极区1522。第二源极153与第二源极区1521接触，第二漏极154与第二漏极区1522接触。第二存储电极122与第二半导体有源图案152中的第二漏极区1522接触，且第二存储电极122与第二漏极区1522为一体结构。此外，如图12和图13所示，第二存储电极122与第一栅极131通过第二过孔1322电连接。
可选的，如图11所示，第二漏极154与第一栅极131在第一方向(即Y方向)上具有间隔。第一栅极131沿第二方向(即X方向)延伸。此处，第一方向和第二方向垂直或大致垂直。这也就是说，第一方向和第二方向之间的夹角为90°或在90°左右，例如略小于90°或略大于90°。在此基础上，结合图11和图12理解，第二存储电极122包括：沿第一方向延伸、且与第二漏极区1522电连接的延伸部1220。延伸部1220的与第二漏极区1522电连接的部分在第二方向上的尺寸、小于延伸部1220的与第一栅极131电连接的部分在第二方向上的尺寸。如此，有利于减小像素驱动电路在亚像素S中占用的面积，以提高亚像素的开口率。
需要说明的是，图11和图12中的第二晶体管T2以顶栅型薄膜晶体管为例进行了示意。在此情况下，第二半导体有源图案152设置于第二栅极151的靠近衬底10一侧，第二栅极151与第二半导体有源图案152通过未图案化的第二栅绝缘层157隔离，第二源极153和第二漏极154与第二栅极151之间通过层间绝缘层20隔离。如图12所示，第二源极153和第二漏极154分别通过贯穿层间绝缘层20和第二栅绝缘层157两层的过孔与第二半导体有源图案152接触。
可选的，如图4和图11所示，第一晶体管T1的第一源极133与电源线14电连接，第一漏极134与第一电极111电连接。电源线14用于给像素驱动电路供电。
可选的，如图4所示，在像素驱动电路包括第二晶体管T2的情况下，像素驱动电路还包括第三晶体管T3。基于此，如图4和图10所示，第三晶体管T3包括第三栅极181、第三半导体有源图案182、第三源极183和第三漏极184。
需要说明的是，图4和图10中的第三晶体管T3以顶栅型薄膜晶体管为例进行了示意。在此情况下，第三半导体有源图案182设置于第三栅极181的靠近衬底10一侧，第三半导体有源图案182与第三栅极181通过第三栅绝缘图案185隔离，第三源极183和第三漏极184二者与第三栅极181之间通过层间绝缘层20隔离。在第一栅绝缘图案135与第一栅极131同步形成的情况下，如图10所示，第三栅绝缘图案185与第三栅极181同步形成。基于此，第三源极183和第三漏极184分别通过贯穿层间绝缘层20的过孔与第三半导体有源图案182接触。此外，与第一晶体管T1类似，在位于第三半导体有源图案182与第三栅极181之间的栅绝缘层未图案化的情况下，第三源极183和第三漏极184分别通过贯穿层间绝缘层20和栅绝缘层两层的过孔与第三半导体有源图案182接触。第三半导体有源图案182的结构与第二半导体有源图案152相似，此处不再详述。
在一些实施例中，如图4和图11所示，第一晶体管T1和第三晶体管T3位于第一存储电容120的沿第一方向(即Y方向)的两侧。显示基板1还包括第二连接电极186。第三源极183通过第二连接电极186与第一漏极134电连接，且第三源极183、第二连接电极186和第一漏极134为一体结构。如图1所示，显示基板1还包括感测信号线19。第三漏极184与感测信号线19电连接。
请结合图4、图9a和图10理解，第二连接电极186通过第三过孔1811与第一电极111电连接。即，第二连接电极186用于实现第一电极111、第二漏极134和第三源极183之间的电连接。
当像素驱动电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3和第一存储电容120时，其等效电路图如图3所示。基于此，可通过感测信号线19感测第一晶体管T1的参数，进而通过外部方式对第一晶体管T1的阈值电压进行补偿。
在上述基础上，示例的，第一栅极131、第二栅极151、第三栅极181，第一源极133、第二源极153、第三源极183、第一漏极134、第二漏极154、第三漏极184以及栅线16、数据线17、电源线14、感测信号线19的材料，可以选自铜(Cu)、铝(Al)、钼(Mo)、钛(Ti)、铬(Cr)和钨(W)的金属单质以及由这些金属单质构成的金属合金中的至少一种。
示例的，第一栅绝缘图案136，第二栅绝缘图案155、第三栅绝缘图案185和层间绝缘层157的材料可以选自氮化硅(SiNx)和二氧化硅(SiO2)等无机氧化物中的一种或多种，且第一栅绝缘图案136，第二栅绝缘图案155、第三栅绝缘图案185和层间绝缘层157可以采用单层结构或多层层叠结构。第一半导体有源图案132、第二半导体有源图案152和第三半导体有源图案182中的半导体材料可以选自透明半导体氧化物，例如铟锌氧化物(IGZO)。
可选的，如图1所示，位于任一行亚像素S中第三晶体管T3的第三栅极181，由距离第三晶体管T3最近的相邻行亚像素对应的栅线16的一部分复用构成。从而有利于在多个亚像素S阵列排布的情况下，减小像素驱动电路在亚像素S中占用的面积，以提高亚像素的开口率。
在第一晶体管T1为顶栅型薄膜晶体管的情况下，可选的，请结合图14～图16理解，显示基板1还包括：设置于第一半导体有源图案132的靠近衬底10一侧的第一金 属图案1313。沿衬底10的厚度方向，第一半导体有源图案131在衬底10上的正投影位于第一金属图案1313在衬底10上的正投影内。此外，第一半导体有源图案132与第一金属图案1313之间通过绝缘层1314隔离。
在此基础上，请结合图14～图17a以及图20理解，显示基板1还包括第二金属图案1851。沿衬底10的厚度方向，第二金属图案1851与第二连接电极186在衬底10上的正投影至少部分重叠。第一金属图案1313和第二金属图案1851为一体结构。第二金属图案1851通过第四过孔1852和第二连接电极186电连接。由于第二连接电极186通过第三过孔1811与第一电极111电连接，因此，第二金属图案1851与第一电极111也电连接。
此外，可选的，像素驱动电路中的存储电容C包括第一存储电容120、以及与第一存储电容120并联的第二存储电容123。如此，第二存储电容123可以由第二存储电极122和第二金属图案1851中每者的至少一部分构成。也即，第二存储电容123的两个电极可以由第二存储电极122的至少一部分和第二金属图案1851的至少一部分复用构成。
在本公开实施例中，一方面，第一金属图案1313可以防止外界光线入射至第一半导体有源图案132，从而避免外界光线对第一晶体管T1的性能产生不良影响。另一方面，通过设置第二金属图案1851，可以利用第二存储电极122和第二金属图案1851构成与第一存储电容120并联的第二存储电容123，使得像素驱动电路的存储电容C包括第一存储电容120与第二存储电容123，从而可以增大像素驱动电路中存储电容C的电容量，进一步避免显示基板1出现画质不均的问题。此外，第二金属图案1851与第二连接电极186在衬底10上的正投影重叠，还可以避免第二金属图案1851影响亚像素S的开口率。
可选的，第一晶体管T1、第二晶体管T2和第三晶体管T3均为顶栅型薄膜晶体管，方便于在衬底上完成像素驱动电路的制作。
可选的，如图1和图14所示，电源线14、感测信号线19以及数据线17平行且同层设置，有利于简化显示基板1中各信号线的布线设计。
在一些实施例中，如图14所示，每行亚像素中，每相邻的两个亚像素S为一组，每组的两个亚像素S之间设置有两根数据线17。每组亚像素的一侧设置有一根电源线14，相对的另一侧设置有一根感测信号线19，且该电源线14和该感测信号线19间隔设置。
针对每行亚像素，位于电源线14的一侧且靠近该电源线14的两个亚像素中的像素驱动电路、以及位于该电源线14的另一侧且靠近该电源线14的两个亚像素中的像素驱动电路，均与该电源线14连接。
针对每行亚像素，位于感测信号19的一侧且靠近该感测信号线19的两个亚像素中的像素驱动电路、以及位于该感测信号线19的另一侧且靠近该感测信号线19的两个亚像素中的像素驱动电路，均与该感测信号线19连接。
在此基础上，可以减少电源线14和感测信号线19的总数量，从而简化显示基板1的制作工艺。
可选的，如图15和图18、图19所示，显示基板1还包括：针对任一根电源线14 设置的第一辅助电极141。沿衬底10的厚度方向，第一辅助电极141在衬底10上的正投影位于电源线14在衬底10上的正投影内。第一辅助电极141与电源线14通过多个第五过孔1411电连接，也即，第一辅助电极141与电源线14并联。如此，有利于减小电源线14的等效电阻，从而降低电源线14所传输信号的损耗。
此外，如图19所示，显示基板1还包括：针对任一根感测信号线19设置的第二辅助电极191。沿衬底10厚度方向，第二辅助电极191在衬底10上的正投影位于感测信号线19在衬底10上的正投影内。第二辅助电极191与感测信号线19通过多个第六过孔1911电连接，也即，第二辅助电极191与感测信号线19并联。如此，有利于减小感测信号线19的等效电阻，从而降低感测信号线19所传输信号的损耗。
第一辅助电极141、第二辅助电极191与第一栅极131同层同材料。基于此，可以在制作第一栅极131的同时制作第一辅助电极141和第二辅助电极191，从而简化显示基板1的制作工艺。
在一些实施例中，显示基板1还包括设置于每个亚像素S中的滤光单元，以利用滤光单元实现显示基板1的彩色化显示。基于此，可选的，如图4和图9b、以及图15和图17b所示，第一电极111包括电连接的第一子电极1111和第二子电极1112，第二子电极1112设置于第一子电极1111的远离衬底10的一侧。显示基板1还包括：层叠设置于第一子电极1111和第二子电极1112之间的滤光单元30和平坦层40；平坦层40位于滤光单元30的靠近第二子电极1112的一侧。第二子电极1112形成于平坦层40的远离滤光单元30的表面上，利于确保形成于第二子电极1112上的发光层113具有较好的平面度，从而确保显示基板1出光均匀。
此外，可选的，滤光单元30为彩色滤光膜。
本公开实施例提供一种显示基板1的制备方法。例如图21中所示，该显示基板1的制备方法包括：S10～S20。
S10、如图1和图4所示，在衬底10上的显示区内形成位于每个亚像素S中的像素驱动电路。像素驱动电路包括第一存储电容120。第一存储电容120包括相对设置的第一存储电极121和第二存储电极122。第一存储电极121和第二存储电极122均为透明电极。
像素驱动电路的结构如前述一些实施例中所示，此处不再详述。
S20、在衬底10上的每个亚像素S中，形成位于像素驱动电路的远离衬底10一侧的底发光型发光器件。
如图2a和图2b所示，发光器件110包括第一电极111。如图1和图4所示，第一电极111由第一存储电极121复用构成。
本公开实施例提供的显示基板1的制备方法所能实现的有益效果，与上述实施例提供的显示基板1所能达到的有益效果相同，在此不做赘述。
可选的，如图4～图5所示，像素驱动电路还包括第一晶体管T1。第一晶体管T1包括第一栅极131、第一半导体有源图案132、第一源极133和第一漏极134。第一晶体管T1为驱动晶体管。
第一半导体有源图案132和第二存储电极122的结构如前述一些实施例中所示。S10中，形成像素驱动电路，还包括：在形成第一半导体有源图案132的过程中，同 步形成第二存储电极122。从而可以简化像素驱动电路的制作工艺。
可选的，如图4和图7所示，显示基板1还包括栅线16和数据线17。像素驱动电路还包括第二晶体管T2。第二晶体管T2包括第二栅极151、第二半导体有源图案152、第二源极153和第二漏极154。第二半导体有源图案152的结构如前述一些实施例中所示。
每个亚像素S对应一条栅线16，该栅线16的一部分可以复用为第二栅极151。如此，显示基板1的制备方法，还包括：在执行S10的过程中，同步形成栅线16和第一栅极131。从而可以简化显示基板的制作工艺。
第二源极153与数据线17电连接，第二漏极154与第一栅极131、第二存储电极122电连接。如此，显示基板1的制备方法，还包括：在执行S10的过程中，同步形成第二半导体有源图案152与第一半导体有源图案132；以及，同步形成第二源极153、第二漏极154、数据线17、第一源极133以及第一漏极134。从而可以简化显示基板的制作工艺。
在此基础上，如图4和图10所示，显示基板1还包括电源线14和感测信号线19。第一源极133与电源线14电连接，第一漏极134与第一电极111电连接。像素驱动电路还包括：第三晶体管T3。第三晶体管T3包括第三栅极181、第三半导体有源图案182、第三源极183和第三漏极184。第三源极183通过第二连接电极186与第一漏极134电连接，且第三源极183、第二连接电极186和第一漏极134为一体结构。第三漏极184与感测信号线19电连接。
此外，如图1所示，位于任一行亚像素S中的第三晶体管T3的第三栅极181，可以由距离第三晶体管T3最近的相邻行亚像素S对应的栅线16的一部分复用构成。
如此，显示基板1的制备方法，还包括：在执行S10的过程中，同步形成第三半导体有源图案182与第一半导体有源图案132；以及，同步形成第三源极183、第三漏极184、电源线14以及感测信号线19。从而可以进一步简化显示基板的制作工艺。
可选的，如图14～图16以及图20所示，在显示基板1还包括第一金属图案1313和第二金属图案1851的情况下，显示基板1的制备方法还包括：在执行S10之前，在衬底10上同步形成第一金属图案1313和第二金属图案1851，以使得执行S10之后，第一半导体有源图案132形成于第一金属图案1313的远离衬底10的一侧，第二连接电极186形成于第二金属图案1851的远离衬底10的一侧。
第一金属图案1313和第二金属图案1851的结构和功能如前一些实施例中所述，此处不再详述。示例的，沿衬底10的厚度方向，第一半导体有源图案132在衬底10上的正投影位于第一金属图案1313在衬底10上的正投影内，第二金属图案1851与第二连接电极186在衬底10上的正投影至少部分重叠。第一金属图案1313和第二金属图案1851为一体结构，第二金属图案1851通过第四过孔1852和第二连接电极186电连接。第二金属图案1851与第三源极183电连接。
本公开实施例提供一种显示装置。例如图22中所示，该显示装置1000包括上述任一些实施例所述的显示基板1。本公开实施例提供的显示装置1000所能实现的有益效果，与上述实施例提供的显示基板1所能达到的有益效果相同，在此不做赘述。
在一些实施例中，显示装置1000为OLED显示面板、OLED显示器、OLED电视 机、手机、平板电脑、笔记本电脑、电子纸、数码相框或导航仪等具有显示功能的产品或部件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种显示基板，包括：衬底，以及设置于所述衬底上的显示区内且位于每个亚像素中的像素驱动电路和底发光型发光器件；所述发光器件包括与所述像素驱动电路电连接的第一电极；
    所述像素驱动电路包括第一存储电容，所述第一存储电容包括相对设置的第一存储电极和第二存储电极；
    所述第一电极复用为所述第一存储电极；所述第二存储电极和所述第一电极均为透明电极。
  2. 根据权利要求1所述的显示基板，还包括：电源线；
    所述像素驱动电路还包括第一晶体管，所述第一晶体管包括第一栅极、第一半导体有源图案、第一源极和第一漏极；所述第一晶体管为驱动晶体管；
    所述第一源极与电源线电连接，所述第一漏极与所述第一电极电连接；
    所述第一半导体有源图案包括第一沟道区、第一源极区和第一漏极区，所述第一源极区和所述第一漏极区的导电性大于所述第一沟道区的导电性，且所述第一源极与所述第一源极区接触，所述第一漏极与所述第一漏极区接触；
    所述第二存储电极为经过导体化处理后的半导体图案，其中，所述第二存储电极与所述第一源极区和所述第一漏极区同层同材料。
  3. 根据权利要求2所述的显示基板，还包括：栅线和数据线；
    所述像素驱动电路还包括第二晶体管，所述第二晶体管包括第二栅极、第二半导体有源图案、第二源极和第二漏极；
    所述栅线中的一部分复用为所述第二栅极；
    所述第二源极与所述数据线电连接；所述第二漏极与所述第二存储电极、所述第一栅极电连接。
  4. 根据权利要求3所述的显示基板，还包括：第一连接电极；
    所述第一连接电极与所述第二漏极为一体结构，且所述第一连接电极通过第一过孔与所述第二存储电极、所述第一栅极分别电连接。
  5. 根据权利要求4所述的显示基板，其中，
    所述第二漏极与所述第一栅极在第一方向上具有间隔；所述第一栅极沿第二方向延伸；所述第一方向和所述第二方向垂直或大致垂直；
    所述第一连接电极沿所述第一方向延伸；所述第一连接电极的与所述第二漏极电连接的部分在所述第二方向上的尺寸、小于所述第一连接电极的与所述第一栅极电连接的部分在所述第二方向上的尺寸。
  6. 根据权利要求3所述的显示基板，其中，所述第二半导体有源图案包括第二沟道区、第二源极区和第二漏极区；所述第二源极与所述第二源极区接触，所述第二漏极与所述第二漏极区接触；
    所述第二存储电极与所述第二漏极区为一体结构；
    所述第二存储电极与所述第一栅极通过第二过孔电连接。
  7. 根据权利要求6所述的显示基板，其中，
    所述第二漏极与所述第一栅极在第一方向上具有间隔；所述第一栅极沿第二方向延伸；所述第一方向和所述第二方向垂直或大致垂直；
    所述第二存储电极包括：沿所述第一方向延伸、且与所述第二漏极区电连接的延伸部；所述延伸部的与所述第二漏极区电连接的部分在第二方向上的尺寸、小于所述延伸部的与所述第一栅极电连接的部分在所述第二方向上的尺寸。
  8. 根据权利要求2～7中任一项所述的显示基板，其中，在所述像素驱动电路包括第二晶体管的情况下，所述像素驱动电路还包括第三晶体管，所述第三晶体管包括第三栅极、第三半导体有源图案、第三源极和第三漏极；
    所述第一晶体管和所述第三晶体管位于所述第一存储电容的沿第一方向的两侧；
    所述显示基板，还包括：第二连接电极和感测信号线；
    所述第三源极通过所述第二连接电极与所述第一漏极电连接，且所述第三源极、所述第二连接电极和所述第一漏极为一体结构；
    所述第三漏极与所述感测信号线电连接；
    所述第二连接电极通过第三过孔与所述第一电极电连接。
  9. 根据权利要求8所述的显示基板，其中，位于任一行亚像素中的所述第三晶体管的所述第三栅极，由距离所述第三晶体管最近的相邻行亚像素对应的所述栅线的一部分复用构成。
  10. 根据权利要求8所述的显示基板，其中，
    所述第一晶体管为顶栅型薄膜晶体管；
    所述显示基板，还包括：设置于所述第一半导体有源图案的靠近所述衬底一侧的第一金属图案；沿所述衬底的厚度方向，所述第一半导体有源图案在所述衬底上的正投影位于所述第一金属图案在所述衬底上的正投影内；
    所述显示基板，还包括：第二金属图案；沿所述衬底的厚度方向，所述第二金属图案与所述第二连接电极在所述衬底上的正投影至少部分重叠；
    所述第一金属图案和所述第二金属图案为一体结构；
    所述第二金属图案通过第四过孔与所述第二连接电极电连接；
    所述像素驱动电路还包括第二存储电容，所述第二存储电容由所述第二存储电极和所述第二金属图案中每者的至少一部分构成。
  11. 根据权利要求10所述的显示基板，其中，在所述显示基板还包括数据线的情况下，所述电源线、所述感测信号线以及所述数据线平行且同层设置；
    每行所述亚像素中，每相邻的两个所述亚像素为一组，每组的两个所述亚像素之间设置有两根所述数据线；每组所述亚像素的一侧设置有一根所述电源线，相对的另一侧设置有一根所述感测信号线，且所述电源线和所述感测信号线间隔设置；
    针对每行所述亚像素，位于所述电源线的一侧且靠近所述电源线的两个所述亚像素中的所述像素驱动电路、以及位于所述电源线的另一侧且靠近所述电源线的两个所述亚像素中的所述像素驱动电路，均与所述电源线连接；
    针对每行所述亚像素，位于所述感测信号线的一侧且靠近所述感测信号线的两个所述亚像素中的所述像素驱动电路、以及位于所述感测信号线的另一侧且靠近所述感测信号线的两个所述亚像素中的所述像素驱动电路，均与所述感测信号线连接。
  12. 根据权利要求11所述的显示基板，还包括：针对任一根所述电源线设置的第一辅助电极，以及针对任一根所述感测信号线设置的第二辅助电极；
    沿所述衬底的厚度方向，所述第一辅助电极在所述衬底上的正投影位于所述电源线在所述衬底上的正投影内；所述第一辅助电极与所述电源线通过多个第五过孔电连接；
    沿所述衬底的厚度方向，所述第二辅助电极在所述衬底上的正投影位于所述感测信号线在所述衬底上的正投影内；所述第二辅助电极与所述感测信号线通过多个第六过孔电连接；
    所述第一辅助电极、所述第二辅助电极与所述第一栅极同层同材料。
  13. 根据权利要求1～12中任一项所述的显示基板，其中，所述第一电极包括相对 设置且电连接的第一子电极和第二子电极，所述第二子电极设置于所述第一子电极的远离所述衬底的一侧；
    所述显示基板，还包括：层叠设置于所述第一子电极和所述第二子电极之间的滤光单元和平坦层；所述平坦层位于所述滤光单元的靠近所述第二子电极的一侧。
  14. 一种显示装置，包括如权利要求1-13中任一项所述的显示基板。
  15. 一种显示基板的制备方法，包括：
    在衬底上的显示区内形成位于每个亚像素中的像素驱动电路；所述像素驱动电路包括第一存储电容，所述第一存储电容包括相对设置的第一存储电极和第二存储电极；所述第一存储电极和所述第二存储电极均为透明电极；
    在所述衬底上的每个所述亚像素中，形成位于所述像素驱动电路的远离所述衬底一侧的底发光型发光器件；
    所述发光器件包括第一电极，所述第一电极由所述第一存储电极复用构成。
  16. 根据权利要求15所述的显示基板的制备方法，其中，所述像素驱动电路还包括第一晶体管，所述第一晶体管包括第一栅极、第一半导体有源图案、第一源极和第一漏极；所述第一晶体管为驱动晶体管；
    形成所述像素驱动电路，还包括：
    在形成所述第一半导体有源图案的过程中，同步形成所述第二存储电极。
  17. 根据权利要求16所述的显示基板的制备方法，其中，所述显示基板还包括栅线和数据线；所述像素驱动电路还包括第二晶体管，所述第二晶体管包括第二栅极、第二半导体有源图案、第二源极和第二漏极；
    其中，所述栅线的一部分复用为所述第二栅极；
    所述显示基板的制备方法，还包括：
    同步形成所述栅线和所述第一栅极；
    其中，所述第二源极与所述数据线电连接，所述第二漏极与所述第一栅极、所述第二存储电极电连接；
    所述显示基板的制备方法，还包括：
    同步形成所述第二半导体有源图案与所述第一半导体有源图案；
    同步形成所述第二源极、所述第二漏极、所述数据线、所述第一源极以及所述第一漏极。
  18. 根据权利要求17所述的显示基板的制备方法，其中，
    所述显示基板还包括电源线；所述第一源极与所述电源线电连接，所述第一漏极与所述第一电极电连接；
    所述显示基板还包括感测信号线；所述像素驱动电路还包括：第三晶体管；所述第三晶体管包括第三栅极、第三半导体有源图案、第三源极和第三漏极；
    其中，所述第三源极通过第二连接电极与所述第一漏极电连接，且所述第三源极、所述第二连接电极和所述第一漏极为一体结构；
    所述第三漏极与感测信号线电连接；
    位于任一行亚像素中的所述第三晶体管的所述第三栅极，由距离所述第三晶体管最近的相邻行亚像素对应的所述栅线的一部分复用构成；
    所述显示基板的制备方法，还包括：
    同步形成所述第三半导体有源图案与所述第一半导体有源图案；
    同步形成所述第三源极、所述第三漏极、所述电源线以及所述感测信号线。
  19. 根据权利要求18所述的显示基板的制备方法，还包括：
    在形成所述像素驱动电路之前，在所述衬底上同步形成第一金属图案和第二金属 图案，以使得在形成所述像素驱动电路之后，所述第一半导体有源图案形成于所述第一金属图案的远离所述衬底的一侧，所述第二连接电极形成于所述第二金属图案的远离所述衬底的一侧；
    其中，沿所述衬底的厚度方向，所述第一半导体有源图案在所述衬底上的正投影位于所述第一金属图案在所述衬底上的正投影内，所述第二金属图案与所述第二连接电极在所述衬底上的正投影至少部分重叠；所述第一金属图案和所述第二金属图案为一体结构，且所述第二金属图案通过第四过孔与所述第二连接电极电连接；所述第二金属图案与所述第三源极电连接。
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