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WO2020224143A1 - 显示面板及其制作方法 - Google Patents

显示面板及其制作方法 Download PDF

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Publication number
WO2020224143A1
WO2020224143A1 PCT/CN2019/105149 CN2019105149W WO2020224143A1 WO 2020224143 A1 WO2020224143 A1 WO 2020224143A1 CN 2019105149 W CN2019105149 W CN 2019105149W WO 2020224143 A1 WO2020224143 A1 WO 2020224143A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
active region
display panel
dielectric layer
Prior art date
Application number
PCT/CN2019/105149
Other languages
English (en)
French (fr)
Inventor
韩佰祥
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/621,259 priority Critical patent/US11315996B2/en
Publication of WO2020224143A1 publication Critical patent/WO2020224143A1/zh

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/121Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/121Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/1201Manufacture or treatment

Definitions

  • This application relates to the field of electronic display, and in particular to a display panel and a manufacturing method thereof.
  • the 3T1C pixel drive circuit is the most commonly used drive circuit in OLED display panels.
  • Fig. 1 and Fig. 2 show a circuit diagram and a schematic structural diagram of a 3T1C pixel driving circuit in the prior art.
  • the light emitting diode 020 can only be placed in the metal avoidance area. That is, the first thin film transistor 010, the second thin film transistor 011, the third thin film transistor 012, the storage capacitor 030, and the light emitting diode 020 are arranged in parallel, and their projections on the horizontal plane do not overlap. Such an arrangement results in a large layout area occupied by each driving circuit. On the one hand, the resolution of the display panel cannot be increased, and on the other hand, the aperture ratio of the display panel is low and the display effect is poor.
  • the present application provides a display panel and a manufacturing method thereof to improve the aperture ratio and resolution of the bottom-emitting display panel.
  • the present application provides a display panel including a first thin film transistor and a second thin film transistor, a storage capacitor and a light emitting structure connected in parallel; wherein,
  • the projection of the first thin film transistor on the light exit surface of the display panel overlaps the projection of the second thin film transistor on the light exit surface of the display panel;
  • the light emitting structure is electrically connected to the first thin film transistor or the second thin film transistor, and the projection of the light emitting structure on the light emitting surface of the display panel is in line with the first thin film transistor and the second thin film transistor.
  • the projections on the light-emitting surface of the display panel do not overlap;
  • the storage capacitor is located under the light-emitting structure, and the projection of the storage capacitor on the light-emitting surface of the display panel overlaps with the projection of the light-emitting structure on the light-emitting surface of the display panel.
  • the first thin film transistor and the second thin film transistor connected in parallel share the same metal gate.
  • the first thin film transistor is a top-gate thin film transistor; wherein, the first thin film transistor includes a first active region and a first source and drain metal, and the first active region and The first source and drain metals are located on the same side of the metal gate.
  • the first thin film transistor includes
  • a substrate, the first active region is located on the substrate
  • a first gate dielectric layer, the first gate dielectric layer is located on the first active region, and the metal gate is located on the first gate dielectric layer;
  • a first interlayer dielectric layer covering the first active region and the metal gate;
  • the first source/drain metal is located on the first interlayer dielectric layer, and is electrically connected to the first active region through a first through hole penetrating the first interlayer dielectric layer.
  • the second thin film transistor is a back-gate thin film transistor; wherein, the second thin film transistor includes a second active region and a second source and drain metal, and the second active region and The second source and drain metals are located on both sides of the metal gate.
  • the second thin film transistor includes:
  • a second gate dielectric layer, the second gate dielectric layer is located on the metal gate
  • a second active region, the second active region is located on the second gate dielectric layer
  • a second interlayer dielectric layer covering the second active region
  • the second source/drain metal is located on the second interlayer dielectric layer, and is electrically connected to the second active region through a second through hole penetrating the second interlayer dielectric layer.
  • the anode of the light-emitting structure is a transparent electrode
  • the cathode of the light-emitting structure is a reflective electrode
  • the first electrode plate of the storage capacitor and the first active region of the first thin film transistor are spaced apart, and the material constituting the first electrode plate is different from the first active region constituting the first active region.
  • the materials of the zones are the same.
  • the second electrode plate of the storage capacitor and the second active region of the second thin film transistor are spaced apart, and the material constituting the second electrode plate is different from the material constituting the second active region.
  • the materials of the zones are the same.
  • the present application also provides a manufacturing method of a display panel, the method includes the following steps:
  • a light emitting structure is formed on the planarization layer.
  • the projection of the first active region on the substrate completely covers the projection of the second active region on the substrate.
  • the areas of the first plate and the second plate of the storage capacitor are equal.
  • the projection of the first plate of the storage capacitor on the substrate overlaps the projection of the second plate on the substrate.
  • the projection of the light-emitting structure on the substrate overlaps the projection of the first plate on the substrate.
  • the method of forming the light-emitting structure includes the following steps:
  • a cathode covering the luminescent material is formed.
  • the present application stacks two transistors of the 3T1C pixel driving circuit to save the area of one transistor.
  • the storage capacitor is arranged under the light emitting structure, which increases the aperture ratio of the pixel.
  • the present application optimizes the device structure without increasing the process complexity, and greatly improves the current situation. There are technical bottom-emitting display panel performance.
  • FIG. 1 is a circuit diagram of a 3T1C pixel driving circuit in the prior art
  • FIG. 2 is a schematic diagram of the structure of some elements of the 3T1C pixel driving circuit in FIG. 1;
  • FIG. 3 is a schematic diagram of the structure of the 3T1C pixel driving circuit after the active area is fabricated in an embodiment of the application;
  • FIG. 4 is a schematic diagram of the structure of the 3T1C pixel driving circuit in an embodiment of the application after the source and drain wiring layers are fabricated;
  • FIG. 5 is a schematic diagram of the structure of the 3T1C pixel driving circuit in an embodiment of the application after the filter is manufactured;
  • FIG. 6 is a schematic diagram of the structure of the 3T1C pixel driving circuit in an embodiment of the application after the anode is manufactured;
  • FIG. 7 is a schematic structural diagram of the 3T1C pixel driving circuit after the light-emitting structure in an embodiment of the application is completed;
  • FIG. 8 is a circuit diagram of the 3T1C pixel driving circuit in FIG. 7.
  • FIG. 1 is a circuit diagram of a 3T1C pixel driving circuit in the prior art
  • FIG. 2 is a schematic structural diagram of some elements of the 3T1C pixel driving circuit in FIG. 1.
  • the 3T1C pixel driving circuit in the prior art includes a driving thin film transistor 010, a light emitting structure 020, a first thin film transistor 011, a second thin film transistor 012, and a storage capacitor 030. Since both thin film transistors and storage capacitors contain opaque metal materials, the light emitting diode 020 can only be arranged in the metal avoidance area.
  • the first thin film transistor 011, the light emitting structure 020 and the storage capacitor 030 are arranged in parallel.
  • the driving thin film transistor 010 and the second thin film transistor 012 not shown in FIG. 2 are also arranged in parallel with the light emitting structure 020.
  • the projections of the first thin film transistor 010, the second thin film transistor 011, the third thin film transistor 012, the storage capacitor 030 and the light emitting diode 020 on the horizontal plane do not overlap.
  • Such an arrangement results in a large layout area occupied by each driving circuit.
  • the resolution of the display panel cannot be increased, and on the other hand, the aperture ratio of the display panel is low and the display effect is poor.
  • the present application provides a display panel and a manufacturing method thereof to improve the aperture ratio and resolution of the bottom emission display panel.
  • FIG. 7 is a schematic structural diagram of a 3T1C pixel driving circuit in an embodiment of the application
  • FIG. 8 is a circuit diagram of the 3T1C pixel driving circuit in FIG. 7.
  • the display panel includes a first thin film transistor 011 and a second thin film transistor 012 connected in parallel, a driving thin film transistor 010, a storage capacitor 030, and a light emitting structure 020.
  • the projection of the first thin film transistor 011 on the light-emitting surface of the display panel overlaps with the projection of the second thin film transistor 012 on the light-emitting surface of the display panel.
  • the light emitting structure 020 is electrically connected to the first thin film transistor 011 or the second thin film transistor 012, and the projection of the light emitting structure 020 on the light emitting surface of the display panel is the same as that of the first thin film transistor 011 and The projection of the second thin film transistor 012 on the light-emitting surface of the display panel does not overlap.
  • the storage capacitor 030 is located under the light-emitting structure 020, and the projection of the storage capacitor 030 on the light-emitting surface of the display panel overlaps with the projection of the light-emitting structure 020 on the light-emitting surface of the display panel.
  • the first thin film transistor 011 and the second thin film transistor 012 connected in parallel share the same metal gate 132.
  • the first thin film transistor 011 is a top-gate thin film transistor.
  • the first thin film transistor 011 includes a first active region 121 and a first source/drain metal 171, and the first active region 121 and the first source/drain metal 171 are located on the same side of the metal gate 132.
  • the first thin film transistor 011 further includes: a first gate dielectric layer 131 of the substrate 11 and a first interlayer dielectric layer 140.
  • the first active region 121 is located on the substrate 110.
  • the first gate dielectric layer 131 is located on the first active region 121, and the metal gate 132 is located on the first gate dielectric layer 131.
  • the first interlayer dielectric layer 140 covers the first active region 121 and the metal gate 132.
  • the first source/drain metal 171 is located on the first interlayer dielectric layer 140 and is electrically connected to the first active region 121 through a first through hole penetrating the first interlayer dielectric layer 140.
  • the second thin film transistor 012 is a back-gate thin film transistor.
  • the second thin film transistor 012 includes a second active region 151 and a second source/drain metal 172, and the second active region 151 and the second source/drain metal 172 are located on both sides of the metal gate 132.
  • the second thin film transistor 012 further includes: a second gate dielectric layer, a second active region 151 and a second interlayer dielectric layer 160.
  • the second gate dielectric layer is located on the metal gate 132.
  • the second interlayer dielectric layer 160 covers the second active region 151, and the top of the second interlayer dielectric layer 160 is higher than the top of the second active region 151 Therefore, in this embodiment, the second interlayer dielectric layer 160 is used as the second gate dielectric layer.
  • the second active region 151 is located on the second interlayer dielectric layer 160.
  • the second source/drain metal 172 is located on the second interlayer dielectric layer 160 and is electrically connected to the second active region 151 through a second through hole penetrating the second interlayer dielectric layer 160.
  • the first electrode plate 122 of the storage capacitor 030 and the first active region 121 of the first thin film transistor 011 are spaced apart, and the material and composition of the first electrode plate 110 The materials of the first active region 121 are the same.
  • the second electrode plate 152 of the storage capacitor 030 and the second active region 151 of the second thin film transistor 012 are spaced apart, and the material constituting the second electrode plate is the same as the material constituting the second active region 151 the same.
  • the projection of the first electrode plate 122 on the substrate 110 overlaps the projection of the second electrode plate 152 on the substrate 110.
  • the projection of the light-emitting structure 020 on the substrate 110 overlaps with the projection of the first electrode plate 122 on the substrate 110.
  • the light-emitting structure 020 is an organic light-emitting diode, and includes an anode 210, a pixel defining layer 220, a light-emitting material 230, a cathode 240, and a color film layer 200.
  • the light-emitting material 230 in this embodiment is a white light-emitting material, so it is also necessary to arrange a color film layer of different colors under the light-emitting material to convert white light into light of other colors, such as red light, blue light, and green light.
  • the light-emitting material may also be a red light-emitting material, a green light-emitting material, and a blue light-emitting material. In this case, there is no need to provide a color film layer.
  • the anode 210 is a transparent electrode, such as indium tin oxide or other transparent conductive materials.
  • the color filter layer 200 is located above the second interlayer dielectric layer 180.
  • the light-emitting structure 020 further includes a protective layer 190 covering the color filter layer 200.
  • the pixel definition layer 220 is located on the protection layer 190 and has an opening exposing the anode 210.
  • the luminescent material 230 is located in the opening.
  • the cathode 240 covers the light-emitting material 230, and the cathode 240 of the light-emitting structure 020 is a reflective electrode.
  • the present application stacks two transistors of the 3T1C pixel driving circuit to save the area of one transistor.
  • the storage capacitor 030 is disposed under the light-emitting structure 020, which increases the aperture ratio of the pixel.
  • the present application optimizes the device structure without increasing the process complexity, which greatly improves The performance of the bottom-emitting display panel in the prior art.
  • the present application also provides a method for manufacturing a display panel, which will be described in detail below with reference to the drawings.
  • a substrate 110 is provided, and the first active region 121 of the first thin film transistor 011 and the first plate 122 of the storage capacitor 030 are formed on the substrate 110.
  • a first gate dielectric layer 131 is formed on the first active region 121, and a metal gate 132 is formed on the first gate dielectric layer 131.
  • a first interlayer dielectric layer 140 covering the metal gate 132, the first active region 121 and the first electrode plate 110 is formed.
  • the second active region 151 of the second thin film transistor 012 and the second plate 152 of the storage capacitor 030 are formed on the first interlayer dielectric layer 140.
  • a second interlayer dielectric layer 160 covering the second active region 151 and the second electrode plate 152 is formed.
  • a first source-drain metal 171 is formed that penetrates the first interlayer dielectric layer 140 and the second interlayer dielectric to be electrically connected to the first active region 121.
  • a second source-drain metal 172 is formed that penetrates the second interlayer dielectric layer 160 and is electrically connected to the second active region 151.
  • the first thin film transistor 011 is a top-gate thin film transistor
  • the second thin film transistor 012 is a back-gate thin film transistor.
  • the first thin film transistor 011 and the second thin film transistor 012 share the same metal gate. This arrangement effectively reduces the area of the non-light-emitting area of the pixel drive circuit, and effectively improves the aperture ratio of the pixel.
  • a planarization layer 180 covering the first source-drain metal 171 and the second source-drain metal 172 is formed. Since the light-emitting material 230 in this embodiment is a white light-emitting material, it is also necessary to arrange a color film layer 200 of different colors under the light-emitting material to convert white light into light of other colors, such as red light, blue light, and green light. After that, a protective layer 190 covering the color filter layer 200 is formed, as shown in FIG. 6.
  • the anode 210 is a transparent electrode, such as indium tin oxide or other transparent conductive materials.
  • the color filter layer 200 is located above the second interlayer dielectric layer 180.
  • the first electrode plate 122 of the storage capacitor 030 and the first active region 121 of the first thin film transistor 011 are spaced apart, and the material constituting the first electrode plate 110 is different from the first active region 121 of the first thin film transistor 011.
  • the material of the active region 121 is the same.
  • the second electrode plate 152 of the storage capacitor 030 and the second active region 151 of the second thin film transistor 012 are spaced apart, and the material constituting the second electrode plate is the same as the material constituting the second active region 151 the same.
  • the projection of the first electrode plate 122 on the substrate 110 overlaps the projection of the second electrode plate 152 on the substrate 110. Moreover, in this embodiment, in order to save as much area as possible, the projection of the light-emitting structure 020 on the substrate 110 overlaps with the projection of the first electrode plate 122 on the substrate 110.
  • the projection of the first active region 121 on the substrate 110 completely covers the projection of the second active region 151 on the substrate 110.
  • the areas of the first plate 122 and the second plate 152 of the storage capacitor 030 are equal.
  • the projection of the first plate 122 of the storage capacitor 030 on the substrate 110 overlaps with the projection of the second plate 152 on the substrate 110.
  • the projection of the light emitting structure 020 on the substrate 110 overlaps with the projection of the first electrode plate 122 on the substrate 110.
  • a light emitting structure 020 is formed on the planarization layer 180.
  • the method of forming the light emitting structure 020 includes the following steps:
  • An anode 210 is formed on the planarization layer 180, and the anode 210 is electrically connected to the first thin film transistor 011 or the second thin film transistor 012;
  • a pixel defining layer 220 covering the planarization layer 180, the pixel defining layer 220 having an opening exposing the anode 210;
  • a cathode 240 covering the luminescent material is formed.
  • the present application stacks two transistors of the 3T1C pixel driving circuit to save the area of one transistor.
  • the storage capacitor 030 is disposed under the light-emitting structure 020, which increases the aperture ratio of the pixel.
  • the present application optimizes the device structure without increasing the process complexity, which greatly improves The performance of the bottom-emitting display panel in the prior art.

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Abstract

本申请提供了一种显示面板及其制作方法。所述显示面板包括并联的第一薄膜晶体管和第二薄膜晶体管、存储电容和发光结构。所述第一薄膜晶体管在所述显示面板的出光面上的投影与所述第二薄膜晶体管在所述显示面板的出光上的投影重叠。所述存储电容位于所述发光结构下方,所述存储电容在所述显示面板的出光面上的投影与所述发光结构在所述显示面板的出光面上的投影重叠。

Description

显示面板及其制作方法 技术领域
本申请涉及电子显示领域,尤其涉及一种显示面板及其制作方法。
背景技术
3T1C像素驱动电路是OLED显示面板中最常用的驱动电路。图1和图2示出了现有技术中的3T1C像素驱动电路的电路图和结构示意图。
技术问题
现有技术中,由于薄膜晶体管和存储电容中都含有不透光的金属材料,因此发光二极管020只能被设置在金属避让区中。即,第一薄膜晶体管010、第二薄膜晶体管011、第三薄膜晶体管012、存储电容030和发光二极管020并列设置,它们在水平面上的投影不重叠。这样的设置导致每一个驱动电路所占的版图面积都很大,一方面使显示面板的分辨率无法提高,另一方面也使得显示面板的开口率低,显示效果差。
技术解决方案
本申请提供了一种显示面板及其制作方法,以提高底发光式显示面板的开口率和分辨率。
为解决上述问题,本申请提供了一种显示面板,所述显示面板包括并联的第一薄膜晶体管和第二薄膜晶体管、存储电容和发光结构;其中,
所述第一薄膜晶体管在所述显示面板的出光面上的投影与所述第二薄膜晶体管在所述显示面板的出光上的投影重叠;
所述发光结构与所述第一薄膜晶体管或所述第二薄膜晶体管电连接,且所述发光结构在所述显示面板的出光面上的投影与所述第一薄膜晶体管和第二薄膜晶体管在所述显示面板的出光面上的投影不重叠;
所述存储电容位于所述发光结构下方,所述存储电容在所述显示面板的出光面上的投影与所述发光结构在所述显示面板的出光面上的投影重叠。
根据本申请的其中一个方面,所述并联的第一薄膜晶体管和第二薄膜晶体管共用同一个金属栅极。
根据本申请的其中一个方面,所述第一薄膜晶体管为顶栅型薄膜晶体管;其中,所述第一薄膜晶体管包括第一有源区和第一源漏金属,所述第一有源区和第一源漏金属位于所述金属栅极的同一侧。
根据本申请的其中一个方面,所述第一薄膜晶体管包括
基板,所述第一有源区位于所述基板上;
第一栅极介质层,所述第一栅极介质层位于所述第一有源区上,所述金属栅极位于所述第一栅极介质层上;
第一层间介质层,所述第一层间介质层覆盖所述第一有源区和所述金属栅极;
所述第一源漏金属位于所述第一层间介质层上,并通过贯穿所述第一层间介质层的第一通孔与所述第一有源区电连接。
根据本申请的其中一个方面,所述第二薄膜晶体管为背栅型薄膜晶体管;其中,所述第二薄膜晶体管包括第二有源区和第二源漏金属,所述第二有源区和第二源漏金属位于所述金属栅极的两侧。
根据本申请的其中一个方面,所述第二薄膜晶体管包括:
第二栅极介质层,所述第二栅极介质层位于所述金属栅极上;
第二有源区,所述第二有源区位于所述第二栅极介质层上;
第二层间介质层,所述第二层间介质层覆盖所述第二有源区;
所述第二源漏金属位于所述第二层间介质层上,并通过贯穿所述第二层间介质层的第二通孔与所述第二有源区电连接。
根据本申请的其中一个方面,所述发光结构的阳极为透明电极,所述发光结构的阴极为反射电极。
根据本申请的其中一个方面,所述存储电容的第一极板与所述第一薄膜晶体管的第一有源区间隔设置,构成所述第一极板的材料与构成所述第一有源区的材料相同。
根据本申请的其中一个方面,所述存储电容的第二极板与所述第二薄膜晶体管的第二有源区间隔设置,构成所述第二极板的材料与构成所述第二有源区的材料相同。
相应的,本申请还提供了一种显示面板的制作方法,所述方法包括以下步骤:
提供基板;
在所述基板上形成第一薄膜晶体管的第一有源区和存储电容的第一极板;
在所述第一有源区上形成第一栅极介质层;
在所述第一栅极介质层上形成金属栅极;
形成覆盖所述金属栅极、所述第一有源区和所述第一极板的第一层间介质层;
在所述第一层间介质层上形成第二薄膜晶体管的第二有源区和存储电容的第二极板;
形成覆盖所述第二有源区和第二极板的第二层间介质层;
形成贯穿所述第一层间介质层和第二层间介质与所述第一有源区电连接的第一源漏金属;
形成贯穿所述第二层间介质层与所述第二有源区电连接的第二源漏金属;
形成覆盖所述第一源漏金属和第二源漏金属的平坦化层;
在所述平坦化层上形成发光结构。
根据本申请的其中一个方面,所述第一有源区在所述基板上的投影完全覆盖所述第二有源区在所述基板上的投影。
根据本申请的其中一个方面,所述存储电容的第一极板和第二极板的面积相等。
根据本申请的其中一个方面,所述存储电容的第一极板在所述基板上的投影与所述第二极板在所述基板上的投影重叠。
根据本申请的其中一个方面,所述发光结构在所述基板上的投影与所述第一极板在所述基板上的投影重叠。
根据本申请的其中一个方面,形成所述发光结构的方法包括以下步骤:
在所述平坦化层上形成阳极,所述阳极与所述第一薄膜晶体管或所述第二薄膜晶体管电连接;
形成覆盖所述平坦化层的像素定义层,所述像素定义层具有暴露出所述阳极的开口;
在所述开口中形成发光材料;
形成覆盖所述发光材料的阴极。
有益效果
相比于现有技术中的底发光式显示面板,本申请将3T1C像素驱动电路的两个晶体管层叠设置,节省了一个晶体管的面积。同时,将存储电容设置在发光结构下方,增大了像素点的开口率。同时,由于本申请中的显示面板的存储电容和两个层叠设置的薄膜晶体管的有源区同时形成,因此本申请在不增加工艺复杂度的情况下优化了器件结构,极大的提升了现有技术中的底发光式显示面板的性能。
附图说明
图1为现有技术中的3T1C像素驱动电路的电路图;
图2为图1中的3T1C像素驱动电路的部分元件的结构示意图;
图3为本申请的一个实施例中的3T1C像素驱动电路的制作完有源区之后的结构示意图;
图4为本申请的一个实施例中的3T1C像素驱动电路的制作完源漏走线层之后的结构示意图;
图5为本申请的一个实施例中的3T1C像素驱动电路的制作完滤光片之后的结构示意图;
图6为本申请的一个实施例中的3T1C像素驱动电路的制作完阳极之后的结构示意图;
图7为本申请的一个实施例中的3T1C像素驱动电路的制作完发光结构之后的结构示意图;
图8为图7中的3T1C像素驱动电路的电路图。
本发明的实施方式
以下各实施例的说明是参考附加的图示,用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语,例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等,仅是参考附加图式的方向。因此,使用的方向用语是用以说明及理解本申请,而非用以限制本申请。在图中,结构相似的单元是用以相同标号表示。
首先对现有技术进行简要说明。参见图1和图2,图1为现有技术中的3T1C像素驱动电路的电路图,图2为图1中的3T1C像素驱动电路的部分元件的结构示意图。现有技术中的3T1C像素驱动电路包括驱动薄膜晶体管010、发光结构020、第一薄膜晶体管011、第二薄膜晶体管012和存储电容030。由于薄膜晶体管和存储电容中都含有不透光的金属材料,因此发光二极管020只能被设置在金属避让区中。
参见图2,所述第一薄膜晶体管011、发光结构020和存储电容030并列设置。同样的,图2中未示出的驱动薄膜晶体管010和第二薄膜晶体管012也与所述发光结构020并列设置。所述第一薄膜晶体管010、第二薄膜晶体管011、第三薄膜晶体管012、存储电容030和发光二极管020在水平面上的投影不重叠。这样的设置导致每一个驱动电路所占的版图面积都很大,一方面使显示面板的分辨率无法提高,另一方面也使得显示面板的开口率低,显示效果差。
因此,本申请提供了一种显示面板及其制作方法,以提高底发光式显示面板的开口率和分辨率。
参见图7和图8,图7为本申请的一个实施例中的3T1C像素驱动电路的结构示意图,图8为图7中的3T1C像素驱动电路的电路图。
所述显示面板包括并联的第一薄膜晶体管011和第二薄膜晶体管012、驱动薄膜晶体管010、存储电容030和发光结构020。
所述第一薄膜晶体管011在所述显示面板的出光面上的投影与所述第二薄膜晶体管012在所述显示面板的出光上的投影重叠。所述发光结构020与所述第一薄膜晶体管011或所述第二薄膜晶体管012电连接,且所述发光结构020在所述显示面板的出光面上的投影与所述第一薄膜晶体管011和第二薄膜晶体管012在所述显示面板的出光面上的投影不重叠。所述存储电容030位于所述发光结构020下方,所述存储电容030在所述显示面板的出光面上的投影与所述发光结构020在所述显示面板的出光面上的投影重叠。
参见图7,所述并联的第一薄膜晶体管011和第二薄膜晶体管012共用同一个金属栅极132。
本实施例中,所述第一薄膜晶体管011为顶栅型薄膜晶体管。所述第一薄膜晶体管011包括第一有源区121和第一源漏金属171,所述第一有源区121和第一源漏金属171位于所述金属栅极132的同一侧。
本实施例中,所述第一薄膜晶体管011还包括:基板11第一栅极介质层131和第一层间介质层140。
所述第一有源区121位于所述基板110上。所述第一栅极介质层131位于所述第一有源区121上,所述金属栅极132位于所述第一栅极介质层131上。所述第一层间介质层140覆盖所述第一有源区121和所述金属栅极132。所述第一源漏金属171位于所述第一层间介质层140上,并通过贯穿所述第一层间介质层140的第一通孔与所述第一有源区121电连接。
本实施例中,所述第二薄膜晶体管012为背栅型薄膜晶体管。所述第二薄膜晶体管012包括第二有源区151和第二源漏金属172,所述第二有源区151和第二源漏金属172位于所述金属栅极132的两侧。
本实施例中,所述第二薄膜晶体管012还包括:第二栅极介质层、第二有源区151和第二层间介质层160。所述第二栅极介质层位于所述金属栅极132上。在本实施例中,由于所述第二层间介质层160覆盖所述第二有源区151,且所述第二层间介质层160的顶部高于所述第二有源区151的顶部,因此本实施例以所述第二层间介质层160作为第二栅极介质层。所述第二有源区151位于所述第二层间介质层160上。所述第二源漏金属172位于所述第二层间介质层160上,并通过贯穿所述第二层间介质层160的第二通孔与所述第二有源区151电连接。
参见图7,本实施例中,所述存储电容030的第一极板122与所述第一薄膜晶体管011的第一有源区121间隔设置,构成所述第一极板110的材料与构成所述第一有源区121的材料相同。所述存储电容030的第二极板152与所述第二薄膜晶体管012的第二有源区151间隔设置,构成所述第二极板的材料与构成所述第二有源区151的材料相同。所述第一极板122在所述基板110上的投影与所述第二极板152在所述基板110上的投影重叠。并且,在本实施例中,为了尽可能的节约面积,所述发光结构020在所述基板110上的投影与所述第一极板122在所述基板110上的投影重叠。
参见图7,本实施例中,所述发光结构020为有机发光二极管,包括阳极210、像素定义层220、发光材料230、阴极240和彩膜层200。
本实施例中的发光材料230为白光发光材料,因此还需要在所述发光材料下方设置不同颜色的彩膜层将白光转化为其他颜色的光,例如红光、蓝光和绿光。在其他实施例中,所述发光材料也可以为红光发光材料、绿光发光材料和蓝光发光材料,在这种情况下,则不需要设置彩膜层。
本实施中,所述阳极210为透明电极,例如氧化铟锡或其他透明导电材料。所述彩膜层200位于所述第二层间介质层180上方。本实施中,所述发光结构020还包括覆盖所述彩膜层200的保护层190。
所述像素定义层220位于所述保护层190上,并且具有暴露出所述阳极210的开口。所述发光材料230位于所述开口中。所述阴极240覆盖所述发光材料230,所述发光结构020的阴极240为反射电极。
相比于现有技术中的底发光式显示面板,本申请将3T1C像素驱动电路的两个晶体管层叠设置,节省了一个晶体管的面积。同时,将存储电容030设置在发光结构020下方,增大了像素点的开口率。同时,由于本申请中的显示面板的存储电容030和两个层叠设置的薄膜晶体管的有源区同时形成,因此本申请在不增加工艺复杂度的情况下优化了器件结构,极大的提升了现有技术中的底发光式显示面板的性能。
参见图3至图7,本申请还提供了一种显示面板的制作方法,下面将结合附图对所述方法进行详细说明。
首先,如图3所示,提供基板110,并在所述基板110上形成第一薄膜晶体管011的第一有源区121和存储电容030的第一极板122。之后,在所述第一有源区121上形成第一栅极介质层131,在所述第一栅极介质层131上形成金属栅极132。之后,形成覆盖所述金属栅极132、所述第一有源区121和所述第一极板110的第一层间介质层140。之后,在所述第一层间介质层140上形成第二薄膜晶体管012的第二有源区151和存储电容030的第二极板152。
之后,参见图4,形成覆盖所述第二有源区151和第二极板152的第二层间介质层160。之后,形成贯穿所述第一层间介质层140和第二层间介质与所述第一有源区121电连接的第一源漏金属171。之后,形成贯穿所述第二层间介质层160与所述第二有源区151电连接的第二源漏金属172。
本实施例中,所述第一薄膜晶体管011为顶栅型薄膜晶体管,所述第二薄膜晶体管012为背栅型薄膜晶体管。所述第一薄膜晶体管011和第二薄膜晶体管012共用同一金属栅极。这样设置有效的减小了像素驱动电路非发光区的面积,有效的提高了像素点的开口率。
之后,参见图5,形成覆盖所述第一源漏金属171和第二源漏金属172的平坦化层180。由于本实施例中的发光材料230为白光发光材料,因此还需要在所述发光材料下方设置不同颜色的彩膜层200将白光转化为其他颜色的光,例如红光、蓝光和绿光。之后,形成覆盖所述彩膜层200的保护层190,如图6所示。
本实施中,所述阳极210为透明电极,例如氧化铟锡或其他透明导电材料。所述彩膜层200位于所述第二层间介质层180上方。本实施例中,所述存储电容030的第一极板122与所述第一薄膜晶体管011的第一有源区121间隔设置,构成所述第一极板110的材料与构成所述第一有源区121的材料相同。所述存储电容030的第二极板152与所述第二薄膜晶体管012的第二有源区151间隔设置,构成所述第二极板的材料与构成所述第二有源区151的材料相同。所述第一极板122在所述基板110上的投影与所述第二极板152在所述基板110上的投影重叠。并且,在本实施例中,为了尽可能的节约面积,所述发光结构020在所述基板110上的投影与所述第一极板122在所述基板110上的投影重叠。
根据本申请的其中一个方面,所述第一有源区121在所述基板110上的投影完全覆盖所述第二有源区151在所述基板110上的投影。
根据本申请的其中一个方面,所述存储电容030的第一极板122和第二极板152的面积相等。
根据本申请的其中一个方面,所述存储电容030的第一极板122在所述基板110上的投影与所述第二极板152在所述基板110上的投影重叠。
根据本申请的其中一个方面,所述发光结构020在所述基板110上的投影与所述第一极板122在所述基板110上的投影重叠。
最后,参见图6和图7,在所述平坦化层180上形成发光结构020。形成所述发光结构020的方法包括以下步骤:
在所述平坦化层180上形成阳极210,所述阳极210与所述第一薄膜晶体管011或所述第二薄膜晶体管012电连接;
形成覆盖所述平坦化层180的像素定义层220,所述像素定义层220具有暴露出所述阳极210的开口;
在所述开口中形成发光材料230;
形成覆盖所述发光材料的阴极240。
相比于现有技术中的底发光式显示面板,本申请将3T1C像素驱动电路的两个晶体管层叠设置,节省了一个晶体管的面积。同时,将存储电容030设置在发光结构020下方,增大了像素点的开口率。同时,由于本申请中的显示面板的存储电容030和两个层叠设置的薄膜晶体管的有源区同时形成,因此本申请在不增加工艺复杂度的情况下优化了器件结构,极大的提升了现有技术中的底发光式显示面板的性能。
综上所述,虽然本申请已以优选实施例揭露如上,但上述优选实施例并非用以限制本申请,本领域的普通技术人员,在不脱离本申请的精神和范围内,均可作各种更动与润饰,因此本申请的保护范围以权利要求界定的范围为准。

Claims (15)

  1. 一种显示面板,其中,所述显示面板包括并联的第一薄膜晶体管和第二薄膜晶体管、存储电容和发光结构;其中,
    所述第一薄膜晶体管在所述显示面板的出光面上的投影与所述第二薄膜晶体管在所述显示面板的出光上的投影重叠;
    所述发光结构与所述第一薄膜晶体管或所述第二薄膜晶体管电连接,且所述发光结构在所述显示面板的出光面上的投影与所述第一薄膜晶体管和第二薄膜晶体管在所述显示面板的出光面上的投影不重叠;
    所述存储电容位于所述发光结构下方,所述存储电容在所述显示面板的出光面上的投影与所述发光结构在所述显示面板的出光面上的投影重叠。
  2. 根据权利要求1所述的显示面板,其中,所述并联的第一薄膜晶体管和第二薄膜晶体管共用同一个金属栅极。
  3. 根据权利要求2所述的显示面板,其中,所述第一薄膜晶体管为顶栅型薄膜晶体管;其中,所述第一薄膜晶体管包括第一有源区和第一源漏金属,所述第一有源区和第一源漏金属位于所述金属栅极的同一侧。
  4. 根据权利要求3所述的显示面板,其中,所述第一薄膜晶体管包括
    基板,所述第一有源区位于所述基板上;
    第一栅极介质层,所述第一栅极介质层位于所述第一有源区上,所述金属栅极位于所述第一栅极介质层上;
    第一层间介质层,所述第一层间介质层覆盖所述第一有源区和所述金属栅极;
    所述第一源漏金属位于所述第一层间介质层上,并通过贯穿所述第一层间介质层的第一通孔与所述第一有源区电连接。
  5. 根据权利要求2所述的显示面板,其中,所述第二薄膜晶体管为背栅型薄膜晶体管;其中,所述第二薄膜晶体管包括第二有源区和第二源漏金属,所述第二有源区和第二源漏金属位于所述金属栅极的两侧。
  6. 根据权利要求5所述的显示面板,其中,所述第二薄膜晶体管包括:
    第二栅极介质层,所述第二栅极介质层位于所述金属栅极上;
    第二有源区,所述第二有源区位于所述第二栅极介质层上;
    第二层间介质层,所述第二层间介质层覆盖所述第二有源区;
    所述第二源漏金属位于所述第二层间介质层上,并通过贯穿所述第二层间介质层的第二通孔与所述第二有源区电连接。
  7. 根据权利要求1所述的显示面板,其中,所述发光结构的阳极为透明电极,所述发光结构的阴极为反射电极。
  8. 根据权利要求3所述的显示面板,其中,所述存储电容的第一极板与所述第一薄膜晶体管的第一有源区间隔设置,构成所述第一极板的材料与构成所述第一有源区的材料相同。
  9. 根据权利要求5所述的显示面板,其中,所述存储电容的第二极板与所述第二薄膜晶体管的第二有源区间隔设置,构成所述第二极板的材料与构成所述第二有源区的材料相同。
  10. 一种显示面板的制作方法,其中,所述方法包括以下步骤:
    提供基板;
    在所述基板上形成第一薄膜晶体管的第一有源区和存储电容的第一极板;
    在所述第一有源区上形成第一栅极介质层;
    在所述第一栅极介质层上形成金属栅极;
    形成覆盖所述金属栅极、所述第一有源区和所述第一极板的第一层间介质层;
    在所述第一层间介质层上形成第二薄膜晶体管的第二有源区和存储电容的第二极板;
    形成覆盖所述第二有源区和第二极板的第二层间介质层;
    形成贯穿所述第一层间介质层和第二层间介质与所述第一有源区电连接的第一源漏金属;
    形成贯穿所述第二层间介质层与所述第二有源区电连接的第二源漏金属;
    形成覆盖所述第一源漏金属和第二源漏金属的平坦化层;
    在所述平坦化层上形成发光结构。
  11. 根据权利要求10所述的显示面板的制作方法,其中,所述第一有源区在所述基板上的投影完全覆盖所述第二有源区在所述基板上的投影。
  12. 根据权利要求10所述的显示面板的制作方法,其中,所述存储电容的第一极板和第二极板的面积相等。
  13. 根据权利要求12所述的显示面板的制作方法,其中,所述存储电容的第一极板在所述基板上的投影与所述第二极板在所述基板上的投影重叠。
  14. 根据权利要求13所述的显示面板的制作方法,其中,所述发光结构在所述基板上的投影与所述第一极板在所述基板上的投影重叠。
  15. 根据权利要求10所述的显示面板的制作方法,其中,形成所述发光结构的方法包括以下步骤:
    在所述平坦化层上形成阳极,所述阳极与所述第一薄膜晶体管或所述第二薄膜晶体管电连接;
    形成覆盖所述平坦化层的像素定义层,所述像素定义层具有暴露出所述阳极的开口;
    在所述开口中形成发光材料;
    形成覆盖所述发光材料的阴极。
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CN110098235B (zh) * 2019-05-08 2021-09-24 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法
CN210607259U (zh) * 2019-12-13 2020-05-22 北京京东方技术开发有限公司 显示基板和显示装置
CN111180491B (zh) * 2020-01-02 2023-04-07 京东方科技集团股份有限公司 显示装置及其显示面板、显示面板的制作方法
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CN113345916A (zh) * 2021-05-19 2021-09-03 深圳市华星光电半导体显示技术有限公司 显示面板及其制备方法
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