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WO2020211158A1 - 显示面板和薄膜晶体管的制作方法 - Google Patents

显示面板和薄膜晶体管的制作方法 Download PDF

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Publication number
WO2020211158A1
WO2020211158A1 PCT/CN2019/088309 CN2019088309W WO2020211158A1 WO 2020211158 A1 WO2020211158 A1 WO 2020211158A1 CN 2019088309 W CN2019088309 W CN 2019088309W WO 2020211158 A1 WO2020211158 A1 WO 2020211158A1
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WIPO (PCT)
Prior art keywords
metal layer
hole
layer
light
thin film
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Application number
PCT/CN2019/088309
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English (en)
French (fr)
Inventor
蔡振飞
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/619,693 priority Critical patent/US11257888B2/en
Publication of WO2020211158A1 publication Critical patent/WO2020211158A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates

Definitions

  • the present invention relates to the field of electronic display, in particular to a manufacturing method of a display panel and a thin film transistor.
  • AMOLED Active-matrix organic light emitting diode
  • FIG. 1 shows the pixel drive circuit of a large-size AMOLED panel.
  • Thin film transistors T1 and T2 are used for data writing, and thin film transistor T3 is used for signal driving.
  • T3 generally works in the saturation region, and the voltage applied to T3 is usually forward biased.
  • T1 and T2 generally work in the linear region, and the voltages applied to T1 and T2 are usually negative biased.
  • T1 and T2 are limited by the process, and no light-shielding metal layer is used, and the increase of light will increase the drift of the threshold voltage of the thin film transistor under the negative bias voltage. Therefore, under the influence of external ambient light and pixel driving voltage, the threshold voltages of T1 and T2 are prone to negative shifts. When the negative drift is too large, T1 and T2 will not be closed, resulting in the drive circuit not being able to write data normally, causing the screen of the display panel to flicker.
  • the invention provides a method for manufacturing a display panel and a thin film transistor to improve the stability of the data writing thin film transistor.
  • the present invention provides a display panel including a thin film transistor layer, the thin film transistor layer including a plurality of driving thin film transistors and a plurality of data writing thin film transistors; wherein,
  • Each of the data writing thin film transistors includes:
  • a light-shielding metal layer, the light-shielding metal layer is located on the substrate;
  • a buffer layer the buffer layer covering the light-shielding metal layer
  • An active region is located on the buffer layer, the active region includes a channel region and a source region and a drain region on both sides of the channel;
  • a gate dielectric layer covering the channel region
  • a gate metal layer covering the gate dielectric layer;
  • the data writing thin film transistor further includes a first through hole penetrating the gate dielectric layer and the buffer layer, and the gate metal layer is electrically connected to the light-shielding metal layer through the first through hole;
  • An interlayer dielectric layer covering the gate metal layer and the active area;
  • a second through hole, the second through hole is located on the interlayer dielectric layer and exposes the source region and the drain region;
  • the source-drain metal layer is located on the interlayer dielectric layer and is electrically connected to the source region and the drain region through the second through hole.
  • the first through hole is located on an extension line of the channel region along the channel width direction.
  • the length of the gate metal layer is greater than the length of the channel region, and the gate metal layer extends toward the first through hole and covers the first through hole.
  • the area of the light-shielding metal layer is larger than the area of the gate metal layer, and the projection of the light-shielding metal layer on the substrate completely covers the area of the gate metal layer on the substrate. projection.
  • the area of the light-shielding metal layer is larger than the area of the active region, and the projection of the light-shielding metal layer on the substrate completely covers the projection of the active region on the substrate.
  • the projection of the light-shielding metal layer on the substrate completely covers the projection of the active area on the substrate and the projection of the first through hole on the substrate.
  • each of the data writing thin film transistors further includes:
  • the present invention provides a display panel including a thin film transistor layer, the thin film transistor layer including a plurality of driving thin film transistors and a plurality of data writing thin film transistors; wherein,
  • Each of the data writing thin film transistors includes:
  • a light-shielding metal layer, the light-shielding metal layer is located on the substrate;
  • a buffer layer the buffer layer covering the light-shielding metal layer
  • An active region is located on the buffer layer, the active region includes a channel region and a source region and a drain region on both sides of the channel;
  • a gate dielectric layer covering the channel region
  • a gate metal layer covering the gate dielectric layer;
  • the data writing thin film transistor further includes a first through hole penetrating the gate dielectric layer and the buffer layer, and the gate metal layer is electrically connected to the light shielding metal layer through the first through hole.
  • the first through hole is located on an extension line of the channel region along the channel width direction.
  • the length of the gate metal layer is greater than the length of the channel region, and the gate metal layer extends toward the first through hole and covers the first through hole.
  • the area of the light-shielding metal layer is larger than the area of the gate metal layer, and the projection of the light-shielding metal layer on the substrate completely covers the area of the gate metal layer on the substrate. projection.
  • the area of the light-shielding metal layer is larger than the area of the active region, and the projection of the light-shielding metal layer on the substrate completely covers the projection of the active region on the substrate.
  • the projection of the light-shielding metal layer on the substrate completely covers the projection of the active area on the substrate and the projection of the first through hole on the substrate.
  • each of the data writing thin film transistors further includes:
  • An interlayer dielectric layer covering the gate metal layer and the active area;
  • a second through hole, the second through hole is located on the interlayer dielectric layer and exposes the source region and the drain region;
  • the source-drain metal layer is located on the interlayer dielectric layer and is electrically connected to the source region and the drain region through the second through hole.
  • the present invention also provides a method for manufacturing a thin film transistor, the method including:
  • the active region is located on the buffer layer, the active region includes a channel region and a source region and a drain region on both sides of the channel;
  • a gate metal layer is formed, the gate metal layer covers the gate dielectric layer, and the gate metal layer is electrically connected to the light-shielding metal layer through the first through hole.
  • the first through hole is located on an extension line of the channel region along the channel width direction; wherein,
  • the length of the gate metal layer is greater than the length of the channel region, and the gate metal layer extends toward the first through hole and covers the first through hole.
  • the method further includes:
  • a source-drain metal layer is formed, the source-drain metal layer is located on the interlayer dielectric layer and is electrically connected to the source region and the drain region through the second through hole.
  • the present invention optimizes the data writing thin film transistor in the display panel.
  • a light-shielding metal is arranged in the buffer layer, and the light-shielding metal is electrically connected to the gate electrode through a through hole.
  • Such a setting can achieve a light shielding effect and prevent external light from affecting the mobility of carriers in the active region.
  • the gate metal and the gate electrode are electrically connected, which effectively increases the area of the gate metal, thereby enhancing the gate control ability of the transistor.
  • FIG. 1 is a circuit diagram of a driving circuit of a display panel in the prior art
  • FIG. 2 is a schematic structural diagram of the thin film transistor in an embodiment of the present invention after the gate dielectric layer and the first through hole are fabricated;
  • FIG. 3 is a schematic diagram of the structure of the thin film transistor after the gate metal is fabricated in an embodiment of the present invention
  • FIG. 4 is a top view of the thin film transistor in FIG. 3;
  • FIG. 5 is a schematic diagram of the structure of the thin film transistor after gate patterning in an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of the structure of the thin film transistor after the second through hole is formed in an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of the structure of the thin film transistor in an embodiment of the present invention after the source and drain electrodes are fabricated;
  • FIG. 8 is a top view of the thin film transistor in FIG. 7;
  • FIG. 9 is a schematic diagram of the structure of the thin film transistor after the planarization layer is formed in an embodiment of the present invention.
  • the invention provides a method for manufacturing a display panel and a thin film transistor to improve the stability of the data writing thin film transistor.
  • the present invention provides a display panel including a thin film transistor layer, and the thin film transistor layer includes a plurality of driving thin film transistors and a plurality of data writing thin film transistors.
  • FIG. 2 is a schematic diagram of the structure of the thin film transistor in an embodiment of the present invention after the gate dielectric layer and the first through hole are fabricated
  • FIG. 3 is the fabrication of the thin film transistor in an embodiment of the present invention
  • FIG. 4 is a top view of the thin film transistor in FIG. 3
  • FIG. 5 is a schematic view of the structure after gate patterning of the thin film transistor in an embodiment of the present invention.
  • each of the data writing thin film transistors includes a substrate 10, a light-shielding metal layer 30, a buffer layer 20, an active region 40, a gate dielectric layer 50, and a gate metal layer 60. .
  • the light shielding metal layer 30 is located on the substrate 10.
  • the light-shielding metal layer can be made of metal materials with good light-shielding performance and good conductivity, such as copper, aluminum, and iron.
  • the buffer layer 20 covers the light-shielding metal layer, and a material forming the buffer layer is a transparent insulating material, such as silicon oxide or silicon nitride.
  • the active region 40 is located on the buffer layer 20, and the active region 40 includes a channel region and a source region and a drain region on both sides of the channel.
  • the source region and the drain region may be formed by in-situ doping or ion implantation.
  • the in-situ doping method is preferably used to form the source and drain regions while forming the active region, so that the doping concentration of the source and drain regions is relatively more uniform.
  • FIG. 5 is a cross-sectional view of the thin film transistor structure in FIG. 4 along the CC' direction.
  • the gate dielectric layer 50 covers the channel region, and the gate metal layer 60 covers the gate dielectric layer 50.
  • the data writing thin film transistor further includes a first through hole A penetrating through the gate dielectric layer 50 and the buffer layer 20, and the gate metal layer 60 passes through the
  • the first through hole A is electrically connected to the light shielding metal layer 30.
  • the first through hole A is located on an extension line of the channel region along the channel width direction.
  • the channel length direction is the connection direction from the source region to the drain region, and the channel width direction is perpendicular to the channel length direction.
  • the length of the gate metal layer 60 is greater than the length of the channel region, and the gate metal layer 60 extends toward the first through hole A and covers the first through hole A.
  • the area of the light-shielding metal layer 30 is larger than the area of the active region 40, and the projection of the light-shielding metal layer 30 on the substrate 10 completely covers the area of the active region 40 on the substrate 10. projection.
  • the projection of the light-shielding metal layer 30 on the substrate 10 completely covers the projection of the active area 40 on the substrate 10 and the projection of the first through hole A on the substrate 10 Projection on.
  • a light-shielding metal layer is provided in the buffer layer, and the light-shielding metal layer and the gate metal layer are electrically connected through a through hole.
  • This arrangement can achieve a light shielding effect and prevent external light from affecting the mobility of carriers in the active region 40.
  • the light-shielding metal layer and the gate metal layer are electrically connected, which effectively increases the area of the gate metal, thereby enhancing the gate control ability of the transistor.
  • each of the data writing thin film transistors further includes: an interlayer dielectric layer 70, a source and drain metal layer 80, and a planarization layer 90.
  • FIG. 6 is a schematic diagram of the structure of the thin film transistor in an embodiment of the present invention after the second through hole is formed.
  • the interlayer dielectric layer 70 covers the gate metal layer 60 and the active region 40, and the second through hole B is located on the interlayer dielectric layer 70, exposing the source region and the drain region.
  • FIG. 7 is a schematic structural diagram of the thin film transistor in an embodiment of the present invention after the source and drain electrodes are fabricated
  • FIG. 8 is a top view of the thin film transistor in FIG. 7.
  • the source-drain metal layer 80 is located on the interlayer dielectric layer 70 and is electrically connected to the source region and the drain region through the second through hole B.
  • a planarization layer 90 covering the source and drain metal layer 80 is formed.
  • the present invention also provides a method for manufacturing a thin film transistor, which will be described in detail below with reference to the accompanying drawings.
  • a substrate 10 is provided, and a light-shielding metal layer 30 is formed on the substrate 10, and then a buffer layer 20 is formed, and the buffer layer 20 covers the light-shielding metal layer 30. Then, an active region 40 is formed.
  • the active region 40 is located on the buffer layer 20.
  • the active region 40 includes a channel region and a source region and a drain region on both sides of the channel.
  • a gate dielectric layer 50 is formed, and the gate dielectric layer 50 covers the channel region.
  • a first through hole A is formed, and the first through hole A penetrates the gate dielectric layer 50 and the buffer layer 20.
  • a gate metal layer 60 is formed, the gate metal layer 60 covers the gate dielectric layer 50, and the gate metal layer 60 passes through the first through hole A and the The light shielding metal layer 30 is electrically connected.
  • the first through hole A is located on the extension line of the channel region along the channel width direction, and the length of the gate metal layer 60 is greater than the length of the channel region.
  • the gate metal layer 60 extends toward the first through hole A and covers the first through hole A.
  • FIG. 5 is a cross-sectional view of the thin film transistor structure in FIG. 4 along the CC' direction.
  • the gate dielectric layer 50 covers the channel region, and the gate metal layer 60 covers the gate dielectric layer 50.
  • the area of the light-shielding metal layer 30 is larger than the area of the active region 40, and the projection of the light-shielding metal layer 30 on the substrate 10 completely covers the area of the active region 40 on the substrate 10. projection.
  • the projection of the light-shielding metal layer 30 on the substrate 10 completely covers the projection of the active area 40 on the substrate 10 and the projection of the first through hole A on the substrate 10 Projection on.
  • a light-shielding metal layer is provided in the buffer layer, and the light-shielding metal layer and the gate metal layer are electrically connected through a through hole.
  • This arrangement can achieve a light shielding effect and prevent external light from affecting the mobility of carriers in the active region 40.
  • the light-shielding metal layer and the gate metal layer are electrically connected, which effectively increases the area of the gate metal, thereby enhancing the gate control ability of the transistor.
  • FIG. 6 is a schematic diagram of the structure of the thin film transistor in an embodiment of the present invention after the second through hole is formed.
  • the interlayer dielectric layer 70 covers the gate metal layer 60 and the active region 40, and the second through hole B is located on the interlayer dielectric layer 70, exposing the source region and the drain region.
  • FIG. 7 is a schematic structural diagram of the thin film transistor in an embodiment of the present invention after the source and drain electrodes are fabricated
  • FIG. 8 is a top view of the thin film transistor in FIG. 7.
  • the source-drain metal layer 80 is located on the interlayer dielectric layer 70 and is electrically connected to the source region and the drain region through the second through hole B.
  • a planarization layer 90 covering the source and drain metal layer 80 is formed.
  • the present invention optimizes the data writing thin film transistor in the display panel.
  • a light-shielding metal is arranged in the buffer layer, and the light-shielding metal is electrically connected to the gate electrode through a through hole.
  • Such a setting can achieve a light shielding effect and prevent external light from affecting the mobility of carriers in the active region.
  • the gate metal and the gate electrode are electrically connected, which effectively increases the area of the gate metal, thereby enhancing the gate control ability of the transistor.

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Abstract

本发明提供一种显示面板和薄膜晶体管。所述显示面板包括多个数据写入薄膜晶体管。每一个所述数据写入薄膜晶体管包括：基板、遮光金属层、缓冲层、有源区、栅极介质层和栅极金属层。所述有源区包括沟道区和位于所述沟道两侧的源区和漏区。所述数据写入薄膜晶体管还包括贯穿所述栅极介质层和缓冲层的第一通孔，所述栅极金属层通过所述第一通孔与所述遮光金属层电连接。

Description

显示面板和薄膜晶体管的制作方法 技术领域
本发明涉及电子显示领域，尤其涉及一种显示面板和薄膜晶体管的制作方法。
 背景技术
由于主动矩阵有机发光二极体（Active-matrix organic lightemitting diode, AMOLED）的对比度高、视角广且响应速度快，其有望取缔液晶成为下一代显示器主流选择。
如图1示出了大尺寸AMOLED面板的像素驱动电路。薄膜晶体管T1和T2用于数据写入，薄膜晶体管T3用于信号驱动。T3一般工作在饱和区，施加在T3上的电压通常为正向偏压。T1和T2一般工作在线性区，施加在T1和T2上的电压通常为负向偏压。
 技术问题
在目前的AMOLED像素驱动电路中，T1和T2受到工艺限制，并没有使用遮光金属层，而光照的增加会增大薄膜晶体管在负偏压下阈值电压的漂移。因此，在外界环境光的照射和像素驱动电压的影响下，T1和T2的阈值电压容易发生的负向漂移。当负向漂移过大时，T1和T2将无法关闭，导致驱动电路无法正常写入数据，使显示面板的画面出现闪烁。
因此，有必要对现有技术进行改进。
 技术解决方案
本发明提供了一种显示面板和薄膜晶体管的制作方法，以提高数据写入薄膜晶体管的稳定性。
为解决上述问题，本发明提供了一种显示面板，所述显示面板包括薄膜晶体管层，所述薄膜晶体管层包括多个驱动薄膜晶体管和多个数据写入薄膜晶体管；其中，
每一个所述数据写入薄膜晶体管包括：
基板；
遮光金属层，所述遮光金属层位于所述基板上；
缓冲层，所述缓冲层覆盖所述遮光金属层；
有源区，所述有源区位于所述缓冲层上，所述有源区包括沟道区和位于所述沟道两侧的源区和漏区；
栅极介质层，所述栅极介质层覆盖所述沟道区；
栅极金属层，所述栅极金属层覆盖所述栅极介质层；并且，
所述数据写入薄膜晶体管还包括贯穿所述栅极介质层和缓冲层的第一通孔，所述栅极金属层通过所述第一通孔与所述遮光金属层电连接；
层间介质层，所述层间介质层覆盖所述栅极金属层和有源区；
第二通孔，所述第二通孔位于所述层间介质层上，暴露出所述源区和漏区；
源漏金属层，所述源漏金属层位于所述层间介质层上，并通过所述第二通孔与所述源区和漏区电连接。
根据本发明的其中一个方面，所述第一通孔位于所述沟道区沿沟道宽度方向的延长线上。
根据本发明的其中一个方面，所述栅极金属层的长度大于所述沟道区的长度，所述栅极金属层朝向所述第一通孔的方向延伸并覆盖所述第一通孔。
根据本发明的其中一个方面，所述遮光金属层的面积大于所述栅极金属层的面积，并且所述遮光金属层在基板上的投影完全覆盖所述栅极金属层在所述基板上的投影。
根据本发明的其中一个方面，所述遮光金属层的面积大于所述有源区的面积，并且所述遮光金属层在基板上的投影完全覆盖所述有源区在所述基板上的投影。
根据本发明的其中一个方面，所述遮光金属层在基板上的投影完全覆盖所述有源区在所述基板上的投影和所述第一通孔在所述基板上的投影。
根据本发明的其中一个方面，每一个所述数据写入薄膜晶体管还包括：
为解决上述问题，本发明提供了一种显示面板，所述显示面板包括薄膜晶体管层，所述薄膜晶体管层包括多个驱动薄膜晶体管和多个数据写入薄膜晶体管；其中，
每一个所述数据写入薄膜晶体管包括：
基板；
遮光金属层，所述遮光金属层位于所述基板上；
缓冲层，所述缓冲层覆盖所述遮光金属层；
有源区，所述有源区位于所述缓冲层上，所述有源区包括沟道区和位于所述沟道两侧的源区和漏区；
栅极介质层，所述栅极介质层覆盖所述沟道区；
栅极金属层，所述栅极金属层覆盖所述栅极介质层；并且，
所述数据写入薄膜晶体管还包括贯穿所述栅极介质层和缓冲层的第一通孔，所述栅极金属层通过所述第一通孔与所述遮光金属层电连接。
根据本发明的其中一个方面，所述第一通孔位于所述沟道区沿沟道宽度方向的延长线上。
根据本发明的其中一个方面，所述栅极金属层的长度大于所述沟道区的长度，所述栅极金属层朝向所述第一通孔的方向延伸并覆盖所述第一通孔。
根据本发明的其中一个方面，所述遮光金属层的面积大于所述栅极金属层的面积，并且所述遮光金属层在基板上的投影完全覆盖所述栅极金属层在所述基板上的投影。
根据本发明的其中一个方面，所述遮光金属层的面积大于所述有源区的面积，并且所述遮光金属层在基板上的投影完全覆盖所述有源区在所述基板上的投影。
根据本发明的其中一个方面，所述遮光金属层在基板上的投影完全覆盖所述有源区在所述基板上的投影和所述第一通孔在所述基板上的投影。
根据本发明的其中一个方面，每一个所述数据写入薄膜晶体管还包括：
层间介质层，所述层间介质层覆盖所述栅极金属层和有源区；
第二通孔，所述第二通孔位于所述层间介质层上，暴露出所述源区和漏区；
源漏金属层，所述源漏金属层位于所述层间介质层上，并通过所述第二通孔与所述源区和漏区电连接。
相应的，本发明还提供了一种薄膜晶体管的制作方法，该方法包括：
提供基板；
形成遮光金属层，所述遮光金属层位于所述基板上；
形成缓冲层，所述缓冲层覆盖所述遮光金属层；
形成有源区，所述有源区位于所述缓冲层上，所述有源区包括沟道区和位于所述沟道两侧的源区和漏区；
形成栅极介质层，所述栅极介质层覆盖所述沟道区；
形成第一通孔，所述第一通孔贯穿所述栅极介质层和缓冲层；
形成栅极金属层，所述栅极金属层覆盖所述栅极介质层，并且，所述栅极金属层通过所述第一通孔与所述遮光金属层电连接。
根据本发明的其中一个方面，所述第一通孔位于所述沟道区沿沟道宽度方向的延长线上；其中，
所述栅极金属层的长度大于所述沟道区的长度，所述栅极金属层朝向所述第一通孔的方向延伸并覆盖所述第一通孔。
根据本发明的其中一个方面，该方法还包括：
形成层间介质层，所述层间介质层覆盖所述栅极金属层和有源区；
形成第二通孔，所述第二通孔位于所述层间介质层上，暴露出所述源区和漏区；
形成源漏金属层，所述源漏金属层位于所述层间介质层上，并通过所述第二通孔与所述源区和漏区电连接。
 有益效果
本发明对显示面板中的数据写入薄膜晶体管进行优化，在缓冲层中设置了遮光金属，并且通过通孔将所述遮光金属和栅极电极电连接。这样设置能够实现遮光作用，避免外界光照影响有源区中的载流子的迁移率。同时，将栅极金属和栅极电极电连接，有效的增大了栅极金属的面积，从而增强了晶体管的栅控制能力。
 附图说明
图1为现有技术中的显示面板的驱动电路的电路图；
图2为本发明的一个实施例中的薄膜晶体管制作完栅极介质层和第一通孔之后的结构示意图；
图3为本发明的一个实施例中的薄膜晶体管制作完栅极金属之后的结构示意图；
图4为图3中的薄膜晶体管的俯视图；
图5为本发明的一个实施例中的薄膜晶体管进行栅极图形化之后的结构示意图；
图6为本发明的一个实施例中的薄膜晶体管制作完第二通孔之后的结构示意图；
图7为本发明的一个实施例中的薄膜晶体管制作完源漏电极之后的结构示意图；
图8为图7中的薄膜晶体管的俯视图；
图9为本发明的一个实施例中的薄膜晶体管制作完平坦化层之后的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明提供了一种显示面板和薄膜晶体管的制作方法，以提高数据写入薄膜晶体管的稳定性。
下面将结合具体实施例对本发明进行详细说明。为解决上述问题，本发明提供了一种显示面板，所述显示面板包括薄膜晶体管层，所述薄膜晶体管层包括多个驱动薄膜晶体管和多个数据写入薄膜晶体管。参见图2至图5，图2为本发明的一个实施例中的薄膜晶体管制作完栅极介质层和第一通孔之后的结构示意图，图3为本发明的一个实施例中的薄膜晶体管制作完栅极金属之后的结构示意图，图4为图3中的薄膜晶体管的俯视图，图5为本发明的一个实施例中的薄膜晶体管进行栅极图形化之后的结构示意图。
如图3所示，在本实施例中，每一个所述数据写入薄膜晶体管包括基板10、遮光金属层30、缓冲层20、有源区40、栅极介质层50、栅极金属层60。
所述遮光金属层30位于所述基板10上。所述遮光金属层可以采用铜、铝、铁等遮光性能良好且导电性佳的金属材料制成。所述缓冲层20覆盖所述遮光金属层，形成所述缓冲层的材料为透明绝缘材料，例如氧化硅或氮化硅。所述有源区40位于所述缓冲层20上，所述有源区40包括沟道区和位于所述沟道两侧的源区和漏区。所述源区和漏区可以通过原位掺杂形成，也可以通过离子注入形成。在本实施例中，优选的采用原位掺杂的方法在形成有源区时同时形成源漏区，使源漏区的掺杂浓度相对更加均匀。
参见图4和图5，其中，图5是图4中的薄膜晶体管结构沿CC’方向的剖面图。所述栅极介质层50覆盖所述沟道区，所述栅极金属层60覆盖所述栅极介质层50。
在本实施例中，参见图2和图3，所述数据写入薄膜晶体管还包括贯穿所述栅极介质层50和缓冲层20的第一通孔A，所述栅极金属层60通过所述第一通孔A与所述遮光金属层30电连接。所述第一通孔A位于所述沟道区沿沟道宽度方向的延长线上。其中，沟道长度方向为从源区到漏区的联线方向，沟道宽度方向与所述沟道长度方向垂直。所述栅极金属层60的长度大于所述沟道区的长度，所述栅极金属层60朝向所述第一通孔A的方向延伸并覆盖所述第一通孔A。
本申请中，所述遮光金属层30的面积大于所述有源区40的面积，并且所述遮光金属层30在基板10上的投影完全覆盖所述有源区40在所述基板10上的投影。优选的，在本实施例中，所述遮光金属层30在基板10上的投影完全覆盖所述有源区40在所述基板10上的投影和所述第一通孔A在所述基板10上的投影。
通过在缓冲层中设置遮光金属层，并且通过通孔将所述遮光金属层和栅极金属层电连接。这样设置能够实现遮光作用，避免外界光照影响有源区40中的载流子的迁移率。同时，将遮光金属层和栅极金属层电连接，有效的增大了栅极金属的面积，从而增强了晶体管的栅控制能力。
如图6至图9所示，本实施例中，每一个所述数据写入薄膜晶体管还包括：层间介质层70、源漏金属层80和平坦化层90。
参见图6，图6为本发明的一个实施例中的薄膜晶体管制作完第二通孔之后的结构示意图。所述层间介质层70覆盖所述栅极金属层60和有源区40，第二通孔B位于所述层间介质层70上，暴露出所述源区和漏区。
参见图7和图8，图7为本发明的一个实施例中的薄膜晶体管制作完源漏电极之后的结构示意图，图8为图7中的薄膜晶体管的俯视图。所述源漏金属层80位于所述层间介质层70上，并通过所述第二通孔B与所述源区和漏区电连接。
最后，如图9所示，形成覆盖所述源漏金属层80的平坦化层90。
相应的，参见图2-图9，本发明还提供了一种薄膜晶体管的制作方法，下面将结合附图对该方法进行详细说明。
首先，如图2所示，提供基板10，并在所述基板10上形成遮光金属层30，之后形成缓冲层20，所述缓冲层20覆盖所述遮光金属层30。之后形成有源区40，所述有源区40位于所述缓冲层20上，所述有源区40包括沟道区和位于所述沟道两侧的源区和漏区。之后形成栅极介质层50，所述栅极介质层50覆盖所述沟道区。之后形成第一通孔A，所述第一通孔A贯穿所述栅极介质层50和缓冲层20。
之后，如图3所示，形成栅极金属层60，所述栅极金属层60覆盖所述栅极介质层50，并且，所述栅极金属层60通过所述第一通孔A与所述遮光金属层30电连接。如图4所示，所述第一通孔A位于所述沟道区沿沟道宽度方向的延长线上，且所述栅极金属层60的长度大于所述沟道区的长度，所述栅极金属层60朝向所述第一通孔A的方向延伸并覆盖所述第一通孔A。
参见图4和图5，其中，图5是图4中的薄膜晶体管结构沿CC’方向的剖面图。所述栅极介质层50覆盖所述沟道区，所述栅极金属层60覆盖所述栅极介质层50。
本申请中，所述遮光金属层30的面积大于所述有源区40的面积，并且所述遮光金属层30在基板10上的投影完全覆盖所述有源区40在所述基板10上的投影。优选的，在本实施例中，所述遮光金属层30在基板10上的投影完全覆盖所述有源区40在所述基板10上的投影和所述第一通孔A在所述基板10上的投影。
通过在缓冲层中设置遮光金属层，并且通过通孔将所述遮光金属层和栅极金属层电连接。这样设置能够实现遮光作用，避免外界光照影响有源区40中的载流子的迁移率。同时，将遮光金属层和栅极金属层电连接，有效的增大了栅极金属的面积，从而增强了晶体管的栅控制能力。
参见图6，图6为本发明的一个实施例中的薄膜晶体管制作完第二通孔之后的结构示意图。所述层间介质层70覆盖所述栅极金属层60和有源区40，第二通孔B位于所述层间介质层70上，暴露出所述源区和漏区。
参见图7和图8，图7为本发明的一个实施例中的薄膜晶体管制作完源漏电极之后的结构示意图，图8为图7中的薄膜晶体管的俯视图。所述源漏金属层80位于所述层间介质层70上，并通过所述第二通孔B与所述源区和漏区电连接。
最后，如图9所示，形成覆盖所述源漏金属层80的平坦化层90。
本发明对显示面板中的数据写入薄膜晶体管进行优化，在缓冲层中设置了遮光金属，并且通过通孔将所述遮光金属和栅极电极电连接。这样设置能够实现遮光作用，避免外界光照影响有源区中的载流子的迁移率。同时，将栅极金属和栅极电极电连接，有效的增大了栅极金属的面积，从而增强了晶体管的栅控制能力。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (16)

  1. 一种显示面板，其中，所述显示面板包括薄膜晶体管层，所述薄膜晶体管层包括多个驱动薄膜晶体管和多个数据写入薄膜晶体管；其中，
    每一个所述数据写入薄膜晶体管包括：
    基板；
    遮光金属层，所述遮光金属层位于所述基板上；
    缓冲层，所述缓冲层覆盖所述遮光金属层；
    有源区，所述有源区位于所述缓冲层上，所述有源区包括沟道区和位于所述沟道两侧的源区和漏区；
    栅极介质层，所述栅极介质层覆盖所述沟道区；
    栅极金属层，所述栅极金属层覆盖所述栅极介质层；并且，
    所述数据写入薄膜晶体管还包括贯穿所述栅极介质层和缓冲层的第一通孔，所述栅极金属层通过所述第一通孔与所述遮光金属层电连接；
    层间介质层，所述层间介质层覆盖所述栅极金属层和有源区；
    第二通孔，所述第二通孔位于所述层间介质层上，暴露出所述源区和漏区；
    源漏金属层，所述源漏金属层位于所述层间介质层上，并通过所述第二通孔与所述源区和漏区电连接。
  2. 根据权利要求1所述的显示面板，其中，所述第一通孔位于所述沟道区沿沟道宽度方向的延长线上。
  3. 根据权利要求2所述的显示面板，其中，所述栅极金属层的长度大于所述沟道区的长度，所述栅极金属层朝向所述第一通孔的方向延伸并覆盖所述第一通孔。
  4. 根据权利要求3所述的显示面板，其中，所述遮光金属层的面积大于所述栅极金属层的面积，并且所述遮光金属层在基板上的投影完全覆盖所述栅极金属层在所述基板上的投影。
  5. 根据权利要求4所述的显示面板，其中，所述遮光金属层的面积大于所述有源区的面积，并且所述遮光金属层在基板上的投影完全覆盖所述有源区在所述基板上的投影。
  6. 根据权利要求5所述的显示面板，其中，所述遮光金属层在基板上的投影完全覆盖所述有源区在所述基板上的投影和所述第一通孔在所述基板上的投影。
  7. 一种显示面板，其中，所述显示面板包括薄膜晶体管层，所述薄膜晶体管层包括多个驱动薄膜晶体管和多个数据写入薄膜晶体管；其中，
    每一个所述数据写入薄膜晶体管包括：
    基板；
    遮光金属层，所述遮光金属层位于所述基板上；
    缓冲层，所述缓冲层覆盖所述遮光金属层；
    有源区，所述有源区位于所述缓冲层上，所述有源区包括沟道区和位于所述沟道两侧的源区和漏区；
    栅极介质层，所述栅极介质层覆盖所述沟道区；
    栅极金属层，所述栅极金属层覆盖所述栅极介质层；并且，
    所述数据写入薄膜晶体管还包括贯穿所述栅极介质层和缓冲层的第一通孔，所述栅极金属层通过所述第一通孔与所述遮光金属层电连接。
  8. 根据权利要求7所述的显示面板，其中，所述第一通孔位于所述沟道区沿沟道宽度方向的延长线上。
  9. 根据权利要求8所述的显示面板，其中，所述栅极金属层的长度大于所述沟道区的长度，所述栅极金属层朝向所述第一通孔的方向延伸并覆盖所述第一通孔。
  10. 根据权利要求9所述的显示面板，其中，所述遮光金属层的面积大于所述栅极金属层的面积，并且所述遮光金属层在基板上的投影完全覆盖所述栅极金属层在所述基板上的投影。
  11. 根据权利要求10所述的显示面板，其中，所述遮光金属层的面积大于所述有源区的面积，并且所述遮光金属层在基板上的投影完全覆盖所述有源区在所述基板上的投影。
  12. 根据权利要求11所述的显示面板，其中，所述遮光金属层在基板上的投影完全覆盖所述有源区在所述基板上的投影和所述第一通孔在所述基板上的投影。
  13. 根据权利要求7所述的显示面板，其中，每一个所述数据写入薄膜晶体管还包括：
    层间介质层，所述层间介质层覆盖所述栅极金属层和有源区；
    第二通孔，所述第二通孔位于所述层间介质层上，暴露出所述源区和漏区；
    源漏金属层，所述源漏金属层位于所述层间介质层上，并通过所述第二通孔与所述源区和漏区电连接。
  14. 一种薄膜晶体管的制作方法，其中，该方法包括：
    提供基板；
    形成遮光金属层，所述遮光金属层位于所述基板上；
    形成缓冲层，所述缓冲层覆盖所述遮光金属层；
    形成有源区，所述有源区位于所述缓冲层上，所述有源区包括沟道区和位于所述沟道两侧的源区和漏区；
    形成栅极介质层，所述栅极介质层覆盖所述沟道区；
    形成第一通孔，所述第一通孔贯穿所述栅极介质层和缓冲层；
    形成栅极金属层，所述栅极金属层覆盖所述栅极介质层，并且，所述栅极金属层通过所述第一通孔与所述遮光金属层电连接。
  15. 根据权利要求14所述的薄膜晶体管的制作方法，其中，所述第一通孔位于所述沟道区沿沟道宽度方向的延长线上；其中，
    所述栅极金属层的长度大于所述沟道区的长度，所述栅极金属层朝向所述第一通孔的方向延伸并覆盖所述第一通孔。
  16. 根据权利要求14所述的薄膜晶体管的制作方法，其中，该方法还包括：
    形成层间介质层，所述层间介质层覆盖所述栅极金属层和有源区；
    形成第二通孔，所述第二通孔位于所述层间介质层上，暴露出所述源区和漏区；
    形成源漏金属层，所述源漏金属层位于所述层间介质层上，并通过所述第二通孔与所述源区和漏区电连接。
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