Nothing Special   »   [go: up one dir, main page]

WO2019109473A1 - Ffs模式阵列基板及其制造方法 - Google Patents

Ffs模式阵列基板及其制造方法 Download PDF

Info

Publication number
WO2019109473A1
WO2019109473A1 PCT/CN2018/072627 CN2018072627W WO2019109473A1 WO 2019109473 A1 WO2019109473 A1 WO 2019109473A1 CN 2018072627 W CN2018072627 W CN 2018072627W WO 2019109473 A1 WO2019109473 A1 WO 2019109473A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
semiconductor layer
array substrate
mode array
ffs mode
Prior art date
Application number
PCT/CN2018/072627
Other languages
English (en)
French (fr)
Inventor
邓永
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Publication of WO2019109473A1 publication Critical patent/WO2019109473A1/zh

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/127Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an FFS mode array substrate and a method of fabricating the same.
  • the existing FFS mode liquid crystal display device has become a hot spot in the industry because of its advantages of high brightness, wide viewing angle, and low color shift.
  • the FFS mode liquid crystal display device includes an FFS mode array substrate.
  • the FFS mode array substrate generally requires more than 5 masks, and the preparation process is complicated and the cost is relatively high.
  • the thin film transistor therein is a BCE structure or a Top-gate structure.
  • the FFS mode array substrate includes a substrate 110 , a source 121 , a common electrode 122 , a planarization layer 130 , a first insulating layer 140 , a pixel electrode 150 , an active layer 160 , and a gate insulating layer 170 .
  • the film layer such as the gate electrode 180, although the thin film transistor of the vertical structure can be made small, the aperture ratio of the FFS mode liquid crystal display device can be improved.
  • the vertical structure thin film transistor itself is complicated, such a structure further complicates the structure of the FFS array substrate, and the number of masks required is higher and the cost is higher.
  • a technical problem to be solved by embodiments of the present invention is to provide an FFS mode array substrate and a method of fabricating the same. It simplifies the process and reduces costs.
  • the first aspect of the present invention provides a method for fabricating an FFS mode array substrate.
  • the FFS mode array substrate includes a vertical structure thin film transistor, and the manufacturing method includes:
  • the drain is electrically connected to the pixel electrode
  • a passivation layer is deposited, and the passivation layer is patterned by a third mask to form via holes.
  • the step of depositing the transparent semiconductor layer and the first metal layer on the substrate further comprises: patterning the first through the first mask
  • the metal layer and the transparent semiconductor layer also form a common trace and a scan line, the common trace being electrically connected to the common electrode, the scan line being electrically connected to the gate.
  • the active layer is of a "Z" type.
  • the pixel electrode is formed by doping hydrogen ions after patterning of the oxide semiconductor layer.
  • the first reticle and the second reticle are halftone reticle.
  • the embodiment of the second aspect of the present invention provides an FFS mode array substrate, including:
  • a common electrode on the substrate which is composed of a transparent semiconductor layer
  • a gate electrode on the substrate which is composed of a transparent semiconductor layer and a first metal layer;
  • a gate insulating layer on the gate, the common electrode and the substrate;
  • a pixel electrode disposed on the gate insulating layer and disposed corresponding to the common electrode, the pixel electrode being electrically connected to the drain;
  • a passivation layer is disposed on the source, the drain, the pixel electrode, and the gate insulating layer, and a via hole is formed on the passivation layer.
  • the scan line and the common trace are further electrically connected to the common electrode, and the scan line is electrically connected to the gate.
  • the active layer is of a "Z" type.
  • the pixel electrode is formed by doping hydrogen ions after patterning of the oxide semiconductor layer.
  • the pixel electrode includes a plurality of strip-shaped sub-electrodes, and the sub-electrodes are disposed apart from each other, and the sub-electrodes are electrically connected to the drains, respectively.
  • the FFS mode array substrate can be fabricated through three masks, the process is greatly simplified, thereby reducing the cost.
  • the FFS mode array substrate is a vertical structure thin film transistor
  • the vertical structure thin film transistor of the embodiment has a simple structure, and the lateral channel width can be made narrow, so that the thin film transistor can be made small, which is advantageous for increasing the aperture ratio. And can increase the on-state current.
  • FIG. 2 is a flow chart showing a method of fabricating an FFS mode array substrate according to an embodiment of the present invention
  • 3a-3c are schematic views showing deposition of respective film layers of an FFS mode array substrate on a substrate
  • 4a and 4b are cross-sectional views of the FFS mode array substrate after being processed by the reticle
  • Figure 4c is an enlarged view of the vicinity of the active layer of Figure 4b;
  • Figure 4d is another cross-sectional view of the FFS mode array substrate after being processed by the reticle
  • 5a and 5b are top views of the FFS mode array substrate after being processed by the mask.
  • Embodiments of the present invention provide a method for fabricating an FFS mode array substrate, the FFS mode array substrate including a vertical structure thin film transistor, which can increase an aperture ratio of an FFS mode array substrate, and a vertical structure thin film transistor The channel can be made shorter so that the on-state current can be increased.
  • the manufacturing method includes:
  • the substrate 210 is a glass substrate.
  • the present invention is not limited thereto.
  • the substrate may also be a transparent substrate such as a flexible substrate or a plastic substrate.
  • S120 sequentially depositing a transparent semiconductor layer and a first metal layer on the substrate, the first metal layer being located on the transparent semiconductor layer;
  • the material of the transparent semiconductor layer 220 is, for example, ITO.
  • the transparent semiconductor layer 220 is deposited on the substrate 210, the first metal layer 230 is deposited on the transparent semiconductor layer 220.
  • the first mask is a half tone mask, so that the photoresist on the first metal layer 230 can be exposed to different degrees by one exposure of the first mask, and thereafter
  • the photoresist is removed from the different regions by several developments, so that the photoresist can be removed by one development after a certain development, and the photoresist is completely removed in some regions, and the etching can form the common electrode 221 and the gate.
  • Extreme 231. Specifically, referring to FIG. 4a and FIG. 5a, after exposing the photoresist on the first metal layer 230, after a first development and etching, the first metal layer 230 and the transparent semiconductor layer 220 of the partial regions are removed.
  • the gate 231 is a two-layer material, and is composed of a first metal layer 230 and a transparent semiconductor layer 220.
  • the first metal layer 230 is located above the transparent semiconductor layer 220.
  • the common electrode 221 is composed of a transparent semiconductor layer 220.
  • Patterning the first metal layer and the transparent semiconductor layer by the first mask further forms a common trace and a scan line, the common trace being electrically connected to the common electrode, the scan line and the gate Electrical connection.
  • the hierarchical structure of the common trace 232 and the scan line 233 is the same as that of the gate 231, and is also composed of two layers of materials.
  • the scan line 233 is electrically connected to the gate 231
  • the common trace 232 is electrically connected to the common electrode 221, so that signals on the scan line 233 can be transmitted to the gate 231, and the common trace 232 is transmitted.
  • the common voltage can be transmitted to the common electrode 221 through the common trace 232.
  • S140 sequentially depositing a gate insulating layer, an oxide semiconductor layer, and a second metal layer from bottom to top;
  • a gate insulating layer 240 is deposited on the formed gate 231, the scan line 233, the common electrode 221, the common trace 232, and the substrate 210, and oxide is deposited on the gate insulating layer 240.
  • the semiconductor layer 250 deposits a second metal layer 260 on the oxide semiconductor layer 250.
  • the specific thickness of each level depends on actual needs.
  • the material of the oxide semiconductor layer 250 is IGZO.
  • S150 patterning the oxide semiconductor layer and the second metal layer by a second mask to form an active layer, a pixel electrode, a source, and a drain, wherein the source and the drain are respectively located on the active layer On the side, the drain is electrically connected to the pixel electrode;
  • the layer 250 is removed, and thereafter, the oxide semiconductor layer 250 corresponding to the pixel electrode 252 region is exposed by the second development and etching, and then the portion of the oxide semiconductor layer 250 is doped with hydrogen ion treatment, thereby forming a conductive
  • the pixel electrode 252 and the pixel electrode 252 are transparent. Thereafter, the active layer 251 corresponding to the channel region is formed by the third development and etching, and then, the fourth development is performed to expose the source and drain electrodes 261 and 262.
  • an oxide semiconductor layer 250 is also present under the source 261 and the drain 262, where the oxide semiconductor layer 250 is a part of the active layer 251, and thus, the active layer 251 is
  • the two parts are composed of the source semiconductor 261 and the oxide semiconductor layer 250 under the drain 262, the oxide semiconductor layer 250 between the source 261 and the drain 262 (which is exposed at this time), and can also be seen in this case.
  • the active layer 251 between the source 261 and the drain 262 is vertically disposed, which may be referred to as a longitudinal portion 251b, and the active layer 251 portion under the source 261 and the drain 262 is laterally disposed.
  • the lateral portion 251a that is, the active layer 251 is composed of a longitudinal portion 251b and a lateral portion 251a.
  • the active layer 251 has a "Z" shape.
  • the drain electrode 262 and the pixel electrode 252 are electrically connected, and the pixel electrode 252 includes a plurality of strip-shaped sub-electrodes, the sub-electrodes are disposed separately from each other, and the sub-electrodes are electrically connected to The drain 262, and thus the signal on the drain 262, can transmit the respective sub-electrodes.
  • the common electrode 221 and the pixel electrode 252 are respectively two electrodes of the FFS mode liquid crystal display panel.
  • step S140 the method further includes:
  • Patterning the second metal layer and the oxide semiconductor layer through the second mask also forms a data line.
  • the oxide semiconductor layer 250 is also disposed under the data line 263.
  • the data line 263 is electrically connected to the source 261.
  • S160 depositing a passivation layer, and patterning the passivation layer through a third mask to form via holes.
  • a passivation layer 270 is formed on the source 261, the drain 262, the active layer 251, the gate insulating layer 240, the pixel electrode 252, and the data line 263.
  • the passivation layer 270 serves to protect each of the underlying film layers, after which the vias 271 are formed by patterning the passivation layer 270 through a third mask.
  • the third photomask is an ordinary photomask, not a halftone mask.
  • the via 271 is located above the source 261 or the data line 263 for electrical connection with other circuits, such as the electrical connection of the data line 263 with the peripheral line.
  • the FFS mode array substrate can be fabricated through three masks, the process is greatly simplified, thereby reducing the cost.
  • the FFS mode array substrate 210 is a vertical structure thin film transistor, the vertical structure thin film transistor of the embodiment has a simple structure, and the lateral channel width can be made narrow, so that the thin film transistor can be made small, which is advantageous for improving the opening. Rate, and can increase the on-state current.
  • the embodiment of the present invention further provides an FFS mode array substrate.
  • the FFS mode array substrate includes:
  • a common electrode 221 on the substrate 210 which is composed of a transparent semiconductor layer 220;
  • a gate 231 which is located on the substrate 210, and is composed of a transparent semiconductor layer 220 and a first metal layer 230;
  • a gate insulating layer 240 which is located on the gate 231, the common electrode 221, and the substrate 210;
  • a source 261 and a drain 262 respectively located on the active layer 251;
  • a passivation layer 270 is disposed on the source electrode 261, the drain electrode 262, the pixel electrode 252, and the gate insulating layer 240, and a via hole 271 is formed in the passivation layer 270.
  • the FFS mode array substrate 210 further includes a scan line 233 and a common trace 232.
  • the common trace 232 is electrically connected to the common electrode 221, and the scan line 233 and the gate 231 are connected. Electrical connection.
  • the active layer 251 is of a "Z" type, and the active layer 251 includes two lateral portions 251a and a longitudinal portion 251b, and the two lateral portions 251a are located under the source 261 and the drain 262, respectively.
  • the two lateral portions 251a form a height difference, and the longitudinal portion 251b is located between the two lateral portions 251a.
  • the pixel electrode 252 is patterned by the oxide semiconductor layer 250 and then doped with hydrogen ions, so that the pixel electrode 252 is made of a light-transmitting material.
  • the pixel electrode 252 includes a plurality of strip-shaped sub-electrodes, and the sub-electrodes are disposed apart from each other, and the sub-electrodes are electrically connected to the drain 262, respectively.
  • the present invention has the following advantages:
  • the FFS mode array substrate can be fabricated through three masks, the process is greatly simplified, thereby reducing the cost.
  • the FFS mode array substrate is a vertical structure thin film transistor
  • the vertical structure thin film transistor of the embodiment has a simple structure, and the lateral channel width can be made narrow, so that the thin film transistor can be made small, which is advantageous for increasing the aperture ratio. And can increase the on-state current.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种FFS模式阵列基板的制造方法, FFS模式阵列基板包括垂直结构薄膜晶体管,包括:(S110)提供基板(210);(S120)在基板(210)上依序沉积透明半导体层(220)和第一金属层(230),(S131)通过第一光罩图案化透明半导体层(220)和第一金属层(230)形成共通电极(221)和栅极(231);(S140)从下到上依序沉积栅极绝缘层(240)、氧化物半导体层(250)和第二金属层(260);(S150)通过第二光罩图案化氧化物半导体层(250)和第二金属层(260)形成有源层(251)、像素电极(252)、源极(261)和漏极(262),其中,源极(261)和漏极(262)分别位于有源层(251)的两侧上,漏极(262)与像素电极(252)电连接;(S160)沉积钝化层(270),且通过第三光罩图案化钝化层(270)形成过孔(271)。还公开了一种FFS模式阵列基板。该方法具有简化制程、降低成本的优点。

Description

FFS模式阵列基板及其制造方法
本发明要求2017年12月06日递交的发明名称为“FFS模式阵列基板及其制造方法”的申请号201711277779.1的在先申请优先权,上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示技术领域,特别是涉及一种FFS模式阵列基板及其制造方法。
背景技术
现有的FFS模式液晶显示装置,因为具有高亮度,广视角,以及较低的色偏等优点,而成为行业研究的热点。FFS模式液晶显示装置包括FFS模式阵列基板,一般说来,所述FFS模式阵列基板普遍需要5道以上的光罩,制备工艺复杂,成本也相对较高。
在上述的FFS模式阵列基板中,其内的薄膜晶体管为BCE结构或者Top-gate结构,随着技术的进步,最近产品上出现了垂直结构的薄膜晶体管,包含该种垂直结构的薄膜晶体管的FFS模式阵列基板请参见图1,该种FFS模式阵列基板包括基板110、源极121、共通电极122、平坦层130、第一绝缘层140、像素电极150、有源层160、栅极绝缘层170和栅极180等膜层,虽然该种垂直结构的薄膜晶体管可以做的很小,可以提高FFS模式液晶显示装置开口率。然而,由于垂直结构薄膜晶体管本身复杂,此种结构进一步使FFS阵列基板结构复杂化,所需要的光罩数目更多,成本更高。
发明内容
本发明实施例所要解决的技术问题在于,提供一种FFS模式阵列基板及其制造方法。可简化制程,降低成本。
为了解决上述技术问题,本发明第一方面实施例提供了一种FFS模式阵列基板的制造方法,所述FFS模式阵列基板包括垂直结构薄膜晶体管,所述制造 方法包括:
提供基板;
在基板上依序沉积透明半导体层和第一金属层,所述第一金属层位于透明半导体层上;
通过第一光罩图案化所述透明半导体层和第一金属层形成共通电极和栅极;
从下到上依序沉积栅极绝缘层、氧化物半导体层和第二金属层;
通过第二光罩图案化所述氧化物半导体层和第二金属层形成有源层、像素电极、源极和漏极,其中,所述源极和漏极分别位于有源层的两侧上,所述漏极与所述像素电极电连接;
沉积钝化层,且通过第三光罩图案化所述钝化层形成过孔。
其中,在所述在基板上依序沉积透明半导体层和第一金属层,所述第一金属层位于透明半导体层上的步骤之后还包括:通过所述第一光罩图案化所述第一金属层和透明半导体层还形成共通走线和扫描线,所述共通走线与所述共通电极电连接,所述扫描线与所述栅极电连接。
其中,所述有源层为“Z”型。
其中,所述像素电极由氧化物半导体层图案化后掺杂氢离子形成。
其中,所述第一光罩和所述第二光罩为半色调光罩。
本发明第二方面实施例提供了一种FFS模式阵列基板,包括:
基板;
共通电极,其位于所述基板上,其由透明半导体层构成;
栅极,其位于所述基板上,其由透明半导体层和第一金属层构成;
栅极绝缘层,其位于所述栅极、共通电极和基板上;
有源层,其位于所述栅极绝缘层上,且由氧化物半导体层构成;
源极和漏极,其分别位于所述有源层上;
像素电极,其位于栅极绝缘层上且对应所述共通电极设置,所述像素电极与所述漏极电连接;
钝化层,其位于源极、漏极、像素电极、栅极绝缘层上,钝化层上形成过孔。
其中,还包括扫描线和共通走线,所述共通走线与所述共通电极电连接,所述扫描线与所述栅极电连接。
其中,所述有源层为“Z”型。
其中,所述像素电极由氧化物半导体层图案化后掺杂氢离子形成。
其中,所述像素电极包括多条条形的子电极,所述子电极互相分离设置,所述子电极分别电连接到所述漏极。
实施本发明实施例,具有如下有益效果:
由于FFS模式阵列基板通过3道光罩就可以制成,极大的简化了制程,从而降低了成本。而且,由于FFS模式阵列基板是形成垂直结构薄膜晶体管,本实施例的垂直结构薄膜晶体管结构简单,而且横向沟道宽度可以做的很窄,可以使薄膜晶体管做的很小,有利于提高开口率,且可以提高开态电流。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是现有技术FFS模式阵列基板包括垂直结构薄膜晶体管的剖视示意图;
图2是本发明一实施例FFS模式阵列基板的制造方法的流程图;
图3a-图3c是FFS模式阵列基板的各个膜层沉积在基板上的示意图;
图4a、图4b是通过光罩处理后FFS模式阵列基板的一种剖视图;
图4c是图4b中有源层附近的放大图;
图4d是通过光罩处理后FFS模式阵列基板的另一剖视图;
图5a、图5b是通过光罩处理后FFS模式阵列基板的俯视图。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
本申请说明书、权利要求书和附图中出现的术语“包括”和“具有”以及它们任何变形,意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元,而是可选地还包括没有列出的步骤或单元,或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。此外,术语“第一”、“第二”和“第三”等是用于区别不同的对象,而并非用于描述特定的顺序。
本发明实施例提供一种FFS模式阵列基板的制造方法,所述FFS模式阵列基板包括垂直结构薄膜晶体管,所述垂直结构薄膜晶体管可以提高FFS模式阵列基板的开口率,并且由于垂直结构薄膜晶体管的沟道可以做的更短,从而可以提高开态电流。请参见图2,所述制造方法包括:
S110:提供基板;
在本实施例中,所述基板210为玻璃基板,当然,本发明不限于此,在本发明的其他实施例中,所述基板还可以为柔性基板、塑料基板等透明基板。
S120:在基板上依序沉积透明半导体层和第一金属层,所述第一金属层位于透明半导体层上;
请参见图3a,在本实施例中,所述透明半导体层220的材料例如为ITO,在基板210上沉积了透明半导体层220后,在透明半导体层220上沉积第一金属层230。
S131:通过第一光罩图案化所述透明半导体层和第一金属层形成共通电极和栅极;
在本实施例中,所述第一光罩是半色调光罩(half tone mask),从而通过第一光罩一次曝光可以对第一金属层230上的光阻形成不同程度的曝光,其后通过几次显影去除掉不同区域的光阻,从而有的区域经过一次显影就可以把光阻去掉,有的区域需要几次显影才能把光阻完全去掉,其后蚀刻可以形成共 通电极221和栅极231。具体说来,请参见图4a和图5a,对所述第一金属层230上的光阻曝光后,经过第一次显影和蚀刻,部分区域的第一金属层230和透明半导体层220被去掉,其后,通过第二次显影和蚀刻,形成共通电极221,最后,通过第三次显影,把剩余的光阻去掉,形成栅极231。在本实施例中,所述栅极231为双层材料,由第一金属层230和透明半导体层220构成,所述第一金属层230位于透明半导体层220上方。所述共通电极221由透明半导体层220构成。
在本实施例中,在步骤S120之后还包括S132:
通过所述第一光罩图案化所述第一金属层和透明半导体层还形成共通走线和扫描线,所述共通走线与所述共通电极电连接,所述扫描线与所述栅极电连接。
在本实施例中,请参见图4a和图5a,所述共通走线232和扫描线233的层级结构于栅极231一样,也是由两层材料构成。所述扫描线233与所述栅极231电连接,所述共通走线232与所述共通电极221电连接,从而扫描线233上的信号可以传输到栅极231,所述共通走线232传输的共通电压可以通过共通走线232传输到共通电极221。
S140:从下到上依序沉积栅极绝缘层、氧化物半导体层和第二金属层;
请参见图3b,在本实施例中,在形成的栅极231、扫描线233、共通电极221、共通走线232、基板210上面沉积栅极绝缘层240,在栅极绝缘层240上沉积氧化物半导体层250,在氧化物半导体层250上沉积第二金属层260。在这里,各层级的具体厚度根据实际需要而定。在本实施例中,所述氧化物半导体层250的材料为IGZO。
S150:通过第二光罩图案化所述氧化物半导体层和第二金属层形成有源层、像素电极、源极和漏极,其中,所述源极和漏极分别位于有源层的两侧上,所述漏极与所述像素电极电连接;
在本实施例中,所述第二光罩是半色调光罩(half tone mask),从而通过第二光罩一次曝光可以对第二金属层260上的光阻形成不同的曝光程度,其后通过几次显影去除掉不同区域的光阻,从而有的区域经过一次显影就可以把光阻去掉,有的区域需要几次显影才能把光阻完全去掉,经过蚀刻可以形成源 极261、漏极262、有源层251和像素电极252。具体说来,请参见图4b、图4c和图5b,对所述第二金属层260上的光阻曝光后,经过第一次显影和蚀刻,部分区域的第二金属层260和氧化物半导体层250被去掉,其后,通过第二次显影和蚀刻,像素电极252区域对应的氧化物半导体层250露出来,然后对该部分氧化物半导体层250进行掺杂氢离子处理,从而形成可以导电的像素电极252,而且像素电极252透光。之后,通过第三次显影、蚀刻,形成沟道区域对应的有源层251,接着,进行第四次显影,露出来源极261和漏极262。
请参见图4c,在本实施例中,源极261和漏极262下方也存在氧化物半导体层250,此处的氧化物半导体层250为有源层251的一部分,从而,有源层251由两部分构成:源极261和漏极262下面的氧化物半导体层250、源极261和漏极262之间的氧化物半导体层250(此时是露出来的),也可以如此看,在本实施例中,源极261和漏极262之间的有源层251竖直设置,可以称作纵向部251b,位于源极261和漏极262下面的有源层251部分为横向设置,可以称作横向部251a,也即有源层251由纵向部251b和横向部251a组成,在本实施例中,有源层251的结构为“Z”型。从而,由于有源层251包括纵向部251b,从而有源层251的横向沟道可以做的更短,可以提高开态电流,而且薄膜晶体管本身可以做的很小,从而可以提高开口率。
在本实施例中,所述漏极262和所述像素电极252电连接,所述像素电极252包括多条条形的子电极,所述子电极互相分离设置,所述子电极分别电连接到所述漏极262,从而漏极262上的信号可以传输各个子电极。在本实施例中,所述共通电极221和所述像素电极252分别是FFS模式液晶显示面板的两个电极。
在本实施例中,在步骤S140之后还包括:
通过所述第二光罩图案化所述第二金属层和所述氧化物半导体层还形成数据线。
在本实施例中,所述数据线263的下方也设有氧化物半导体层250。在本实施例中,所述数据线263与所述源极261电连接。
S160:沉积钝化层,且通过第三光罩图案化所述钝化层形成过孔。
请参见图3c和图4d,在本实施例中,在所述源极261、漏极262、有源 层251、栅极绝缘层240、像素电极252、数据线263上形成钝化层270,所述钝化层270用于保护下面的各个膜层,其后,通过第三光罩图案化所述钝化层270形成过孔271。在本实施例中,所述第三光罩为普通的光罩,不是半色调光罩。在本实施例中,所述过孔271位于源极261或者数据线263上方,用于与其他电路电连接,例如数据线263与周边线路的电连接等。
在本实施例中,由于FFS模式阵列基板通过3道光罩就可以制成,极大的简化了制程,从而降低了成本。而且,由于FFS模式阵列基板210是形成垂直结构薄膜晶体管,本实施例的垂直结构薄膜晶体管结构简单,而且横向沟道宽度可以做的很窄,可以使薄膜晶体管做的很小,有利于提高开口率,且可以提高开态电流。
本发明实施例还提供一种FFS模式阵列基板,请参见图3a-图5b,所述FFS模式阵列基板包括:
基板210;
共通电极221,其位于所述基板210上,其由透明半导体层220构成;
栅极231,其位于所述基板210上,其由透明半导体层220和第一金属层230构成;
栅极绝缘层240,其位于所述栅极231、共通电极221和基板210上;
有源层251,其位于所述栅极绝缘层240上,且由氧化物半导体层250构成;
源极261和漏极262,其分别位于所述有源层251上;
像素电极252,其位于栅极绝缘层240上且对应所述共通电极221设置,所述像素电极252与所述漏极262电连接;
钝化层270,其位于源极261、漏极262、像素电极252、栅极绝缘层240上,钝化层270上形成过孔271。
在本实施例中,所述FFS模式阵列基板210还包括扫描线233和共通走线232,所述共通走线232与所述共通电极221电连接,所述扫描线233与所述栅极231电连接。
在本实施例中,所述有源层251为“Z”型,所述有源层251包括两横向 部251a和纵向部251b,所述两横向部251a分别位于源极261和漏极262下方,所述两横向部251a形成高度差,所述纵向部251b位于两横向部251a之间。
在本实施例中,为了兼顾简化制程和提高穿透率,所述像素电极252由氧化物半导体层250图案化后掺杂氢离子形成,从而像素电极252由透光材料制成。
在本实施例中,所述像素电极252包括多条条形的子电极,所述子电极互相分离设置,所述子电极分别电连接到所述漏极262。
需要说明的是,本说明书中的各个实施例均采用递进的方式描述,每个实施例重点说明的都是与其它实施例的不同之处,各个实施例之间相同相似的部分互相参见即可。对于装置实施例而言,由于其与方法实施例基本相似,所以描述的比较简单,相关之处参见方法实施例的部分说明即可。
通过上述实施例的描述,本发明具有以下优点:
由于FFS模式阵列基板通过3道光罩就可以制成,极大的简化了制程,从而降低了成本。而且,由于FFS模式阵列基板是采用垂直结构薄膜晶体管,本实施例的垂直结构薄膜晶体管结构简单,而且横向沟道宽度可以做的很窄,可以使薄膜晶体管做的很小,有利于提高开口率,且可以提高开态电流。
以上所揭露的仅为本发明较佳实施例而已,当然不能以此来限定本发明之权利范围,因此依本发明权利要求所作的等同变化,仍属本发明所涵盖的范围。

Claims (10)

  1. 一种FFS模式阵列基板的制造方法,其中,所述FFS模式阵列基板包括垂直结构薄膜晶体管,所述方法包括:
    提供基板;
    在基板上依序沉积透明半导体层和第一金属层,所述第一金属层位于透明半导体层上;
    通过第一光罩图案化所述透明半导体层和第一金属层形成共通电极和栅极;
    从下到上依序沉积栅极绝缘层、氧化物半导体层和第二金属层;
    通过第二光罩图案化所述氧化物半导体层和第二金属层形成有源层、像素电极、源极和漏极,其中,所述源极和漏极分别位于有源层的两侧上,所述漏极与所述像素电极电连接;
    沉积钝化层,且通过第三光罩图案化所述钝化层形成过孔。
  2. 如权利要求1所述的FFS模式阵列基板的制造方法,其中,在所述在基板上依序沉积透明半导体层和第一金属层,所述第一金属层位于透明半导体层上的步骤之后还包括:
    通过所述第一光罩图案化所述第一金属层和透明半导体层,还形成共通走线和扫描线,所述共通走线与所述共通电极电连接,所述扫描线与所述栅极电连接。
  3. 如权利要求1所述的FFS模式阵列基板的制造方法,其中,所述有源层为“Z”型。
  4. 如权利要求1所述的FFS模式阵列基板的制造方法,其中,所述像素电极由氧化物半导体层图案化后掺杂氢离子形成。
  5. 如权利要求1所述的FFS模式阵列基板的制造方法,其中,所述第一 光罩和所述第二光罩为半色调光罩。
  6. 一种FFS模式阵列基板,其中,包括:
    基板;
    共通电极,其位于所述基板上,其由透明半导体层构成;
    栅极,其位于所述基板上,其由透明半导体层和第一金属层构成;
    栅极绝缘层,其位于所述栅极、共通电极和基板上;
    有源层,其位于所述栅极绝缘层上,且由氧化物半导体层构成;
    源极和漏极,其分别位于所述有源层上;
    像素电极,其位于栅极绝缘层上且对应所述共通电极设置,所述像素电极与所述漏极电连接;
    钝化层,其位于源极、漏极、像素电极、栅极绝缘层上,钝化层上形成过孔。
  7. 如权利要求6所述的FFS模式阵列基板,其中,还包括扫描线和共通走线,所述共通走线与所述共通电极电连接,所述扫描线与所述栅极电连接。
  8. 如权利要求6所述的FFS模式阵列基板,其中,所述有源层为“Z”型。
  9. 如权利要求6所述的FFS模式阵列基板,其中,所述像素电极由氧化物半导体层图案化后掺杂氢离子形成。
  10. 如权利要求6所述的FFS模式阵列基板,其中,所述像素电极包括多条条形的子电极,所述子电极互相分离设置,所述子电极分别连接到所述漏极。
PCT/CN2018/072627 2017-12-06 2018-01-15 Ffs模式阵列基板及其制造方法 WO2019109473A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201711277779.1 2017-12-06
CN201711277779.1A CN108054140B (zh) 2017-12-06 2017-12-06 Ffs模式阵列基板的制造方法

Publications (1)

Publication Number Publication Date
WO2019109473A1 true WO2019109473A1 (zh) 2019-06-13

Family

ID=62122377

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/072627 WO2019109473A1 (zh) 2017-12-06 2018-01-15 Ffs模式阵列基板及其制造方法

Country Status (2)

Country Link
CN (1) CN108054140B (zh)
WO (1) WO2019109473A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109119428B (zh) * 2018-07-18 2020-07-28 深圳市华星光电技术有限公司 Tft基板的制作方法
CN110600425B (zh) * 2019-08-20 2023-07-04 武汉华星光电技术有限公司 阵列基板的制备方法及阵列基板
CN110854203B (zh) * 2019-11-21 2023-10-03 京东方科技集团股份有限公司 薄膜晶体管、阵列基板、显示面板及显示装置
CN111261120B (zh) * 2020-01-21 2022-03-18 合肥京东方卓印科技有限公司 显示设备及其像素电路和显示面板
CN113690257B (zh) * 2021-08-26 2024-07-05 昆山龙腾光电股份有限公司 阵列基板及其制作方法和显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105068335A (zh) * 2015-08-12 2015-11-18 深圳市华星光电技术有限公司 一种ffs阵列基板的制造方法
CN106024706A (zh) * 2016-06-22 2016-10-12 深圳市华星光电技术有限公司 阵列基板及其制作方法
US20160372501A1 (en) * 2014-07-07 2016-12-22 Mitsubishi Electric Corporation Thin film transistor substrate and method for manufacturing the same
US20170069665A1 (en) * 2013-06-27 2017-03-09 Mitsubishi Electric Corporation Active matrix substrate and manufacturing method of the same
CN106502012A (zh) * 2017-01-03 2017-03-15 深圳市华星光电技术有限公司 Ffs模式的阵列基板及其制作方法
CN106910778A (zh) * 2017-03-29 2017-06-30 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102544029A (zh) * 2012-02-07 2012-07-04 深圳市华星光电技术有限公司 一种薄膜晶体管阵列基板及其制作方法
CN107068694B (zh) * 2017-04-26 2019-10-01 厦门天马微电子有限公司 半导体器件结构及其制作方法、阵列基板和显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170069665A1 (en) * 2013-06-27 2017-03-09 Mitsubishi Electric Corporation Active matrix substrate and manufacturing method of the same
US20160372501A1 (en) * 2014-07-07 2016-12-22 Mitsubishi Electric Corporation Thin film transistor substrate and method for manufacturing the same
CN105068335A (zh) * 2015-08-12 2015-11-18 深圳市华星光电技术有限公司 一种ffs阵列基板的制造方法
CN106024706A (zh) * 2016-06-22 2016-10-12 深圳市华星光电技术有限公司 阵列基板及其制作方法
CN106502012A (zh) * 2017-01-03 2017-03-15 深圳市华星光电技术有限公司 Ffs模式的阵列基板及其制作方法
CN106910778A (zh) * 2017-03-29 2017-06-30 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板

Also Published As

Publication number Publication date
CN108054140B (zh) 2020-11-06
CN108054140A (zh) 2018-05-18

Similar Documents

Publication Publication Date Title
US10795478B2 (en) Array substrate and preparation method therefor, and display apparatus
WO2019109473A1 (zh) Ffs模式阵列基板及其制造方法
JP5564464B2 (ja) Tft−lcdアレー基板及びその製造方法
CN106802519B (zh) 液晶显示装置及其制造方法
US8218117B2 (en) Liquid crystal display and method of manufacturing the same
WO2017166341A1 (zh) Tft基板的制作方法及制得的tft基板
US8860898B2 (en) Array substrate and liquid crystal display
US7799619B2 (en) Thin film transistor array substrate and fabricating method thereof
CN106024813B (zh) 一种低温多晶硅tft阵列基板的制作方法及相应装置
WO2013127201A1 (zh) 阵列基板和其制造方法以及显示装置
CN108400110B (zh) 薄膜晶体管阵列基板及其制备方法
WO2018205886A1 (zh) 薄膜晶体管及其制作方法、阵列基板和显示装置
CN103681514B (zh) 阵列基板及其制作方法、显示装置
US8067767B2 (en) Display substrate having vertical thin film transistor having a channel including an oxide semiconductor pattern
WO2019184416A1 (zh) 阵列基板及其制造方法、显示装置
CN111048524A (zh) 阵列基板及制备方法、显示面板
KR102224457B1 (ko) 표시장치와 그 제조 방법
WO2019090868A1 (zh) 垂直结构薄膜晶体管的制造方法及垂直结构薄膜晶体管
WO2016201778A1 (zh) 阵列基板及其制造方法
CN101419973B (zh) 一种三次光刻实现的tft像素结构及其制作方法
CN111739841A (zh) 一种顶栅结构的In-cell触控面板及制作方法
CN109037241B (zh) Ltps阵列基板及其制造方法、显示面板
WO2021097995A1 (zh) 一种阵列基板及其制备方法
CN106298523B (zh) 薄膜晶体管、薄膜晶体管的制造方法及阵列基板的制造方法
WO2020047957A1 (zh) 一种阵列基板的制造方法、阵列基板及显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18885038

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18885038

Country of ref document: EP

Kind code of ref document: A1