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WO2019102834A1 - Dispositif d'affichage et procédé de production de dispositif d'affichage - Google Patents

Dispositif d'affichage et procédé de production de dispositif d'affichage Download PDF

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Publication number
WO2019102834A1
WO2019102834A1 PCT/JP2018/041046 JP2018041046W WO2019102834A1 WO 2019102834 A1 WO2019102834 A1 WO 2019102834A1 JP 2018041046 W JP2018041046 W JP 2018041046W WO 2019102834 A1 WO2019102834 A1 WO 2019102834A1
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WO
WIPO (PCT)
Prior art keywords
insulating film
wiring
display device
film
groove
Prior art date
Application number
PCT/JP2018/041046
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English (en)
Japanese (ja)
Inventor
武 栗谷川
Original Assignee
株式会社ジャパンディスプレイ
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Filing date
Publication date
Application filed by 株式会社ジャパンディスプレイ filed Critical 株式会社ジャパンディスプレイ
Publication of WO2019102834A1 publication Critical patent/WO2019102834A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/10—Apparatus or processes specially adapted to the manufacture of electroluminescent light sources
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional radiating surfaces
    • H05B33/22—Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of auxiliary dielectric or reflective layers

Definitions

  • One embodiment of the present invention relates to a display device, for example, a display device having an organic light emitting element as a display element, and a method of manufacturing the same.
  • Examples of the display device include a liquid crystal display device and an organic EL (Electroluminescence) display device. These display devices each have a liquid crystal element or an organic light emitting element (hereinafter, light emitting element) as a display element in each of a plurality of pixels formed on a substrate.
  • a liquid crystal element or a light emitting element has a layer containing a compound exhibiting liquid crystallinity, or a layer containing a light emitting organic compound (hereinafter referred to as an electroluminescent layer or an EL layer), between a pair of electrodes (cathode and anode) It is driven by applying a voltage or supplying a current between the electrodes.
  • a display device having a curved shape and a display device which can be freely deformed by the user can be provided.
  • the area ratio of the display area is apparently increased by bending the substrate so that the portion not involved in the display overlaps the display area as disclosed in Patent Document 1, and the designability is improved.
  • the display device includes: a substrate having a display region and a wiring region, a pixel on the display region, a substrate in contact with the substrate on the wiring region, an organic compound, an insulating film having a groove, and an insulating film And a wiring extending from the display area to the edge of the substrate.
  • the wiring intersects the groove.
  • One of the embodiments of the present invention is a method of manufacturing a display device.
  • an undercoat that overlaps the display area and the wiring area is formed on a substrate having the display area and the wiring area, a semiconductor film, a gate electrode, and a semiconductor film and a gate electrode on the undercoat of the display area.
  • a gate insulating film to be sandwiched such that the gate insulating film extends from the display region to the wiring region, forming an interlayer film overlapping the semiconductor film, the gate electrode, and the gate insulating film of the wiring region, an undercoat, Exposing the substrate in the wiring region by partially removing the gate insulating film and the interlayer film, forming an insulating film in contact with the exposed substrate in the wiring region, forming a trench in the insulating film, Forming a wire that intersects the trench.
  • FIG. 1 is a schematic top view of a display device according to an embodiment of the present invention.
  • FIG. 1 is a schematic side view of a display device according to an embodiment of the present invention.
  • FIG. 1 is a schematic top view of a display device according to an embodiment of the present invention.
  • FIG. 1 is a schematic top view of a display device according to an embodiment of the present invention.
  • 6 illustrates an example of an equivalent circuit of a pixel of a display device according to an embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the display device of the embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the display device of the embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the display device of the embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the display device of the embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the display device of the embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the display device of the embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the display device of the embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the display device of the embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the display device of the embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the display device of the embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the display device of the embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the display device of the embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the display device of the embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the display device of the embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the display device of the embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the display device of the embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the display device of the embodiment of the present invention.
  • the plurality of films when a plurality of films are formed by performing etching or light irradiation on a certain film, the plurality of films may have different functions and roles. However, the plurality of films are derived from the film formed as the same layer in the same step, and have the same layer structure and the same material. Therefore, these multiple films are defined as existing in the same layer.
  • a certain structure is exposed from another structure means an aspect in which a part of a certain structure is not covered by another structure.
  • the part not covered by the structure also includes the aspect covered by another structure.
  • the structure of the display device 100 which is one of the embodiments of the present invention will be described.
  • a schematic top view of the display device 100 is shown in FIG.
  • the display device 100 has a substrate 102, and has various insulating films, semiconductor films, and conductive films patterned thereon. By appropriately combining these films, a scan line driver circuit 108 for driving the plurality of pixels 104 and the pixels 104 is formed.
  • Each pixel 104 is a minimum unit for providing color information, and is an area including a pixel circuit for driving a display element as described later.
  • the plurality of pixels 104 are periodically arranged to define a display area 106.
  • a light emitting element is used as a display element will be described.
  • the scanning line side drive circuit 108 is disposed around the display area 106.
  • Wiring 112 extends from the display area 106 and the scanning line drive circuit 108 to the end of the substrate 102, and the wiring is exposed near the end of the substrate 102 to form a terminal 128 (described later).
  • These terminals 128 are electrically connected to a connector 114 such as a flexible printed circuit board (FPC).
  • a drive IC 116 having an integrated circuit formed on a semiconductor substrate is further mounted on the connector 114. Video signals and power are transmitted from the external circuit (not shown) to the scan line driver circuit 108 and each pixel 104 through the driver IC 116, the connector 114, and the wiring 112.
  • the pixels 104 are controlled and driven based on these video signals and power sources, and a video is displayed on the display area 106.
  • the mode of the drive circuit and the drive IC 116 is not limited to the mode shown in FIG. 1.
  • the drive IC 116 may be mounted on the substrate 102, and a part of the functions of the drive IC 116 is formed on the substrate 102 as a drive circuit. It is also good.
  • the display device 100 can be deformed into any shape.
  • the display device 100 can be bent in a region (hereinafter, a wiring region) 120 in which the wiring 112 is provided, that is, a region between the display region 106 and an end portion of the substrate 102.
  • a wiring region 120 A schematic side view of the three-dimensional structure at this time is shown in FIG.
  • FIG. 2 by bending the wiring region 120 and the wiring 112 provided in this region, the end portion of the substrate 102 and the connector 114 can be arranged so as to overlap with the display region 106.
  • a spacer 122 may be provided to stabilize the three-dimensional structure.
  • FIGS. 3A and 3B An enlarged top view of the wiring area 120 is schematically shown in FIGS. 3A and 3B.
  • the wiring 112 is provided between the display area 106 and the edge of the substrate 102. As shown in FIG. 3A, the wiring 112 may be formed in a straight line from the display area 106 and the scanning line driver circuit 108 to the end of the substrate 102, and as shown in FIG. 3B, a zigzag shape in plan view It may be formed to have In the latter case, each wire 112 has a plurality of straight portions, and the directions of the vectors of the adjacent straight portions are different.
  • the insulating film 124 is provided under the wiring 112, and the insulating film 124 is provided with one or a plurality of grooves 126 intersecting with the wiring 112.
  • Pixel structure 2-1. Pixel Circuit
  • a pixel circuit including the light emitting element OLED is formed of various patterned insulating films, semiconductor films, and conductive films.
  • the configuration of the pixel circuit can be arbitrarily selected, an example of which is shown in FIG. 4 as an equivalent circuit.
  • the pixel circuit shown by the equivalent circuit of FIG. 4 includes, in addition to the light emitting element OLED, a drive transistor DRT, a light emission control transistor BCT, a correction transistor CCT, an initialization transistor IST, a write transistor SST, a holding capacitance Cs, and an additional capacitance Cad. ing.
  • the capacitance Cel is not an independent capacitance element but a parasitic capacitance of the light emitting element OLED.
  • the high potential power supply line 130 is supplied with the high potential PVDD, and this potential is supplied to the pixels 104 arranged in each column via the current supply line 132.
  • the light emitting element OLED, the drive transistor DRT, the light emission control transistor BCT, and the correction transistor CCT are connected in series between the high potential power supply line 130 and the low potential power supply line 134.
  • Low potential power supply line 134 is supplied with low potential PVSS.
  • One terminal of the drive transistor DRT is electrically connected to the high potential power supply line 130 via the light emission control transistor BCT and the correction transistor CCT, and the other terminal is electrically connected to the light emitting element OLED.
  • the gate of the drive transistor DRT is electrically connected to the first signal line 136 via the initialization transistor IST, and electrically connected to the second signal line 138 via the write transistor SST.
  • the initialization signal Vini is applied to the first signal line 136, and the video signal Vsig is applied to the second signal line 138.
  • the initialization signal Vini is a signal giving an initialization potential of a fixed level.
  • Write transistor SST has its operation (on / off) controlled by scan signal SG applied to write control scan line 140 connected to its gate.
  • the gate of the initialization transistor IST is connected to an initialization control scan line 142 to which an initialization control signal IG is applied, and the operation is controlled by the initialization control signal IG.
  • the write transistor SST is on and the initialization transistor IST is off, the potential of the video signal Vsig is applied to the gate of the drive transistor DRT.
  • the write transistor SST is off and the initialization transistor IST is on, the potential of the initialization signal Vini is applied to the gate of the drive transistor DRT.
  • a correction control scanning line 144 to which a correction control signal CG is applied and a light emission control scanning line 148 to which a light emission control signal BG is applied are connected to the gates of the correction transistor CCT and the light emission control transistor BCT, respectively.
  • the reset control line 146 is connected to one terminal of the drive transistor DRT via the correction transistor CCT.
  • the reset control line 146 is connected to a reset transistor RST provided in the scan line driver circuit 108.
  • the reset transistor RST is controlled by the reset control signal RG, whereby the reset potential Vrst applied to the reset signal line 150 can be applied to one terminal of the drive transistor DRT via the correction transistor CCT.
  • a storage capacitor Cs is provided between the other terminal of the drive transistor DRT and the gate.
  • One terminal of the additional capacitance Cad is connected to the other terminal of the drive transistor DRT, and the other terminal is connected to the high potential power supply line 130.
  • the additional capacitance Cad may be provided such that the other terminal is connected to the low potential power supply line 134.
  • the storage capacitor Cs and the additional capacitor Cad are provided to hold a gate-source voltage Vgs according to the video signal Vsig when the video signal Vsig is applied to the gate of the drive transistor DRT.
  • the drive IC 116 outputs the initialization signal Vini and the video signal Vsig to the first signal line 136 and the second signal line 138, respectively.
  • the scanning line drive circuit 108 outputs the scanning signal SG to the write control scanning line 140, outputs the initialization control signal IG to the initialization control scanning line 142, and outputs the correction control signal CG to the correction control scanning line 144.
  • the light emission control signal BG is output to the light emission control scanning line 148, and the reset control signal RG is output to the gate of the reset transistor RST.
  • FIG. 5 shows a schematic cross-sectional view of the display device 100. As shown in FIG. FIG. 5 shows a cross-sectional structure of the drive transistor DRT, the storage capacitor Cs, the additional capacitor Cad, and the light emitting element OLED among the pixel circuits of the three adjacent pixels 104 formed on the substrate 102.
  • the substrate 102 can include glass, quartz, or plastic. By using a plastic, the substrate 102 can have flexibility. Examples of the plastic include polymers such as polyimide, polyamide, polyester, polycarbonate and the like, and among them, polyimide having high heat resistance is preferable.
  • the undercoat 160 may have a single layer structure as shown in FIG. 5 or may be composed of a plurality of films. In the case of using a plurality of films, a film containing silicon oxide, a film containing silicon nitride, and a film containing silicon oxide may be sequentially formed over the substrate 102.
  • the driving transistor DRT includes a semiconductor film 162, a gate insulating film 164, a gate electrode 166, and source / drain electrodes 168 and 170.
  • the gate insulating film 164 is sandwiched between the gate electrode 166 and the semiconductor film 162.
  • the gate electrode 166 is disposed to intersect at least a part of the semiconductor film 162 with the gate insulating film 164 interposed therebetween, and a channel region 162 a is formed in a region where the gate electrode 166 of the semiconductor film 162 overlaps.
  • the semiconductor film 162 further includes a channel region 162a, a low concentration impurity region 162c doped with an impurity, and a source / drain region 162b doped with an impurity.
  • the impurity concentration of the low concentration impurity region 162c is lower than that of the source / drain region 162b.
  • the drive transistor DRT is a top gate type transistor, but there is no limitation on the structure of the transistor included in the pixel circuit, and it may be a bottom gate type transistor.
  • the upper / lower relationship between the source / drain electrodes 168 and 170 and the semiconductor film 162 is not limited.
  • a capacitor electrode 172 present in the same layer as the gate electrode 166 is provided to overlap with one of the source / drain regions 162 b via the gate insulating film 164.
  • An interlayer film 174 is provided on the gate electrode 166 and the capacitor electrode 172.
  • An opening reaching the semiconductor film 162 is formed in the interlayer film 174 and the gate insulating film 164, and source / drain electrodes 168 and 170 are disposed to cover the opening.
  • a part of the source / drain electrode 170 overlaps with a part of the source / drain region 162 b and the capacitor electrode 172 through the interlayer film 174, and a part of the source / drain region 162 b, a part of the gate insulating film 164, a capacitor electrode A storage capacitance Cs is formed by the portion 172, the interlayer film 174, and a part of the source / drain electrode 170.
  • a planarization film 176 is further provided on the drive transistor DRT and the storage capacitor Cs.
  • the planarization film 176 has an opening reaching the source / drain electrode 170, and a connection electrode 178 covering the opening and a part of the top surface of the planarization film 176 is provided in contact with the source / drain electrode 170.
  • An additional capacitance electrode 180 is further provided on the planarization film 176.
  • the connection electrode 178 and the additional capacitance electrode 180 may be formed at the same time, or may be formed in different steps so as to have different materials. In the former case, the connection electrode 178 and the additional capacitance electrode 180 exist in the same layer and have the same composition.
  • An additional capacitance insulating film 182 is formed to cover the connection electrode 178 and the additional capacitance electrode 180.
  • the additional capacitance insulating film 182 does not cover a part of the connection electrode 178 at the opening of the planarization film 176, and exposes the upper surface of the connection electrode 178. Thereby, the electrical connection between the pixel electrode 190 and the source / drain electrode 170 provided thereon is enabled via the connection electrode 178.
  • the additional capacitance insulating film 182 may be provided with an opening 186 for permitting contact between the partition 184 provided thereon and the planarizing film 176. The formation of the connection electrode 178 and the opening 186 is optional.
  • connection electrode 178 By providing the connection electrode 178, corrosion of the surface of the source / drain electrode 168 can be prevented in a subsequent process, and an increase in contact resistance of the source / drain electrode 168 can be prevented. Impurities in the planarization film 176 can be removed through the opening 186, which can improve the reliability of the pixel circuit and the light emitting element OLED included in the pixel circuit.
  • a pixel electrode 190 is provided on the additional capacitance insulating film 182 so as to cover the connection electrode 178 and the additional capacitance electrode 180.
  • the storage capacitor insulating film 182 is sandwiched between the storage capacitor electrode 180 and the pixel electrode 190, and a storage capacitor Cad is formed by this structure.
  • the pixel electrode 190 is shared by the additional capacitance Cad and the light emitting element OLED.
  • a partition 184 covering the end of the pixel electrode 190 is provided on the pixel electrode 190.
  • the partition wall 184 unevenness due to the pixel electrode 190 can be alleviated, and cutting of the electroluminescent layer (hereinafter, EL layer) 192 and the counter electrode 194 provided thereon can be prevented.
  • An EL layer 192 and a counter electrode 194 covering the EL layer 192 are provided to cover the partition wall 184 and the pixel electrode 190.
  • the pixel electrode 190 is configured to transmit visible light.
  • the pixel electrode 190 is configured to reflect visible light.
  • the pixel electrode 190 contains a metal such as silver or aluminum having a high reflectance of visible light.
  • the pixel electrode 190 may have a stacked structure of a film containing a conductive oxide and a film containing a metal with high reflectance. For example, a stacked structure of a first conductive film containing a conductive oxide, a second conductive film containing a metal such as silver or aluminum, and a third conductive film containing a conductive oxide can be employed.
  • the structure of the EL layer 192 is arbitrary, and the EL layer 192 includes a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer, an electron blocking layer, a hole blocking layer, an exciton blocking layer, etc. These functional layers can be combined as appropriate.
  • the structure of the EL layer 192 may be the same between all the pixels 104, and some structures may differ between the adjacent pixels 104.
  • the pixels 104 may be configured such that the structure or material of the light emitting layer is different between adjacent pixels 104, and the other layers have the same structure.
  • a hole transport layer 192a, a light emitting layer 192b, and an electron transport layer 192c are shown as representative functional layers in consideration of easy viewing.
  • the counter electrode 194 is configured to reflect visible light.
  • the counter electrode 194 is formed using a metal with high reflectance such as aluminum, silver, magnesium or an alloy thereof (for example, an alloy of magnesium and silver).
  • the pixel electrode 190 is configured to include a conductive oxide capable of transmitting visible light.
  • the above-described metal or alloy film may be formed to a thickness that allows visible light to pass. In this case, a conductive oxide film showing translucency to visible light may be further formed.
  • a passivation film 196 is disposed on the counter electrode 194 as an optional configuration.
  • the structure of the passivation film 196 can be arbitrarily determined, and either a single layer structure or a laminated structure may be employed. In the case of having a stacked structure, for example, a structure in which a first layer 196a containing a silicon-containing inorganic compound, a second layer 196b containing a resin, and a third layer 196c containing a silicon-containing inorganic compound can be sequentially stacked can be employed.
  • the silicon-containing inorganic compound include silicon nitride and silicon oxide.
  • the resin include epoxy resin, acrylic resin, polyester, polycarbonate and the like.
  • FIG. 6 is a schematic cross-sectional view taken along the dashed-dotted line AA 'in FIG.
  • the undercoat 160, the gate insulating film 164, and the interlayer film 174 are provided in the display region 106. These are provided so as to extend also in the wiring region 120, but some of these are removed in the wiring region 120 as shown in FIG. That is, the undercoat 160, the gate insulating film 164, and the interlayer film 174 all have openings overlapping each other, and the substrate 102 is exposed at these openings. In the example shown in FIG. 6, the entire opening of the undercoat 160 overlaps the opening of the gate insulating film 164 and the interlayer film 174.
  • these openings may be formed so that the sidewalls of the openings of the undercoat 160, the gate insulating film 164, and the interlayer film 174 are coplanar.
  • An insulating film 124 is provided to cover these openings. The insulating film 124 covers the undercoat 160, the gate insulating film 164, and part of the interlayer film 174.
  • the insulating film 124 contains an organic compound, and examples of the organic compound include polymers such as resin.
  • the polymer is selected from acrylic resins, epoxy resins, polyimides, polyamides, polyesters, polyolefins, polycarbonates, polysiloxanes, etc., and may have a chain structure or may be crosslinked between molecules .
  • the insulating film 124 is provided with one or more grooves 126. As shown in FIGS. 3A and 3B, the groove 126 may be disposed parallel to the short side of the substrate 102 or may be disposed to be inclined from the short side.
  • the width of the groove 126 can be, for example, 100 ⁇ m to 2 mm, 100 ⁇ m to 1 mm, or 200 ⁇ m to 500 ⁇ m.
  • the wiring 112 is provided on the insulating film 124, contacts the insulating film 124 in the wiring region 120, and intersects with the groove 126 as shown in FIGS. 3A and 3B. Therefore, the wiring 112 is also in contact with the side wall and the bottom of the groove 126.
  • the interlayer film 174 is in contact with the wiring 112 in a region where the insulating film 124 is not provided in the wiring region 120.
  • the wiring 112 may be any of the first signal line 136, the second signal line 138, or the current supply line 132 shown in FIG.
  • the wiring 112 is configured to transmit the initialization signal Vini
  • the wiring 112 is configured to transmit the video signal Vsig
  • the high potential PVDD is configured to be transmitted.
  • the wiring 112 may be in the same layer as the source / drain electrodes of the transistor provided in the pixel 104 (eg, the source / drain electrodes 168 and 170 of the driving transistor DRT).
  • a current supply line 132 not shown in FIG. 5 is provided between the gate electrode 166 and the source / drain electrodes 168 and 170, and exists in the same layer as the current supply line 132.
  • the wiring 112 may be formed by the following wiring.
  • the thickness of the insulating film 124 can be set arbitrarily.
  • the thickness T between adjacent grooves 126 is the total thickness of the undercoat 160, the gate insulating film 164, and the interlayer film 174. It may be smaller or the same. In this case, as shown in FIG. 6, the insulating film 124 may have a convex portion in a region overlapping with the interlayer film 174.
  • the thickness T may be larger than the total thickness of the undercoat 160, the gate insulating film 164, and the interlayer film 174.
  • the groove 126 may be provided to expose the substrate 102 in the groove 126. In this case, the wiring 112 is in contact with the substrate 102 in the groove 126.
  • an insulating film is provided on the wiring 112 and the wiring 112 is protected.
  • the additional capacitance insulating film 182 provided in the pixel 104 extends from the display region 106 to the wiring region 120 and is disposed on the wiring 112 so as to be in contact with the wiring 112.
  • the wire 112 extends to near the end of the substrate 102 and is exposed from the additional capacitance insulating film 182 to provide a terminal 128.
  • a protective conductive film 188 for protecting the wiring 112 is provided over the wiring 112, and the additional capacitance insulating film 182 covers a part of the protective conductive film 188.
  • the protective conductive film 188 is present, for example, in the same layer as the connection electrode 178 or the additional capacitance electrode 180, and preferably contains a conductive oxide such as ITO or IZO.
  • planarizing film 176 and the passivation film 196 do not overlap with the insulating film 124 in the example shown in FIG. 6, the planarizing film 176 may overlap with part of the insulating film 124 as shown in FIG. However, it may overlap with all of the plurality of grooves 126. Further, as shown in FIG. 10, the passivation film 196 may overlap with part of the insulating film 124, and although not shown, it may overlap with all of the plurality of grooves 126.
  • the cross-sectional shape of the groove 126 of the insulating film 124 does not have to be a strict polygon. For example, as shown in the enlarged view (FIG. 11) of the region surrounded by the dotted line in FIG. May be formed.
  • the insulating film 124 may be formed so that the top of the insulating film 124 located on the interlayer film 174 is also rounded.
  • the cross-sectional shape of the wiring 112 in the wiring region 120 is constituted by a plurality of straight portions, and the adjacent straight portions have different vector directions.
  • the wiring 112 has a plurality of bending points. Therefore, when the wiring region 120 is bent to deform the display device 100, not only the deformation of the linear portion but also the change in angle between the vectors of two adjacent linear portions contributes to the deformation of the display device 100. be able to. Therefore, the force applied to the wiring 112 at the time of deformation of the display device 100 is delocalized, and destruction of the wiring 112 can be prevented. Accordingly, the occurrence of defects due to the disconnection of the wiring 112 can be suppressed, and high reliability can be given to the display device 100.
  • FIGS. 12A to 20 a method for manufacturing the flexible display device 100 will be described with reference to FIGS. 12A to 20.
  • the one on the left shows the pixel 104 in the display area 106 and corresponds to a part of the cross-sectional view of FIG.
  • the drawing on the right side is a cross-sectional view of a part of the wiring region 120, which corresponds to a part of the cross-sectional view of FIG. Description of the same or similar configuration as the first embodiment may be omitted.
  • the substrate 102 is formed on the support substrate 118 (FIG. 12A).
  • the support substrate 118 contains glass, quartz or the like, and its size and thickness can be arbitrarily selected.
  • a glass plate having a size of 68 cm ⁇ 88 cm, 110 cm ⁇ 130 cm, 150 cm ⁇ 185 cm, or 220 cm ⁇ 250 cm can be used as the support substrate 118.
  • the thickness of the support substrate 118 can be arbitrarily selected in the range of 0.1 mm to 10 mm, and is typically 0.5 mm to 0.7 mm.
  • the substrate 102 is an insulating film exhibiting flexibility, and can include a material selected from polymeric materials exemplified by polyimide, polyamide, polyester, and polycarbonate.
  • the substrate 102 is formed by applying a wet film forming method such as a printing method, an inkjet method, a spin coating method, a dip coating method, or a laminating method. When flexibility is not given to the display device 100, the formation of the substrate 102 may be omitted.
  • an undercoat 160 is formed on the substrate 102 (FIG. 12A).
  • the undercoat 160 is provided in both the display area 106 and the wiring area 120.
  • FIG. 12A shows a form in which the undercoat 160 is composed of a single layer, the undercoat 160 may have a three-layer structure as described in the first embodiment.
  • the undercoat 160 can be formed using a chemical vapor deposition (CVD) method or a sputtering method.
  • CVD chemical vapor deposition
  • a light shielding film that blocks visible light may be provided in a region where a transistor is formed.
  • a semiconductor film 162 is formed on the undercoat 160 (FIG. 12A).
  • the semiconductor film 162 may be formed by a CVD method using a silane gas or the like as a raw material.
  • the obtained amorphous silicon may be crystallized by heat treatment or light irradiation with a laser or the like.
  • a resist mask (not shown) is formed in a region where the channel region 162a and the low concentration impurity region 162c of the semiconductor film 162 are formed, and doping (first doping) is performed on the semiconductor film 162 to form a source / drain region 162b.
  • Form FIG. 12A. Doping can be carried out by applying known methods.
  • a gate insulating film 164 is formed to cover the semiconductor film 162 (FIG. 12B).
  • the gate insulating film 164 is also provided on the undercoat 160 in the wiring region 120.
  • the gate insulating film 164 also includes one or more films containing silicon nitride or silicon oxide, and is formed by applying a CVD method or a sputtering method.
  • the gate electrode 166 and the capacitor electrode 172 are formed on the gate insulating film 164 by sputtering or CVD (FIG. 12B).
  • various scanning lines write control scanning line 140, initialization control scanning line 142, correction control scanning line 144, light emission control scanning line 148, reset control line 146, etc.
  • the metal contained in the gate electrode 166 and the capacitor electrode 172 include titanium, aluminum, copper, molybdenum, tungsten, tantalum, an alloy of these, and the like.
  • These electrodes and wirings may have a single-layer structure or a stacked structure. For example, a structure in which a metal having high conductivity such as copper or aluminum is sandwiched between metals having a high melting point such as molybdenum or titanium can be employed.
  • doping (second doping) is performed on the semiconductor film 162 by a known method using the gate electrode 166 as a mask.
  • a low concentration impurity region 162c is formed, and a channel region 162a overlapping with the gate electrode 166 is formed (FIG. 12C).
  • an interlayer film 174 is formed over the gate electrode 166 and the capacitor electrode 172 (FIG. 12C). Interlayer film 174 is also formed in interconnection region 120.
  • the interlayer film 174 also contains a material that can be used for the undercoat 160 and the gate insulating film 164, and is formed to have a single layer structure or a laminated structure by applying a CVD method or a sputtering method.
  • the interlayer film 174 and the gate insulating film 164 are etched to form an opening 210 reaching the source / drain region 162b (FIG. 13A). At this time, etching is simultaneously performed on the interlayer film 174 and the gate insulating film 164 located in the wiring region 120 to form the opening 212.
  • the undercoat 160 is exposed in the wiring region 120.
  • the exposed undercoat 160 in the wiring area 120 is etched to form an opening 214 for exposing the substrate 102 (FIG. 13B).
  • the openings 210, 212, and 214 can be formed, for example, by performing plasma etching in a gas containing a fluorine-containing hydrocarbon.
  • the insulating film 124 is formed in the wiring region 120.
  • the polymer described in the first embodiment is used as a basic skeleton, and a photosensitive resin (hereinafter, photosensitive resin) 200 is formed on the substrate 102 (FIG. 13C).
  • the photosensitive resin 200 is formed on the display area 106 and the wiring area 120 using a spin coating method, a printing method, an inkjet method, or the like.
  • the upper surface of the photosensitive resin 200 may be at a position lower than the upper surface of the photosensitive resin 200 in the area where the openings 212 and 214 do not exist.
  • the photomask 204 is a half tone mask or a gray tone mask which has a substrate 204 a which transmits light to be irradiated, and on which a light shielding portion 204 b and a semi-light transmitting portion 204 c are provided. A portion where neither the light shielding portion 204 b nor the semi-light transmitting portion 204 c is provided functions as a light transmitting portion, and the transmittance for the irradiation light is, for example, 75% to 100%, or 80% to 100%.
  • the light blocking portion 204b is a region that blocks the irradiation light, and the transmittance thereof is, for example, 0% or more and 5% or less, 0% or more and 2% or less, or 0% or more and 1% or less, and may be substantially 0%.
  • the semi-transparent portion 204c partially transmits the irradiation light and blocks a part. Therefore, the transmittance to the irradiation light is 20% or more and 60% or less, 30% or more and 50% or less, and typically 40%.
  • the photo mask is formed so that the semitransparent portion 204c overlaps the region where the groove 126 is provided, the light shielding portion 204b overlaps the region where the groove 126 is not formed although the insulating film 124 is provided, and the light transmission portion overlaps the region where the insulating film 124 is not formed.
  • the semi-translucent part 204 c when the substrate 102 is exposed in the groove 126, the semi-translucent part 204 c is not provided, and a photo is emitted so that the region where the groove 126 is to be formed is transmitted through the translucent part.
  • the mask 204 may be designed and arranged.
  • a metal film is formed on the substrate 102, and etching is performed to form the source / drain electrodes 168 and 170 connected to the source / drain region 162b.
  • the wiring 112 in contact with the film 124 is formed (FIG. 14B).
  • the first signal line 136, the second signal line 138, the high potential power supply line 130, the low potential power supply line 134, and the current supply line 132 may be formed.
  • the drive transistor DRT and the storage capacitor Cs are formed by the process up to this point.
  • the current supply line 132 is formed on the interlayer film 174, and the second interlayer film is formed thereon, and then the first signal line 136, the second signal line 138, the high potential power supply line 130, and the low potential
  • the power supply line 134 may be formed simultaneously with the wiring 112 and the source / drain electrodes 168 and 170.
  • a planarization film 176 is formed to cover the drive transistor DRT, the storage capacitor Cs, and the like (FIG. 14B).
  • the planarizing film 176 contains a polymer material such as epoxy resin, acrylic resin, polyimide, polyester, polycarbonate, etc., and can be formed by applying a spin coating method, an ink jet method, a printing method, a dip coating method, or the like. Thereafter, the planarizing film 176 is etched to form an opening reaching the source / drain electrode 170, and the unnecessary planarizing film 176 is appropriately removed in the wiring region 120 to expose a part of the wiring 112 (see FIG. Figure 14C).
  • connection electrode 178 is formed so as to cover the opening for exposing the source / drain electrode 168, and the additional capacitance electrode 180 is formed on the flattening film 176 (FIG. 14C).
  • a protective conductive film 188 is simultaneously formed on the wiring 112 (see FIG. 6).
  • the connection electrode 178, the additional capacitance electrode 180, and the protective conductive film 188 can be formed, for example, by sputtering a conductive oxide.
  • a storage capacitor insulating film 182 is formed so as to cover the connection electrode 178, the storage capacitor electrode 180, and the protective conductive film 188 (FIG. 15A, FIG. 6).
  • the additional capacitance insulating film 182 can also contain an inorganic compound such as silicon nitride or silicon oxide, and can be formed by applying a CVD method or a sputtering method.
  • the additional capacitance insulating film 182 has an opening that exposes a part of the top surface of the connection electrode 178. In this opening, electrical connection between the pixel electrode 190 of the light emitting element OLED and the connection electrode 178 is performed.
  • the pixel electrode 190 is formed using a sputtering method or a CVD method so as to be in contact with the connection electrode 178 and to overlap with the additional capacitance electrode 180. (FIG. 15A). Thereafter, a partition wall 184 is formed to cover the end of the pixel electrode 190 (FIG. 15B).
  • the partition wall 184 can be formed using a polymer material such as an epoxy resin or an acrylic resin, and using a spin coating method, an inkjet method, or the like.
  • the partition wall 184 can absorb a difference in level due to the pixel electrode 190 and the like, and electrically insulate the pixel electrodes 190 of the adjacent pixels 104 from each other.
  • the EL layer 192 and the counter electrode 194 of the light emitting element OLED are formed so as to cover the pixel electrode 190 and the partition 184 (FIG. 16A).
  • the EL layer 192 is formed by applying a dry film formation method such as an inkjet method, a printing method, or a vapor deposition method.
  • the counter electrode 194 can also be formed using a sputtering method or an evaporation method.
  • a passivation film 196 is formed. As shown in FIG. 5, when the passivation film 196 has a three-layer structure, first, the first layer 196a is formed to cover the counter electrode 194 (FIG. 16A).
  • the first layer 196a contains an inorganic material such as silicon nitride or silicon oxide, for example, and is formed by applying a CVD method or a sputtering method.
  • the first layer 196 a can be provided so as to overlap with the wiring 112 and may be formed so as to cover the protective conductive film 188 although not shown.
  • the second layer 196 b is formed.
  • the second layer 196 b may be formed to have a flat surface so as to absorb unevenness due to the partition wall 184 and to provide a flat surface as shown in FIG. 16B.
  • the second layer 196 b can be formed by a printing method, an inkjet method, a spin coating method, or the like.
  • the oligomer serving as a raw material of the resin described in the first embodiment is atomized or gasified under reduced pressure, sprayed onto the first layer 196a, and then the second layer 196b is formed by polymerizing the oligomer. You may form.
  • the second layer 196 b is preferably formed so as not to cover the terminal 128. In the example shown in FIG.
  • the second layer 196 b is provided such that its end is farther from the terminal 128 than the end of the planarization film 176. That is, the second layer 196 b is formed such that the entire second layer 196 b overlaps with the planarization film 176.
  • a third layer 196c is formed in contact with the second layer 196b (FIG. 17).
  • the third layer 196c can comprise the materials available for the first layer 196a and can be formed in a manner applicable to the formation of the first layer 196a.
  • the third layer 196 c may also be formed to cover the protective conductive film 188.
  • a resin mask 216 is formed to cover the display region 106 and a part of the wiring region 120 (FIG. 17), and the first layer 196a exposed from the resin mask 216 is used.
  • the three layers 196c are removed by etching (FIG. 18). Although not shown, this exposes the protective conductive film 188 at the terminal 128.
  • the cap film 220 is disposed via the adhesive layer 218 so as to cover the display area 106 and the wiring area 120 (FIG. 19).
  • the cap film 220 can include a polyester such as poly (ethylene terephthalate), poly (ethylene naphthalate), a polyolefin such as polyethylene or polypropylene, a polymer such as polycarbonate, polyacrylate, or the like.
  • the cap film 220 can be formed by a lamination method or a wet film formation method.
  • the surface of the cap film 220 may be provided with a fluorine-containing polymer film such as polyvinylidene fluoride (PVDF) or polytetrafluoroethylene, or a polymer film having low gas permeability such as polyvinylidene chloride.
  • PVDF polyvinylidene fluoride
  • a polymer film having low gas permeability such as polyvinylidene chloride.
  • a light source such as a laser light source or a flash lamp to reduce the adhesion between the support substrate 118 and the substrate 102.
  • the support substrate 118 is physically peeled along the interface shown by the arrow in FIG. 19, that is, the interface between the support substrate 118 and the substrate 102. Thereby, the bottom surface of the substrate 102 is exposed.
  • the base film 222 is fixed to the bottom of the substrate 102 as an optional configuration.
  • the base film 222 can be fixed using a laminating method.
  • an adhesive layer may be used.
  • Base film 222 can include materials that can be used for cap film 220.
  • the flexible display device 100 can be manufactured by the above process.
  • the display device 100 can be manufactured by using a normal semiconductor manufacturing process. Therefore, by applying the present embodiment, it is possible to provide a highly reliable display device and a flexible display device without burdening the process.
  • an EL display device is mainly illustrated as a disclosed example
  • an electronic paper type display having another self-light emitting display device, a liquid crystal display device, or an electrophoretic element as another application example Devices include any flat panel type display device. Moreover, it is applicable without particular limitation from medium size to large size.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

La présente invention concerne un dispositif d'affichage comprenant : un substrat (102) doté d'une région d'affichage (106) et d'une région de câblage (120) ; un pixel (104) situé sur la région d'affichage (106) ; un film isolant (124) qui est en contact avec le substrat (102) sur la région de câblage (120), contient un composé organique et est pourvu d'une rainure (126) ; et une ligne de câblage (112) qui est positionnée sur le film isolant (124), est en contact avec le film isolant (124) et s'étend de la région d'affichage (106) à une extrémité du substrat (102). La ligne de câblage (112) croise la rainure (126). La ligne de câblage (112) peut être en contact avec le substrat (102) dans la rainure (126). Le pixel (104) peut comprendre un transistor comprenant lui-même un film d'isolation de grille (164) ; dans ce cas, le film d'isolation de grille (164) s'étend jusqu'à la région de câblage (120) et le film isolant (124) recouvre une partie du film d'isolation de grille (164).
PCT/JP2018/041046 2017-11-24 2018-11-05 Dispositif d'affichage et procédé de production de dispositif d'affichage WO2019102834A1 (fr)

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JP2017111435A (ja) * 2015-12-15 2017-06-22 エルジー ディスプレイ カンパニー リミテッド フレキシブル表示装置
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JP2018036761A (ja) * 2016-08-30 2018-03-08 株式会社ジャパンディスプレイ 表示装置
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JP2005150105A (ja) * 2003-10-24 2005-06-09 Semiconductor Energy Lab Co Ltd 表示装置及び表示装置の作製方法
JP2011034066A (ja) * 2009-07-07 2011-02-17 Semiconductor Energy Lab Co Ltd 表示装置
JP2014232300A (ja) * 2013-05-28 2014-12-11 エルジー ディスプレイ カンパニー リミテッド フレキシブル表示装置及びその製造方法
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JP2018180413A (ja) * 2017-04-19 2018-11-15 株式会社ジャパンディスプレイ 表示装置、および表示装置の製造方法

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