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WO2019007086A1 - 一种阵列基板及其制作方法、显示装置 - Google Patents

一种阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2019007086A1
WO2019007086A1 PCT/CN2018/077561 CN2018077561W WO2019007086A1 WO 2019007086 A1 WO2019007086 A1 WO 2019007086A1 CN 2018077561 W CN2018077561 W CN 2018077561W WO 2019007086 A1 WO2019007086 A1 WO 2019007086A1
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WIPO (PCT)
Prior art keywords
electrode
pad electrode
pad
sub
insulating layer
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Application number
PCT/CN2018/077561
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English (en)
French (fr)
Inventor
李云泽
杨妮
齐智坚
王小元
李少茹
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Publication date
Application filed by 京东方科技集团股份有限公司, 重庆京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/304,737 priority Critical patent/US11215893B2/en
Publication of WO2019007086A1 publication Critical patent/WO2019007086A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the ground is used in the field of high performance display.
  • Embodiments of the present disclosure provide an array substrate, a method of fabricating the same, and a display device.
  • Embodiments of the present disclosure adopt the following technical solutions.
  • An aspect of an embodiment of the present disclosure provides an array substrate including a plurality of pad structures in a bonding region and a plurality of data leads located in the lead regions, each data lead corresponding to a pad structure.
  • the pad structure includes at least two pad electrodes that are insulated from each other. In the pad structure, each pad electrode and the data lead corresponding to the pad structure are electrically connected to form different signal writing paths.
  • the array substrate further includes a substrate substrate, wherein the pad structure is sequentially disposed on the substrate substrate in a direction perpendicular to the substrate substrate, and is insulated from each other by a first pad electrode and Second pad electrode.
  • the array substrate further includes: a first insulating layer between the first pad electrode and the second pad electrode; and a second insulation covering the first insulating layer and the second pad electrode a first via located in the first insulating layer and the second insulating layer and reaching the first pad electrode, and located in the second insulating layer and reaching the second pad electrode a second via hole; a first via electrode and a second via electrode on the second insulating layer, wherein the first via electrode is electrically connected to the first pad electrode through the first via hole Connected, the second conductive electrode is electrically connected to the second pad electrode through the second via.
  • the extending direction of the first pad electrode is the same as the extending direction of the second pad electrode, and the orthographic projection of the second pad electrode on the substrate substrate is only A portion of the first pad electrode that is adjacent to the lead region in an orthographic projection on the base substrate overlaps. An end of the first pad electrode and the second pad electrode adjacent to the lead region is electrically connected to the data lead.
  • an orthographic projection of the first pad electrode on the substrate substrate and a front projection of the second pad electrode on the substrate substrate do not overlap.
  • the first pad electrode includes a first sub-portion and a second sub-portion, the first sub-portion being located at an end of the second pad electrode facing away from the data lead, and extending direction of the first sub-portion The direction of extension of the second pad electrode is the same.
  • the second sub-portion is located on a side of the second pad electrode in a direction perpendicular to the extending direction, and one end of the second sub-portion is connected to the first sub-portion, and the other end is Electrically connected to the data lead. An end of the second pad electrode adjacent to the lead region is electrically connected to the data lead.
  • the data lead is disposed in the same layer as the first pad electrode.
  • the array substrate further includes: a third via located in the first insulating layer and the second insulating layer and reaching a portion of the data lead adjacent to the binding region, wherein the second conductive electrode The data lead is also electrically connected through the third via.
  • the data lead includes a first sub-electrode and a second sub-electrode that overlap each other in a direction perpendicular to the base substrate.
  • the first sub-electrode is disposed in the same layer and connected to the first pad electrode
  • the second sub-electrode is disposed in the same layer and connected to the second pad electrode.
  • the array substrate further includes: a fourth via located in the first insulating layer and the second insulating layer and reaching a portion of the first sub-electrode remote from the binding region; a fifth via in the layer and reaching a portion of the second sub-electrode remote from the bonding region; and a third via electrode on the second insulating layer, the third via electrode passing through The fourth via and the fifth via electrically connect the first sub-electrode and the second sub-electrode.
  • the lead region includes a near terminal region at a central location and a distal subregion at both sides of the proximal terminal region.
  • the data lead in the near terminal region is a straight line extending in a first direction.
  • a portion of the data lead in the distal sub-region adjacent to the binding region is a straight line extending along the first direction, and the data lead in the distal sub-region is remote from the binding region Portion is a diagonal line that is inclined in a direction away from the near terminal region.
  • the first direction and the signal line connected to the data lead extend in the same direction.
  • the length of the second sub-electrode in the near-terminal region is smaller than the length of the second sub-electrode in the distal sub-region.
  • the array substrate further includes a gate line and a data line.
  • the gate line is disposed in the same layer as the first pad electrode, and the data line is disposed in the same layer as the second pad electrode.
  • the array substrate further includes a conductive protective layer covering the second conductive electrode, wherein the orthographic projection of the conductive protective layer on the base substrate and the third via are on the base substrate The orthographic projections on the top overlap.
  • Another aspect of an embodiment of the present disclosure provides a display device including the array substrate described in an aspect of an embodiment of the present disclosure.
  • Yet another aspect of an embodiment of the present disclosure provides a method for fabricating an array substrate described in an aspect of an embodiment of the present disclosure.
  • the method includes providing a substrate including a bonding region and a lead region, and forming a plurality of pad structures on the substrate in the bonding region, wherein the bonding pad
  • the structure includes at least two mutually insulated pad electrodes; a plurality of data leads are formed in the lead region on the base substrate, wherein each data lead corresponds to a pad structure, in the pad In the structure, each pad electrode and the data lead corresponding to the pad structure are electrically connected to form different signal writing paths.
  • the method for forming the pad structure includes: forming a first metal layer on the base substrate; patterning the first metal layer to form a first pad electrode; forming a first insulating layer to cover the a base substrate and the first pad electrode; forming a second metal layer on the first insulating layer; patterning the second metal layer to form a second pad electrode; forming a second insulating layer to cover the a first insulating layer and the second pad electrode; patterning the first insulating layer and the second insulating layer to form a second via reaching the second pad electrode and reaching the first solder a first via of the pad electrode; a conductive layer formed on the second insulating layer to fill the first via and the second via; patterning the conductive layer to form a first via and a second Conducting an electrode, the first conductive electrode is electrically connected to the first pad electrode through the first via hole, and the second via electrode passes through the second via hole and the second pad The electrodes are electrically connected.
  • the method for forming the data lead includes: forming the data lead disposed in the same layer as the first pad electrode and connected to the first pad electrode while forming the first pad electrode; Forming a first via hole in the first insulating layer and the second insulating layer to form a third via hole reaching a portion of the data lead adjacent to the binding region, wherein the second via The through electrode is also electrically connected to the data lead through the third via.
  • the method of forming the data lead includes: forming a first sub-paragraph of the data lead disposed in the same layer and connected to the first pad electrode while forming the first pad electrode An electrode; forming a second sub-electrode of the data lead disposed in the same layer and connected to the second pad electrode while forming the second pad electrode; forming the first via hole and the Forming a fourth via hole reaching a portion of the first sub-electrode away from the binding region and reaching the second in the first insulating layer and the second insulating layer while the second via hole is described a fifth via of the sub-electrode away from a portion of the bonding region; forming a third via electrode on the second insulating layer while forming the first via electrode and the second via electrode The third via electrode electrically connects the first sub-electrode and the second sub-electrode through the fourth via hole and the fifth via hole.
  • the first sub-electrode and the second sub-electrode constitute the data lead.
  • the method further includes forming a gate line and a data line in a display area of the array substrate. Forming the gate line in the same layer as the first pad electrode in the display region while forming the first pad electrode, and simultaneously forming the second pad electrode The display area forms the data line disposed in the same layer as the second pad electrode.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure
  • Figure 2 is a schematic structural view taken along line B-B of Figure 1;
  • FIG. 3a is a schematic view showing a specific structure of the pad structure of FIG. 1;
  • Figure 3b is a schematic structural view taken along line A-A of Figure 3a;
  • Figure 3c is a schematic structural view taken along line C-C of Figure 3a;
  • Figure 3d is a schematic structural view taken along line D-D of Figure 3a;
  • FIG. 4 is a schematic view showing a specific structure of the data lead of FIG. 1;
  • Figure 5 is a schematic view showing the specific division structure of the lead region of Figure 4.
  • Figure 6a is a schematic view showing another specific structure of the pad structure of Figure 1;
  • Figure 6b is a schematic structural view taken along line E-E of Figure 6a;
  • FIG. 7 is another schematic structural diagram of the data lead of FIG. 1;
  • FIG. 8 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • FIG. 9 is a flowchart of a specific method of step S102 in FIG. 8.
  • the TFT-LCD controls the electric field between the pixel electrode and the common electrode by binding some driving chips to achieve the purpose of controlling the deflection angle of the liquid crystal molecules, and finally displays the expected picture.
  • a pad electrode is usually formed in the bonding region of the array substrate of the TFT-LCD, and the surface of the pad electrode is covered with an insulating layer or a transparent conductive layer.
  • Embodiments of the present disclosure provide an array substrate. As shown in FIG. 1, the array substrate includes a plurality of pad structures 10 in the bonding region 01, and a plurality of data leads 20 in the lead regions 02. Each data lead 20 corresponds to a pad structure 10.
  • the array substrate includes a display area provided with sub-pixels, and a non-display area located around the display area. Binding area 01 and lead area 02 are located in the non-display area. Binding area 01 is used to bind the driver chip.
  • the driving chip may be, for example, a source driving chip that supplies a driving signal to the data line; or may be a gate driving chip that supplies a driving signal to the gate; or alternatively, may be in the array substrate a touch chip for reading a signal line to provide a touch signal; or, for an array substrate having a GOA (Gate Driver on Array) circuit, the driver chip may be used to provide the GOA circuit
  • the chip of the clock signal and the voltage source (VSS, VDD, VGL, VGH, etc.) is not limited in this disclosure.
  • the data lead 20 is used to connect the source driving chip with a data line (not shown) in the display area; or, when the driving chip is a gate driving chip
  • the data lead 20 is used to connect the gate drive chip to a gate line (not shown) in the display area.
  • the lead area 02 is located between the binding area 01 and the display area.
  • the data lead 20 can be referred to as a fan out lead.
  • the other data leads 20 in the non-display area are referred to as PLG (Propel Link Gate) traces.
  • the PLG trace is used to phase the driver chip with the signal control terminal (eg, the clock signal terminal, the voltage terminal) of each shift register unit in the GOA circuit. connection.
  • the pad structure 10 includes at least two pad electrodes that are insulated from each other.
  • each pad electrode is electrically connected to the data lead 20 corresponding to the pad structure 10 to constitute a different signal writing path.
  • the other pad electrode can still maintain the normal signal transmission of the pad structure 10 and the data lead 20, thereby improving the array substrate. Quality, reducing the risk of substrate defects and manufacturing costs.
  • the pad structure 10 includes first pad electrodes sequentially disposed on the substrate substrate 03 in the direction perpendicular to the substrate substrate 03 and insulated from each other. 101 and second pad electrode 102.
  • the array substrate further includes: a first insulating layer between the first pad electrode 101 and the second pad electrode 102 a second insulating layer 112 covering the first insulating layer 111 and the second pad electrode 102; a first via 131 located in the first insulating layer 111 and the second insulating layer 112 and reaching the first pad electrode 101, And a second via 132 located in the second insulating layer 112 and reaching the second pad electrode 102; a first via electrode 121 and a second via electrode 122 on the second insulating layer 112.
  • the first via electrode 121 is electrically connected to the first pad electrode 101 through the first via 131.
  • a contact structure on the driving chip (not shown) is in contact with the first conductive electrode 121 in a pad structure 10 on the array substrate. Since the first pad electrode 101 is electrically connected to the data lead 20, the first pad electrode 101 and the data lead 20 constitute a first signal writing path for driving the chip output signal, so that the signal output by the driving chip passes through the first conducting electrode. 121 enters the first signal write path to implement transmission of the drive signal.
  • the second via electrode 122 is electrically connected to the second pad electrode 102 through the second via 132.
  • the contact structure on the driving chip is in contact with the second conductive electrode 122 in the pad structure 10 on the array substrate. Since the second pad electrode 102 is electrically connected to the data lead 20, the second pad electrode 102 and the data lead 20 constitute a second signal writing path for driving the chip output signal, so that the signal output by the driving chip passes through the second guiding The through electrode 122 enters the second signal write path to effect transmission of the drive signal.
  • the first pad electrode 101 and the second pad electrode 102 are respectively in contact with the same contact structure in the driving chip through the first via electrode 121 and the second via electrode 122 which are independent of each other, thereby making it possible to The first pad electrode 101 and the second pad electrode 102 are independent of each other during signal transmission.
  • the first pad electrode 101 is etched to cause the first signal writing path to be interrupted
  • the second signal writing path can still operate normally, thereby performing normal transmission of the signal output from the driving chip.
  • the second pad electrode 102 is etched to cause the second signal write path to be interrupted
  • the first signal write path can still operate normally, thereby performing normal transmission of the signal output by the driver chip.
  • the material constituting the first conductive electrode 121 or the second conductive electrode 122 may be, for example, a transparent conductive material such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). Wait.
  • ITO Indium Tin Oxide
  • IZO Indium Zinc Oxide
  • the present disclosure does not limit the number of the first via holes 131, the second via holes 132, and the first via electrodes 121 covering the first via holes 131 and the second via electrodes 122 covering the second via holes 132.
  • Those skilled in the art can adjust the number of the above structures according to the pad structure 10 and the size of the bonded driver chip. For example, when the length of the pad structure 10 is long, the number of the above structures can be increased; when the length of the pad structure 10 is short, the number of the above structures can be reduced.
  • the number of MASK (lithography) processes is not increased.
  • the first pad electrode 101 can be connected to the gate.
  • the line is disposed in the same layer, and the second pad electrode 102 can be disposed in the same layer as the data line.
  • “same layer” herein refers to a layer structure formed by forming a film layer for forming a specific pattern by the same film forming process, and then forming the pattern by one patterning process using the same mask.
  • a patterning process may include multiple exposure, development, or etching processes, and the particular pattern in the resulting layer structure may be continuous or discontinuous, and these particular patterns may also be at different heights. Or have different thicknesses. .
  • the fabrication of the first pad electrode 101 can be completed while the gate line is being formed; and the fabrication of the second pad electrode 102 can be completed while the data line is being formed.
  • the first insulating layer 111 is a gate insulating layer (GI)
  • the second insulating layer 112 is a passivation layer (PVX).
  • the extending direction of the first pad electrode 101 is the same as the extending direction of the second pad electrode 102, and the orthographic projection of the second pad electrode 102 on the substrate substrate 03 is only the first pad electrode.
  • the second via 132 and the second via electrode 122 are provided at positions where the first pad electrode 101 and the second pad electrode 102 are orthogonally projected on the base substrate 03. Specifically, as shown in FIG. 3b (a cross-sectional view taken along AA in FIG. 3a), the second via 132 passes through the second insulating layer 112, so that the second via electrode 122 can pass through the second via 132. It is electrically connected to the second pad electrode 102.
  • the first via 131 and the first via 121 are provided at a position where the first pad electrode 101 and the second pad electrode 102 are projected on the base substrate 03 at a non-overlapping position.
  • the first via hole 131 passes through the first insulating layer 111 and the second insulating layer 112, thereby enabling the first via electrode 121 to The first via 131 is electrically connected to the first pad electrode 101.
  • both ends of the first pad electrode 101 and the second pad electrode 102 near the lead region 02 are electrically connected to the data lead 20.
  • the data lead 20 can form an independent signal writing path with the first pad electrode 101 and the second pad electrode 102, respectively.
  • the data lead 20 can be a single layer wiring structure.
  • the data lead 20 may be disposed in the same layer as the first pad electrode 101.
  • the material of the data lead 20 is the same as the material of the gate line.
  • the array substrate further includes a portion located in the first insulating layer 111 and the second insulating layer 112 and reaching the portion of the data lead 20 close to the binding region 01.
  • the third via 133 The second via electrode 122 is also electrically connected to the data lead 20 through the third via 133.
  • the second via electrode 122 electrically connects the second pad electrode 102 and the data lead 20 through the second via 132 and the third via 133, respectively.
  • the second via 132 is located in the bonding region 01, and the position of the upper surface of the second via electrode 122 corresponding to the second via 132 is covered by the driving chip bound in the bonding region 01.
  • the third via 133 is located in the lead region 02, the position of the upper surface of the second via electrode 122 corresponding to the third via 133 is not covered by the driving chip. Therefore, as shown in FIG. 3d, when the denseness of the conductive thin film layer constituting the second conductive electrode 122 is poor, the data lead 20 located at the position of the third via hole 133 is exposed, which is liable to cause electrochemical corrosion. .
  • the array substrate further includes a conductive protective layer 113 covering the second conductive electrode 122, and the conductive protective layer 113 is lining.
  • the orthographic projection on the base substrate 03 overlaps with the orthographic projection of the third via 133 on the substrate substrate 03, so that the data leads 20 at the position of the third via 133 can be protected.
  • the conductive protective layer 113 may be an anisotropic conductive film (ACF). Since the ACF needs to be applied to the surface of the pad structure 10 before the driver chip is bonded, the surface of the second via electrode 122 at the position of the third via 133 may be used in the coating process. The ACF is also applied together so that no additional conductive material is added.
  • the data lead 20 may be arranged in a double layer wiring structure.
  • the data lead 20 includes a first sub-electrode 201 and a second sub-electrode 202 which overlap each other in a direction perpendicular to the base substrate 03.
  • the first sub-electrode 201 is disposed in the same layer and connected to the first pad electrode 101, that is, the first sub-electrode 201 and the first pad electrode 101 are of a unitary structure. Therefore, the surface of the first sub-electrode 201 is covered with the first insulating layer 111 and the second insulating layer 112.
  • the second sub-electrode 202 is disposed in the same layer as the second pad electrode 102, that is, the second sub-electrode 202 and the second pad electrode 102 are integrated. Therefore, the surface of the second sub-electrode 202 is covered with the second insulating layer 112.
  • the array substrate further includes a first insulating layer 111 and a second layer.
  • the array substrate further includes a fifth via 135 located in the second insulating layer 112 and reaching a portion of the second sub-electrode 202 away from the bonding region 01.
  • the third via electrode 123 electrically connects the first sub-electrode 201 and the second sub-electrode 202 through the fourth via 134 and the fifth via 135.
  • one end of the data lead 20 in the lead region 02 is connected to the pad structure 10 in the bonding region 01, and the other end is connected to the gate line or the data line.
  • the data lead 20 and the data line as an example, as the resolution of the display panel is increased, the number of data lines is also increasing.
  • the size of the driving chip is getting smaller and smaller, thus driving The width of the chip will be much smaller than the width of the display area in the array substrate.
  • the data lead 20 in the lead area 02 is arranged as shown in FIG. Show.
  • the lead region 02 includes a near terminal region 04 located at a center position of the lead region, and a distal sub-region 05 located at both sides of the near terminal region 04.
  • the data lead 20 in the near terminal region 04 is a straight line extending in the first direction.
  • the portion of the data lead 20 in the remote sub-region 05 that is close to the binding region 01 i.e., the lower end of the data lead 20 in Fig. 5
  • the portion of the data lead 20 in the distal sub-region 05 that is remote from the binding region 01 is a diagonal line that is inclined in a direction away from the near terminal region 04.
  • the data lead 20 in the near terminal area 04 is closer to the center portion of the display area, so the data lead 20 is a straight line so that it can be electrically connected with the data line with the shortest distance.
  • the portion of the data lead 20 in the remote sub-area 05 is obliquely lined so as to be electrically connectable to the data line at the edge of the display area.
  • the first direction and the signal line (not shown) connected to the data lead 20 extend in the same direction.
  • the first direction is the same as the extending direction of the gate line.
  • the first direction is the same as the extending direction of the data line.
  • the data lead 20 is a PLG trace
  • the PLG trace is connected to a signal line in the GOA circuit
  • the first direction and the signal line in the GOA circuit extend in the same direction.
  • the length of the data lead 20 in the remote sub-area 05 is greater than the length of the data lead 20 in the near-terminal area 04, so the resistance of the data lead 20 in the far-end sub-area 05 is greater than the data lead 20 in the near-terminal area 04.
  • the resistance This will result in a delay in the drive signal outputted to the data line by the data lead 20 in the remote sub-area 05 as compared to the drive signal output from the data lead 20 in the near terminal area 04, thereby displaying The effect is affected.
  • the length of the second sub-electrode 202 in the near terminal region 04 is smaller than the length of the second sub-electrode 202 in the distal sub-region 05.
  • the resistance of the data lead 20 in the remote sub-area 05 is the same as or approximately the same as the resistance of the data lead 20 in the near-terminal area 04, so that the phenomenon that the signal transmission speed is inconsistent can be avoided.
  • the data lead 20 adopts a two-layer wiring structure. Compared with the single-layer wiring structure in FIG. 3a, the double-layer wiring structure can reduce the resistance of the data lead 20, thereby achieving the purpose of reducing power consumption.
  • the orthographic projection of the first pad electrode 101 on the base substrate 03 does not overlap with the orthographic projection of the second pad electrode 102 on the base substrate 03.
  • the first pad electrode 101 includes a first sub-portion 1011 and a second sub-portion 1012.
  • the first sub-portion 1011 is located at an end of the second pad electrode 102 that faces away from the data lead 20.
  • the extending direction of the first sub-portion 1011 is the same as the extending direction of the second pad electrode 102.
  • the second sub-portion 1012 is located on a side of the second pad electrode 102 in a direction perpendicular to the extending direction. One end of the second sub-portion 1012 is connected to the first sub-portion 1011, and the other end is electrically connected to the data lead 20.
  • the first pad electrode 101 has a bow shape.
  • the second via 132 and the second via 122 are disposed on the upper surface of the second pad electrode 102.
  • the second via 132 passes through the second insulating layer 112, so that the second via electrode 122 can pass through the second via 132. It is electrically connected to the second pad electrode 102.
  • a first via 131 and a first via 121 are provided on the upper surface of the first sub-portion 1011 of the first pad electrode 101.
  • the first via hole 131 passes through the first insulating layer 111 and the second insulating layer 112, thereby enabling the first via electrode 121 to The first sub-portion 1011 of the first pad electrode 101 is electrically connected through the first via 131.
  • the second pad electrode 102 is electrically connected to the data lead 20 at one end of the lead region 02. Thereby, the data lead 20 can form an independent signal writing path with the first pad electrode 101 and the second pad electrode 102, respectively.
  • the first pad electrode 101 is located directly below the second pad electrode 102.
  • the second sub-portion 1012 of the first pad electrode 101 is located on the side of the second pad electrode 102. Therefore, the distance between the second via electrode 122 in FIG. 6b from the substrate substrate 03 is smaller than the distance from the second via electrode 122 in FIG. 3b from the substrate substrate 03. Therefore, when the first pad electrode 101 and the second pad electrode 102 adopt the structure shown in FIG. 6a, the step difference between the second via electrode 122 and the first conductive electrode 121 is small, so that the pad structure 10 and the driving chip are The flatness of the contacted surface is higher, which facilitates the bonding of the driving chip.
  • the data lead 20 is disposed as described above.
  • the data lead 20 may be a two-layer wiring structure.
  • the data lead 20 includes a first sub-electrode 201 and a second sub-electrode 202 that overlap each other in a direction perpendicular to the 03 substrate.
  • the manner in which the first sub-electrode 201 and the second sub-electrode 202 are electrically connected is as described above, and will not be described herein.
  • the data lead 20 may be a single layer wiring structure.
  • the data lead 20 may be disposed in the same layer as the first pad electrode 101.
  • the manner in which the data lead 20 and the second pad electrode 102 are electrically connected is as described above, and will not be described herein.
  • Embodiments of the present disclosure also provide a display device including the array substrate as described above.
  • the display device may specifically include at least a liquid crystal display device and an organic light emitting diode display device.
  • the display device can be any product or component having a display function such as a display, a television, a digital photo frame, a mobile phone, or a tablet.
  • Embodiments of the present disclosure also provide a method for fabricating an array substrate as described above. As shown in Fig. 8, the method includes steps S101 to S103.
  • a base substrate 03 is provided.
  • a plurality of pad structures 10 are formed in the bonding region 01 on the base substrate 03.
  • the pad structure 10 includes at least two pad electrodes that are insulated from one another.
  • each data lead 20 corresponds to a pad structure 10.
  • each pad electrode and the data lead 20 corresponding to the pad structure 10 are electrically connected to form different signal writing paths, respectively.
  • the other pad electrode can still maintain the normal signal transmission of the pad structure 10 and the data lead 20, thereby improving the quality of the array substrate. Reduce the risk of substrate defects and manufacturing costs.
  • the step of forming the pad structure 10 includes S201 to S209.
  • a first metal layer is formed on the base substrate 03.
  • the first metal layer is patterned to form the first pad electrode 101.
  • the patterning process may include a photolithography process, etching, or other processes for forming a predetermined pattern such as printing, inkjet, or the like.
  • the photolithography process refers to a process of forming a pattern by using a photoresist, a mask, an exposure machine, or the like in a process of film formation, exposure, development, and the like.
  • the corresponding patterning process can be selected in accordance with the structure formed in the present disclosure.
  • the one-time patterning process in the embodiment of the present disclosure specifically forms different exposure regions by one mask exposure process, and then performs multiple etching, ashing, and the like removal processes on different exposure regions to finally obtain a desired pattern.
  • the first insulating layer 111 is formed to cover the base substrate 03 and the first pad electrode 101.
  • a second metal layer is formed on the first insulating layer 111.
  • the second metal layer is patterned to form the second pad electrode 102.
  • the materials of the first metal layer and the second metal layer may be the same or different.
  • the material of the first metal layer may be the same as the material of the gate line
  • the material of the second metal layer may be the same as the material of the data line.
  • the gate line provided in the same layer as the first pad electrode 101 may be formed in the display region while forming the first pad electrode 101 described above by one patterning process.
  • the data line disposed in the same layer as the second pad electrode 102 may be formed in the display region while forming the second pad electrode 102 by one patterning process.
  • a second insulating layer 112 is formed to cover the first insulating layer 111 and the second pad electrode 102.
  • the first insulating layer 111 and the second insulating layer 112 are patterned to form a second via 132 reaching the second pad electrode 102 and a first via 131 reaching the first pad electrode 101.
  • a conductive layer is formed on the second insulating layer 112 to fill the first via 131 and the second via 132.
  • the conductive layer can be, for example, transparent or opaque.
  • the conductive layer is patterned to form the first via electrode 121 and the second via electrode 122.
  • the first via electrode 121 is electrically connected to the first pad electrode 101 through the first via 131.
  • the second via electrode 122 is electrically connected to the second pad electrode power 102 through the second via 132.
  • the contact structure (not shown) on the driving chip is in contact with the first conductive electrode 121 in the pad structure 10 on the array substrate.
  • the first pad electrode 101 is electrically connected to the data lead 20
  • the first pad electrode 101 and the data lead 20 constitute a first signal writing path of the output signal of the driving chip, so that the signal output by the driving chip passes through the first guiding.
  • the through electrode 121 enters the first signal write path to effect transmission of the drive signal.
  • the contact structure on the driver chip is in contact with the second via electrode 122 in the pad structure 10 on the array substrate. Since the second pad electrode 102 is electrically connected to the data lead 20, the second pad electrode 102 and the data lead 20 form a second signal writing path of the driving chip output signal, so that the signal output by the driving chip passes through the second guiding The through electrode 122 enters the second signal write path to effect transmission of the drive signal.
  • the first pad electrode 101 and the second pad electrode 102 are respectively in contact with the same contact structure in the driving chip through the first conduction electrode 121 and the second conduction electrode 122 which are independent from each other, thereby making it possible to make A pad electrode 101 and a second pad electrode 102 are independent of each other during signal transmission.
  • the first pad electrode 101 is etched to cause the first signal writing path to be interrupted
  • the second signal writing path can still operate normally, thereby performing normal transmission of the signal output from the driving chip.
  • the second pad electrode 102 is etched to cause the second signal write path to be interrupted
  • the first signal write path can still operate normally, thereby performing normal transmission of the signal output by the driver chip.
  • the orthographic projections of the first pad electrode 101 and the second pad electrode 102 respectively formed by the above method on the base substrate 03 may overlap.
  • the orthographic projections of the first pad electrode 101 and the second pad electrode 102 on the base substrate 03 may not overlap.
  • the data lead 20 can be a single layer wiring structure.
  • the method of forming the data lead 20 is as follows.
  • the data leads 20 disposed in the same layer as the first pad electrode 101 are connected.
  • a third via hole 133 reaching a portion of the data lead 20 close to the bonding region 01 is formed in the first insulating layer 111 and the second insulating layer 112.
  • the second via electrode is also electrically connected to the data lead 20 through the third via 133.
  • the data lead 20 can be a two-layer wiring structure.
  • the method of forming the data lead 20 is as follows.
  • the first sub-electrode 201 of the data lead 20 disposed and connected in the same layer as the first pad electrode 101 is formed.
  • the second sub-electrode 202 of the data lead 20 disposed in the same layer as the second pad electrode 102 and connected thereto is formed.
  • the third conduction electrode 123 is formed on the second insulating layer 112.
  • the third via electrode 123 electrically connects the first sub-electrode 201 and the second sub-electrode 202 through the fourth via 134 and the fifth via 135.
  • the first sub-electrode 201 and the second sub-electrode 202 constitute the above-described data lead 20.

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Abstract

一种阵列基板及其制作方法、显示装置。该阵列基板包括位于绑定区（01）的多个焊垫结构（10）、以及位于引线区（02）的多条数据引线（20）。每条数据引线（20）与一个焊垫结构（10）相对应。该焊垫结构（10）包括至少两个相互绝缘的焊垫电极。在该焊垫结构（10）中，每个焊垫电极和与该焊垫结构（10）相对应的数据引线（20）分别电连接，以构成不同的信号写入通路。

Description

一种阵列基板及其制作方法、显示装置
相关申请的交叉引用
本申请要求于2017年7月4日递交的中国专利申请第201710540286.6号优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制作方法、显示装置。
背景技术
TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管-液晶显示器)作为一种平板显示装置，因其具有体积小、功耗低、无辐射以及制作成本相对较低等特点，而越来越多地被应用于高性能显示领域当中。
发明内容
本公开的实施例提供一种阵列基板及其制作方法、显示装置。
本公开的实施例采用如下技术方案。
本公开实施例的一方面提供了一种阵列基板，包括位于绑定区的多个焊垫结构、以及位于引线区的多条数据引线，每条数据引线与一个焊垫结构相对应。所述焊垫结构包括至少两个相互绝缘的焊垫电极。在所述焊垫结构中，每个焊垫电极和与所述焊垫结构相对应的所述数据引线分别电连接，以构成不同的信号写入通路。
可选的，所述阵列基板还包括衬底基板，其中，所述焊垫结构沿垂直于所述衬底基板的方向在所述衬底基板上依次设置且彼此绝缘的第一 焊垫电极和第二焊垫电极。所述阵列基板还包括：位于所述第一焊垫电极与所述第二焊垫电极之间的第一绝缘层；覆盖所述第一绝缘层和所述第二焊垫电极的第二绝缘层；位于所述第一绝缘层和所述第二绝缘层中且到达所述第一焊垫电极的第一过孔，以及位于所述第二绝缘层中且到达所述第二焊垫电极的第二过孔；位于所述第二绝缘层上的第一导通电极和第二导通电极，所述第一导通电极通过所述第一过孔与所述第一焊垫电极电连接，所述第二导通电极通过所述第二过孔与所述第二焊垫电极电连接。
进一步可选的，所述第一焊垫电极的延伸方向与所述第二焊垫电极的延伸方向相同，并且所述第二焊垫电极在所述衬底基板上的正投影仅与所述第一焊垫电极在所述衬底基板上正投影中靠近所述引线区的部分重叠。所述第一焊垫电极与所述第二焊垫电极靠近所述引线区的一端均与所述数据引线电连接。
或者，进一步可选的，所述第一焊垫电极在所述衬底基板上的正投影与所述第二焊垫电极在所述衬底基板上正投影不重叠。所述第一焊垫电极包括第一子部和第二子部，所述第一子部位于所述第二焊垫电极背离所述数据引线的一端，并且所述第一子部的延伸方向与所述第二焊垫电极的延伸方向相同。所述第二子部位于所述第二焊垫电极的在与所述延伸方向垂直的方向上的一侧，并且所述第二子部的一端与所述第一子部相连接，另一端与数据引线电连接。所述第二焊垫电极靠近所述引线区的一端与所述数据引线电连接。
可选的，所述数据引线与所述第一焊垫电极同层设置。所述阵列基板还包括：位于所述第一绝缘层和所述第二绝缘层中且到达所述数据引线靠近所述绑定区的部分的第三过孔，其中所述第二导通电极还通过所述第三过孔与所述数据引线电连接。
或者，可选的，所述数据引线包括在垂直于所述衬底基板的方向上彼此重叠的第一子电极和第二子电极。所述第一子电极与所述第一焊垫 电极同层设置且相连接，所述第二子电极与所述第二焊垫电极同层设置且相连接。所述阵列基板还包括：位于所述第一绝缘层和所述第二绝缘层中且到达所述第一子电极远离所述绑定区的部分的第四过孔；位于所述第二绝缘层中且到达所述第二子电极远离所述绑定区的部分的第五过孔；以及位于所述第二绝缘层上的第三导通电极，所述第三导通电极通过所述第四过孔和所述第五过孔，将所述第一子电极和所述第二子电极电连接。
进一步可选的，所述引线区包括位于中心位置的近端子区、以及位于所述近端子区两侧的远端子区。所述近端子区中的所述数据引线为沿第一方向延伸的直线。所述远端子区中的所述数据引线的靠近所述绑定区的部分为沿所述第一方向延伸的直线，所述远端子区中的所述数据引线的远离所述绑定区的部分为沿背离所述近端子区的方向倾斜的斜线。所述第一方向和与所述数据引线相连接的信号线的延伸方向相同。所述近端子区中所述第二子电极的长度小于所述远端子区中所述第二子电极的长度。
可选的，所述阵列基板还包括栅线和数据线。所述栅线与所述第一焊垫电极同层设置，所述数据线与所述第二焊垫电极同层设置。
可选的，所述阵列基板还包括覆盖所述第二导通电极的导电保护层，其中所述导电保护层在所述衬底基板上的正投影与所述第三过孔在衬底基板上的正投影重叠。
本公开实施例的另一方面提供了一种显示装置，其包括在本公开实施例的一方面中描述的阵列基板。
本公开实施例的又一方面提供了一种用于制作在本公开实施例的一方面中描述的阵列基板的方法。所述方法包括：提供衬底基板，所述衬底基板包括绑定区和引线区；在所述衬底基板上在所述绑定区中形成多个焊垫结构，其中，所述焊垫结构包括至少两个相互绝缘的焊垫电极；在所述衬底基板上在所述引线区中形成多个数据引线，其中，每条数据 引线与一个焊垫结构相对应，在所述焊垫结构中，每个焊垫电极和与所述焊垫结构相对应的所述数据引线分别电连接，以构成不同的信号写入通路。
可选的，形成所述焊垫结构的方法包括：在所述衬底基板上形成第一金属层；构图所述第一金属层以形成第一焊垫电极；形成第一绝缘层以覆盖所述衬底基板和所述第一焊垫电极；在所述第一绝缘层上形成第二金属层；构图所述第二金属层以形成第二焊垫电极；形成第二绝缘层以覆盖所述第一绝缘层和所述第二焊垫电极；构图所述第一绝缘层和所述第二绝缘层以形成到达所述第二焊垫电极的第二过孔和到达所述第一焊垫电极的第一过孔；在所述第二绝缘层上形成导电层以填充所述第一过孔和所述第二过孔；构图所述导电层以形成第一导通电极和第二导通电极，所述第一导通电极通过所述第一过孔与所述第一焊垫电极电连接，所述第二导通电极通过所述第二过孔与所述第二焊垫电极电连接。
进一步可选的，形成所述数据引线的方法包括：在形成所述第一焊垫电极的同时，形成与所述第一焊垫电极同层设置且相连接的所述数据引线；在形成所述第一过孔的同时，在所述第一绝缘层和所述第二绝缘层中形成到达所述数据引线靠近所述绑定区的部分的第三过孔，其中，所述第二导通电极还通过所述第三过孔与所述数据引线电连接。
进一步可选的，形成所述数据引线的方法包括：在形成所述第一焊垫电极的同时，形成与所述第一焊垫电极同层设置且相连接的所述数据引线的第一子电极；在形成所述第二焊垫电极的同时，形成与所述第二焊垫电极同层设置且相连接的所述数据引线的第二子电极；在形成所述第一过孔和所述第二过孔的同时，在所述第一绝缘层和所述第二绝缘层中形成到达所述第一子电极远离所述绑定区的部分的第四过孔和到达所述第二子电极远离所述绑定区的部分的第五过孔；在形成所述第一导通电极和所述第二导通电极的同时，在所述第二绝缘层上形成第三导通电极，所述第三导通电极通过所述第四过孔和所述第五过孔，将所述第一 子电极和所述第二子电极电连接。所述第一子电极和所述第二子电极构成所述数据引线。
可选的，所述方法还包括在所述阵列基板的显示区形成栅线和数据线。在形成所述第一焊垫电极的同时，在所述显示区形成与所述第一焊垫电极同层设置的所述栅线，以及在形成所述第二焊垫电极的同时，在所述显示区形成与所述第二焊垫电极同层设置的所述数据线。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的一种阵列基板结构示意图；
图2为沿图1中B-B进行剖切得到的结构示意图；
图3a为图1中焊垫结构的一种具体结构示意图；
图3b为沿图3a中A-A进行剖切得到的结构示意图；
图3c为沿图3a中C-C进行剖切得到的结构示意图；
图3d为沿图3a中D-D进行剖切得到的结构示意图；
图4为图1中数据引线的一种具体结构示意图；
图5为图4中引线区的具体划分结构示意图；
图6a为图1中焊垫结构的另一种具体结构示意图；
图6b为沿图6a中E-E进行剖切得到的结构示意图；
图7为图1中数据引线的另一种具体结构示意图；
图8为本公开实施例提供的一种阵列基板的制作方法流程图；
图9为图8中的步骤S102的具体方法流程图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
TFT-LCD是通过绑定(Bonding)一些驱动芯片，来控制像素电极和公共电极之间的电场大小，以达到控制液晶分子偏转角度的目的，最终显示预期的画面。为了实现驱动芯片的绑定，通常在该TFT-LCD的阵列基板的绑定区，制作焊垫电极(pad electrode)，该焊垫电极的表面覆盖有绝缘层或者透明导电层。然而，在制作的过程中，由于上述焊垫电极侧面角度过大，或者透明导电层的致密性不足，导致焊垫电极的一部分会暴露于空气中，从而在显示面板工作时，在电场作用下导致焊垫电极的一部分发生电化学腐蚀，出现断路(Open)导致的非正常显示(Abnormal Display，AD)现象，例如亮线条、暗线条、块状(Block)不良等。由于上述腐蚀引起的不良无法修复，从而严重影响产品良率，增加制作成本。
本公开实施例提供了一种阵列基板。如图1所示，该阵列基板包括位于绑定区01的多个焊垫结构10、以及位于引线区02的多条数据引线20。每条数据引线20与一个焊垫结构10相对应。
需要说明的是，阵列基板包括设置有亚像素的显示区、以及位于该显示区周边的非显示区。绑定区01和引线区02位于非显示区内。绑定区01用于绑定驱动芯片。该驱动芯片例如可以为向数据线(Data)提供驱动信号的源极驱动芯片；或者，可以为向栅线(Gate)提供驱动信号的栅极驱动芯片；又或者，可以为向阵列基板中的读取信号线提供触控信号的触控芯片；再或者，对于具有GOA(Gate Driver on Array，阵列基板行驱动)电路的阵列基板而言，上述驱动芯片还可以为用于向该GOA 电路提供时钟信号、电压源(VSS、VDD、VGL、VGH等)的芯片，本公开对此不作限定。
基于此，当上述驱动芯片为源极驱动芯片时，数据引线20用于将源极驱动芯片与显示区中的数据线(未示出)相连接；或者，当上述驱动芯片为栅极驱动芯片时，数据引线20用于将栅极驱动芯片与显示区中的栅线(未示出)相连接。在此情况下，引线区02位于绑定区01与显示区之间。此时，可以将数据引线20称为扇出(Fan out)引线。在此情况下，除了上述扇出引线以外，非显示区内的其他数据引线20称为PLG(Propel Link Gate，连接栅极)走线。例如，当驱动芯片用于向GOA电路提供时钟信号或电压源时，PLG走线用于将驱动芯片与GOA电路中每个移位寄存器单元的信号控制端(例如时钟信号端、电压端)相连接。
在此基础上，焊垫结构10包括至少两个相互绝缘的焊垫电极。在该焊垫结构10中，每个焊垫电极均与该焊垫结构10相对应的数据引线20电连接，以构成不同的信号写入通路。在此情况下，当一个焊垫电极被腐蚀且无法修复而导致其工作异常时，另一个焊垫电极仍然能够使得焊垫结构10与数据引线20保持正常的信号传输，从而能够提高阵列基板的质量，降低基板的不良风险以及制作成本。
如图2所示，在该阵列基板包括衬底基板03的情况下，焊垫结构10包括沿垂直于衬底基板03的方向在衬底基板03上依次设置且彼此绝缘的第一焊垫电极101和第二焊垫电极102。
具体的，如图2所示(图1中沿B-B进行剖切得到的截面图)，该阵列基板还包括：位于第一焊垫电极101与第二焊垫电极102之间的第一绝缘层111；覆盖第一绝缘层111和第二焊垫电极102的第二绝缘层112；位于第一绝缘层111和第二绝缘层112中且到达第一焊垫电极101的第一过孔131，以及位于第二绝缘层112中且到达第二焊垫电极102的第二过孔132；位于第二绝缘层112上的第一导通电极121和第二导通电极122。
第一导通电极121通过第一过孔131与第一焊垫电极101电连接。此时，当将驱动芯片绑定于绑定区01时，驱动芯片(未示出)上的一接触结构会与该阵列基板上一焊垫结构10中的第一导通电极121相接触。由于第一焊垫电极101与数据引线20电连接，因此第一焊垫电极101与数据引线20构成驱动芯片输出信号的第一信号写入通路，使得驱动芯片输出的信号通过第一导通电极121进入至该第一信号写入通路，以实现驱动信号的传输。
第二导通电极122通过第二过孔132与第二焊垫电极102电连接。此时，当将驱动芯片绑定于绑定区01时，驱动芯片上的上述接触结构会与该阵列基板上的上述焊垫结构10中的第二导通电极122相接触。由于第二焊垫电极102与该数据引线20电连接，因此第二焊垫电极102与数据引线20构成驱动芯片输出信号的第二信号写入通路，使得驱动芯片输出的信号通过上述第二导通电极122进入至该第二信号写入通路，以实现驱动信号的传输。
由上述可知，第一焊垫电极101和第二焊垫电极102分别通过相互独立的第一导通电极121和第二导通电极122与上述驱动芯片中同一个接触结构相接触，从而可以使得第一焊垫电极101和第二焊垫电极102在信号传输过程中彼此独立。在此情况下，当第一焊垫电极101被腐蚀而导致第一信号写入通路中断时，第二信号写入通路仍然可以正常工作，从而对驱动芯片输出的信号进行正常的传输。或者，当第二焊垫电极102被腐蚀导致第二信号写入通路中断时，第一信号写入通路仍然可以正常工作，从而对驱动芯片输出的信号进行正常的传输。
需要说明的是，构成第一导通电极121或第二导通电极122的材料例如可以为透明导电材料，诸如氧化铟锡(Indium Tin Oxide，ITO)或氧化铟锌(Indium Zinc Oxide，IZO)等。
此外，本公开对第一过孔131、第二过孔132以及覆盖第一过孔131的第一导通电极121、覆盖第二过孔132的第二导通电极122的数量不做 限定。本领域技术人员可以根据焊垫结构10以及被绑定的驱动芯片的尺寸对上述结构的数量进行调节。例如当焊垫结构10的长度较长时，可以增加上述结构的数量；当焊垫结构10的长度较短时，可以减小上述结构的数量。
在此基础上，为了在制作阵列基板的过程中，不增加MASK(光刻)工艺的次数，可选的，在该阵列基板包括栅线和数据线时，第一焊垫电极101可以与栅线同层设置，第二焊垫电极102可以与数据线同层设置。应理解，这里的“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。。在此情况下，可以在制作栅线的同时，完成第一焊垫电极101的制作；在制作数据线的同时，完成第二焊垫电极102的制作。
基于此，当第一焊垫电极101与栅线同层设置时，第一绝缘层111为栅极绝缘层(GI)，第二绝缘层112为钝化层(PVX)。
下面对第一焊垫电极101和第二焊垫电极102的一种设置方式进行说明。
在第一焊垫电极101在衬底基板03上的正投影与第二焊垫电极102在衬底基板03上的正投影重叠的情况下，第一焊垫电极101和第二焊垫电极102的设置方式如下所述。
如图3a所示，第一焊垫电极101的延伸方向和第二焊垫电极102的延伸方向相同，并且第二焊垫电极102在衬底基板03上的正投影仅与第一焊垫电极101在衬底基板03上正投影中靠近引线区02的部分重叠。
在此情况下，在第一焊垫电极101和第二焊垫电极102在衬底基板03上正投影重叠的位置处，设置有第二过孔132和第二导通电极122。具体的，如图3b(图3a中沿A-A进行剖切得到的剖视图)所示，第二 过孔132穿过第二绝缘层112，从而使得第二导通电极122能够通过第二过孔132与第二焊垫电极102电连接。
此外，在第一焊垫电极101和第二焊垫电极102在衬底基板03上正投影的不重叠的位置处，设置有第一过孔131和第一导通电极121。具体的，如图3c(图3a中沿C-C进行剖切得到的剖视图)所示，第一过孔131穿过第一绝缘层111和第二绝缘层112，从而使得第一导通电极121能够通过第一过孔131与第一焊垫电极101电连接。
基于此，第一焊垫电极101与第二焊垫电极102靠近引线区02的一端均与数据引线20电连接。从而使得数据引线20能够分别与第一焊垫电极101与第二焊垫电极102构成独立的信号写入通路。
在此基础上，面对数据引线20的设置方式进行说明。
例如，数据引线20可以为单层布线结构。在此情况下，如图3a所示，可选的，数据引线20可以与第一焊垫电极101同层设置。此时，当第一焊垫电极101与栅线同层设置时，数据引线20的材料与栅线的材料相同。这样，在制作栅线的同时，还可以完成第一焊垫电极101和数据引线20的制备，并且第一焊垫电极101和数据引线20为一体结构。
基于此，由于数据引线20与第一焊垫电极101同层设置，并且第一焊垫电极101的表面设置有第一绝缘层111和第二绝缘层112，因此数据引线20的表面也设置有第一绝缘层111和第二绝缘层112。为了使得第二焊垫电极102与数据引线20电连接，可选的，该阵列基板还包括位于第一绝缘层111和第二绝缘层112中且到达数据引线20靠近绑定区01的部分的第三过孔133。上述第二导通电极122还通过第三过孔133与数据引线20电连接。这样，第二导通电极122分别通过第二过孔132和第三过孔133将第二焊垫电极102与数据引线20电连接。
由上述可知，第二过孔132位于绑定区01内，第二导通电极122的上表面的对应于第二过孔132的位置被绑定于绑定区01内的驱动芯片覆盖。然而，因为第三过孔133位于引线区02内，所以第二导通电极122 的上表面的对应于第三过孔133的位置没有被驱动芯片覆盖。因此，如图3d所示，当构成第二导通电极122的导电薄膜层的致密性较差时，将会导致位于第三过孔133位置处的数据引线20裸露，从而容易发生电化学腐蚀。
在此情况下，为了避免第三过孔133位置处的数据引线20被腐蚀，可选的，该阵列基板还包括覆盖第二导通电极122的导电保护层113，该导电保护层113在衬底基板03上的正投影与第三过孔133在衬底基板03上的正投影重叠，从而可以对第三过孔133位置处的数据引线20进行保护。可选的，导电保护层113可以为异方性导电胶膜(Anisotropic Conductive Film，简称ACF)。由于在绑定驱动芯片之前，需要在上述焊垫结构10的表面涂覆该ACF，因此可以在该涂覆过程中，将第二导通电极122的位于第三过孔133的位置处的表面也一并涂覆该ACF，从而无需增加额外的导电材料。
或者，又例如，数据引线20的设置方式还可以为双层布线结构。具体的，如图4所示，数据引线20包括在垂直于衬底基板03的方向上彼此重叠的第一子电极201和第二子电极202。
第一子电极201与第一焊垫电极101同层设置且相连接，即，该第一子电极201和第一焊垫电极101为一体结构。因此，该第一子电极201的表面覆盖有第一绝缘层111和第二绝缘层112。
第二子电极202与第二焊垫电极102同层设置且相连接，即，该第二子电极202与第二焊垫电极102为一体结构。因此，该第二子电极202的表面覆盖有第二绝缘层112。
在此情况下，为了使得第一子电极201和第二子电极202在引线区02内电连接，可选的，如图4所示，该阵列基板还包括位于第一绝缘层111和第二绝缘层112中且到达第一子电极201远离绑定区01的部分的第四过孔134。此外，该阵列基板还包括位于第二绝缘层112中且到达第二子电极202远离绑定区01的部分的第五过孔135。
基于此，第三导通电极123通过第四过孔134和第五过孔135，将第一子电极201和第二子电极202电连接。
由上述可知，引线区02中的数据引线20的一端与绑定区01中的焊垫结构10相连接，另一端与栅线或者数据线相连接。以数据引线20与数据线相连接为例，随着显示面板分辨率的提高，数据线的数量也不断增加，然而为了提高电子设备的集成效果，驱动芯片的尺寸越来越小，这样，驱动芯片的宽度将远远小于阵列基板中显示区的宽度。
在此情况下，为了使得通过焊垫结构10绑定于绑定区01的驱动芯片能够与所有的数据线相连接，可选的，引线区02中的数据引线20的设置方式如图5所示。具体的，引线区02包括位于引线区的中心位置的近端子区04、以及位于近端子区04两侧的远端子区05。
在该实施例中，近端子区04中的数据引线20为沿第一方向延伸的直线。远端子区05中的数据引线20的靠近绑定区01的部分(即图5中数据引线20的下端)为沿第一方向延伸的直线。远端子区05中的数据引线20的远离绑定区01的部分为沿背离近端子区04的方向倾斜的斜线。这样，近端子区04中的数据引线20与显示区中心部分的距离较近，因此数据引线20为直线，从而可以以最短的距离和数据线电连接。此外，远端子区05中的数据引线20的部分为斜线，从而可以与显示区边缘位置的数据线电连接。
需要说明的是，上述第一方向和与该数据引线20相连接的信号线(未示出)的延伸方向相同。例如，当数据引线20与栅线相连接时，上述第一方向与该栅线的延伸方向相同。当数据引线20与数据线相连接时，上述第一方向与该数据线的延伸方向相同。或者，当数据引线20为PLG走线，并且当该PLG走线与GOA电路中的信号线相连接时，上述第一方向和该GOA电路中的信号线的延伸方向相同。
由上述可知，远端子区05中的数据引线20的长度大于近端子区04中的数据引线20的长度，因此远端子区05中的数据引线20的电阻大于 近端子区04中的数据引线20的电阻。这将导致与由近端子区04中的数据引线20输出值数据线的驱动信号相比，由远端子区05中的数据引线20输出至数据线的驱动信号存在延迟(Delay)，从而对显示效果造成影响。
为了解决上述问题，可选的，如图5所示，近端子区04中第二子电极202的长度小于远端子区05中第二子电极202的长度。从而使得远端子区05中的数据引线20的电阻与近端子区04中的数据引线20的电阻相同或近似相同，从而可以避免信号传输速度不一致的现象。
此外，在图4或图5所示的实施例中，数据引线20采用双层布线结构。相对于图3a中的单层布线结构而言，双层布线结构可以降低数据引线20的电阻，从而达到减小功耗的目的。
下面对第一焊垫电极101和第二焊垫电极102的另一设置方式进行说明。
如图6a所示，第一焊垫电极101在衬底基板03上的正投影与第二焊垫电极102在衬底基板03上的正投影不重叠。第一焊垫电极101包括第一子部1011和第二子部1012。
在该实施例中，第一子部1011位于第二焊垫电极102背离数据引线20的一端。第一子部1011的延伸方向与第二焊垫电极102的延伸方向相同。第二子部1012位于第二焊垫电极102的在与该延伸方向垂直的方向上的一侧。第二子部1012的一端与第一子部1011相连接，另一端与数据引线20电连接。此时，该第一焊垫电极101为弓字形。
在此情况下，第二焊垫电极102的上表面设置有第二过孔132和第二导通电极122。具体的，如图6b(图6a中沿E-E进行剖切得到的剖视图)所示，第二过孔132穿过第二绝缘层112，从而使得第二导通电极122能够通过第二过孔132与第二焊垫电极102电连接。
此外，在第一焊垫电极101的第一子部1011的上表面设置有第一过孔131和第一导通电极121。具体的，如图3c(图3a中沿C-C进行剖切 得到的剖视图)所示，第一过孔131穿过第一绝缘层111和第二绝缘层112，从而使得第一导通电极121能够通过第一过孔131与第一焊垫电极101的第一子部1011电连接。
基于此，第二焊垫电极102靠近引线区02的一端与数据引线20电连接。从而使得数据引线20能够分别与第一焊垫电极101与第二焊垫电极102构成独立的信号写入通路。
综上所述，如图3b所示，第一焊垫电极101位于第二焊垫电极102的正下方。然而，如图6b所示，第一焊垫电极101的第二子部1012位于第二焊垫电极102的侧面。因此，图6b中第二导通电极122距离衬底基板03的距离小于图3b中第二导通电极122距离衬底基板03的距离。所以当第一焊垫电极101和第二焊垫电极102采用图6a所示结构时，第二导通电极122与第一导电电极121之间的段差较小，使得焊垫结构10与驱动芯片相接触的表面的平整度较高，从而有利于驱动芯片的绑定。
此外，在第一焊垫电极101和第二焊垫电极102采用图6a所示结构的情况下，数据引线20的设置方式如上所述。例如，如图6a所示，数据引线20可以为双层布线结构。具体的，数据引线20包括在垂直于03衬底基板的方向上彼此重叠的第一子电极201和第二子电极202。第一子电极201和第二子电极202电连接的方式如上所述，此处不再赘述。
或者，如图7所示，数据引线20可以为单层布线结构。可选的，数据引线20可以与第一焊垫电极101同层设置。在此情况下，数据引线20与第二焊垫电极102的电连接的方式如上所述，此处不再赘述。
本公开实施例还提供了一种显示装置，包括如上所述的阵列基板。
需要说明的是，在本公开实施例中，显示装置具体至少可以包括液晶显示装置和有机发光二极管显示装置。例如，该显示装置可以为显示器、电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件。
本公开实施例还提供一种用于制作如上所述的阵列基板的方法。如 图8所示，该方法包括步骤S101至S103。
在S101中，提供衬底基板03。
在S102中，在衬底基板03上在绑定区01中形成多个焊垫结构10。该焊垫结构10包括至少两个相互绝缘的焊垫电极。
在S103中，在衬底基板03上在引线区02中形成多个数据引线20。每条数据引线20与一个焊垫结构10相对应。在该焊垫结构10中，每个焊垫电极和与该焊垫结构10相对应的数据引线20分别电连接，以构成不同的信号写入通路。
这样，当其中一个焊垫电极被腐蚀且无法修复而导致其工作异常时，另一个焊垫电极仍然能够使得焊垫结构10与数据引线20保持正常的信号传输，从而能够提高阵列基板的质量，降低基板的不良风险以及制作成本。
接下来，将对制作上述焊垫结构10的方法进行说明。这里，以图2所示的结构为例。。
具体的，如图9所示，形成焊垫结构10的步骤包括S201至S209。
参考图2，在S201中，在衬底基板03上形成第一金属层。
在S202中，构图第一金属层以形成第一焊垫电极101。
需要说明的是，在本公开中，构图工艺可以为包括光刻工艺、刻蚀或诸如打印、喷墨等其他用于形成预定图形的工艺。光刻工艺是指在成膜、曝光、显影等工艺过程，利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本公开中所形成的结构选择相应的构图工艺。
此外，本公开实施例中的一次构图工艺具体为通过一次掩膜曝光工艺形成不同的曝光区域，然后对不同的曝光区域进行多次刻蚀、灰化等去除工艺而最终得到预期图案。
在S203中，形成第一绝缘层111以覆盖衬底基板03和第一焊垫电极101。
在S204中，在第一绝缘层111上形成第二金属层。
在S205中，构图第二金属层以形成第二焊垫电极102。
需要说明的是，上述第一金属层和第二金属层的材料可以相同，也可以不同。为了在制作阵列基板的过程中，不增加MASK(光刻)工艺的次数，上述第一金属层的材料可以与栅线的材料相同，第二金属层的材料可以与数据线的材料形同。在此情况下，可以通过一次构图工艺在形成上述第一焊垫电极101的同时，在显示区形成与第一焊垫电极101同层设置的栅线。此外，可以通过一次构图工艺在形成上述第二焊垫电极102的同时，在显示区形成与第二焊垫电极102同层设置的数据线。
在S206中，形成第二绝缘层112以覆盖第一绝缘层111和第二焊垫电极102。
在S207中，构图第一绝缘层111和第二绝缘层112以形成到达第二焊垫电极102的第二过孔132和到达第一焊垫电极101的第一过孔131。
在S208中，在第二绝缘层112上形成导电层以填充第一过孔131和第二过孔132。在该实施例中，该导电层例如可以为透明的或不透明的。
在S209中，构图导电层以形成第一导通电极121和第二导通电极122。第一导通电极121通过第一过孔131与第一焊垫电极101电连接。第二导通电极122通过第二过孔132与第二焊垫电极电102电连接。
在此情况下，当将驱动芯片绑定于上述绑定区01时，驱动芯片上的接触结构(未示出)会与该阵列基板上焊垫结构10中的第一导通电极121相接触。由于第一焊垫电极101与数据引线20电连接，因此第一焊垫电极101与数据引线20构成上述驱动芯片输出信号的第一信号写入通路，使得驱动芯片输出的信号通过上述第一导通电极121进入至该第一信号写入通路，以实现驱动信号的传输。
此外，驱动芯片上的接触结构会与该阵列基板上的焊垫结构10中的第二导通电极122相接触。由于第二焊垫电极102与数据引线20电连接， 因此第二焊垫电极102与数据引线20构成上述驱动芯片输出信号的第二信号写入通路，使得驱动芯片输出的信号通过上述第二导通电极122进入至该第二信号写入通路，以实现驱动信号的传输。
由上述可知，第一焊垫电极101和第二焊垫电极102分别通过相互独立的第一导通电极121和第二导通电极122与驱动芯片中同一个接触结构相接触，从而可以使得第一焊垫电极101和第二焊垫电极102在信号传输过程中彼此独立。在此情况下，当第一焊垫电极101被腐蚀而导致第一信号写入通路中断时，第二信号写入通路仍然可以正常工作，从而对驱动芯片输出的信号进行正常的传输。或者，当第二焊垫电极102被腐蚀导致第二信号写入通路中断时，第一信号写入通路仍然可以正常工作，从而对驱动芯片输出的信号进行正常的传输。
基于此，如图4所示，通过上述方法制作的第一焊垫电极101和第二焊垫电极102分别在衬底基板03上的正投影可以重叠。或者，如图6a所示，第一焊垫电极101和第二焊垫电极102在衬底基板03上的正投影可以不重叠。
在此基础上，以下对形成数据引线20的方法进行说明。
一方面，数据引线20可以为单层布线结构。在此情况下，形成数据引线20的方法如下所述。
参考图3a或图7，首先，在形成第一焊垫电极101的同时，形成与该第一焊垫电极101同层设置且相连接的数据引线20。
接下来，在形成第一过孔131的同时，在第一绝缘层111和第二绝缘层112中形成到达数据引线20靠近绑定区01的部分的第三过孔133。第二导通电极还通过第三过孔133与数据引线20电连接。
另一方面，数据引线20可以为双层布线结构。在此情况下，形成数据引线20的方法如下所述。
参考图4或图6a，首先，在形成第一焊垫电极101的同时，形成与 第一焊垫电极101同层设置且相连接的数据引线20的第一子电极201。
接下来，在形成第二焊垫电极102的同时，形成与第二焊垫电极102同层设置且相连接的数据引线20的第二子电极202。
接下来，在形成第一过孔131的同时，在第一绝缘层111和第二绝缘层112中形成到达第一子电极201远离绑定区01的部分的第四过孔134和到达第二子电极202远离绑定区01的部分的第五过孔135。
接下来，在形成第一导通电极121和第二导通电极122的同时，在第二绝缘层112上形成第三导通电极123。该第三导通电极123通过第四过孔134和第五过孔135，将第一子电极201和第二子电极202电连接。第一子电极201和第二子电极202构成上述数据引线20。
需要说明的是，当数据引线20采用上述单层和双层结构时的有益效果、以及双层走线在引线区02的近端子区04和远端子区05的长度设置方式同上所述，此处不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种阵列基板，包括位于绑定区的多个焊垫结构、以及位于引线区的多条数据引线，每条数据引线与一个焊垫结构相对应，
    其中，所述焊垫结构包括至少两个相互绝缘的焊垫电极，在所述焊垫结构中，每个焊垫电极和与所述焊垫结构相对应的所述数据引线分别电连接，以构成不同的信号写入通路。
  2. 根据权利要求1所述的阵列基板，还包括衬底基板，
    其中，所述焊垫结构包括沿垂直于所述衬底基板的方向在所述衬底基板上依次设置且彼此绝缘的第一焊垫电极和第二焊垫电极，
    所述阵列基板还包括：
    位于所述第一焊垫电极与所述第二焊垫电极之间的第一绝缘层；
    覆盖所述第一绝缘层和所述第二焊垫电极的第二绝缘层；
    位于所述第一绝缘层和所述第二绝缘层中且到达所述第一焊垫电极的第一过孔，以及位于所述第二绝缘层中且到达所述第二焊垫电极的第二过孔；
    位于所述第二绝缘层上的第一导通电极和第二导通电极，所述第一导通电极通过所述第一过孔与所述第一焊垫电极电连接，所述第二导通电极通过所述第二过孔与所述第二焊垫电极电连接。
  3. 根据权利要求2所述的阵列基板，其中，所述第一焊垫电极的延伸方向与所述第二焊垫电极的延伸方向相同，并且所述第二焊垫电极在所述衬底基板上的正投影与所述第一焊垫电极在所述衬底基板上正投影中靠近所述引线区的部分重叠，
    所述第一焊垫电极与所述第二焊垫电极靠近所述引线区的一端均与所述数据引线电连接。
  4. 根据权利要求2所述的阵列基板，其中，所述第一焊垫电极在所述衬底基板上的正投影与所述第二焊垫电极在所述衬底基板上正投影不重叠，
    所述第一焊垫电极包括第一子部和第二子部，所述第一子部位于所述第二焊垫电极背离所述数据引线的一端，并且所述第一子部的延伸方向与所述第二焊垫电极的延伸方向相同，所述第二子部位于所述第二焊垫电极的在与所述延伸方向垂直的方向上的一侧，并且所述第二子部的一端与所述第一子部相连接，另一端与所述数据引线电连接，
    所述第二焊垫电极靠近所述引线区的一端与所述数据引线电连接。
  5. 根据权利要求2-4中任一项所述的阵列基板，其中，所述数据引线与所述第一焊垫电极同层设置，
    所述阵列基板还包括：位于所述第一绝缘层和所述第二绝缘层中且到达所述数据引线靠近所述绑定区的部分的第三过孔，其中，所述第二导通电极还通过所述第三过孔与所述数据引线电连接。
  6. 根据权利要求2-4中任一项所述的阵列基板，其中，所述数据引线包括第一子电极和第二子电极，所述第一子电极和第二子电极在衬底基板上的正投影重叠，所述第一子电极与所述第一焊垫电极同层设置且电连接，所述第二子电极与所述第二焊垫电极同层设置且电连接，
    所述阵列基板还包括：位于所述第一绝缘层和所述第二绝缘层中且到达所述第一子电极远离所述绑定区的部分的第四过孔；
    位于所述第二绝缘层中且到达所述第二子电极远离所述绑定区的部分的第五过孔；以及
    位于所述第二绝缘层上的第三导通电极，所述第三导通电极通过所述第四过孔和所述第五过孔，将所述第一子电极和所述第二子电极电连接。
  7. 根据权利要求6所述的阵列基板，其中，所述引线区包括位于所述引线区的中心位置的近端子区、以及位于所述近端子区两侧的远端子区，
    其中，所述近端子区中的所述数据引线为沿第一方向延伸的直线，
    所述远端子区中的所述数据引线的靠近所述绑定区的部分为沿所述 第一方向延伸的直线，所述远端子区中的所述数据引线的远离所述绑定区的部分为沿背离所述近端子区的方向倾斜的斜线，所述第一方向和与所述数据引线相连接的信号线的延伸方向相同，
    所述近端子区中所述第二子电极的长度小于所述远端子区中所述第二子电极的长度。
  8. 根据权利要求2所述的阵列基板，还包括栅线和数据线，
    其中，所述栅线与所述第一焊垫电极同层设置，所述数据线与所述第二焊垫电极同层设置。
  9. 根据权利要求5所述的阵列基板，还包括覆盖所述第二导通电极的导电保护层，其中所述导电保护层在所述衬底基板上的正投影与所述第三过孔在衬底基板上的正投影重叠。
  10. 一种显示装置，包括如权利要求1-9中任一项所述的阵列基板。
  11. 一种用于制作如权利要求1-9中任一项所述的阵列基板的方法，所述方法包括：
    提供衬底基板，所述衬底基板包括绑定区和引线区；
    在所述衬底基板上在所述绑定区中形成多个焊垫结构，其中，所述焊垫结构包括至少两个相互绝缘的焊垫电极；
    在所述衬底基板上在所述引线区中形成多个数据引线，
    其中，每条数据引线与一个焊垫结构相对应，在所述焊垫结构中，每个焊垫电极和与所述焊垫结构相对应的所述数据引线分别电连接，以构成不同的信号写入通路。
  12. 根据权利要求11所述的方法，其中，形成所述焊垫结构的方法包括：
    在所述衬底基板上形成第一金属层；
    构图所述第一金属层以形成第一焊垫电极；
    形成第一绝缘层以覆盖所述衬底基板和所述第一焊垫电极；
    在所述第一绝缘层上形成第二金属层；
    构图所述第二金属层以形成第二焊垫电极；
    形成第二绝缘层以覆盖所述第一绝缘层和所述第二焊垫电极；
    构图所述第一绝缘层和所述第二绝缘层以形成到达所述第二焊垫电极的第二过孔和到达所述第一焊垫电极的第一过孔；
    在所述第二绝缘层上形成导电层以填充所述第一过孔和所述第二过孔；
    构图所述导电层以形成第一导通电极和第二导通电极，所述第一导通电极通过所述第一过孔与所述第一焊垫电极电连接，所述第二导通电极通过所述第二过孔与所述第二焊垫电极电连接。
  13. 根据权利要求12所述的方法，其中，形成所述数据引线的方法包括：
    在形成所述第一焊垫电极的同时，形成与所述第一焊垫电极同层设置且相连接的所述数据引线；
    在形成所述第一过孔的同时，在所述第一绝缘层和所述第二绝缘层中形成到达所述数据引线靠近所述绑定区的部分的第三过孔，其中，所述第二导通电极还通过所述第三过孔与所述数据引线电连接。
  14. 根据权利要求12所述的方法，其中，形成所述数据引线的方法包括：
    在形成所述第一焊垫电极的同时，形成与所述第一焊垫电极同层设置且相连接的所述数据引线的第一子电极；
    在形成所述第二焊垫电极的同时，形成与所述第二焊垫电极同层设置且相连接的所述数据引线的第二子电极；
    在形成所述第一过孔和所述第二过孔的同时，在所述第一绝缘层和所述第二绝缘层中形成到达所述第一子电极远离所述绑定区的部分的第四过孔和到达所述第二子电极远离所述绑定区的部分的第五过孔；
    在形成所述第一导通电极和所述第二导通电极的同时，在所述第二绝缘层上形成第三导通电极，所述第三导通电极通过所述第四过孔和所 述第五过孔，将所述第一子电极和所述第二子电极电连接，其中，所述第一子电极和所述第二子电极构成所述数据引线。
  15. 根据权利要求12-14中任一项所述的方法，还包括在所述阵列基板的显示区形成栅线和数据线，
    其中，在形成所述第一焊垫电极的同时，在所述显示区形成与所述第一焊垫电极同层设置的所述栅线，以及
    在形成所述第二焊垫电极的同时，在所述显示区形成与所述第二焊垫电极同层设置的所述数据线。
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