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WO2017215065A1 - 阵列基板、阵列基板的制备方法及液晶显示面板 - Google Patents

阵列基板、阵列基板的制备方法及液晶显示面板 Download PDF

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Publication number
WO2017215065A1
WO2017215065A1 PCT/CN2016/089999 CN2016089999W WO2017215065A1 WO 2017215065 A1 WO2017215065 A1 WO 2017215065A1 CN 2016089999 W CN2016089999 W CN 2016089999W WO 2017215065 A1 WO2017215065 A1 WO 2017215065A1
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layer
hole
drain
end surface
disposed
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PCT/CN2016/089999
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English (en)
French (fr)
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秦芳
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武汉华星光电技术有限公司
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Priority to US15/126,381 priority Critical patent/US20180031931A1/en
Publication of WO2017215065A1 publication Critical patent/WO2017215065A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present invention claims the prior application priority of the invention titled "Array substrate, method for preparing array substrate, and liquid crystal display panel", which is filed on June 17, 2016.
  • the content of the above-mentioned prior application is incorporated by reference. Into this text.
  • the present invention relates to the field of display, and in particular, to an array substrate, a method for preparing an array substrate, and a liquid crystal display panel.
  • a display device such as a liquid crystal display (LCD) is a commonly used electronic device that is favored by users because of its low power consumption, small size, and light weight.
  • the liquid crystal display panel generally includes an array substrate, a color filter substrate, and a liquid crystal layer.
  • the array substrate and the color filter substrate are opposite and spaced apart, and the liquid crystal layer is interposed between the array substrate and the color filter substrate.
  • the array substrate includes thin film transistors distributed in an array, each thin film transistor being connected to a storage capacitor.
  • the dielectric layer constituting the storage capacitor is usually SiOx, the dielectric layer is usually small, resulting in a small capacitance value of the storage capacitor.
  • the invention provides an array substrate, the array substrate comprising:
  • a channel layer disposed adjacent to a surface of the substrate
  • a gate disposed on a surface of the first insulating layer away from the channel layer
  • a second insulating layer covering the gate, and the second insulating layer is provided with a first through hole and a second through hole spaced apart;
  • a source disposed on the second insulating layer, and the source is electrically connected to the channel layer through the first through hole;
  • drain disposed on the second insulating layer, wherein the drain is electrically connected to the channel layer through the second through hole, and the drain is spaced apart from the source;
  • the passivation layer includes HfO 2 , the passivation layer defines a fourth through hole corresponding to the drain, and the fourth through hole is connected to the third through hole ;
  • a pixel electrode is disposed on the passivation layer, the pixel electrode is electrically connected to the drain through the third through hole and the fourth through hole, and the pixel electrode is disposed corresponding to the common electrode,
  • the pixel electrode, the passivation layer, and the common electrode constitute a storage capacitor.
  • the array substrate further includes:
  • a buffer layer disposed on the substrate
  • the channel layer is disposed on a surface of the buffer layer away from the substrate.
  • the array substrate further includes:
  • first contact portion and the second contact portion are respectively in contact with the channel layer, and the first contact portion and the second contact portion are spaced apart;
  • the source is connected to the first contact portion through the first through hole, and the first contact portion is configured to reduce a contact resistance between the source and the channel layer;
  • the drain is connected to the second contact portion through the second through hole, and the second contact portion is for reducing a contact resistance between the drain and the channel layer.
  • the channel layer includes opposite first and second end faces, the first end surface and the second end surface intersecting a surface of the channel layer disposed adjacent to the substrate
  • the first The insulating layer includes oppositely disposed third end faces and fourth end faces, each of the third end face and the fourth end face intersecting a surface of the first insulating layer covering the channel layer
  • the gate includes a relative setting a fifth end surface and a sixth end surface, each of the fifth end surface and the sixth end surface intersecting a surface of the gate disposed on the first insulating layer
  • the first end surface, the third end surface, and the fifth end surface are coplanar, and the second end surface, the fourth end surface, and the sixth end surface are coplanar.
  • the fifth end surface is disposed adjacent to the source end than the sixth end surface, the sixth end The surface is disposed closer to the drain than the fifth end surface, and a distance between the fifth end surface and a plane of the source adjacent to the surface of the gate is greater than or equal to zero; The distance between the planes of the drains adjacent to the surface of the gate is greater than or equal to zero.
  • the passivation layer in the array substrate of the present invention includes HfO2, which has a high dielectric constant and a high light transmittance.
  • HfO2 has a high dielectric constant and a high light transmittance.
  • the invention also provides a method for preparing an array substrate, and the method for preparing the array substrate comprises:
  • a pixel electrode disposed on the passivation layer, corresponding to the common electrode, and electrically connected to the drain through the third through hole and the fourth through hole, the pixel electrode, the The passivation layer and the common electrode constitute a storage capacitor.
  • the method for preparing the array substrate further includes:
  • the step of “forming a channel layer adjacent to a surface of the substrate” includes:
  • the channel layer is formed on a surface of the buffer layer away from the substrate.
  • the gate includes:
  • the exposed oxide semiconductor layer is subjected to ion treatment to form a first contact portion and a second contact portion, and the oxide semiconductor layer not subjected to ion treatment is the channel layer;
  • the first photoresist pattern is stripped.
  • the step of “forming a source and a drain disposed at intervals on the second insulating layer, and the source is electrically connected to the channel layer through the first through hole, and the drain passes The second through hole is electrically connected to the channel layer” includes:
  • the second photoresist pattern is stripped.
  • the present invention also provides a liquid crystal display panel comprising the array substrate of any of the foregoing embodiments.
  • FIG. 1 is a schematic cross-sectional view of an array substrate according to a preferred embodiment of the present invention.
  • FIG. 2 is a flow chart of a method of fabricating an array substrate according to a preferred embodiment of the present invention.
  • FIG. 18 are schematic diagrams showing the corresponding steps in the method for fabricating the array substrate of the present invention.
  • FIG. 19 is a schematic structural view of a liquid crystal display panel according to a preferred embodiment of the present invention.
  • FIG. 1 is a cross-sectional structural view of an array substrate according to a preferred embodiment of the present invention.
  • the array substrate 10 includes a substrate 100, a channel layer 110, a first insulating layer 120, a gate 130, a second insulating layer 140, a source 150a, a drain 150b, a flat layer 160, a common electrode 170, and a passivation layer 180. And a pixel electrode 190.
  • the channel layer 110 is disposed adjacent to a surface of the substrate 10.
  • the first insulating layer 120 covers the channel layer 110.
  • the gate electrode 130 is disposed on a surface of the first insulating layer 120 away from the channel layer 110.
  • the second insulating layer 140 covers the gate 130, and the second insulating layer 140 defines a first through hole 141 and a second through hole 142 which are spaced apart from each other.
  • the source 150 a is disposed on the second insulating layer 140 , and the source 141 is electrically connected to the channel layer 110 through the first through hole 141 .
  • the drain 150b is disposed on the second insulating layer 140, and the drain 150b is electrically connected to the channel layer 110 through the second through hole 142, and the drain 150b and the source
  • the poles 141 are spaced apart.
  • the flat layer 160 covers the source 150a and the drain 150b, and the flat layer 160 defines a third through hole 161 corresponding to the drain 150b.
  • the common electrode 170 is disposed on the flat layer 160.
  • the passivation layer 180 covers the common electrode 170, and the passivation layer 180 includes HfO2, and the passivation layer 180 defines a fourth through hole 181 corresponding to the drain 150b.
  • the fourth through hole 181 is in communication with the third through hole 161.
  • the pixel electrode 190 is disposed on the passivation layer 180, and the pixel electrode 190 is electrically connected to the drain 150b through the third through hole 161 and the fourth through hole 181, and the pixel electrode 190 corresponds to the common electrode 170.
  • the pixel electrode 190, the passivation layer 180, and the common electrode 170 constitute a storage capacitor.
  • the gate 130, the source 150a, and the drain 150b are respectively a gate, a source, and a drain in a thin film transistor.
  • the material of the substrate 100 includes any one or more of electrical insulating materials such as quartz, mica, alumina or transparent plastic.
  • the substrate 110 is an insulating layer substrate capable of reducing high frequency loss of the substrate 110.
  • the array substrate 10 further includes a buffer layer 101 on which the buffer layer 101 is disposed. At this time, the channel layer 110 is disposed on a surface of the buffer layer 101 away from the substrate 100.
  • the buffer layer 101 can reduce damage to the substrate 100 during the preparation of the array substrate 10.
  • the material of the channel layer 110 may be an oxidized semiconductor material such as Amorphous Indium Gallium Zinc Oxide (a-IGZO).
  • a-IGZO Amorphous Indium Gallium Zinc Oxide
  • the first insulating layer 120 includes, but is not limited to, silicon nitride (SiNx), silicon oxide (SiOx) materials, and the like.
  • the material of the gate electrode 130 includes, but is not limited to, one or more of metal materials such as Al, Mo, Cu, Ag, Cr, Ti, AlNi, MoTi.
  • the second insulating layer 140 includes, but is not limited to, silicon nitride (SiNx), silicon oxide (SiOx) materials, and the like.
  • the material of the source 150a and the drain 150b includes, but is not limited to, one or more of metal materials such as Al, Mo, Cu, Ag, Cr, Ti, AlNi, MoTi.
  • the common electrode 170 includes a transparent conductive material.
  • the common electrode 170 may include, but is not limited to, one or more of the following materials: a ZnO-based transparent oxide semiconductor material, a SnO 2 -based transparent oxide semiconductor material, In 2 O 3 -based transparent oxide semiconductor material or the like.
  • the pixel electrode 190 includes a transparent conductive material.
  • the pixel electrode 190 may include, but is not limited to, one or more of the following materials: a ZnO-based transparent oxide semiconductor material, a SnO 2 -based transparent oxide semiconductor material, In 2 O 3 -based transparent oxide semiconductor material or the like.
  • the array substrate 10 further includes a first contact portion 102 and a second contact portion 103.
  • the first contact portion 102 and the second contact portion 103 are respectively in contact with the channel layer 110 , and the first contact portion 102 is spaced apart from the second contact portion 103 .
  • the source 150 a is connected to the first contact portion 102 through the first through hole 141 , and the first contact portion 102 is configured to reduce contact between the source 150 a and the channel layer 110 . resistance.
  • the drain 150b is connected to the second contact portion 103 through the second through hole 142, and the second contact portion 103 is for reducing contact between the drain 150b and the channel layer 110. resistance.
  • the first contact portion 102 and the second contact portion 103 may be obtained by ion treatment of an oxidized semiconductor material. For example, it can be formed by a-IGZO treatment with H2 or Ar ions.
  • the channel layer 110 includes a first end surface 111 and a second end surface 112 that are oppositely disposed.
  • the first end surface 111 and the second end surface 112 both intersect the surface of the channel layer 110 adjacent to the substrate 100.
  • the first insulating layer 120 includes a third end surface 121 and a fourth end surface 122 that are oppositely disposed.
  • the third end surface 121 and the fourth end surface 122 both intersect the surface of the first insulating layer 120 covering the channel layer 110.
  • the gate 130 includes a fifth end surface 131 and a sixth end surface 132 that are oppositely disposed.
  • the fifth end surface 131 and the sixth end surface 132 both intersect the surface of the gate 130 disposed on the first insulating layer 120.
  • the first end surface 111, the second end surface 121, and the fifth end surface 131 are coplanar, and the second end surface 112, the fourth end surface 122, and the sixth end surface 132 are coplanar.
  • the fifth end surface 131 is disposed adjacent to the source 150a than the sixth end surface 132, and the sixth end surface 132 is disposed adjacent to the drain 150b than the fifth end surface 131.
  • the distance between the fifth end surface 131 and the plane of the source 150a adjacent to the surface of the gate 130 is greater than or equal to zero.
  • a distance between the sixth end surface 132 and a plane of the drain 150b adjacent to a surface of the gate 130 is greater than or equal to zero.
  • the passivation layer 180 in the array substrate 10 of the present invention includes HfO2 having a high dielectric constant and a high light transmittance.
  • the common electrode 170, the passivation layer 180, and the pixel electrode 190 form a storage capacitor
  • the capacitance of the storage capacitor can be increased.
  • the capacitance of the storage capacitor is constant and the thickness of the passivation layer 180 is constant, the area of the storage capacitor can be reduced. Therefore, the pixel stability of the display panel to which the array substrate 10 is applied can be improved. And an aperture ratio of the array substrate 10.
  • the fifth end surface 131 is disposed adjacent to the source 150a than the sixth end surface 132, and the fifth end surface 131 and the source 150a are adjacent to the surface of the gate 130.
  • the distance between the planes is greater than or equal to zero. That is, there is no overlapping area between the gate 130 and the source 150a. Therefore, there is no parasitic capacitance between the gate 130 and the source 150a.
  • the sixth end surface 132 is disposed adjacent to the drain 150b than the fifth end surface 131, the sixth end surface 132 and the drain 150b are adjacent to a plane where the surface of the gate 130 is located. The distance between them is greater than or equal to zero. That is, there is no overlapping area between the gate 130 and the drain 150b, and therefore, there is no parasitic capacitance between the gate 130 and the drain 150b.
  • FIG. 2 is a flowchart of a method for fabricating an array substrate according to a preferred embodiment of the present invention.
  • the method of preparing the array substrate 10 includes, but is not limited to, the following steps.
  • step S101 the substrate 100 is provided, please refer to FIG. 3.
  • the method for preparing the array substrate further includes step I.
  • Step I forming a buffer layer 101 disposed on the substrate 10, please refer to FIG.
  • step S102 the channel layer 110 is formed adjacent to the surface of the substrate 100.
  • the step S102 specifically includes: forming the channel layer 110 on a surface of the buffer layer 101 away from the substrate 10, please refer to FIG. 5.
  • step S103 a first insulating layer 120 covering the channel layer 110 is formed.
  • Step S104 forming a gate 130 disposed on the first insulating layer 120 away from the channel layer 110.
  • step S102, the step S103, and the step S104 may specifically include the following steps.
  • step S1 the stacked oxide semiconductor layer 210, the first insulating material layer 220, and the first metal layer 230 are sequentially formed adjacent to the surface of the substrate 100. Please refer to FIG. 6.
  • Step S2 forming a first photoresist layer 240 covering the first metal layer 230, please refer to FIG.
  • Step S3 patterning the first photoresist layer 240 to retain the first photoresist pattern 241 disposed in the middle of the first metal layer 230, please refer to FIG.
  • step S4 the first metal layer 230 and the first insulating material layer 220 not protected by the first photoresist pattern 241 are etched by using the first photoresist pattern 241 as a mask to form the gate electrode 130, respectively.
  • the first insulating layer 120 please refer to FIG. 9 together.
  • step S5 the exposed oxide semiconductor layer 210 is subjected to ion treatment to form the first contact portion 102 and the second contact portion 103, and the oxide semiconductor layer 210 not subjected to ion treatment is the channel layer 110, see FIG. 10.
  • steps S1 to S5 are used, and the first contact portion is formed by using the first photoresist pattern 241 and the gate electrode 1130 and the first insulating layer 120 as a mask. 102.
  • the second contact portion 103 and the channel layer 110 are not provided with a photomask.
  • step S6 the first photoresist pattern 241 is peeled off, please refer to FIG.
  • Step S105 forming a second insulating layer 140 covering the gate 130, and forming a first through hole 141 and a second through hole 142 spaced apart from each other on the second insulating layer 140, please refer to FIG.
  • Step S106 forming a source 150a and a drain 150b spaced apart from each other on the second insulating layer 140, and the source 150a is electrically connected to the channel layer 110 through the first through hole 141, The drain 150b is electrically connected to the channel layer 110 through the second through hole 142.
  • the step S106 includes the following steps.
  • Step S1061 forming a second metal layer 250 on the second insulating layer 140, please refer to FIG.
  • Step S1062 forming a second photoresist layer 260 covering the second metal layer 250, please refer to FIG.
  • Step S1063 removing the second photoresist layer 260 facing the gate 130, and removing the second photoresist layer 260 having a size greater than or equal to the length of the gate 130, the second photoresist
  • the layer 260 forms a second photoresist pattern 261, please refer to FIG. 15 together.
  • Step S1064 using the second photoresist pattern 261 as a mask, etching the second metal layer 250 not covered by the second photoresist pattern 261 to form the source 150a and the drain 150b. Please refer to Figure 16.
  • step S1065 the second photoresist pattern 261 is peeled off, please refer to FIG.
  • Step S107 forming a flat layer 160 covering the source 150a and the drain 150b.
  • the flat layer 160 defines a third through hole 161 corresponding to the drain 150b.
  • step S108 the common electrode 170 disposed on the flat layer 160 is formed.
  • step S109 a passivation layer 180 covering the common electrode 170 and including HfO2 is formed, and a fourth via hole 181 is formed on the passivation layer 180 corresponding to the drain 150b.
  • Step S110 forming a pixel electrode disposed on the passivation layer 180, corresponding to the common electrode 170, and electrically connected to the drain 150b through the third through hole 161 and the fourth through hole 181 190, the pixel electrode 190, the passivation layer 180, and the common electrode 170 constitute a storage capacitor, and the steps S107 to S110 are referred to FIG.
  • FIG. 19 is a schematic structural diagram of a liquid crystal display panel according to a preferred embodiment of the present invention.
  • the liquid crystal display panel 1 includes an array substrate 10.
  • the array substrate 10 is as described above and will not be described herein.

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Abstract

一种阵列基板（10）、阵列基板（10）的制备方法及液晶显示面板（1）。阵列基板（10）包括：基板（100）；沟道层（110），邻近基板（100）的表面设置；第一绝缘层（120），覆盖沟道层（110）；栅极（130），设置在第一绝缘层（120）上；第二绝缘层（140），覆盖栅极（130），开设有第一贯孔（141）、第二贯孔（142）；源极（150a），设置在第二绝缘层（140）上且通过第一贯孔（141）与沟道层（110）电连接；漏极（150b），设置在第二绝缘层（140）上，与漏极（150b）间隔设置且通过第二贯孔（142）与沟道层（110）电连接；平坦层（160），覆盖源极（150a）及漏极（150b），开设第三贯孔（161）；公共电极（170），设置在平坦层（160）上；钝化层（180），覆盖公共电极（170），钝化层（180）包括HfO2，钝化层（180）开设有与第三贯孔（161）连通的第四贯孔（181）；像素电极（190），设置在钝化层（180）上，通过第三贯孔（161）、第四贯孔（181）与漏极（150b）电连接，且像素电极（190）对应公共电极（170）设置，像素电极（190）、钝化层（180）及公共电极（170）构成存储电容。

Description

阵列基板、阵列基板的制备方法及液晶显示面板
本发明要求2016年6月17日递交的发明名称为“阵列基板、阵列基板的制备方法及液晶显示面板”的申请号201610431928.4的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示领域，尤其涉及一种阵列基板、阵列基板的制备方法及液晶显示面板。
背景技术
显示设备，比如液晶显示器(Liquid Crystal Display，LCD)是一种常用的电子设备，由于其具有功耗低、体积小、重量轻等特点，因此备受用户的青睐。液晶显示面板通常包括阵列基板、彩膜基板及液晶层。所述阵列基板和所述彩膜基板相对且间隔设置，所述液晶层夹设在所述阵列基板及所述彩膜基板之间。所述阵列基板包括呈阵列状分布的薄膜晶体管，每个薄膜晶体管均与一个存储电容相连。现有技术中，由于构成存储电容中的介质层的通常为SiOx，因此，所述介质层的通常较小，从而导致存储电容的电容值较小。
发明内容
本发明提供一种阵列基板，所述阵列基板包括：
基板；
沟道层，邻近所述基板的表面设置；
第一绝缘层，覆盖所述沟道层；
栅极，设置在所述第一绝缘层远离所述沟道层的表面；
第二绝缘层，覆盖所述栅极，且所述第二绝缘层上开设有间隔设置的第一贯孔和第二贯孔；
源极，设置在所述第二绝缘层上，且所述源极通过所述第一贯孔与所述沟道层电连接；
漏极，设置在所述第二绝缘层上，且所述漏极通过所述第二贯孔与所述沟道层电连接，且所述漏极与所述源极间隔设置；
平坦层，覆盖所述源极及所述漏极，所述平坦层对应所述漏极开设第三贯孔；
公共电极，设置在所述平坦层上；
钝化层，覆盖所述公共电极，且所述钝化层包括HfO2，所述钝化层对应所述漏极开设第四贯孔，且所述第四贯孔与所述第三贯孔连通；
像素电极，设置在所述钝化层上，所述像素电极通过所述第三贯孔及所述第四贯孔与所述漏极电连接，且所述像素电极对应所述公共电极设置，所述像素电极、所述钝化层及所述公共电极构成存储电容。
其中，所述阵列基板还包括：
缓冲层，设置在所述基板上；
所述沟道层设置在所述缓冲层远离所述基板的表面。
其中，所述阵列基板还包括：
第一接触部和第二接触部，所述第一接触部和所述第二接触部分别与所述沟道层接触，且所述第一接触部与所述第二接触部间隔设置；
所述源极通过所述第一贯孔与所述第一接触部相连，所述第一接触部用于减小所述源极与所述沟道层之间的接触电阻；
所述漏极通过所述第二贯孔与所述第二接触部相连，所述第二接触部用于减小所述漏极与所述沟道层之间的接触电阻。
其中，所述沟道层包括相对设置的第一端面和第二端面，所述第一端面和所述第二端面均与所述沟道层邻近所述基板设置的表面相交，所述第一绝缘层包括相对设置的第三端面和第四端面，所述第三端面和所述第四端面均与所述第一绝缘层覆盖所述沟道层的表面相交，所述栅极包括相对设置的第五端面和第六端面，所述第五端面和所述第六端面均与所述栅极设置在所述第一绝缘层上的表面相交，
且所述第一端面、所述第三端面及所述第五端面共面，所述第二端面、所述第四端面及所述第六端面共面。
其中，所述第五端面相较于所述第六端面邻近所述源极设置，所述第六端 面相较于所述第五端面邻近所述漏极设置，所述第五端面与所述源极邻近所述栅极的表面所在的平面之间的距离大于或者等于零；所述第六端面与所述漏极邻近所述栅极的表面所在的平面之间的距离大于或者等于零。
相较于现有技术，本发明的阵列基板中的钝化层中包括HfO2，所述HfO2具有较高的介电常数和较高的透光率。当所述公共电极、所述钝化层及所述像素电极形成存储电容时，在所述公共电极和所述钝化层的正对面积不变时，且所述钝化层厚度一定的情况下，可以提高所述存储电容的电容大小。当所述存储电容的电容大小不变，且所述钝化层的厚度不变时，可以减小存储电容的面积，因此，可以提高所述阵列基板所应用的显示面板的画素稳定性及所述阵列基板的开口率。
本发明还提供了一种阵列基板的制备方法，所述阵列基板的制备方法包括：
提供基板；
邻近所述基板的表面形成沟道层；
形成覆盖所述沟道层的第一绝缘层；
形成设置在所述第一绝缘层远离所述沟道层的栅极；
形成覆盖所述栅极的第二绝缘层，且在所述第二绝缘层上开设间隔设置的第一贯孔和第二贯孔；
在所述第二绝缘层上形成间隔设置的源极和漏极，且所述源极通过所述第一贯孔与所述沟道层电连接，所述漏极通过所述第二贯孔与所述沟道层电连接；
形成覆盖所述源极和所述漏极的平坦层，所述平坦层对应所述漏极开设第三贯孔；
形成设置在所述平坦层的公共电极；
形成覆盖所述公共电极且包括HfO2的钝化层，且在所述钝化层上对应所述漏极开设第四贯孔，且所述第四贯孔与所述第三贯孔连通；
形成设置在所述钝化层上，对应所述公共电极设置，且通过所述第三贯孔及所述第四贯孔与所述漏极电连接的像素电极，所述像素电极、所述钝化层及所述公共电极构成存储电容。
其中，所述阵列基板的制备方法还包括：
形成设置在所述基板上的缓冲层；
所述步骤“邻近所述基板的表面形成沟道层”包括：
在所述缓冲层远离所述基板的表面形成所述沟道层。
其中，所述步骤“邻近所述基板的表面形成沟道层”，“形成覆盖所述沟道层的第一绝缘层，”及“形成设置在所述第一绝缘层远离所述沟道层的栅极”包括：
邻近所述基板的表面依次形成层叠设置的氧化物半导体层、第一绝缘材料层及第一金属层；
形成覆盖所述第一金属层的第一光刻胶层；
图案化所述第一光刻胶层以保留设置在所述第一金属层中部的第一光刻胶图案；
以所述第一光刻胶图案为掩膜，蚀刻未被所述第一光刻胶图案保护的第一金属层及第一绝缘材料层以分别形成栅极及第一绝缘层；
对裸露的氧化物半导体层进行离子处理，以形成第一接触部及第二接触部，未进行离子处理的氧化物半导体层为所述沟道层；
剥离所述第一光刻胶图案。
其中，所述步骤“在所述第二绝缘层上形成间隔设置的源极和漏极，且所述源极通过所述第一贯孔与所述沟道层电连接，所述漏极通过所述第二贯孔与所述沟道层电连接”包括：
在所述第二绝缘层上形成第二金属层；
形成覆盖所述第二金属层的第二光刻胶层；
移除正对所述栅极的第二光刻胶层，且移除的第二光刻胶层的尺寸大于或等于所述栅极的长度，第二光刻胶层形成第二光刻胶图案；
以所述第二光刻胶图案为掩膜，蚀刻未被所述第二光刻胶图案覆盖的第二金属层以形成所述源极及所述漏极；
剥离所述第二光刻胶图案。
本发明还提供了一种液晶显示面板，所述液晶显示面板包括前述任意实施方式所述的阵列基板。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的阵列基板的剖面结构示意图。
图2为本发明一较佳实施方式的阵列基板的制备方法的流程图。
图3至图18为本发明阵列基板的制备方法中各步骤对应的结构示意图。
图19为本发明一较佳实施方式的液晶显示面板的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，图1为本发明一较佳实施方式的阵列基板的剖面结构示意图。所述阵列基板10包括基板100、沟道层110、第一绝缘层120、栅极130、第二绝缘层140、源极150a、漏极150b、平坦层160、公共电极170、钝化层180及像素电极190。所述沟道层110邻近所述基板10的表面设置。所述第一绝缘层120覆盖所述沟道层110。所述栅极130设置在所述第一绝缘层120远离所述沟道层110的表面。所述第二绝缘层140覆盖所述栅极130，且所述第二绝缘层140开设有间隔设置的第一贯孔141和第二贯孔142。所述源极150a设置在所述第二绝缘层140上，且所述源极141通过所述第一贯孔141与所述沟道层110电连接。所述漏极150b设置在所述第二绝缘层140上，且所述漏极150b通过所述第二贯孔142与所述沟道层110电连接，且所述漏极150b与所述源极141间隔设置。所述平坦层160覆盖所述源极150a及所述漏极150b，且所述平坦层160对应所述漏极150b开设第三贯孔161。所述公共电极170设置在所述平坦层160上。所述钝化层180覆盖所述公共电极170，且所述钝化层180包括HfO2，所述钝化层180对应所述漏极150b开设第四贯孔181， 且所述第四贯孔181与所述第三贯孔161连通。所述像素电极190设置在所述钝化层180上，所述像素电极190通过所述第三贯孔161及所述第四贯孔181与所述漏极150b电连接，且所述像素电极190对应所述公共电极170设置。所述像素电极190、所述钝化层180及所述公共电极170构成存储电容。
在这里，所述栅极130、所述源极150a及所述漏极150b分别为薄膜晶体管中的栅极、源极及漏极。
所述基板100的材料包括石英、云母、氧化铝或者透明塑料等电绝缘材料中的任意一种或者多种。所述基板110为绝缘层衬底能够减小所述基板110的高频损耗。
所述阵列基板10还包括缓冲层101，所述缓冲层101设置在所述基板100上。此时，所述沟道层110设置在所述缓冲层101远离所述基板100的表面。所述缓冲层101可以减小所述阵列基板10在制备的过程中对所述基板100的损伤。
所述沟道层110的材料可以为氧化半导体材料，比如，非晶铟镓锌氧化物(Amorphous Indium Gallium Zinc Oxide，a-IGZO)。
所述第一绝缘层120包括但不仅限于氮化硅(SiNx)、氧化硅(SiOx)材料等。
所述栅极130的材料包括但不仅限于Al，Mo，Cu，Ag、Cr、Ti、AlNi、MoTi等金属材料材料中的一种或者多种。
所述第二绝缘层140包括但不仅限于氮化硅(SiNx)、氧化硅(SiOx)材料等。
所述源极150a及所述漏极150b的材料包括但不仅限于Al，Mo，Cu，Ag、Cr、Ti、AlNi、MoTi等金属材料材料中的一种或者多种。
所述公共电极170包括透明导电材料，比如，所述公共电极170可以包括但不仅限于以下材料中的一种或者多种：ZnO基透明氧化物半导体材料，SnO2基透明氧化物半导体材料，In2O3基透明氧化物半导体材料等。
所述像素电极190包括透明导电材料，比如，所述像素电极190可以包括但不仅限于以下材料中的一种或者多种：ZnO基透明氧化物半导体材料，SnO2基透明氧化物半导体材料，In2O3基透明氧化物半导体材料等。
在本实施方式中，所述阵列基板10还包括第一接触部102和第二接触部103。所述第一接触部102和所述第二接触部103分别与所述沟道层110接触，且所述第一接触部102与所述第二接触部103间隔设置。所述源极150a通过所述第一贯孔141与所述第一接触部102相连，所述第一接触部102用于减小所述源极150a与所述沟道层110之间的接触电阻。所述漏极150b通过所述第二贯孔142与所述第二接触部103相连，所述第二接触部103用于减小所述漏极150b与所述沟道层110之间的接触电阻。所述第一接触部102和所述第二接触部103可以由氧化半导体材料进行离子处理而得到。比如，可以用a-IGZO进行H2或者Ar离子处理而形成。
所述沟道层110包括相对设置的第一端面111和第二端面112。所述第一端面111和所述第二端面112均与所述沟道层110邻近所述基板100的表面相交。所述第一绝缘层120包括相对设置的第三端面121和第四端面122。所述第三端面121和所述第四端面122均与所述第一绝缘层120覆盖所述沟道层110的表面相交。所述栅极130包括相对设置的第五端面131和第六端面132。所述第五端面131和所述第六端面132均与所述栅极130设置在所述第一绝缘层120上的表面相交。所述第一端面111、所述第二端面121及所述第五端面131共面，所述第二端面112、所述第四端面122及所述第六端面132共面。
所述第五端面131相较于所述第六端面132邻近所述源极150a设置，所述第六端面132相较于所述第五端面131邻近所述漏极150b设置。所述第五端面131与所述源极150a邻近所述栅极130的表面所在的平面之间的距离大于或者等于零。所述第六端面132与所述漏极150b邻近所述栅极130的表面所在的平面之间的距离大于或者等于零。
相较于现有技术，本发明的阵列基板10中的钝化层180中包括HfO2，所述HfO2具有较高的介电常数和较高的透光率。当所述公共电极170、所述钝化层180及所述像素电极190形成存储电容时，在所述公共电极170和所述钝化层180的正对面积不变时，且所述钝化层180厚度一定的情况下，可以提高所述存储电容的电容大小。当所述存储电容的电容大小不变，且所述钝化层180的厚度不变时，可以减小存储电容的面积，因此，可以提高所述阵列基板10所应用的显示面板的画素稳定性及所述阵列基板10的开口率。
进一步地，由于所述第五端面131相较于所述第六端面132邻近所述源极150a设置，且所述第五端面131与所述源极150a邻近所述栅极130的表面所在的平面之间的距离大于等于零。即，所述栅极130与所述源极150a之间没有重合的面积，因此，所述栅极130与所述源极150a之间不存在寄生电容。且，由于所述第六端面132相较于所述第五端面131邻近所述漏极150b设置，所述第六端面132与所述漏极150b邻近所述栅极130的表面所在的平面之间的距离大于或等于零。即，所述栅极130与所述漏极150b之间没有重合面积，因此，所述栅极130与所述漏极150b之间不存在寄生电容。
下面结合前面描述的阵列基板10，对本发明的阵列基板的制备方法进行介绍。请一并参阅图2，图2为本发明一较佳实施方式的阵列基板的制备方法的流程图。所述阵列基板10的制备方法包括但不仅限于以下步骤。
步骤S101，提供基板100，请参阅图3。
在本实施方式中，所述阵列基板的制备方法还包括步骤I。
步骤I，形成设置在所述基板10上的缓冲层101，请参阅图4。
步骤S102，邻近所述基板100的表面形成沟道层110。当所述阵列基板的制备方法中包括步骤I时，所述步骤S102具体包括：在所述缓冲层101远离所述基板10的表面形成所述沟道层110，请参阅图5。
步骤S103，形成覆盖所述沟道层110的第一绝缘层120。
步骤S104，形成设置在所述第一绝缘层120远离所述沟道层110的栅极130。
在本实施方式中，所述步骤S102、所述步骤S103及所述步骤S104可以具体包括如下步骤。
步骤S1，邻近所述基板100的表面依次形成层叠设置的氧化物半导体层210、第一绝缘材料层220及第一金属层230，请参阅图6。
步骤S2，形成覆盖所述第一金属层230的第一光刻胶层240，请参阅图7。
步骤S3，图案化所述第一光刻胶层240以保留设置在所述第一金属层230中部的第一光刻胶图案241，请参阅图8。
步骤S4，以所述第一光刻胶图案241为掩膜，蚀刻未被所述第一光刻胶图案241保护的第一金属层230及第一绝缘材料层220以分别形成栅极130 及第一绝缘层120，请一并参阅图9。
步骤S5，对裸露的氧化物半导体层210进行离子处理，以形成第一接触部102及第二接触部103，未进行离子处理的氧化物半导体层210为所述沟道层110，请参阅图10。
相较于现有技术，本发明阵列基板的制备方法中采用步骤S1～步骤S5，利用第一光刻胶图案241及栅极1130和第一绝缘层120为掩膜，形成了第一接触部102、第二接触部103及所述沟道层110，没有增加光罩。
步骤S6，剥离所述第一光刻胶图案241，请参阅图11。
步骤S105，形成覆盖所述栅极130的第二绝缘层140，且在所述第二绝缘层140上开设间隔设置的第一贯孔141和第二贯孔142，请参阅图12。
步骤S106，在所述第二绝缘层140上形成间隔设置的源极150a和漏极150b，且所述源极150a通过所述第一贯孔141与所述沟道层110电连接，所述漏极150b通过所述第二贯孔142与所述沟道层110电连接。
具体地，所述步骤S106包括如下步骤。
步骤S1061，在所述第二绝缘层140上形成第二金属层250，请参阅图13。
步骤S1062，形成覆盖所述第二金属层250的第二光刻胶层260，请参阅图14。
步骤S1063，移除正对所述栅极130的第二光刻胶层260，且移除的第二光刻胶层260的尺寸大于或等于所述栅极130的长度，第二光刻胶层260形成第二光刻胶图案261，请一并参阅图15。
步骤S1064，以所述第二光刻胶图案261为掩膜，蚀刻未被所述第二光刻胶图案261覆盖的第二金属层250以形成所述源极150a及所述漏极150b，请参阅图16。
步骤S1065，剥离所述第二光刻胶图案261，请参阅图17。
步骤S107，形成覆盖所述源极150a和所述漏极150b的平坦层160，所述平坦层160对应所述漏极150b开设第三贯孔161。
步骤S108，形成设置在所述平坦层160的公共电极170。
步骤S109，形成覆盖所述公共电极170且包括HfO2的钝化层180，且在所述钝化层180上对应所述漏极150b开设第四贯孔181。
步骤S110，形成设置在所述钝化层180上，对应所述公共电极170设置，且通过所述第三贯孔161及所述第四贯孔181与所述漏极150b电连接的像素电极190，所述像素电极190、所述钝化层180及所述公共电极170构成存储电容，所述步骤S107～步骤S110请参阅图18。
请参阅图19，图19为本发明一较佳实施方式的液晶显示面板的结构示意图。所述液晶显示面板1包括阵列基板10，所述阵列基板10如前面所述，在此不再赘述。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (14)

  1. 一种阵列基板，其中，所述阵列基板包括：
    基板；
    沟道层，邻近所述基板的表面设置；
    第一绝缘层，覆盖所述沟道层；
    栅极，设置在所述第一绝缘层远离所述沟道层的表面；
    第二绝缘层，覆盖所述栅极，且所述第二绝缘层上开设有间隔设置的第一贯孔和第二贯孔；
    源极，设置在所述第二绝缘层上，且所述源极通过所述第一贯孔与所述沟道层电连接；
    漏极，设置在所述第二绝缘层上，且所述漏极通过所述第二贯孔与所述沟道层电连接，且所述漏极与所述源极间隔设置；
    平坦层，覆盖所述源极及所述漏极，所述平坦层对应所述漏极开设第三贯孔；
    公共电极，设置在所述平坦层上；
    钝化层，覆盖所述公共电极，且所述钝化层包括HfO2，所述钝化层对应所述漏极开设第四贯孔，且所述第四贯孔与所述第三贯孔连通；
    像素电极，设置在所述钝化层上，所述像素电极通过所述第三贯孔及所述第四贯孔与所述漏极电连接，且所述像素电极对应所述公共电极设置，所述像素电极、所述钝化层及所述公共电极构成存储电容。
  2. 如权利要求1所述的阵列基板，其中，所述阵列基板还包括：
    缓冲层，设置在所述基板上；
    所述沟道层设置在所述缓冲层远离所述基板的表面。
  3. 如权利要求1所述的阵列基板，其中，所述阵列基板还包括：
    第一接触部和第二接触部，所述第一接触部和所述第二接触部分别与所述沟道层接触，且所述第一接触部与所述第二接触部间隔设置；
    所述源极通过所述第一贯孔与所述第一接触部相连，所述第一接触部用于减小所述源极与所述沟道层之间的接触电阻；
    所述漏极通过所述第二贯孔与所述第二接触部相连，所述第二接触部用于减小所述漏极与所述沟道层之间的接触电阻。
  4. 如权利要求3所述的阵列基板，其中，所述沟道层包括相对设置的第一端面和第二端面，所述第一端面和所述第二端面均与所述沟道层邻近所述基板设置的表面相交，所述第一绝缘层包括相对设置的第三端面和第四端面，所述第三端面和所述第四端面均与所述第一绝缘层覆盖所述沟道层的表面相交，所述栅极包括相对设置的第五端面和第六端面，所述第五端面和所述第六端面均与所述栅极设置在所述第一绝缘层上的表面相交，
    且所述第一端面、所述第三端面及所述第五端面共面，所述第二端面、所述第四端面及所述第六端面共面。
  5. 如权利要求4所述的阵列基板，其中，所述第五端面相较于所述第六端面邻近所述源极设置，所述第六端面相较于所述第五端面邻近所述漏极设置，所述第五端面与所述源极邻近所述栅极的表面所在的平面之间的距离大于或者等于零；所述第六端面与所述漏极邻近所述栅极的表面所在的平面之间的距离大于或者等于零。
  6. 一种阵列基板的制备方法，其中，所述阵列基板的制备方法包括：
    提供基板；
    邻近所述基板的表面形成沟道层；
    形成覆盖所述沟道层的第一绝缘层；
    形成设置在所述第一绝缘层远离所述沟道层的栅极；
    形成覆盖所述栅极的第二绝缘层，且在所述第二绝缘层上开设间隔设置的第一贯孔和第二贯孔；
    在所述第二绝缘层上形成间隔设置的源极和漏极，且所述源极通过所述第一贯孔与所述沟道层电连接，所述漏极通过所述第二贯孔与所述沟道层电连 接；
    形成覆盖所述源极和所述漏极的平坦层，所述平坦层对应所述漏极开设第三贯孔；
    形成设置在所述平坦层的公共电极；
    形成覆盖所述公共电极且包括HfO2的钝化层，且在所述钝化层上对应所述漏极开设第四贯孔，且所述第四贯孔与所述第三贯孔连通；
    形成设置在所述钝化层上，对应所述公共电极设置，且通过所述第三贯孔及所述第四贯孔与所述漏极电连接的像素电极，所述像素电极、所述钝化层及所述公共电极构成存储电容。
  7. 如权利要求6所述的阵列基板的制备方法，其中，所述阵列基板的制备方法还包括：
    形成设置在所述基板上的缓冲层；
    所述步骤“邻近所述基板的表面形成沟道层”包括：
    在所述缓冲层远离所述基板的表面形成所述沟道层。
  8. 如权利要求6所述的阵列基板的制备方法，其中，所述步骤“邻近所述基板的表面形成沟道层”，“形成覆盖所述沟道层的第一绝缘层；”及“形成设置在所述第一绝缘层远离所述沟道层的栅极”包括：
    邻近所述基板的表面依次形成层叠设置的氧化物半导体层、第一绝缘材料层及第一金属层；
    形成覆盖所述第一金属层的第一光刻胶层；
    图案化所述第一光刻胶层以保留设置在所述第一金属层中部的第一光刻胶图案；
    以所述第一光刻胶图案为掩膜，蚀刻未被所述第一光刻胶图案保护的第一金属层及第一绝缘材料层以分别形成栅极及第一绝缘层；
    对裸露的氧化物半导体层进行离子处理，以形成第一接触部及第二接触部，未进行离子处理的氧化物半导体层为所述沟道层；
    剥离所述第一光刻胶图案。
  9. 如权利要求6所述的阵列基板的制备方法，其中，所述步骤“在所述第二绝缘层上形成间隔设置的源极和漏极，且所述源极通过所述第一贯孔与所述沟道层电连接，所述漏极通过所述第二贯孔与所述沟道层电连接”包括：
    在所述第二绝缘层上形成第二金属层；
    形成覆盖所述第二金属层的第二光刻胶层；
    移除正对所述栅极的第二光刻胶层，且移除的第二光刻胶层的尺寸大于或等于所述栅极的长度，第二光刻胶层形成第二光刻胶图案；
    以所述第二光刻胶图案为掩膜，蚀刻未被所述第二光刻胶图案覆盖的第二金属层以形成所述源极及所述漏极；
    剥离所述第二光刻胶图案。
  10. 一种液晶显示面板，其中，所述液晶显示面板包括阵列基板，所述阵列基板包括：
    基板；
    沟道层，邻近所述基板的表面设置；
    第一绝缘层，覆盖所述沟道层；
    栅极，设置在所述第一绝缘层远离所述沟道层的表面；
    第二绝缘层，覆盖所述栅极，且所述第二绝缘层上开设有间隔设置的第一贯孔和第二贯孔；
    源极，设置在所述第二绝缘层上，且所述源极通过所述第一贯孔与所述沟道层电连接；
    漏极，设置在所述第二绝缘层上，且所述漏极通过所述第二贯孔与所述沟道层电连接，且所述漏极与所述源极间隔设置；
    平坦层，覆盖所述源极及所述漏极，所述平坦层对应所述漏极开设第三贯孔；
    公共电极，设置在所述平坦层上；
    钝化层，覆盖所述公共电极，且所述钝化层包括HfO2，所述钝化层对应所述漏极开设第四贯孔，且所述第四贯孔与所述第三贯孔连通；
    像素电极，设置在所述钝化层上，所述像素电极通过所述第三贯孔及所述第四贯孔与所述漏极电连接，且所述像素电极对应所述公共电极设置，所述像素电极、所述钝化层及所述公共电极构成存储电容。
  11. 如权利要求10所述的液晶显示面板，其中，所述阵列基板还包括：
    缓冲层，设置在所述基板上；
    所述沟道层设置在所述缓冲层远离所述基板的表面。
  12. 如权利要求10所述的液晶显示面板，其中，所述阵列基板还包括：
    第一接触部和第二接触部，所述第一接触部和所述第二接触部分别与所述沟道层接触，且所述第一接触部与所述第二接触部间隔设置；
    所述源极通过所述第一贯孔与所述第一接触部相连，所述第一接触部用于减小所述源极与所述沟道层之间的接触电阻；
    所述漏极通过所述第二贯孔与所述第二接触部相连，所述第二接触部用于减小所述漏极与所述沟道层之间的接触电阻。
  13. 如权利要求12所述的液晶显示面板，其中，所述沟道层包括相对设置的第一端面和第二端面，所述第一端面和所述第二端面均与所述沟道层邻近所述基板设置的表面相交，所述第一绝缘层包括相对设置的第三端面和第四端面，所述第三端面和所述第四端面均与所述第一绝缘层覆盖所述沟道层的表面相交，所述栅极包括相对设置的第五端面和第六端面，所述第五端面和所述第六端面均与所述栅极设置在所述第一绝缘层上的表面相交，
    且所述第一端面、所述第三端面及所述第五端面共面，所述第二端面、所述第四端面及所述第六端面共面。
  14. 如权利要求13所述的液晶显示面板，其中，所述第五端面相较于所述第六端面邻近所述源极设置，所述第六端面相较于所述第五端面邻近所述漏极设置，所述第五端面与所述源极邻近所述栅极的表面所在的平面之间的距离大于或者等于零；所述第六端面与所述漏极邻近所述栅极的表面所在的平面之间 的距离大于或者等于零。
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Publication number Priority date Publication date Assignee Title
US10411047B2 (en) 2017-04-28 2019-09-10 Shenzhen China Star Optoelectronics Technology Co., Ltd Array substrate, manufacturing method thereof and display device
CN106898624B (zh) * 2017-04-28 2019-08-02 深圳市华星光电技术有限公司 一种阵列基板及制备方法、显示装置
US10459300B2 (en) 2017-05-18 2019-10-29 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd Array substrate and a method for fabricating the same, a liquid crystal display panel
CN107065357A (zh) * 2017-05-18 2017-08-18 深圳市华星光电技术有限公司 阵列基板及其制造方法、液晶显示面板
CN107680993B (zh) * 2017-10-23 2019-12-24 深圳市华星光电半导体显示技术有限公司 Oled面板及其制作方法
CN110275357A (zh) 2019-06-25 2019-09-24 武汉华星光电技术有限公司 像素电极、阵列基板及显示装置
CN110600482B (zh) * 2019-08-09 2022-02-22 武汉华星光电半导体显示技术有限公司 一种阵列基板及其制作方法、显示面板
CN111625118A (zh) * 2020-05-06 2020-09-04 武汉华星光电技术有限公司 显示面板及显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101109879A (zh) * 2006-07-19 2008-01-23 株式会社日立显示器 液晶显示装置及其制造方法
CN103235455A (zh) * 2013-03-25 2013-08-07 南京中电熊猫液晶显示科技有限公司 一种液晶显示面板及其制造方法
US20150221684A1 (en) * 2014-01-31 2015-08-06 Japan Display Inc. Manufacturing method of display device
CN105404048A (zh) * 2015-12-17 2016-03-16 武汉华星光电技术有限公司 液晶显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101496148B1 (ko) * 2008-05-15 2015-02-27 삼성전자주식회사 반도체소자 및 그 제조방법
CN104362125B (zh) * 2014-09-25 2017-10-13 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN104730782B (zh) * 2015-04-01 2018-03-27 上海天马微电子有限公司 一种阵列基板、显示面板和显示装置
US10468434B2 (en) * 2016-04-08 2019-11-05 Innolux Corporation Hybrid thin film transistor structure, display device, and method of making the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101109879A (zh) * 2006-07-19 2008-01-23 株式会社日立显示器 液晶显示装置及其制造方法
CN103235455A (zh) * 2013-03-25 2013-08-07 南京中电熊猫液晶显示科技有限公司 一种液晶显示面板及其制造方法
US20150221684A1 (en) * 2014-01-31 2015-08-06 Japan Display Inc. Manufacturing method of display device
CN105404048A (zh) * 2015-12-17 2016-03-16 武汉华星光电技术有限公司 液晶显示装置

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