WO2017118105A1 - 阵列基板及其制作方法、显示装置 - Google Patents
阵列基板及其制作方法、显示装置 Download PDFInfo
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- WO2017118105A1 WO2017118105A1 PCT/CN2016/099880 CN2016099880W WO2017118105A1 WO 2017118105 A1 WO2017118105 A1 WO 2017118105A1 CN 2016099880 W CN2016099880 W CN 2016099880W WO 2017118105 A1 WO2017118105 A1 WO 2017118105A1
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- 239000000758 substrate Substances 0.000 title claims abstract description 125
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims description 49
- 238000000059 patterning Methods 0.000 claims description 24
- 239000010408 film Substances 0.000 claims description 20
- 238000002161 passivation Methods 0.000 claims description 17
- 239000010409 thin film Substances 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000002294 plasma sputter deposition Methods 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 238000002207 thermal evaporation Methods 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 206010047571 Visual impairment Diseases 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000470 constituent Substances 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
Definitions
- Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device.
- the array substrate of the display device includes a plurality of mutually parallel gate lines 1 and a plurality of parallel data lines 2, and the gate lines 1 and the data lines 2 enclose a plurality of pixel units 3 at the gate lines.
- a thin film transistor 4 is disposed at an intersection of the first and the data lines 2. By controlling the on and off of the thin film transistor 4, the pixel unit 3 corresponding to the thin film transistor 4 can be controlled to display a screen, and the display screen of the display device can be controlled.
- Embodiments of the present invention provide an array substrate, a method for fabricating the same, and a display device, which can improve the problem that the display device cannot display the screen normally due to signal delay.
- At least one embodiment of the present invention provides an array substrate including a plurality of mutually parallel gate lines, an insulating layer on a film layer on which the plurality of gate lines are located, and at least one first conductive layer on the insulating layer a structure, the insulating layer is provided with at least two first vias corresponding to the first conductive structure, and the first conductive structure is electrically connected to the gate line through the first via.
- At least one embodiment of the present invention also provides a display device including the array substrate as described above.
- At least one embodiment of the present invention further provides a method for fabricating an array substrate, the method comprising: forming a gate metal layer, forming a pattern including a gate line through a patterning process; and forming a gate line on the film layer Forming an insulating layer, forming at least two first via holes corresponding to the first conductive structure on the insulating layer through a patterning process; forming a first conductive layer on the insulating layer, forming a first process by a patterning process a pattern of a conductive structure, wherein the first conductive structure is electrically connected to the gate line through the first via.
- 1 is a plan view showing the structure of an array substrate
- FIG. 2 is a plan view of a planar structure of an array substrate according to an embodiment of the present invention.
- Figure 3 is a cross-sectional view taken along line C-C' of Figure 2;
- FIG. 4 is a plan view 2 of a planar structure of an array substrate according to an embodiment of the present invention.
- FIG. 5 is a third structural diagram of an array substrate according to an embodiment of the present invention.
- FIG. 6 is a plan view 4 of a planar structure of an array substrate according to an embodiment of the present invention.
- FIG. 7 is a fifth structural diagram of an array substrate according to an embodiment of the present invention.
- Figure 8 is a cross-sectional view taken along line D-D' of Figure 7;
- FIG. 9 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention.
- FIG. 10 is a flowchart of another method for fabricating an array substrate according to an embodiment of the present invention.
- 0-substrate substrate 1-gate line/signal line; 2-data line; 3-pixel unit; 4-thin film transistor; 5-insulating layer; 6-first conductive structure; 7-first via hole; Source; 9-drain; 10-active layer; 11-etch barrier layer; 12-second via; 13-third via; 14-passivation layer; 15-second conductive structure; Fourth via; 17-pixel electrode.
- the process of displaying the picture by the pixel unit 3 at the A position is that the driving signal of the gate line 1 reaches the pixel unit 3 at the A position, and the thin film transistor 4 corresponding to the pixel unit 3 at the A position is turned on.
- the drive signal (data signal) of the data line 2 also reaches the pixel unit 3 at the A position, the voltage is applied to the pixel electrode of the pixel unit 3 at the A position, and the pixel unit 3 that drives the A position displays the picture.
- the inventor of the present application found in the actual research process that, as shown in FIG. 1, since the driving manner of the pixel unit 3 is generally scanning a single gate line 1 from left to right and scanning a single data line 2 from above to the left, The gate line 1 of the display device of the large-size display screen is relatively long, and a signal delay is generated.
- the driving signal of the gate line 1 reaches the pixel unit 3 of the A position later than the driving signal of the data line 2, and thus the gate
- the driving signal of the data line 2 has passed through the pixel unit 3 at the A position, so that the pixel unit 3 at the A position cannot display the picture normally, and thus the display screen of the display device is not displayed. Complete, the afterimage appears.
- Embodiments of the present invention provide an array substrate, a method of manufacturing the same, and a display device.
- the array substrate includes: a plurality of mutually parallel signal lines, an insulating layer on the film layer on which the plurality of signal lines are located, and at least one first conductive structure on the insulating layer. At least two first vias corresponding to the first conductive structure are disposed on the insulating layer, and the first conductive structure is electrically connected to the signal line through the at least two first vias.
- the array substrate can be applied to a display device having a large-sized display panel, and can also help the display panel including the array substrate to be completely displayed, avoiding the occurrence of afterimages.
- This embodiment provides an array substrate, as shown in FIG. 2 and FIG. 3, the array substrate includes multiple strips.
- the gate lines 1 parallel to each other further include an insulating layer 5 on the film layer where the plurality of gate lines 1 are located, and at least one first conductive structure 6 on the insulating layer 5.
- the insulating layer 5 is provided with a corresponding first conductive structure.
- the at least two first vias 7 of the first conductive structure 6 are electrically connected to the gate line 1 through the at least two first vias 7.
- the first conductive structure 6 is electrically connected to the gate line 1 through the at least two first via holes 7, the first conductive structure 6 is connected in parallel with the gate line 1, which is equivalent to the gate line. 1 a resistor is connected in parallel, thereby reducing the resistance value of the entire gate line 1 as a whole. Moreover, according to the relationship between the resistance value and the signal delay time, the resistance value is proportional to the signal delay time, and thus reducing the resistance value of the gate line 1 can reduce the signal delay time of the gate line 1. Compared with the position of the first pixel unit 3 that cannot be normally displayed in the normal array substrate in the row (for example, the pixel unit 3 at the A position in FIG.
- the signal of the pixel unit 3 reaching the A position is obtained.
- the resistance of the passed gate line 1 is reduced, thereby reducing the signal delay time, so that when the driving signal of the gate line 1 reaches the pixel unit 3 at the A position, the driving signal of the data line 2 can just reach the A position as set.
- the pixel unit 3 is such that the pixel unit 3 at the A position can display the picture normally, and thus cannot be normally displayed in the embodiment of the present invention compared with the number of the pixel units 3 that cannot be normally displayed in the technical solution scheme shown in FIG.
- the number of pixel units 3 can be significantly reduced, thereby improving the problem that the display device cannot display the screen normally. It is to be noted that the present embodiment is described in detail with the signal line as the gate line.
- the embodiments of the present invention include but are not limited thereto, and the signal line may also be other signal lines such as data lines.
- the signal line may be a data line.
- the first conductive structure 6 is strip-shaped, and the extending direction of the first conductive structure 6 is the same as the extending direction of the gate line 1.
- At least two first via holes 7 are disposed at least at both ends of the first conductive structure 6, so that the size of the first conductive structure 6 is not In the case of a change, the utilization efficiency of the first conductive structure 6 is improved, and the overall resistance value of the entire gate line 1 is reduced.
- the “at least one first conductive structure” may be one first conductive structure 6 or multiple first conductive structures 6 .
- the first conductive structure 6 when the array substrate includes a first conductive structure 6, "the first conductive structure 6 is electrically connected to the gate line 1 through at least two first via holes 7" may be the first conductive structure 6 through the first The via hole 7 is electrically connected to one of the plurality of gate lines 1.
- the array substrate includes more When the first conductive structures 6 are, "the first conductive structures 6 are electrically connected to the gate lines 1 through the at least two first via holes 7", as shown in FIG.
- each group includes a specific number of first conductive structures 6, each of which includes a first conductive structure 6 corresponding to a gate line 1, in the direction in which the gate lines 1 extend, each group includes A conductive structure 6 is electrically connected to a gate line 1 through a plurality of first via holes 7, respectively.
- the first conductive structure 6 is electrically connected to the gate line 1 through the at least two first via holes 7" may also be other cases, which are not enumerated here.
- each of the first conductive structures 6 included in each group corresponds to one gate line 1.
- each of the first conductive structures 6 included in each group passes through the first vias, respectively. 7 is electrically connected to a gate line 1.
- the resistance of each gate line 1 can be reduced, so that the signal delay time of each gate line 1 can be reduced, so that the number of pixel units 3 that cannot be normally displayed is further reduced. Further, the problem that the display device cannot display the screen normally can be improved.
- the insulating layer 5 may be a gate insulating layer or another insulating layer, which is not specifically limited.
- the projection of the first conductive structure 6 on the array substrate (eg, the substrate substrate 0) and the projection of the gate lines 1 on the array substrate may at least partially overlap, disposed on the insulating layer 5.
- the first via 7 is at least partially located in the overlapping region, and the first conductive structure 6 is electrically connected to the gate line 1 through at least two first vias 7; further, the projection and gate of the first conductive structure 6 on the array substrate
- the projection of the line 1 on the array substrate may also not overlap.
- the projection of the first conductive structure 6 on the array substrate is just in contact with the projection of the gate line 1 on the array substrate, and the first via hole 7 is located at the first conductive layer.
- the first via hole 7 may be filled with a conductive material, and the first conductive structure 6 is in contact with the edge of the gate line 1 through the conductive material in the first via hole 7, thereby achieving electrical connection.
- the projection of the first conductive structure 6 on the array substrate and the projection of the gate line 1 on the array substrate at least partially overlap, and the first via 7 disposed on the insulating layer 5 is at least partially located.
- the first conductive structure 6 has a larger contact area with the gate line 1 than the projection of the first conductive structure 6 on the array substrate and the projection of the gate line 1 on the array substrate. The connection of the first conductive structure 6 and the gate line 1 is made more stable.
- the projection of the first conductive structure 6 on the array substrate can be within the projection of the gate line 1 on the array substrate. Since the gate line 1 is located in a light-shielding region of the array substrate (for example, covered by a black matrix), The first conductive structure 6 is also located in the light-shielding region and does not affect the aperture ratio of the display device.
- the array substrate further includes a thin film transistor including a source 8 and a drain 9, and the source 8 and the drain 9 are both in the same layer as the first conductive structure 6. They are disposed and are not in contact with the first conductive structure 6.
- the array substrate further includes a data line 2 that intersects the gate lines to define pixel units arranged in sequence, and the first conductive structure 6 is also disposed in the same layer as the data lines 2, and thus can be formed in the same preparation process, thereby simplifying The fabrication process of the array substrate.
- the first conductive structure 6 needs to be disposed along the direction of the gate line 1 between the adjacent two drains 9, that is, the first conductive structure 6 is disposed between the adjacent two pixel units in the direction of the gate line 1.
- the thin film transistor may further include an active layer 10 and an etch stop layer 11 between the insulating layer 5 and the film layer where the source 8 and the drain 9 are located, and the etch barrier
- the layer 11 is provided with a second via 12 corresponding to the source 8 and a third via 13 corresponding to the drain, and the source 8 and the drain 9 are respectively activated through the second via 12 and the third via 13 Layer 10 is connected. Since the etch stop layer 11 is provided on the active layer 10, when the source 8 and the drain 9 are etched on the active layer 10, the active layer 10 is not etched, so that the active layer 10 is not affected. Performance.
- the array substrate can include a passivation layer 14 on the film layer on which the first conductive structure 6 is located, and at least one second conductive layer on the passivation layer 14.
- the passivation layer 14 is provided with at least two fourth via holes 16 corresponding to the second conductive structure 15, and the second conductive structure 15 is electrically connected to the first conductive structure 6 through at least two fourth via holes 16.
- the second conductive structure 15 is electrically connected to the first conductive structure 6 through the at least two fourth vias 16, the second conductive structure 15 and the gate line 1 and the first conductive structure 6 are The constituent structures are connected in parallel, which is equivalent to a resistor in parallel with the structure composed of the gate line 1 and the first conductive structure 6, so that the resistance value of the entire gate line 1 as a whole can be further reduced.
- the addition of the second conductive structure 15 can further improve the problem that the display device cannot display the screen normally.
- the "at least one second conductive structure 15" may be a second conductive structure 15 or a plurality of second conductive structures 15.
- the second conductive structure 15 is electrically connected to the first conductive structure 6 through the at least two fourth vias 16
- the structure 6 is electrically connected;
- a second conductive structure 15 may also be electrically connected to the plurality of first conductive structures 6 through at least two fourth vias 16.
- a second conductive structure 15 is electrically connected to the two first conductive structures 6 through the two fourth via holes 16, respectively.
- the array substrate includes a plurality of second conductive structures 15, "the second conductive structures 15 are electrically connected to the first conductive structures through the at least two fourth vias 16" may be in the extending direction of the gate lines 1, each of the first The two conductive structures 15 are respectively electrically connected to a first conductive structure 6; or, as shown in FIG. 6, in the extending direction of the at least one gate line 1, a plurality of first conductive structures 6 are sequentially disposed, and the second conductive structures 15 are located.
- the second conductive structure 15 is electrically connected to the two first conductive structures 6 adjacent to the second conductive structure 15 through the two fourth via holes 16, respectively. That is, in the extending direction of the gate line 1, the second conductive structure 15 connects the first conductive structures 6 together through the fourth via holes 16; further, “the second conductive structure 15 passes through at least two fourth via holes 16 Electrically connected to the first conductive structure 6" may also be other structures, which are not enumerated here.
- each gate line 1 a plurality of first conductive structures 6 are sequentially spaced apart, and a second conductive structure 15 is located between any adjacent two first conductive structures 6, and the second conductive structure 15 passes
- the fourth via holes 16 are electrically connected to the two first conductive structures 6 adjacent to the second conductive structure 15 respectively.
- the first conductive structures 6 and the second conductive structures 15 may cover the entire gate lines, which is equivalent to
- Each of the gate lines 1 is connected in parallel with a plurality of resistors, so that the overall resistance of the gate lines is further reduced, and the signal delay time of each of the gate lines 1 can be further reduced, so that the display device can normally display the picture.
- the array substrate further includes a plurality of parallel data lines 2, and the data lines 2 can be disposed in the same layer as the source 8 and the drain 9.
- the data line 2 and the source 8 The drain electrode 9 and the drain electrode 9 can be formed simultaneously, thereby simplifying the fabrication process of the array substrate.
- the gate line 1 and the data line 2 may enclose a plurality of pixel units 3, and a thin film transistor is disposed in the pixel unit 3.
- the thin film transistor includes a source 8 and a drain 9 disposed in the pixel unit 3 Inside.
- the first conductive structure 6 is also disposed in the pixel unit 3, the first conductive structure 6 is in one-to-one correspondence with the pixel unit 3, and the second conductive structure 15 is disposed in any adjacent two pixel units 3. between.
- the first conductive structure 6 is in one-to-one correspondence with the pixel unit 3, which can reduce the process complexity; moreover, the second conductive structure 15 is disposed between any adjacent two pixel units 3, and can be not in the gate line 1
- the second conductive structure 15 is connected in parallel at a position covered by the conductive structure 6, so that the entire gate line 1 is connected in parallel with a conductive structure, thereby reducing the resistance of the gate line 1. Therefore, such a design can reduce the process complexity and reduce the resistance of the gate line 1 to cause the display device to display the picture normally.
- the projection of the second conductive structure 15 on the array substrate and the projection of the first conductive structure 6 on the array substrate may at least partially overlap, and the fourth via 16 disposed on the passivation layer 14 Located in the overlapping region, the second conductive structure 15 is electrically connected to the first conductive structure 6 through the fourth via 16; further, the projection of the second conductive structure 15 on the array substrate and the first conductive structure 6 on the array substrate The projections of the second conductive structure 15 on the array substrate and the projection of the first conductive structure 6 on the array substrate are just in contact, and the fourth via 16 is located at the contact of the second conductive structure 15 .
- the fourth via 16 may be filled with a conductive material, and the second conductive structure 15 is in contact with the edge of the first conductive structure 6 through the conductive material in the fourth via 16, thereby achieving electrical connection.
- the projection of the second conductive structure 15 on the array substrate and the projection of the first conductive structure 6 on the array substrate at least partially overlap with the projection of the second conductive structure 15 on the array substrate.
- the contact area of the second conductive structure 15 with the first conductive structure 6 is larger than the projection of the conductive structure 6 on the array substrate, so that the connection between the second conductive structure 15 and the first conductive structure 6 can be made more. stable.
- the array substrate further includes a gate disposed in the same layer as the gate line 1, and the projection of the second conductive structure 15 on the array substrate and the projection of the gate on the array substrate may at least partially overlap.
- the above gate is also included in the thin film transistor.
- the second conductive structure 15 is electrically connected to the first conductive structure 6, the first conductive structure 6 is electrically connected to the gate line 1, and thus the second conductive structure 15 is electrically connected to the gate line 1, and further, since the gate line 1 is connected to the gate line , for example, formed integrally, so that the signal loaded on the second conductive structure 15 is the same as the gate signal loaded on the gate; in addition, due to the projection of the second conductive structure 15 on the array substrate and the gate on the array substrate The projections at least partially overlap, and in the thin film transistor, the projection of the gate on the array substrate overlaps with the projection of the active layer 10 on the array substrate, and thus, the second conductive structure 15 at least partially overlaps the active layer 10. This causes the second conductive structure 15 and the gate to collectively drive the active layer 10 when the gate signal is applied to the second conductive structure 15 and the gate, thereby increasing the carrier mobility in the active layer 10, Improve the display performance of the display device.
- the array substrate may further include a pixel electrode 17 disposed on the passivation layer 14, and the second conductive structure 15 is disposed in the same material as the pixel electrode 17.
- the second conductive structure 15 can be formed simultaneously with the pixel electrode 17, thereby simplifying the fabrication process of the array substrate.
- the gate line 1 since the gate line 1 has the first conductive structure 6 and the second conductive structure 15 connected in parallel thereto, the resistance of the gate line 1 is small, and slightly increasing the resistance of the gate line 1 does not affect the display effect of the display screen.
- the width of the gate line 1 can be reduced such that the width of the gate line 1 ranges from 2 ⁇ m to 10 ⁇ m, and the width of the gate line 1 can be reduced as compared with the width of the gate line of the prior art of 20 ⁇ m or more. Increase the aperture ratio of the display device.
- the width of the gate line 1 at the position of the first via hole 7 is made to make the first conductive structure 6 and the gate line 1 electrically connected more stably.
- the width of the first via hole 7 formed at this time is larger than the width at other positions of the gate line 1, and thus the connection between the first conductive structure 6 and the gate line 1 can be made more stable.
- the gate line 1 is wider at the position of the second via 16 than at other positions of the gate line 1.
- the embodiment further provides a display device, including the array substrate provided by the above technical solution. Since the display device includes the array substrate in the above technical solution, the display device has the same beneficial effects as the array substrate in the above technical solution, and details are not described herein again.
- the display device may be any product or component having a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a navigator, and the like.
- This embodiment further provides a method for fabricating an array substrate. As shown in FIG. 9, the method includes the following steps S801-S803.
- S801 forming a metal layer, and forming a pattern including signal lines through a patterning process.
- S802 forming an insulating layer on the film layer where the signal line is located, and forming at least two first via holes corresponding to the first conductive structure to be formed on the insulating layer through a patterning process.
- S803 forming a first conductive layer on the insulating layer, and forming a pattern including the first conductive structure through a patterning process, wherein the first conductive structure is electrically connected to the signal line through the at least two first via holes.
- This embodiment provides a method for fabricating an array substrate. As shown in FIG. 10, the method includes the following steps S901 to S903:
- a gate metal layer is formed by plasma enhanced chemical vapor deposition, sputtering, or thermal evaporation, a photoresist is coated on the gate metal layer, and a mask mask having a pattern of gate lines is used to cover the photolithography. After the step of exposing, developing, etching, etc., the gate metal layer of the glue forms a pattern including the gate lines.
- an insulating layer on the film layer where the gate line is located, and forming at least two first via holes corresponding to the first conductive structure (the first conductive structure to be formed) on the insulating layer through a patterning process.
- an insulating layer is formed on the film layer where the gate line is formed by plasma enhanced chemical vapor deposition, sputtering or thermal evaporation, and then at least two corresponding to the first conductive structure are formed on the insulating layer by a patterning process.
- the first via is formed on the film layer where the gate line is formed by plasma enhanced chemical vapor deposition, sputtering or thermal evaporation, and then at least two corresponding to the first conductive structure are formed on the insulating layer by a patterning process.
- a first conductive layer is formed by plasma enhanced chemical vapor deposition, sputtering or thermal evaporation, a photoresist is coated on the first conductive layer, and a mask is coated with a pattern having a first conductive structure.
- the gate layer coated with the photoresist is subjected to exposure, development, etching, etc. to form a pattern including the first conductive structure.
- the first conductive structure Since the first conductive structure is electrically connected to the gate line through the at least two first via holes, the first conductive structure is connected in parallel with the gate line, which is equivalent to connecting a resistor in parallel with the gate line, thereby reducing the overall gate line as a whole.
- the resistance value and, according to the relationship between the resistance value and the signal delay time, the resistance value is proportional to the signal delay time, so reducing the resistance value of the gate line can reduce the signal delay time of the gate line, so that Some of the pixel units that may not be normally displayed in the illustrated technical solution become normal display, and the number of pixel units that cannot be normally displayed in the present invention is compared with the number of pixel units that cannot be normally displayed in the technical solution shown in FIG.
- the present embodiment is described in detail with the signal line as the gate line.
- the embodiments of the present invention include but are not limited thereto, and the signal line may also be other signal lines such as data lines.
- the signal line can be a data line.
- the method for fabricating the array substrate may further include: forming an active layer film layer on the insulating layer, forming a pattern including the active layer by a patterning process; and forming a layer on the active layer Forming an etch barrier layer, forming a second via hole corresponding to the source (source to be formed) and a third via corresponding to the drain (drain to be formed) on the etch barrier layer through a patterning process
- the pattern of the first conductive structure and the pattern of the source and drain are simultaneously formed by one patterning process.
- the source and the drain are electrically connected to the active layer through the second via and the third via, respectively.
- Forming at least two second vias of the structure Forming at least two second vias of the structure; forming a second conductive layer on the passivation layer, forming a pattern including the second conductive structure through a patterning process, the second conductive structure being electrically connected to the first conductive structure through the second via hole,
- a second conductive layer is formed by plasma enhanced chemical vapor deposition, sputtering or thermal evaporation, a photoresist is coated on the second conductive layer, and a mask is coated with a pattern having a second conductive structure.
- the gate layer coated with the photoresist is subjected to exposure, development, etching, etc. to form a pattern including the second conductive structure.
- the method of fabricating the array substrate further includes: forming a gate electrode, the projection of the second conductive structure on the array substrate and the projection of the gate on the array substrate at least partially overlapping.
- the design allows the second conductive structure and the gate to drive the active layer together, thereby increasing the carrier mobility in the active layer and improving the display performance of the display device.
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Abstract
Description
Claims (20)
- 一种阵列基板,包括:多条相互平行的信号线;位于所述多条信号线所在膜层上的绝缘层;以及位于所述绝缘层上的至少一个第一导电结构,其中,所述绝缘层上设置有对应于所述第一导电结构的至少两个第一过孔,所述第一导电结构通过所述至少两个第一过孔与所述信号线电连接。
- 根据权利要求1所述的阵列基板,其中,所述信号线包括栅线。
- 根据权利要求2所述的阵列基板,其中,所述第一导电结构为条状,所述第一导电结构的延伸方向与所述栅线的延伸方向相同。
- 根据权利要求2所述的阵列基板,其中,所述至少两个第一过孔至少设置在所述第一导电结构的两端。
- 根据权利要求2-4中任一项所述的阵列基板,其中,所述第一导电结构在所述阵列基板上的投影与所述栅线在所述阵列基板上的投影至少部分交叠,所述第一过孔位于所述交叠区域内。
- 根据权利要求2-5中任一项所述的阵列基板,其中,所述阵列基板还包括薄膜晶体管,所述薄膜晶体管包括源极和漏极,所述源极和所述漏极均与所述第一导电结构同层设置,且均与所述第一导电结构不接触。
- 根据权利要求6所述的阵列基板,其中,所述薄膜晶体管还包括位于所述绝缘层和所述源极和漏极所在膜层之间的有源层和刻蚀阻挡层,所述刻蚀阻挡层上设置有对应于所述源极的第二过孔和对应于所述漏极的第三过孔,所述源极和所述漏极分别通过所述第二过孔和所述第三过孔与所述有源层电连接。
- 根据权利要求2-5中任一项所述的阵列基板,其中,所述阵列基板还包括位于所述第一导电结构所在膜层上的钝化层,以及位于所述钝化层上的至少一个第二导电结构,所述钝化层上设置有对应于所述第二导电结构的至少两个第四过孔,所述第二导电结构通过所述至少两个第四过孔与所述第一导电结构电连接。
- 根据权利要求8所述的阵列基板,其中,在每条所述栅线的延伸方向上,多个所述第一导电结构依次间隔设置,所述第二导电结构位于任意相邻的 两个第一导电结构之间,所述第二导电结构通过所述至少两个第四过孔分别和与所述第二导电结构相邻的两个所述第一导电结构电连接。
- 根据权利要求8所述的阵列基板,其中,所述阵列基板还包括多条相互平行的数据线,所述多条栅线和所述多条数据线围成多个像素单元,各所述第一导电结构分别设置在各所述像素单元内,且所述第一导电结构与所述像素单元一一对应,所述第二导电结构设置在任意相邻的两个所述像素单元之间。
- 根据权利要求8所述的阵列基板,其中,所述第二导电结构在所述阵列基板上的投影与所述栅线在所述阵列基板上的投影至少部分交叠,所述第四过孔位于所述交叠区域内。
- 根据权利要求8所述的阵列基板,其中,所述阵列基板还包括与所述栅线同层设置的栅极,所述第二导电结构在所述阵列基板上的投影与所述栅极在所述阵列基板上的投影至少部分交叠。
- 根据权利要求8所述的阵列基板,其中,所述阵列基板还包括设置在所述钝化层上的像素电极,所述第二导电结构与所述像素电极同层同材料设置。
- 根据权利要求8所述的阵列基板,其中,所述栅线的宽度范围为2μm-10μm。
- 一种显示装置,包括如权利要求1-14任一项所述的阵列基板。
- 一种阵列基板的制作方法,包括:形成金属层,经过构图工艺形成包括信号线的图形;在所述信号线所在膜层上形成绝缘层,经过构图工艺在所述绝缘层上形成对应于待形成的第一导电结构的至少两个第一过孔;以及在所述绝缘层上形成第一导电层,经过构图工艺形成包括所述第一导电结构的图形,其中,所述第一导电结构通过所述至少两个第一过孔与所述信号线电连接。
- 根据权利要求16所述的阵列基板的制作方法,其中,所述金属层为栅金属层,所述信号线为栅线。
- 根据权利要求17所述的阵列基板的制作方法,在形成所述第一导电层之前,还包括:在所述绝缘层上形成有源层膜层,经过构图工艺,形成包括有源层的图形;在所述有源层所在膜层上形成刻蚀阻挡层,经过构图工艺,在所述刻蚀阻 挡层上形成对应于待形成的源极的第二过孔和对应于待形成的漏极的第三过孔;以及通过一次构图工艺同时形成第一导电结构的图形和源极和漏极的图形,其中,所述源极和所述漏极分别通过所述第二过孔和所述第三过孔与所述有源层电连接。
- 根据权利要求17或18所述的阵列基板的制作方法,在形成第一导电结构之后,还包括:在所述第一导电结构所在膜层上,形成钝化层,经过构图工艺形成对应于待形成的第二导电结构的至少两个第四过孔;以及在所述钝化层上形成第二导电层,经过构图工艺形成包括第二导电结构的图形,所述第二导电结构通过所述至少两个第四过孔与所述第一导电结构电连接。
- 根据权利要求19所述的阵列基板的制作方法,在形成栅线的同时,还包括:形成栅极,所述第二导电结构在所述阵列基板上的投影与所述栅极在所述阵列基板上的投影至少部分交叠。
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1832184A (zh) * | 2006-02-24 | 2006-09-13 | 广辉电子股份有限公司 | 有源元件阵列基板 |
CN103296033A (zh) * | 2013-05-28 | 2013-09-11 | 京东方科技集团股份有限公司 | 一种阵列基板及其制作方法 |
CN104216182A (zh) * | 2014-08-22 | 2014-12-17 | 京东方科技集团股份有限公司 | 阵列基板及其制造方法和显示面板 |
CN105448935A (zh) * | 2016-01-04 | 2016-03-30 | 京东方科技集团股份有限公司 | 一种阵列基板及其制作方法、显示装置 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1832184A (zh) * | 2006-02-24 | 2006-09-13 | 广辉电子股份有限公司 | 有源元件阵列基板 |
CN103296033A (zh) * | 2013-05-28 | 2013-09-11 | 京东方科技集团股份有限公司 | 一种阵列基板及其制作方法 |
CN104216182A (zh) * | 2014-08-22 | 2014-12-17 | 京东方科技集团股份有限公司 | 阵列基板及其制造方法和显示面板 |
CN105448935A (zh) * | 2016-01-04 | 2016-03-30 | 京东方科技集团股份有限公司 | 一种阵列基板及其制作方法、显示装置 |
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