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WO2019095764A1 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

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Publication number
WO2019095764A1
WO2019095764A1 PCT/CN2018/101448 CN2018101448W WO2019095764A1 WO 2019095764 A1 WO2019095764 A1 WO 2019095764A1 CN 2018101448 W CN2018101448 W CN 2018101448W WO 2019095764 A1 WO2019095764 A1 WO 2019095764A1
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WIPO (PCT)
Prior art keywords
pixel
gate
array substrate
sub
pixel groups
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Application number
PCT/CN2018/101448
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English (en)
French (fr)
Inventor
程鸿飞
李盼
Original Assignee
京东方科技集团股份有限公司
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Priority to US16/335,066 priority Critical patent/US11327378B2/en
Priority to EP18865351.3A priority patent/EP3712692B1/en
Publication of WO2019095764A1 publication Critical patent/WO2019095764A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134336—Matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a display panel, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the display device is generally provided with a plurality of sub-pixels arranged in a matrix, wherein sub-pixels located in the same row are connected to the same gate line, and sub-pixels in the same column are connected to the same data line.
  • the data line is connected to the data driving chip in the non-display area.
  • the number of data drive chips required is determined by the number of data lines.
  • an array substrate including: a substrate substrate; a plurality of gate lines extending in a row direction on the substrate substrate; and a plurality of data lines on the substrate substrate a column direction extending intersecting the row direction; and a plurality of pixel groups arranged in rows and columns, each of the plurality of pixel groups including two sub-pixels arranged side by side in the row direction.
  • Each row of pixel groups is connected to a corresponding one of the gate lines, and two sub-pixels of each pixel group in the row of pixel groups are respectively connected to different ones of the corresponding two gate lines.
  • the data line and each column of pixel groups are alternately arranged in the row direction, and two sub-pixels of each of the plurality of pixel groups are directly adjacent to the pixel group of the plurality of data lines Corresponding to a data line connection.
  • each row of pixel groups is located between the respective two gate lines.
  • each column of pixel groups is coupled to a respective one of the plurality of data lines directly adjacent to the column of pixel groups.
  • each two directly adjacent pixel groups in each column of pixel groups are respectively connected to different ones of the two data lines of the plurality of data lines directly adjacent to the column pixel group.
  • each of the sub-pixels of the plurality of pixel groups includes a pixel electrode and a thin film transistor connecting the pixel electrode to the corresponding one of the data lines.
  • each thin film transistor of each sub-pixel of each column of pixel groups is arranged along a center line between two of the plurality of data lines directly adjacent to the column of pixel groups, and The pixel electrodes of two sub-pixels of each pixel group in each column pixel group are respectively located on both sides of the center line.
  • the thin film transistor of each of the sub-pixels includes: a gate connected to a first gate line of the plurality of gate lines connected to the sub-pixel, the gate Arranging in a gate pattern; and a source connected to the data line connected to the sub-pixel, the source being arranged in a source pattern, the source pattern being included in the first gate line and the same a first sub-pattern extending parallel to the gate line in a gap between the second gate lines of the plurality of gate lines directly adjacent to one gate line, and away from the first sub-pattern A second sub-pattern of one end of the data line extending toward the gate pattern.
  • the array substrate further includes a common electrode and a plurality of common electrode lines extending in the row direction and connected to respective ones of the rows of pixel groups.
  • the common electrode line is connected to the common electrode at a center position of a corresponding pixel group in the pixel group.
  • the common electrode has a corresponding opening at a location corresponding to each thin film transistor.
  • the common electrode has a corresponding opening at a position corresponding to the intersection of the gate line and the data line.
  • the common electrode comprises a strip-shaped sub-electrode, and wherein the pixel electrode is a planar electrode.
  • the common electrode is located on a side of the pixel electrode facing away from the substrate substrate.
  • the array substrate further includes a gate drive circuit coupled to the gate line.
  • a display panel comprising the array substrate as described above.
  • a display device comprising the display panel as described above.
  • FIG. 1 is a schematic plan view of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic plan view of another array substrate according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic plan view of still another array substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic plan view of still another array substrate according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic plan view of still another array substrate according to an embodiment of the present disclosure.
  • Figure 6 is an enlarged schematic view of a pixel group of Figure 5;
  • Figure 7 is a cross-sectional view taken along line A-A' of Figure 6;
  • Figure 8 is a combined view of a cross-sectional view taken along line B-B' and line C-C' in Figure 6;
  • FIG. 9 is a partial cross-sectional view of a display device according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic block diagram of a display device according to an embodiment of the present disclosure.
  • first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/ Some should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer Thus, a first element, component, region, layer, or section, which is discussed below, may be referred to as a second element, component, region, layer or section without departing from the teachings of the disclosure.
  • under and under can encompass both the ⁇ RTIgt; Terms such as “before” or “before” and “after” or “following” may be used, for example, to indicate the order in which light passes through the elements.
  • the device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • a layer is referred to as “between two layers,” it may be a single layer between the two layers, or one or more intermediate layers may be present.
  • FIG. 1 is a schematic plan view of an array substrate according to an embodiment of the present disclosure.
  • the array substrate 01 includes a base substrate 100 and a plurality of gate lines 101 and a plurality of data lines 102 on the base substrate 100.
  • the gate line 101 extends in the row direction XX'
  • the data line 102 extends in a column direction crossing the row direction X-X'.
  • the array substrate 01 further includes a plurality of pixel groups 200 arranged in rows and columns.
  • Each of the pixel groups 200 includes two sub-pixels P and P' arranged side by side in the row direction X-X'.
  • the array substrate 01 includes a plurality of pixel groups 200 arranged in a matrix of m x n, where m and n are positive integers. Therefore, the array substrate 01 includes sub-pixels arranged in a matrix of m ⁇ 2n.
  • Each of the sub-pixels includes a pixel electrode PE and a thin film transistor that connects the pixel electrode PE to a corresponding one of the data lines 102.
  • the two sub-pixels P, P' of each pixel group 200 in the i-th row pixel group are respectively connected to different ones of the corresponding two gate lines.
  • the sub-pixel P is connected to the gate line G(1, 2)
  • the sub-pixel P' is connected to the gate line G(1, 1).
  • N data lines D1, D2, ... Dn are provided in the array substrate 01 of FIG.
  • Each of the data lines D1, D2, ... Dn and each column of pixel groups 200 are alternately arranged in the row direction X-X', and two sub-pixels of each of the plurality of pixel groups 200 P, P' is connected to a corresponding one of the plurality of data lines D1, D2 ... Dn directly adjacent to the pixel group 200.
  • each column of pixel groups 200 is connected to a corresponding one of the plurality of data lines D1, D2 . . . Dn directly adjacent to the column of pixel groups 200.
  • two sub-pixels P, P' of each of each pixel group 200 are connected to data lines on the same side (left side in this example) of the pixel group 200.
  • the array substrate embodiment of Figure 1 is advantageous because it reduces the required data lines and thus the data driven chips required. Specifically, for sub-pixels arranged in a matrix of m ⁇ 2n, only n data lines are required. This is half of the data line of a conventional array substrate in which each column of sub-pixels requires a corresponding one of the data lines. Although the reduction of the data line is achieved at the expense of the increase in the gate line, this is still worthwhile because the number of data lines in the display device is usually much larger than the number of gate lines.
  • FIG. 2 is a schematic plan view of another array substrate according to an embodiment of the present disclosure.
  • each row of pixel groups 200 is located between respective two gate lines 101 connected to the row of pixel groups 200.
  • the pixel group 200 of the first row is located between the gate lines G(1, 1) and G(1, 2)
  • the pixel group 200 of the second row is located between the gate lines G(2, 1) and G(2, 2).
  • the mth row pixel group 200 is located between the gate lines G(m, 1) and G(m, 2).
  • the grid line arrangement of Figure 2 provides advantages over the grid line arrangement of Figure 1 .
  • For the grid line arrangement in FIG. 1 since two gate lines connected to the peer pixel group are located on the same side of the row pixel group, two gate lines need to be respectively fabricated through two patterning processes in the fabrication process. On different layers to avoid short circuits.
  • two gate lines are formed by one patterning process, it is necessary to separate the gates of the thin film transistors connected to one of the two gate lines away from the one of the row of pixel groups by a separate patterning process. .
  • by arranging each row of pixel groups 200 between two gate lines 101 connected thereto two gate lines and two gate lines can be completed by one patterning process. The fabrication of the gate. Therefore, the fabrication process is simplified and the thickness of the array substrate is reduced.
  • the patterning process may include one or more of the following: photolithography, etching, printing, inkjet, and the like.
  • Photolithography refers to a process including forming a film, exposing, developing, etc., which forms a pattern using a photoresist, a mask, an exposure machine, or the like.
  • the corresponding patterning process can be selected according to the specific structure.
  • FIG. 3 is a schematic plan view of still another array substrate according to an embodiment of the present disclosure.
  • n+1 data lines D1, D2, ... Dn+1 are provided in the array substrate 01 of FIG.
  • Each of the two directly adjacent pixel groups in each column of pixel groups 200 is respectively connected to two of the plurality of data lines D1, D2, ..., Dn+1 directly adjacent to the column of pixel groups 200.
  • Different data lines in the data line For example, the pixel group 200 in the first row and the first column is connected to the data line D1, the pixel group 200 in the second row and the first column is connected to the data line D2, and the pixel group 200 in the third row and the first column is connected to Data line D1, and so on.
  • the embodiment of Figure 3 provides advantages over the embodiment of Figures 1 and 2.
  • the polarity of the electrical signal loaded on the data line 102 needs to be reversed in a display frame time. Turn 2m times.
  • the electrical signal loaded on the data line 102 needs to be reversed in polarity at a frequency of 120 m Hz, resulting in higher energy consumption.
  • the electrical signal loaded on the data line 102 only needs to be reversed at a frequency of 60 m Hz, thereby greatly reducing Energy consumption.
  • FIG. 4 is a schematic plan view of still another array substrate according to an embodiment of the present disclosure.
  • the array substrate 01 further includes a gate driving circuit connected to the gate line 101, more specifically, a Gate Driver on Array (GOA) circuit. Since the manufacturing cost of the GOA circuit is much lower than that of the discrete gate driving chip, the manufacturing cost can be reduced, although the number of gate lines is doubled.
  • GOA Gate Driver on Array
  • the GOA circuit is disposed in the non-display area of the array substrate 01.
  • the gate line 101 is connected to the output of the GOA circuit.
  • the fabrication of the GOA circuit is completed by a patterning process in the fabrication process of the array substrate.
  • FIG. 5 is a schematic plan view of still another array substrate according to an embodiment of the present disclosure.
  • the two sub-pixels of each pixel group include respective thin film transistors TFT1, TFT2.
  • the thin film transistors TFT1 and TFT2 of each sub-pixel of each column pixel group are arranged along a center line L between two data lines among the data lines directly adjacent to the pixel group 200.
  • the embodiment of Figure 5 provides advantages over the embodiment of Figures 1-3.
  • the distance between the two sub-pixels P and P' in the same pixel group 200 is different from the connected data line 102, resulting in pixel electrodes in the two sub-pixels P and P'.
  • the data transmission path of PE differs greatly. This may result in uneven brightness of the display.
  • the embodiment of Fig. 5 allows the data signal transmission paths of the two sub-pixels P and P' in the same pixel group 200 to be the same or similar, thereby improving the uniformity of the display picture.
  • FIG. 6 shows an enlarged schematic view of one pixel group 200 of FIG.
  • the two thin film transistors TFT1 and TFT2 of the pixel group 200 are arranged along the center line L.
  • the two thin film transistors TFT1 and TFT2 are located inside the two gate lines connected to the pixel group 200 and adjacent to the pixel electrode PE.
  • the thin film transistor TFT1 includes a gate electrode connected to the first gate line G1 and arranged in a gate pattern GP, and a source connected to the data line 102 and arranged in a source pattern S.
  • the second gate line G2 is directly adjacent to the first gate line G1, and they have a gap R before.
  • the source pattern S includes a first sub-pattern S1 extending from the connection point T of the source pattern S and the data line 102 toward the center line L in the gap R, and from the end of the first sub-pattern S1 away from the connection point T toward the thin film transistor
  • the second sub-pattern S2 of the gate pattern GP of the TFT extends.
  • the first sub-pattern S1 does not overlap with the gate lines G1, G2, and the parasitic capacitance between the source pattern S and the gate lines G1, G2 is lowered.
  • the two pixel electrodes PE in the pixel group 200 are respectively located on both sides of the center line L. This further equalizes the data signal transmission paths of the two sub-pixels P and P', thereby improving the uniformity of the display picture.
  • Fig. 7 is a schematic cross-sectional view taken along line A-A' of Fig. 6.
  • the array substrate further includes a common electrode CE and a common electrode line 10 connected to the common electrode CE.
  • the common electrode line 10 and the common electrode CE are connected at a central position O of the pixel group 200.
  • the common voltage transmitted through the common electrode line 10 can be uniformly applied to the common electrode region corresponding to the pixel group 200, thereby further improving the uniformity of the display screen.
  • the array substrate can be an Advanced-Super Dimensional Switching (ADS) type, an In Plane Switch (IPS) type, and a high aperture ratio advanced super-dimensional field switch (Higher Aperture Advanced).
  • ADS Advanced-Super Dimensional Switching
  • IPS In Plane Switch
  • HADS High aperture ratio advanced super-dimensional field switch
  • the pixel electrode and the common electrode are strip electrodes, and the strip electrode electrodes of the pixel electrode and the common electrode are spaced apart.
  • the pixel electrode is a slit electrode
  • the common electrode is a planar electrode, and the pixel electrode is located on a side of the common electrode away from the substrate.
  • the common electrode is a slit electrode
  • the pixel electrode is a planar electrode
  • the common electrode is located on a side of the pixel electrode away from the substrate.
  • the common electrode may not be disposed in the array substrate, but is disposed, for example, in the color filter substrate.
  • Figure 8 is a combined diagram of a cross-sectional view taken along line B-B' and line C-C' in Figure 6.
  • the common electrode CE has an opening 300 at a position corresponding to the thin film transistor TFT.
  • the presence of the opening 300 is advantageous in reducing the parasitic capacitance between the common electrode CE and the thin film transistor TFT, thereby improving the performance stability of the thin film transistor TFT.
  • the common electrode CE has an opening 300 at a position where the corresponding gate line 101 and the data line 102 intersect, thereby reducing parasitics between the common electrode CE and the gate line 101/data line 102. Capacitance, thereby reducing the effect of signals on the gate and data lines on the common voltage on the common electrode CE.
  • the opening 300 in Figure 8 is exemplary and schematic.
  • the overall area of the corresponding thin film transistor TFT of the common electrode CE is an opening.
  • only a part of the area of the common thin film transistor TFT of the common electrode CE is an opening.
  • the overall area of the intersection of the corresponding gate line 101 and the data line 102 of the common electrode CE is an opening.
  • only a part of the intersection of the corresponding gate line 101 of the common electrode CE and the data line 102 is an opening.
  • the thin film transistor TFT is illustrated as a bottom gate type in FIG. 8, the present disclosure is not limited thereto. In other embodiments, the thin film transistor TFT may also be of a top gate type. The appropriate thin film transistor type can be selected as needed.
  • the gate lines (including the gate electrode) and other conductive structures in the same layer as the gate lines may be made of one or more of chromium, tantalum, aluminum, titanium, magnesium or copper, and alloys thereof.
  • the data lines and other conductive structures in the same layer as the data lines may be made of one or more of chromium, tantalum, aluminum, titanium, magnesium or copper and alloys thereof.
  • Indium Tin Oxide (ITO), Indium Gallium Zinc (Indium Tin Oxide (ITO), Indium Gallium Zinc) may be used for the pixel electrode, other conductive structures in the same layer as the pixel electrode, the common electrode, and other conductive structures in the same layer as the common electrode.
  • the gate insulating layer may be one or more materials selected from the group consisting of silicon nitride, silicon oxide, and silicon oxynitride, and the gate insulating layer may be a single layer structure or a multilayer structure.
  • the passivation layer may be one or more of silicon nitride, silicon oxide, silicon oxynitride, or it may be a resin material.
  • the passivation layer may be a single layer structure or a multilayer structure.
  • the active layer may be made of a polysilicon (a-Si) material. The present disclosure is not limited thereto.
  • FIG. 9 is a partial cross-sectional view of a display device according to an embodiment of the present disclosure. Specifically, FIG. 9 schematically shows a cross-sectional structure of the display device from the perspective of one pixel group 200.
  • the display device includes the array substrate 01, the counter substrate 02, and the liquid crystal layer 03 between the array substrate 01 and the counter substrate 02 as described in any of the above embodiments.
  • the cartridge substrate 02 is provided with a color resist pattern of a different primary color (in this case, the pair of cassette substrates may also be referred to as a color filter substrate).
  • the card substrate 02 is respectively provided with a red color resist pattern (R) and a green color resist pattern (G) at positions corresponding to two sub-pixels in the pixel group 200.
  • the color resist patterns may be sequentially arranged in the order of red, green, and blue in the row direction.
  • a black matrix is also provided to the cartridge substrate 02 at a region between adjacent sub-pixels and at a non-display region around a display region corresponding to all sub-pixels. In order not to obscure the subject matter of the present disclosure, a detailed description of the cartridge substrate 02 is omitted herein.
  • FIG. 10 is a block diagram showing a display device 1000 according to an embodiment of the present disclosure.
  • the display device 1000 includes a display panel 1100 for displaying an image, a gate driver 1200 for outputting a gate scan signal to the display panel 1100, a data driver 1300 for outputting a data voltage to the display panel 1100, and The timing controller 1400 controls the gate driver 1200 and the data driver 1300.
  • the display panel 1100 includes an array substrate 1110 and an opposite substrate 1120 opposite to the array substrate 1110.
  • the display panel 110 further includes a liquid crystal layer (not shown) sandwiched between the array substrate 1110 and the opposite substrate 1120, and the opposite substrate 1120 may be a color filter substrate.
  • the opposite substrate 1120 may be a cover.
  • the array substrate 1110 includes a plurality of pixel regions PX arranged in an array. Each of the pixel regions PX is located at a corresponding intersection of the plurality of gate lines GL and the plurality of data lines DL. Each pixel region includes a pixel that includes a thin film transistor (not shown) and other associated components.
  • the array substrate 1110 can take the form of any of the array substrates described above with respect to Figures 1-9.
  • the gate driver 1200 is electrically connected to the first ends of the respective gate lines GL, thereby sequentially applying gate scan signals to the respective gate lines GL.
  • the gate driver 1200 may be directly mounted (eg, integrated) in the array substrate 1110.
  • the gate driver 1200 may be connected to the display panel 1100 through a Tape Carrier Package (TCP).
  • TCP Tape Carrier Package
  • the data driver 1300 is electrically connected to the first ends of the respective data lines DL to output data voltages to the respective data lines DL.
  • data driver 1300 can include a plurality of data driven chips operating in parallel.
  • the timing controller 1400 controls the operation of each of the gate driver 1200 and the data driver 1300. Specifically, the timing controller 1400 outputs data control signals and image data to control the driving operation of the data driver 1300, and outputs a gate control signal to control the driving operation of the gate driver 1200. Data control signals and image data are applied to the data driver 1300. A gate control signal is applied to the gate driver 1200.
  • the display device 1000 may be any product or component having a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种阵列基板，包括：衬底基板；多条栅线，在所述衬底基板上沿行方向延伸；多条数据线，在所述衬底基板上沿与所述行方向交叉的列方向延伸；以及多个像素组，呈行和列排列，所述多个像素组中的每一组包括沿所述行方向并排设置的两个亚像素。每一行像素组与所述栅线中的相应两条栅线连接，并且该行像素组中每个像素组的两个亚像素分别连接所述相应两条栅线中的不同栅线。所述数据线和各列像素组在所述行方向上交替排列，并且所述多个像素组中的每一组的两个亚像素与所述多条数据线中的与该像素组直接相邻的对应一条数据线连接。

Description

阵列基板、显示面板及显示装置
相关申请的交叉引用
本申请要求2017年11月17日提交的中国专利申请No.201721551996.0的权益，其全部公开内容通过引用合并于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板、显示面板及显示装置。
背景技术
TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管-液晶显示器)因其具有体积小、功耗低、无辐射以及制作成本相对较低等特点，而越来越多地被应用于高性能显示领域当中。
现有技术中，显示装置一般设置有呈矩阵排列的多个亚像素，其中位于同行的亚像素与同一栅线连接，位于同列的亚像素与同一数据线连接。数据线在非显示区与数据驱动芯片连接。所需的数据驱动芯片的数量根据数据线的数量来确定。
发明内容
根据本公开的一方面，提供了一种阵列基板，包括：衬底基板；多条栅线，在所述衬底基板上沿行方向延伸；多条数据线，在所述衬底基板上沿与所述行方向交叉的列方向延伸；以及多个像素组，呈行和列排列，所述多个像素组中的每一组包括沿所述行方向并排设置的两个亚像素。每一行像素组与所述栅线中的相应两条栅线连接，并且该行像素组中每个像素组的两个亚像素分别连接所述相应两条栅线中的不同栅线。所述数据线和各列像素组在所述行方向上交替排列，并且所述多个像素组中的每一组的两个亚像素与所述多条数据线中的与该像素组直接相邻的对应一条数据线连接。
在一些实施例中，每一行像素组位于所述相应两条栅线之间。
在一些实施例中，每一列像素组连接到与该列像素组直接相邻的、所述多条数据线中的相应一条数据线。
在一些实施例中，每一列像素组中每两个直接相邻的像素组分别连接到与该列像素组直接相邻的、所述多条数据线中的两条数据线中的不同数据线。
在一些实施例中，所述多个像素组的各亚像素中的每一个包括像素电极和将该像素电极连接到所述对应一条数据线的薄膜晶体管。
在一些实施例中，每一列像素组的各亚像素的各薄膜晶体管沿着与该列像素组直接相邻的、所述多条数据线中的两条数据线之间的中线排布，并且每一列像素组中每个像素组的两个亚像素的像素电极分别位于所述中线的两侧。
在一些实施例中，各亚像素中的每一个的所述薄膜晶体管包括：栅极，其连接到与该亚像素连接的、所述多条栅线中的第一栅线，所述栅极呈一栅极图案布置；以及源极，其连接到与该亚像素连接的数据线，所述源极呈一源极图案布置，该源极图案包括在所述第一栅线与同该第一栅线直接相邻的、所述多条栅线中的第二栅线之间的间隙中平行于所述栅线延伸的第一子图案，以及从所述第一子图案的远离所述数据线的一端朝向所述栅极图案延伸的第二子图案。
在一些实施例中，所述阵列基板还包括公共电极和沿所述行方向延伸且连接到各行像素组中的相应行的多条公共电极线。所述公共电极线在所述像素组中的相应像素组的中心位置处连接到所述公共电极。
在一些实施例中，所述公共电极在对应各薄膜晶体管的位置处具有相应的开口。
在一些实施例中，所述公共电极在对应所述栅线和所述数据线的交叉的位置处具有相应的开口。
在一些实施例中，所述公共电极包括条状子电极，并且其中所述像素电极为面状电极。
在一些实施例中，所述公共电极位于所述像素电极背离所述衬底基板的一侧。
在一些实施例中，所述阵列基板还包括与所述栅线连接的栅极驱动电路。
根据本公开的另一方面，提供了一种显示面板，包括如上所述的阵列基板。
根据本公开的又另一方面，提供了一种显示装置，包括如上所述 的显示面板。
根据在下文中所描述的实施例，本公开的这些和其它方面将是清楚明白的，并且将参考在下文中所描述的实施例而被阐明。
附图说明
在下面结合附图对于示例性实施例的描述中，本公开的更多细节、特征和优点被公开，在附图中：
图1为本公开实施例提供的一种阵列基板的示意性平面图；
图2为本公开实施例提供的另一种阵列基板的示意性平面图；
图3为本公开实施例提供的再一种阵列基板的示意性平面图；
图4为本公开实施例提供的又一种阵列基板的示意性平面图；
图5为本公开实施例提供的又一种阵列基板的示意性平面图；
图6为图5中一个像素组的放大示意图；
图7为沿图6中的A-A’线截取的剖面示意图；
图8为沿图6中的B-B’线和C-C’线截取的剖面图的组合图示；
图9为本公开实施例提供的一种显示装置的局部剖面示意图；并且
图10为本公开实施例提供的一种显示装置的示意性框图。
具体实施方式
将理解的是，尽管术语第一、第二、第三等等在本文中可以用来描述各种元件、部件、区、层和/或部分，但是这些元件、部件、区、层和/或部分不应当由这些术语限制。这些术语仅用来将一个元件、部件、区、层或部分与另一个区、层或部分相区分。因此，下面讨论的第一元件、部件、区、层或部分可以被称为第二元件、部件、区、层或部分而不偏离本公开的教导。
诸如“在...下面”、“在...之下”、“较下”、“在...下方”、“在...之上”、“较上”等等之类的空间相对术语在本文中可以为了便于描述而用来描述如图中所图示的一个元件或特征与另一个(些)元件或特征的关系。将理解的是，这些空间相对术语意图涵盖除了图中描绘的取向之外在使用或操作中的器件的不同取向。例如，如果翻转图中的器件，那么被描述为“在其他元件或特征之下”或“在其他 元件或特征下面”或“在其他元件或特征下方”的元件将取向为“在其他元件或特征之上”。因此，示例性术语“在...之下”和“在...下方”可以涵盖在...之上和在...之下的取向两者。诸如“在...之前”或“在...前”和“在...之后”或“接着是”之类的术语可以类似地例如用来指示光穿过元件所依的次序。器件可以取向为其他方式(旋转90度或以其他取向)并且相应地解释本文中使用的空间相对描述符。另外，还将理解的是，当层被称为“在两个层之间”时，其可以是在该两个层之间的唯一的层，或者也可以存在一个或多个中间层。
本文中使用的术语仅出于描述特定实施例的目的并且不意图限制本公开。如本文中使用的，单数形式“一个”、“一”和“该”意图也包括复数形式，除非上下文清楚地另有指示。将进一步理解的是，术语“包括”和/或“包含”当在本说明书中使用时指定所述及特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在或添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组。如本文中使用的，术语“和/或”包括相关联的列出项目中的一个或多个的任意和全部组合。
将理解的是，当元件或层被称为“在另一个元件或层上”、“连接到另一个元件或层”、“耦合到另一个元件或层”或“邻近另一个元件或层”时，其可以直接在另一个元件或层上、直接连接到另一个元件或层、直接耦合到另一个元件或层或者直接邻近另一个元件或层，或者可以存在中间元件或层。相反，当元件被称为“直接在另一个元件或层上”、“直接连接到另一个元件或层”、“直接耦合到另一个元件或层”、“直接邻近另一个元件或层”时，没有中间元件或层存在。然而，在任何情况下“在...上”或“直接在...上”都不应当被解释为要求一个层完全覆盖下面的层。
本文中参考本公开的理想化实施例的示意性图示(以及中间结构)描述本公开的实施例。正因为如此，应预期例如作为制造技术和/或公差的结果而对于图示形状的变化。因此，本公开的实施例不应当被解释为限于本文中图示的区的特定形状，而应包括例如由于制造导致的形状偏差。因此，图中图示的区本质上是示意性的，并且其形状不意图图示器件的区的实际形状并且不意图限制本公开的范围。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术语)具有与本公开所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。
下面将结合附图对本公开实施例进行清楚、完整地描述。
图1为本公开实施例提供的一种阵列基板的示意性平面图。
如图1所示，该阵列基板01包括衬底基板100和位于衬底基板100上的多条栅线101和多条数据线102。栅线101沿行方向X-X'延伸，并且数据线102在沿与所述行方向X-X’交叉的列方向延伸。
该阵列基板01还包括呈行和列排列的多个像素组200。每一像素组200包括沿行方向X-X’并排设置的两个亚像素P和P’。在该示例中，该阵列基板01包括以m×n的矩阵排列的多个像素组200，其中，m和n为正整数。因此，该阵列基板01包括以m×2n的矩阵排列的亚像素。各亚像素中的每一个包括像素电极PE和将该像素电极PE连接到对应一条数据线102的薄膜晶体管。
图1的阵列基板01中提供了2m条栅线。每一行像素组200与2m条栅线中的相应两条栅线连接。更一般地，第i行像素组200连接到两条栅线G(i，1)和G(i，2)，其中i＝1，2，......m。例如，第1行像素组200连接到两条栅线G(1，1)和G(1，2)，第2行像素组200连接到两条栅线G(2，1)和G(2，2)，并且第m行像素组200连接到两条栅线G(m，1)和G(m，2)。第i行像素组中每个像素组200的两个亚像素P、P’分别连接所述相应两条栅线中的不同栅线。例如，对于第一行和第一列中的像素组200，亚像素P连接到栅线G(1，2)，并且亚像素P’连接到栅线G(1，1)。
图1的阵列基板01中提供了n条数据线D1，D2......Dn。各数据线D1，D2......Dn和各列像素组200在所述行方向X-X'上交替排列，并且所述多个像素组200中的每一组的两个亚像素P、P’与所述多条数据线D1，D2......Dn中的与该像素组200直接相邻的对应一条数据线连接。具体地，每一列像素组200连接到与该列像素组200直接相邻的、所述多条数据线D1，D2......Dn中的相应一条数据线。更具体 地，在图1的示例中，各像素组200中的每一个的两个亚像素P、P’与位于该像素组200同一侧(在该示例中为左侧)的数据线连接。
图1的阵列基板实施例是有利的，因为它减少了所需的数据线以及因此所需的数据驱动芯片。具体地，对于以m×2n的矩阵排列的亚像素，仅仅需要n条数据线。这是其中每列亚像素都需要相应的一条数据线的常规阵列基板的数据线的一半。虽然数据线的减少是以栅线的增加为代价实现的，但是这仍然是值得的，因为在显示装置中数据线的数目通常远远多于栅线的数目。
图2为本公开实施例提供的另一种阵列基板的示意性平面图。
与图1的实施例不同，在图2的阵列基板01中，每一行像素组200位于与该行像素组200相连接的相应两条栅线101之间。例如，第1行像素组200位于栅线G(1，1)和G(1，2)之间，第2行像素组200位于栅线G(2，1)和G(2，2)之间，并且第m行像素组200位于栅线G(m，1)和G(m，2)之间。
图2的栅线布置方式提供了相对于图1的栅线布置方式的优点。对于图1中的栅线布置方式而言，由于与同行像素组连接的两条栅线位于该行像素组的同侧，所以在制作过程中需要将两条栅线分别通过两次构图工艺制作于不同层以便避免短路。替换地，如果将两条栅线通过一次构图工艺制作，则需要将与两条栅线中远离该行像素组中的一条栅线连接的薄膜晶体管的栅极，采用单独的构图工艺异层设置。这导致复杂的制作工艺和阵列基板的厚度增加。相比之下，在图2的实施例中，通过将每一行像素组200设置在与其连接的两条栅线101之间，能够通过一次构图工艺完成两条栅线以及两条栅线对应的栅极的制作。因此，简化了制作工艺，并且减小了阵列基板的厚度。
需要说明的是，在本公开中，构图工艺，可指包括下列中的一项或多项：光刻、刻蚀、打印、喷墨等。光刻是指包括成膜、曝光、显影等工艺过程，其利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据具体结构选择相应的构图工艺。
图3为本公开实施例提供的再一种阵列基板的示意性平面图。
不同于图1和2的实施例，图3的阵列基板01中提供了n+1条数据线D1，D2......Dn+1。每一列像素组200中每两个直接相邻的像素组分别连接到与该列像素组200直接相邻的、所述多条数据线D1， D2......Dn+1中的两条数据线中的不同数据线。例如，第一行和第一列中的像素组200连接到数据线D1，第二行和第一列的像素组200连接到数据线D2，第三行和第一列的像素组200连接到数据线D1，以此类推。
图3的实施例提供了相对于图1和2的实施例的优点。对于图1或图2中示出的阵列基板，在采用点反转的方式驱动各亚像素的像素电极PE时，数据线102上加载的电信号的极性在一显示帧的时间内需要反转2m次。在例如60Hz的显示格式的情况下，数据线102上加载的电信号需要以120m Hz的频率进行极性反转，从而导致能耗较高。相比之下，对于图3中示出的阵列基板，在同样的60Hz的显示格式的情况下，数据线102上加载的电信号只需要以60m Hz的频率进行极性反转，从而大幅降低了能耗。
图4为本公开实施例提供的又一种阵列基板的示意性平面图。
如图4所示，该阵列基板01还包括与栅线101连接的栅极驱动电路，更具体地，阵列基板行驱动(Gate Driver on Array，GOA)电路。由于GOA电路的制作费用相比于分立的栅极驱动芯片的价格低很多，所以能够降低制作成本，尽管栅线的数量加倍。
在实施例中，GOA电路设置在阵列基板01的非显示区。栅线101与GOA电路的输出端连接。在阵列基板的制作过程中通过构图工艺制作完成GOA电路的制作。
图5为本公开实施例提供的又一种阵列基板的示意性平面图。
如图5所示，每个像素组的两个亚像素包括各自的薄膜晶体管TFT1、TFT2。每一列像素组的各亚像素的各薄膜晶体管TFT1、TFT2沿着与该像素组200直接相邻的、各数据线中的两条数据线之间的中线L排布。
图5的实施例提供了相对于图1-3的实施例的优点。在图1-3的实施例中，同一像素组200中的两个亚像素P和P’与所连接的数据线102的距离不同，导致到这两个亚像素P和P’中的像素电极PE的数据信号传输路径差异较大。这可能导致显示画面的亮度不均匀。相比之下，图5的实施例允许同一像素组200中的两个亚像素P和P’的数据信号传输路径相同或者相近，从而改善显示画面的均匀性。
图6示出了图5中一个像素组200的放大示意图。
如图6所示，该像素组200的两个薄膜晶体管TFT1和TFT2沿着中线L排布。考虑到亚像素的开口率，两个薄膜晶体管TFT1和TFT2位于连接到该像素组200的两条栅线内侧并且紧邻像素电极PE。
以薄膜晶体管TFT1为例，它包括连接到第一栅线G1且呈一栅极图案GP布置的栅极，和连接到数据线102且呈一源极图案S布置的源极。第二栅线G2与第一栅线G1直接相邻，并且它们之前存在间隙R。该源极图案S包括在间隙R中从源极图案S与数据线102的连接点T向中线L延伸的第一子图案S1，以及从第一子图案S1在远离连接点T一端朝向薄膜晶体管TFT的栅极图案GP延伸的第二子图案S2。这样，第一子图案S1与栅线G1、G2之间不发生重叠，降低了源极图案S与栅线G1、G2之间的寄生电容。
另外，像素组200中的两个像素电极PE分别位于中线L的两侧。这进一步均衡了两个亚像素P和P’的数据信号传输路径，从而改善显示画面的均匀性。
图7为沿图6中的A-A’线截取的剖面示意图。
如图6和7所示，该阵列基板还包括公共电极CE和与公共电极CE连接的公共电极线10。公共电极线10与公共电极CE在像素组200的中心位置O处连接。这样，通过公共电极线10传输的公共电压能够均匀施加在对应该像素组200的公共电极区域，从而进一步改善显示画面的均匀性。
在实施例中，该阵列基板可以为高级超维场开关(Advanced-Super Dimensional Switching，ADS)型、横向电场效应(In Plane Switch，IPS)型、高开口率高级超维场开关(Higher Aperture Advanced Super Dimension Switch，HADS)型等等。对于IPS型阵列基板，像素电极和公共电极均为条状电极，且像素电极和公共电极中的条状子电极间隔设置。对于ADS型阵列基板而言，像素电极为狭缝电极，公共电极为面状电极，且像素电极位于公共电极远离衬底基板的一侧。对于HADS型阵列基板而言，公共电极为狭缝电极，像素电极为面状电极，且公共电极位于像素电极远离衬底基板的一侧。
应当理解到，在其他实施例中，公共电极可以不设置在阵列基板中，而是例如设置在彩膜基板中。
图8为沿图6中的B-B’线和C-C’线截取的剖面图的组合图示。
如图8所示，公共电极CE在对应薄膜晶体管TFT的位置处具有开300。开300的存在有利于降低因公共电极CE与薄膜晶体管TFT之间的寄生电容，从而改善薄膜晶体管TFT的性能稳定性。替换地或附加地，如图8所示，公共电极CE在对应栅线101和数据线102的交叉的位置处具有开300，从而降低公共电极CE与栅线101/数据线102之间的寄生电容，从而降低栅线和数据线上的信号对公共电极CE上的公共电压的影响。
图8中的开300是示例性和示意性的。在一些实施例中，公共电极CE的对应薄膜晶体管TFT的整体区域为开口。替换地，公共电极CE的对应薄膜晶体管TFT的区域的仅一部分为开口。在一些实施例中，公共电极CE的对应栅线101和数据线102的交叉的整体区域为开口。替换地，公共电极CE的对应栅线101和数据线102的交叉的区域的仅一部分为开口。
需要说明的是，虽然在图8中薄膜晶体管TFT被示出为底栅型，但本公开并不限制于此。在其他实施例中，该薄膜晶体管TFT也可以为顶栅型。可以根据需要选择适当的薄膜晶体管类型。
另外，栅线(包括栅极)以及与栅线同层的其他导电结构可以采用铬、钕、铝、钛、镁或铜以及它们的合金中的一种或多种材料。数据线以及与数据线同层的其他导电结构可以采用铬、钕、铝、钛、镁或铜以及它们的合金中的一种或多种材料。像素电极、与像素电极同层的其他导电结构、公共电极以及与公共电极同层的其他导电结构，均可以采用铟锡氧化物(Indium Tin Oxide，ITO)、铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)、铟锌氧化物(Indium Zinc Oxide，IZO)中的一种或多种材料。栅极绝缘层可以采用氮化硅、氧化硅、氮氧化硅中的一种或多种材料，且栅极绝缘层可以为单层结构或多层结构。钝化层可以采用氮化硅、氧化硅、氮氧化硅中的一种或多种材料，或者它还可以为树脂类材料。钝化层可以为单层结构或多层结构。有源层可以采用多晶硅(a-Si)材料。本公开并不限制于此。
图9为本公开实施例提供的一种显示装置的局部剖面示意图。具体地，图9从一个像素组200的视角示意性地示出了该显示装置的剖面结构。
该显示装置包括如上面实施例中的任一个所描述的阵列基板01、 对盒基板02以及位于阵列基板01和对盒基板02之间的液晶层03。
在图9的示例中，对盒基板02被提供有不同原色的色阻图案(此时，该对盒基板也可称为彩膜基板)。例如，针对三原色(RGB)的颜色配置，对盒基板02在对应于像素组200中两个亚像素的位置处分别设置有红色色阻图案(R)和绿色色阻图案(G)。应当理解到，尽管未示出，色阻图案在行方向上可以按照红色、绿色、蓝色的顺序依次重复排列。对盒基板02在相邻亚像素之间的区域处以及在对应于所有亚像素构成的显示区域周围的非显示区域处还设置有黑矩阵。为了不模糊本公开的主题，对盒基板02的详细描述在此被省略。
图10为示出根据本公开实施方式的显示装置1000的框图。
参照图10，显示装置1000包括用于显示图像的显示面板1100、用于向显示面板1100输出栅极扫描信号的栅极驱动器1200、用于向显示面板1100输出数据电压的数据驱动器1300、以及用于控制栅极驱动器1200和数据驱动器1300的时序控制器1400。
显示面板1100包括阵列基板1110和与阵列基板1110相对的对向基板1120。在液晶显示装置的情况下，显示面板110还包括夹在阵列基板1110和对向基板1120之间的液晶层(未示出)，并且对向基板1120可以是彩膜基板。在有机发光二极管显示装置的情况下，对向基板1120可以是盖板。阵列基板1110包括呈阵列排布的多个像素区域PX。各像素区域PX位于多条栅极线GL和多条数据线DL的相应交叉处。每个像素区域都包括像素，该像素包括薄膜晶体管(未示出)和其他相关联的元件。阵列基板1110可以采取上面关于图1-9描述的各阵列基板中的任一个的形式。
栅极驱动器1200电连接到各栅极线GL的第一端，从而顺序地向各栅极线GL施加栅极扫描信号。在一些示例性实施例中，栅极驱动器1200可以被直接安装(例如，集成)在阵列基板1110中。替换地，栅极驱动器1200可以通过带式载体封装(Tape Carrier Package，TCP)连接至显示面板1100。
数据驱动器1300电连接至各数据线DL的第一端，以将数据电压输出至各数据线DL。在一些实施例中，数据驱动器1300可以包括多个并行操作的数据驱动芯片。
时序控制器1400控制栅极驱动器1200和数据驱动器1300中的每 一个的操作。具体地，时序控制器1400输出数据控制信号和图像数据以控制数据驱动器1300的驱动操作，以及输出栅极控制信号以控制栅极驱动器1200的驱动操作。数据控制信号和图像数据被施加至数据驱动器1300。栅极控制信号被施加至栅极驱动器1200。
在实施例中，显示装置1000可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅为本公开的具体实施方式，但本公开的范围并不局限于此。本技术领域的技术人员可以对所公开的实施例做出各种变化或替换而不偏离本公开的范围。因此，本公开的范围应以所附的权利要求为准。

Claims (15)

  1. 一种阵列基板，包括：
    衬底基板；
    多条栅线，在所述衬底基板上沿行方向延伸；
    多条数据线，在所述衬底基板上沿与所述行方向交叉的列方向延伸；以及
    多个像素组，呈行和列排列，所述多个像素组中的每一组包括沿所述行方向并排设置的两个亚像素，
    其中每一行像素组与所述栅线中的相应两条栅线连接，并且该行像素组中每个像素组的两个亚像素分别连接所述相应两条栅线中的不同栅线，并且
    其中所述数据线和各列像素组在所述行方向上交替排列，并且所述多个像素组中的每一组的两个亚像素与所述多条数据线中的与该像素组直接相邻的对应一条数据线连接。
  2. 根据权利要求1所述的阵列基板，其中每一行像素组位于所述相应两条栅线之间。
  3. 根据权利要求1或2所述的阵列基板，其中每一列像素组连接到与该列像素组直接相邻的、所述多条数据线中的相应一条数据线。
  4. 根据权利要求1或2所述的阵列基板，其中每一列像素组中每两个直接相邻的像素组分别连接到与该列像素组直接相邻的、所述多条数据线中的两条数据线中的不同数据线。
  5. 根据权利要求2所述的阵列基板，其中所述多个像素组的各亚像素中的每一个包括像素电极和将该像素电极连接到所述对应一条数据线的薄膜晶体管。
  6. 根据权利要求5所述的阵列基板，其中每一列像素组的各亚像素的各薄膜晶体管沿着与该列像素组直接相邻的、所述多条数据线中的两条数据线之间的中线排布，并且其中每一列像素组中每个像素组的两个亚像素的像素电极分别位于所述中线的两侧。
  7. 根据权利要求6所述的阵列基板，其中各亚像素中的每一个的所述薄膜晶体管包括：
    栅极，其连接到与该亚像素连接的、所述多条栅线中的第一栅线， 所述栅极呈一栅极图案布置；以及
    源极，其连接到与该亚像素连接的数据线，所述源极呈一源极图案布置，该源极图案包括在所述第一栅线与同该第一栅线直接相邻的、所述多条栅线中的第二栅线之间的间隙中平行于所述栅线延伸的第一子图案，以及从所述第一子图案的远离所述数据线的一端朝向所述栅极图案延伸的第二子图案。
  8. 根据权利要求6所述的阵列基板，还包括公共电极和沿所述行方向延伸且连接到各行像素组中的相应行的多条公共电极线，其中所述公共电极线在所述像素组中的相应像素组的中心位置处连接到所述公共电极。
  9. 根据权利要求8所述的阵列基板，其中所述公共电极在对应各薄膜晶体管的位置处具有相应的开口。
  10. 根据权利要求8所述的阵列基板，其中所述公共电极在对应所述栅线和所述数据线的交叉的位置处具有相应的开口。
  11. 根据权利要求8所述的阵列基板，其中所述公共电极包括条状子电极，并且其中所述像素电极为面状电极。
  12. 根据权利要求11所述的阵列基板，其中所述公共电极位于所述像素电极背离所述衬底基板的一侧。
  13. 根据权利要求1所述的阵列基板，还包括与所述栅线连接的栅极驱动电路。
  14. 一种显示面板，包括权利要求1-13任一项所述的阵列基板。
  15. 一种显示装置，包括权利要求14所述的显示面板。
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