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WO2017118073A1 - 阵列基板及其制备方法和显示装置 - Google Patents

阵列基板及其制备方法和显示装置 Download PDF

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Publication number
WO2017118073A1
WO2017118073A1 PCT/CN2016/098497 CN2016098497W WO2017118073A1 WO 2017118073 A1 WO2017118073 A1 WO 2017118073A1 CN 2016098497 W CN2016098497 W CN 2016098497W WO 2017118073 A1 WO2017118073 A1 WO 2017118073A1
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WIPO (PCT)
Prior art keywords
test
pattern
layer
transistor
array substrate
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PCT/CN2016/098497
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English (en)
French (fr)
Inventor
詹裕程
张帅
Original Assignee
京东方科技集团股份有限公司
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Priority to US15/504,083 priority Critical patent/US10197877B2/en
Publication of WO2017118073A1 publication Critical patent/WO2017118073A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display device.
  • the test unit is usually produced in the non-display area of the display product, the line width of the signal line in the test unit, and the upper and lower conductive film layers are
  • the test of the overlay condition is to monitor the stability and accuracy of the preparation process of each film layer in the display area.
  • the performance of the transistor in the display area is monitored, so that the defects in the process can be found in time through the monitoring of the test unit, thereby reducing the manufacturing cost. waste.
  • test elements are a plurality of test elements respectively disposed in different layers in the non-display area.
  • test elements for testing the signal line line width, the overlap between the upper and lower conductive film layers, and the transistor characteristics of the long channel and the short channel are independently disposed, and the test elements are in the non-display area.
  • the distribution is relatively scattered, which not only makes the test component occupy a large space in the non-display area, which is not conducive to saving the preparation cost, and needs to be tested when testing different process parameters. Frequent movements (such as optical test equipment and electrical test equipment) greatly reduce test efficiency and increase test costs.
  • the present disclosure provides an array substrate, a method of fabricating the same, and a display device.
  • the array substrate can realize the integration test of the pattern size of the multi-layer pattern layer in the display area and the mutual overlap degree between the multi-layer pattern layers, and can also realize the integration test of the transistor characteristics in the display area, thereby not only reducing the process. Test costs and improve process testing timeliness.
  • An embodiment of the present invention provides an array substrate including a multi-layer pattern layer disposed in a display area and a test unit disposed in the non-display area, the test unit including at least one test component and at least one test transistor, the test Components include test block graphics and test line graphics.
  • the test block pattern is disposed in the same layer as one of the plurality of pattern layers
  • the test line pattern is disposed in the same layer as one of the plurality of pattern layers
  • the test block pattern and the test are Line graphics are set in different layers.
  • An orthographic projection of the test line pattern on the array substrate surrounds a periphery of an orthographic projection of the test block pattern on the array substrate.
  • the test block pattern or the test line pattern is connected to the test transistor.
  • an orthographic projection of the test line pattern on the array substrate and an orthographic projection of the test block pattern on the array substrate are spaced apart from each other.
  • the multi-layer pattern layer comprises at least two pattern layers of a source/drain electrode layer, a transparent electrode layer, a gate layer, an active layer and a dielectric layer, and the at least two pattern layers are different layers.
  • the multilayer pattern layer includes the source/drain electrode layer, the gate layer, and the active layer.
  • the test unit includes a first test component, the first test component including a first test block graphic and a first test line graphic.
  • the first test block pattern is disposed in the same layer as the gate layer, and the first test line pattern is disposed in the same layer as the source/drain electrode layer.
  • the testing unit includes a second testing component, and the second testing group
  • the piece includes a second test block pattern and a second test line pattern.
  • the second test block pattern is disposed in the same layer as the gate layer, and the second test line pattern is disposed in the same layer as the active layer.
  • the multi-layer pattern layer further includes the transparent electrode layer
  • the test unit includes a third test component
  • the third test component includes a third test block pattern and a third test line pattern.
  • the third test block pattern is disposed in the same layer as the source/drain electrode layer
  • the third test line pattern is disposed in the same layer as the transparent electrode layer.
  • the multi-layer pattern layer further includes the dielectric layer
  • the test unit includes a fourth test component
  • the fourth test component includes a fourth test block graphic and a fourth test line graphic.
  • the fourth test block pattern is disposed in the same layer as the gate layer
  • the fourth test line pattern is disposed in the same layer as the dielectric layer.
  • the orthographic projections of the test components in the test unit on the array substrate are spaced apart from each other and arranged in a row.
  • the test transistor includes a first test transistor and a second test transistor, and a channel size between a source and a drain of the first test transistor and the second test transistor is different, the channel Dimensions include any of length, width, and aspect ratio.
  • the test unit further includes a first gate connection line connected to a gate of the first test transistor and a second gate connection line connected to a gate of the second test transistor.
  • the test block pattern or the test line pattern of the two test components are respectively connected to the first gate connection line and the second gate connection line.
  • the second test block pattern is connected to one of the first gate connection line and the second gate connection line, the fourth test block pattern and the first gate connection line and The other of the second gate connection lines is connected.
  • the test unit further includes a source connection line connected to sources of the first test transistor and the second test transistor, and a drain of the first test transistor and the second test transistor The drain connection line of the pole connection.
  • the first test block pattern is connected to one of the source connection line and the drain connection line
  • the third test block pattern is connected to the other of the source connection line and the drain connection line .
  • the active layers of the first test transistor and the second test transistor are disposed in the same layer as the active layer in the display region.
  • the gates of the first test transistor and the second test transistor, the first gate connection line and the second gate connection line are in the same layer as the gate layer in the display area Settings.
  • the embodiment of the invention further provides a display device comprising the above array substrate.
  • the present invention also provides a method of preparing the above array substrate, comprising forming a plurality of pattern layers in the display region, and forming a test unit in the non-display region.
  • Forming the test unit includes forming at least one test component and at least one test transistor, and forming the test component includes forming a test block pattern and a test line pattern.
  • An orthographic projection of the test line pattern on the array substrate surrounds a periphery of an orthographic projection of the test block pattern on the array substrate.
  • the test block pattern or the test line pattern is connected to the test transistor.
  • an orthographic projection of the test line pattern on the array substrate and an orthographic projection of the test block pattern on the array substrate are spaced apart from each other.
  • an array substrate by setting a test component and a test transistor, and orthographic projection of the test line pattern on the array substrate in the test component around the periphery of the orthographic projection of the test block pattern on the array substrate, Integration testing of the pattern size of the multi-layer pattern layers in the display area and the degree of overlap between the multi-layer pattern layers can be achieved.
  • the test transistor by connecting the test transistor to the test block pattern or the test line pattern, the integration test of the transistor characteristics in the display area can be realized, so that it is not necessary to separately set more test elements for the test of the process performance of each pattern layer in the display area.
  • the space occupied by the test unit in the non-display area is saved, and the process test cost is reduced.
  • test components and test crystals in the test unit The integrated setting of the tube, when the test unit is tested by the test device, the test device can effectively test the performance of the array substrate without frequently moving the position, thereby improving the timeliness of the process test.
  • the display device according to the embodiment of the invention adopts the above array substrate, thereby not only reducing the process capability test cost of the display device, but also improving the process capability test aging of the display device.
  • FIG. 1 is a top plan view showing the structure of a test unit on an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view showing the structure of the array substrate of FIG. 1 taken along line BB.
  • 3 is a cross-sectional view showing the structure of the array substrate taken along line AA after forming the buffer layer and the active layer.
  • FIG. 4 is a cross-sectional view showing the structure of the array substrate taken along line AA after exposure and development of the photoresist.
  • FIG. 6 is a cross-sectional view showing the structure of the array substrate taken along line AA after the gate insulating layer is formed.
  • FIG. 7 is a cross-sectional view showing the structure of the array substrate taken along line AA after forming the gate metal layer.
  • Figure 8 is a cross-sectional view showing the structure of the array substrate taken along line AA after exposure and development of the photoresist.
  • FIG. 9 is a cross-sectional view showing the structure of the array substrate taken along line AA after completion of gate metal layer etching and photoresist stripping.
  • Figure 10 is a cross-sectional view showing the structure of the array substrate taken along line AA after forming the dielectric layer.
  • Figure 11 is a cross-sectional view showing the structure of the array substrate taken along line AA after exposure and development of the photoresist.
  • Figure 12 is an array after the dielectric layer and the gate insulating layer are etched and the photoresist is stripped.
  • Figure 13 is a cross-sectional view showing the structure of the array substrate taken along line AA after forming the source and drain metal layers.
  • Figure 14 is a cross-sectional view showing the structure of the array substrate taken along line AA after exposure and development of the photoresist.
  • 15 is a cross-sectional view showing the structure of the array substrate taken along line AA after the source-drain metal layer etching and the photoresist stripping are completed.
  • an embodiment of the present invention provides an array substrate including a multi-layer pattern layer disposed in a display region and a test unit 1 disposed in a non-display region.
  • the test unit 1 comprises at least one test component 10 and at least one test transistor 13.
  • the test assembly 10 includes a test block pattern 11 and a test line pattern 12.
  • the test block pattern 11 is disposed in the same layer as one of the multi-layer pattern layers
  • the test line pattern 12 is disposed in the same layer as one of the multi-layer pattern layers
  • the test block pattern 11 and the test line pattern 12 are disposed in different layers.
  • the orthographic projection of the test line pattern 12 on the array substrate surrounds the periphery of the orthographic projection of the test block pattern 11 on the array substrate.
  • the test block pattern 11 is connected to the test transistor 13.
  • the orthographic projection of the test line pattern 12 on the array substrate and the orthographic projection of the test block pattern 11 on the array substrate are spaced apart from each other. That is, the orthographic projection of the test line pattern 12 on the array substrate is completely spaced from the orthographic projection of the test block pattern 11 on the array substrate, thereby ensuring accurate detection of the overlapping condition of the test line pattern 12 and the test block pattern 11. Sex. It should be noted that it is only necessary to ensure that the orthographic projection of at least part of the pattern on the test pattern 12 on the array substrate and the orthographic projection of the test block pattern 11 on the array substrate are spaced apart from each other.
  • the orthographic projection of the test line pattern 12 on the array substrate surrounds the orthographic projection periphery of the test block pattern 11 on the array substrate.
  • the test block pattern may be A rectangular block pattern, a polygonal block pattern, a circular block pattern, and the like are described in the present embodiment by taking a rectangular block pattern as an example.
  • the orthographic projection of the test line pattern 12 can surround the orthographic projection periphery of the test block pattern 11 in an arbitrary shape.
  • the test line pattern 12 may be set to be continuous around the figure, or may be set to be discontinuous around the figure.
  • test line pattern 12 may also be disposed to be connected to the test transistor 13. Both the test block pattern 11 and the test line pattern 12 are connected to the test transistor 13 in order to provide the corresponding gate, source and drain test signals to the test transistor 13. Since the area of the test line pattern 12 is small relative to the area of the test block pattern 11, the test signal is difficult to introduce during testing. Therefore, in general, the test signal is introduced to the test transistor 13 through the test block pattern 11, that is, the test block pattern 11 is usually set to be connected to the test transistor 13.
  • the setting of the test line pattern 12 and the test block pattern 11 in the test assembly 10 can respectively test whether the pattern size of the multi-layer pattern layer in the display area satisfies the design and process requirements.
  • the separation distance between the test line pattern 12 and the orthographic projection of the test block pattern 11 on the array substrate enables testing of the degree of overlap between the multilayer pattern layers disposed on different layers in the display area to meet design and process requirements.
  • the pattern size of the multilayer pattern layer and the degree of mutual overlap between the plurality of pattern layers are obtained by optical testing by an optical test apparatus.
  • the setup of test transistor 13 enables testing of the characteristics of the transistors used to control the display within the display area to meet design and process requirements.
  • the test of the transistor characteristics in the display area is obtained by electrical testing by an electrical test device.
  • the process level of each pattern layer in the display area can be detected, the defects occurring in the preparation process can be found in time, and the defects can be improved in time, thereby greatly reducing the cost waste of the array substrate in the preparation process.
  • the process stability and accuracy of the film layers of the array substrate during the preparation process are ensured, thereby ensuring the process quality of each film layer in the array substrate.
  • the orthographic projection of the test line pattern 12 on the array substrate surrounds the periphery of the orthographic projection of the test block pattern 11 on the array substrate, and the test line pattern 12 is on the array substrate.
  • the orthographic projection and the orthographic projection of the test block pattern 11 on the array substrate are spaced apart from each other, and can realize multiple layers in the display area. Integration test of the pattern size of the pattern layer and the degree of overlap between the plurality of pattern layers, that is, by the above-described integrated arrangement of the test block pattern 11 and the test line pattern 12, the pattern of each pattern layer in the display area can be realized. Process parameter testing of dimensions and degree of overlap between individual pattern layers.
  • test transistor 13 by connecting the test transistor 13 to the test block pattern 11, an integration test of the transistor characteristics in the display region can be realized, that is, by the above-described integrated arrangement of the test block pattern 11 and the test transistor 13, it is possible to realize the transistor in the display region.
  • the characteristic process parameter test so that the test performance of each pattern layer in the display area does not need to be separately set more test elements, thereby saving the space occupied by the test unit 1 in the non-display area and reducing the test cost.
  • the test line pattern 12 and the test transistor 13 in the test unit 1 when testing the test unit 1 through the test device, the test device can move the position of the array substrate without frequently moving the position. The performance of the item is effectively tested, which improves the timeliness of the test.
  • the multi-layer pattern layer includes at least two pattern layers of the source-drain electrode layer, the transparent electrode layer, the gate layer, the active layer, and the dielectric layer, and at least two pattern layers are disposed in different layers.
  • the multilayer pattern layer includes a source/drain electrode layer (which is located in the same layer as the source/drain metal layer 500 to be described later), and a gate layer (which is on the same layer as the gate metal layer 300 described later). And an active layer (which is in the same layer as the active layer film 102 described later).
  • the test unit 1 includes a first test component 20, and the first test component 20 includes a first test block graphic 112 and a first test line graphic 122.
  • the first test block graphic 112 is disposed in the same layer as the gate layer.
  • a test line pattern 122 is disposed in the same layer as the source and drain electrode layers.
  • the test unit 1 further includes a second test component 30.
  • the second test component 30 includes a second test block pattern 113 and a second test line pattern 123.
  • the second test block pattern 113 is disposed in the same layer as the gate layer.
  • the second test line pattern 123 is disposed in the same layer as the active layer. So set up, not only can test the gate layer and active in the display area The pattern size of the layer, and can test the degree of overlap between the gate layer and the active layer in the display region, thereby realizing timely and effective monitoring of the process of the gate layer and the active layer in the display region.
  • the multilayer pattern layer further includes a transparent electrode layer.
  • the test unit 1 further includes a third test component 40.
  • the third test component 40 includes a third test block pattern 111 and a third test line pattern 121.
  • the third test block pattern 111 is disposed in the same layer as the source/drain electrode layer, and the third test line
  • the pattern 121 is disposed in the same layer as the transparent electrode layer. In this way, not only the pattern size of the source/drain electrode layer and the transparent electrode layer in the display region can be tested, but also the degree of overlap between the source and drain electrode layers and the transparent electrode layer in the display region can be tested, thereby realizing the source in the display region. Timely and effective monitoring of the process of draining the electrode layer and the transparent electrode layer.
  • the transparent electrode layer may be a pixel electrode layer. It should be noted that the transparent electrode layer may also be a common electrode layer.
  • the multi-layer pattern layer further includes a dielectric layer.
  • the test unit 1 further includes a fourth test component 50.
  • the fourth test component 50 includes a fourth test block graphic 114 and a fourth test line graphic 124.
  • the fourth test block graphic 114 is disposed in the same layer as the gate layer, and the fourth test line graphic 124 is set in the same layer as the media layer. In this way, not only the pattern size of the gate layer and the dielectric layer in the display region can be tested, but also the degree of overlap between the gate layer and the dielectric layer in the display region can be tested, thereby realizing the gate layer and the medium in the display region. Timely and effective monitoring of the layer's process.
  • the orthographic projections of the plurality of test components 10 in the test unit 1 on the array substrate are spaced apart from each other and arranged in a row. That is, the orthographic projections of the first test component 20, the second test component 30, the third test component 40, and the fourth test component 50 on the array substrate are spaced apart from each other and arranged in a row.
  • integration settings for multiple test components 10 are achieved.
  • the test light is irradiated onto each of the test block patterns 11 and the respective test line patterns 12 by the optical test equipment, thereby detecting the obtained pattern size of each tested film layer in the display area and the measured film layer in the different layers.
  • the degree of overlap between each other saves test costs and improves the efficiency of the test.
  • the test transistor 13 includes a first test transistor 131 and a second test transistor 132.
  • the first test transistor 131 and the second test transistor 132 have different channel sizes, and the channel size includes any one of length, width, and aspect ratio.
  • the test unit 1 further includes a first gate connection line 14 connected to the gate of the first test transistor 131 and a second gate connection line 15 connected to the gate of the second test transistor 132.
  • the second test block pattern 113 is connected to one of the first gate connection line 14 and the second gate connection line 15, and the fourth test block pattern 114 and the other of the first gate connection line 14 and the second gate connection line 15 Connected.
  • the second test block pattern 113 is connected to the first gate connection line 14, and the fourth test block pattern 114 is connected to the second gate connection line 15.
  • the test unit 1 further includes a source connection line 16 connected to the sources of the first test transistor 131 and the second test transistor 132 and a drain connected to the first test transistor 131 and the second test transistor 132. Drain connection line 17.
  • the first test block pattern 112 is connected to one of the source connection line 16 and the drain connection line 17, and the third test block pattern 111 is connected to the other of the source connection line 16 and the drain connection line 17. In FIG. 1, the first test block pattern 112 is connected to the source connection line 16, and the third test block pattern 111 is connected to the drain connection line 17.
  • the first test transistor 131 and the second test transistor 132 can respectively test the characteristics of the transistor with the same channel size in the display area, thereby testing whether the process parameters of the transistor in the display area meet the requirements during the preparation process, thereby realizing the display area Timely and effective monitoring of the process of the internal transistor.
  • the transistor channel refers to the active layer region between the source region and the drain region under the action of an applied electric field.
  • the channel size is one of the parameters characterizing the performance of the transistor, including the length of the channel. , width, width to length ratio, etc.
  • the electrical test signals are respectively applied to the first test block pattern 112, the second test block pattern 113, and the fourth test block pattern 114 by the electrical test equipment, thereby providing the first test transistor 131 and the second test transistor 132.
  • the input gate test signal and the source test signal output a signal output from the third test block pattern 111 to the electrical test device, thereby performing electrical performance tests on the first test transistor 131 and the second test transistor 132.
  • the electrical test device can apply an electrical test signal to the test transistor 13 for testing without further moving the position during the test, thereby enabling the test unit 1 to achieve the light. Integration of testing and electrical testing, which in turn not only saves testing Test costs and improve test efficiency.
  • the active layers of the first test transistor 131 and the second test transistor 132 are disposed in the same layer as the active layer in the display region.
  • the gates of the first test transistor 131 and the second test transistor 132, the first gate connection line 14 and the second gate connection line 15 are disposed in the same layer as the gate layer in the display region.
  • the source, drain, source connection line 16 and drain connection line 17 of the first test transistor 131 and the second test transistor 132 are disposed in the same layer as the source and drain electrode layers in the display region.
  • the source/drain electrode layer is located above the gate layer, and the dielectric layer 400 is disposed between the source/drain electrode layer and the gate layer.
  • the first test line pattern 122 is located above the first test block pattern 112.
  • the source connection line 16 is disposed in the same layer as the first test line pattern 122, and the source connection line 16 is connected to the first test block pattern 112 through a via (not shown in FIG. 2) opened in the dielectric layer.
  • the thickness of the dielectric layer 400 is relatively thick, when the size of the block test pattern is large, the size of the linear test pattern is small, and the block test pattern is located below the dielectric layer 400, the light is irradiated. When the alignment accuracy between the test pattern and the line pattern is measured, the block test pattern located below the dielectric layer 400 is more easily seen, thereby making the alignment detection more accurate.
  • the embodiment further provides a method for preparing the array substrate, comprising forming a multi-layer pattern layer in the display area, and forming a test unit in the non-display area.
  • Forming the test unit includes forming at least one of the test component and the test transistor.
  • Forming the test component includes forming a test block pattern and a test line pattern, wherein one of the test block pattern and the multi-layer pattern layer is formed by one patterning process, and one of the test line pattern and the multi-layer pattern layer is formed by one patterning process, and The test block pattern and the test line pattern are formed in different layers.
  • the orthographic projection of the test line pattern on the array substrate surrounds the periphery of the orthographic projection of the test block pattern on the array substrate, and the orthographic projection of the test line pattern on the array substrate and the orthographic projection of the test block pattern on the array substrate are spaced apart from each other.
  • the test block pattern is connected to the test transistor.
  • the test block pattern can be formed of the same material as one of the layers of the multi-layer pattern layer and formed by one patterning process to simplify the process flow.
  • the test line pattern can be formed of the same material as another layer of the multi-layer pattern layer and formed by one patterning process to simplify the process flow.
  • the substrate 100 is cleaned, and the substrate 100 is made of a transparent material such as glass.
  • the buffer layer 101 and the amorphous silicon active layer film 102 are sequentially formed on the substrate 100 by plasma enhanced chemical vapor deposition as shown in FIG.
  • the buffer layer 101 is composed of a single layer or a composite layer formed of silicon oxide or silicon nitride, the thickness of the silicon oxide is in the range of 50 nm to 100 nm, and the thickness of the silicon nitride is in the range of 100 nm to 300 nm, and the thickness of the amorphous silicon film is The range is from 40 nanometers to 50 nanometers.
  • the substrate 100 is sent to a high-temperature furnace for treatment to achieve dehydrogenation (reducing the content of hydrogen in the amorphous silicon film), and the content of hydrogen is generally controlled to be within 2%.
  • the active layer is etched by etching, and then the photoresist on the active layer pattern and the photoresist on the second test line pattern 123 are stripped to form a first test transistor and a second test transistor.
  • the pattern of the active layer and the pattern of the second test line pattern 123 are as shown in FIGS. 2 and 5.
  • the gate insulating layer 200 is deposited by plasma enhanced chemical vapor deposition as shown in FIG.
  • the gate metal layer 300 is deposited by sputtering as shown in FIG. Forming a pattern 301 of the photoresist corresponding to the gates of the first test transistor and the second test transistor, a pattern of the photoresist corresponding to the first test block pattern 112, and a pattern corresponding to the second test block pattern 113 by exposure development a pattern of the photoresist, a pattern of the photoresist corresponding to the fourth test block pattern 114, and a pattern of the photoresist corresponding to the first gate connection line 14. (not shown) and a pattern (not shown) of the photoresist corresponding to the second gate connection line 15, as shown in FIGS. 2 and 8.
  • the gate metal layer is not etched by the photoresist, and the photoresist on the gate pattern is stripped to form a pattern of the gates of the first test transistor and the second test transistor.
  • a pattern of the first test block pattern 112 a pattern of the second test block pattern 113, a pattern of the fourth test block pattern 114, a pattern of the first gate connection line 14, and a pattern of the second gate connection line 15 (not shown) , as shown in Figure 2 and Figure 9.
  • the dielectric layer 400 is deposited by plasma enhanced chemical vapor deposition as shown in FIG. After the dielectric layer is formed, a pattern 401 of the photoresist corresponding to the via holes in the dielectric layer and a pattern of the photoresist corresponding to the fourth test line pattern 124 are formed by exposure development, as shown in FIGS. 2 and 11. Then, the dielectric layer 400 is not etched by the photoresist, and the photoresist corresponding to the vias in the dielectric layer 400 and the photoresist corresponding to the fourth test line pattern 124 are stripped. To form a pattern of vias and a fourth test line pattern 124, as shown in FIGS. 2 and 12.
  • the source and drain metal layer 500 is deposited by sputtering as shown in FIG. Further, a pattern 501 of the photoresist corresponding to the source and drain of the first test transistor and the second test transistor, a pattern of the photoresist corresponding to the first test line pattern 122, and a pattern corresponding to the source connection line 16 are formed by exposure and development. A pattern of photoresist (not shown) and a pattern of photoresist corresponding to the drain connection line 17 (not shown) are shown in FIGS. 2 and 14.
  • the source and drain metal layers are not etched by the photoresist, and the photoresist on the source and drain, the photoresist on the first test line pattern 122, and the source connection line 16 are etched.
  • the photoresist on the photoresist and the drain connection line 17 are stripped to form a pattern of source and drain of the first test transistor and the second test transistor, a pattern of the first test line pattern 122, and a source connection.
  • the pattern of line 16 and the pattern of drain connection line 17 are shown in FIG.
  • the passivation layer is deposited by plasma enhanced chemical vapor deposition. Then, a transparent electrode layer (ie, a pixel electrode layer) is deposited by sputtering, and a pattern of the photoresist corresponding to the third test line pattern 121 is formed by exposure and development, and the pixel electrode layer is not covered by the photoresist by etching. Area etching, and third test line pattern The photoresist on 121 is peeled off to form a third test line pattern 121 in the pixel electrode layer, as shown in FIG.
  • the third test block pattern 111, the first test line pattern 122, the source connection line 16, the drain connection line 17, and the source and drain of the first test transistor and the second test transistor in the non-display area The source and the drain of the transistor in the pole and the display region are made of the same material and simultaneously formed by one patterning process.
  • the source and drain of the transistor in the display area are made of the same material and arranged in the same layer.
  • the gate electrode and the gate layer in the display region are made of the same material and simultaneously formed by one patterning process.
  • the second test line pattern 123 in the non-display area and the active layers of the first test transistor and the second test transistor are formed of the same material as the active layers of the transistors in the display region and simultaneously formed by one patterning process.
  • the third test line pattern 121 in the non-display area is formed of the same material as the pixel electrode in the display area and simultaneously formed by one patterning process.
  • the fourth test line pattern 124 in the non-display area is formed of the same material as the dielectric layer in the display area and simultaneously formed by one patterning process.
  • test unit in this embodiment includes only one test component, which may be the first test component or the second test. Component, third test component, or fourth test component. Alternatively, the test component may also be other test components similar in setup to the first test component, the second test component, the third test component, or the fourth test component.
  • the test unit may include a test transistor or may not include a test transistor.
  • the gate, source and drain of the test transistor can be respectively connected to different test block patterns or test line patterns, and the test signals are input from the test block pattern or the test line pattern.
  • the gate, source and drain of the test transistor may also not be associated with the test block pattern or test line diagram The connection is made, and the test signal is directly input by the external test equipment.
  • the test unit may also include two, three or more test components, each of which is similar in setup manner to the first test in the above embodiment.
  • an array substrate by setting a test component and a test transistor, and orthographic projection of the test line pattern on the array substrate in the test component around the periphery of the orthographic projection of the test block pattern on the array substrate, Integration testing of the pattern size of the multi-layer pattern layers in the display area and the degree of overlap between the multi-layer pattern layers can be achieved.
  • the integration test of the transistor characteristics in the display area can be realized, so that it is not necessary to separately set more test elements for the test of the process performance of each pattern layer in the display area.
  • the space occupied by the test unit in the non-display area is saved, and the process test cost is reduced.
  • the integrated setting of the test component and the test transistor in the test unit when the test unit is tested by the test device, the test device can effectively test the performance of the array substrate without frequently moving the position, thereby improving the process test. Timeliness.
  • the embodiment of the invention further provides a display device comprising the array substrate in the above embodiment.
  • the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种阵列基板及其制备方法和显示装置。该阵列基板包括显示区内的多层图案层和非显示区内的测试单元（1），测试单元包括测试组件（10）和测试晶体管（13）中的至少一个。测试组件包括测试块图形（11）和测试线图形（12），测试块图形与多层图案层中的一层同层，测试线图形与多层图案层中的一层同层，且测试块图形和测试线图形设置在不同层中，测试线图形在阵列基板上的正投影围绕在测试块图形在阵列基板上的正投影的外围，测试块图形或者测试线图形连接至测试晶体管。该阵列基板能实现对显示区内多层图案层的图形尺寸以及多层图案层相互覆叠程度的整合测试，还能实现对显示区内晶体管特性的整合测试。

Description

阵列基板及其制备方法和显示装置 技术领域
本发明涉及显示技术领域，具体地涉及阵列基板及其制备方法和显示装置。
背景技术
随着人们对显示器的高分辨率的需求越来越高，高分辨率的显示产品对于工艺能力的要求也越来越高。因此，显示器制备过程中对于工艺能力检测的时效性要求也相对提高。
特别是针对类似于顶栅型结构的多晶硅显示器件而言，由于该显示器件在制备过程中的曝光次数较多，工艺较为复杂，如果不能够即时地检测出生产过程中工艺的不良，将造成产品的制作成本与时间上的极大浪费，这就需要在工艺进行中或工艺结束后对工艺的稳定性和精准性进行监测。
目前在对显示产品的制备过程中工艺的稳定性和精准性的监测中，通常通过在显示产品的非显示区制作测试单元、通过对测试单元中信号线线宽以及上下导电膜层之间的覆叠情况的测试，来监测显示区内各个膜层制备工艺的稳定性和精准性。同时，通过对测试单元中长沟道和短沟道的晶体管特性的测试，来监测显示区内晶体管的性能，从而能够通过测试单元的监测及时发现工艺过程中的不良，以减少制备成本上的浪费。
现有的测试单元是在非显示区内的不同层中分别设置的多个测试元件。这些测试元件中，用于测试信号线线宽、上下导电膜层之间的覆叠情况以及长沟道和短沟道的晶体管特性的测试元件各自独立设置，且测试元件在非显示区内的分布比较分散，这不仅使得测试元件在非显示区内的占用空间很大，不利于节约制备成本，而且在对不同的工艺参数进行测试时，需要对测试设 备(如光测试设备和电测试设备)进行频繁挪动，大大降低了测试效率，同时还增加了测试成本。
发明内容
针对现有技术中存在的上述技术问题，本公开提供阵列基板及其制备方法和显示装置。该阵列基板能够实现对显示区内多层图案层的图形尺寸以及多层图案层之间的相互覆叠程度的整合测试，还能够实现对显示区内晶体管特性的整合测试，从而不仅降低了工艺测试成本，而且提高了工艺测试时效。
本发明实施例提供一种阵列基板，包括设置在显示区内的多层图案层和设置在非显示区内的测试单元，所述测试单元包括至少一个测试组件和至少一个测试晶体管，所述测试组件包括测试块图形和测试线图形。所述测试块图形与所述多层图案层中的一层同层设置，所述测试线图形与所述多层图案层中的一层同层设置，且所述测试块图形和所述测试线图形设置在不同层中。所述测试线图形在所述阵列基板上的正投影围绕在所述测试块图形在所述阵列基板上的正投影的外围。所述测试块图形或者所述测试线图形连接至所述测试晶体管。
可选地，所述测试线图形在所述阵列基板上的正投影与所述测试块图形在所述阵列基板上的正投影相互间隔。
可选地，所述多层图案层包括源漏电极层、透明电极层、栅极层、有源层和介质层中的至少两层图案层，且所述至少两层图案层为不同层。
可选地，所述多层图案层包括所述源漏电极层、所述栅极层和所述有源层。
可选地，所述测试单元包括第一测试组件，所述第一测试组件包括第一测试块图形和第一测试线图形。所述第一测试块图形与所述栅极层同层设置，所述第一测试线图形与所述源漏电极层同层设置。
可选地，所述测试单元包括第二测试组件，所述第二测试组 件包括第二测试块图形和第二测试线图形。所述第二测试块图形与所述栅极层同层设置，所述第二测试线图形与所述有源层同层设置。
可选地，所述多层图案层还包括所述透明电极层，所述测试单元包括第三测试组件，所述第三测试组件包括第三测试块图形和第三测试线图形。所述第三测试块图形与所述源漏电极层同层设置，所述第三测试线图形与所述透明电极层同层设置。
可选地，所述多层图案层还包括所述介质层，所述测试单元包括第四测试组件，所述第四测试组件包括第四测试块图形和第四测试线图形。所述第四测试块图形与所述栅极层同层设置，所述第四测试线图形与所述介质层同层设置。
可选地，所述测试单元中的所述测试组件在所述阵列基板上的正投影相互间隔并排成一排。
可选地，所述测试晶体管包括第一测试晶体管和第二测试晶体管，所述第一测试晶体管和所述第二测试晶体管的源极和漏极之间的沟道尺寸不同，所述沟道尺寸包括长度、宽度、宽长比中任意一种。
可选地，所述测试单元还包括与所述第一测试晶体管的栅极连接的第一栅连接线和与所述第二测试晶体管的栅极连接的第二栅连接线。两个所述测试组件中的所述测试块图形或者所述测试线图形分别与所述第一栅连接线以及所述第二栅连接线连接。
可选地，所述第二测试块图形与所述第一栅连接线和所述第二栅连接线中的一者连接，所述第四测试块图形与所述第一栅连接线和所述第二栅连接线中的另一者连接。
可选地，所述测试单元还包括与所述第一测试晶体管和所述第二测试晶体管的源极连接的源极连接线和与所述第一测试晶体管和所述第二测试晶体管的漏极连接的漏极连接线。所述第一测试块图形与所述源极连接线和漏极连接线中的一者连接，所述第三测试块图形与所述源极连接线和漏极连接线中的另一者连接。
可选地，所述第一测试晶体管和所述第二测试晶体管的有源层与所述显示区内的所述有源层同层设置。
可选地，所述第一测试晶体管和所述第二测试晶体管的栅极、所述第一栅连接线和所述第二栅连接线与所述显示区内的所述栅极层同层设置。
可选地，所述第一测试晶体管和所述第二测试晶体管的源极、漏极、所述源极连接线和所述漏极连接线与所述显示区内的所述源漏电极层同层设置。
本发明实施例还提供一种显示装置，包括上述阵列基板。
本发明还提供一种制备上述阵列基板的方法，包括在显示区内形成多层图案层，以及在非显示区内形成测试单元。形成所述测试单元包括形成至少一个测试组件和至少一个测试晶体管，形成所述测试组件包括形成测试块图形和测试线图形。所述测试块图形与所述多层图案层中的一层通过一次构图工艺形成，所述测试线图形与所述多层图案层中的一层通过一次构图工艺形成，且所述测试块图形和所述测试线图形设置在不同层中。所述测试线图形在所述阵列基板上的正投影围绕在所述测试块图形在所述阵列基板上的正投影的外围。所述测试块图形或者所述测试线图形连接至所述测试晶体管。
可选地，所述测试线图形在所述阵列基板上的正投影与所述测试块图形在所述阵列基板上的正投影相互间隔。
在根据本发明实施例的阵列基板中，通过设置测试组件和测试晶体管，并使测试组件中的测试线图形在阵列基板上的正投影围绕在测试块图形在阵列基板上的正投影的外围，能够实现对显示区内多层图案层的图形尺寸以及多层图案层之间的相互覆叠程度的整合测试。同时，通过使测试晶体管连接至测试块图形或者测试线图形，能够实现对显示区内晶体管特性的整合测试，从而针对显示区内各图案层工艺性能的测试无需再独立设置更多的测试元件，进而节约了测试单元在非显示区内的占用空间，并降低了工艺测试成本。同时，对测试单元中测试组件和测试晶体 管的整合设置，针对测试单元在通过测试设备进行测试时，测试设备无需再频繁挪动位置就能对阵列基板的各项性能进行有效测试，从而提高了工艺测试的时效性。
根据本发明实施例的显示装置采用上述阵列基板，从而不仅降低了该显示装置的工艺能力测试成本，而且提高了该显示装置的工艺能力测试时效。
附图说明
图1为根据本发明实施例的阵列基板上的测试单元的结构俯视图。
图2为图1中的阵列基板沿BB剖切线的结构剖视图。
图3为在形成缓冲层与有源层之后的阵列基板沿AA剖切线的结构剖视图。
图4为在对光刻胶进行曝光显影之后的阵列基板沿AA剖切线的结构剖视图。
图5为完成有源层刻蚀与光刻胶剥离之后的阵列基板沿AA剖切线的结构剖视图。
图6为在形成栅绝缘层之后的阵列基板沿AA剖切线的结构剖视图。
图7为在形成栅极金属层之后的阵列基板沿AA剖切线的结构剖视图。
图8为在对光刻胶进行曝光显影之后的阵列基板沿AA剖切线的结构剖视图。
图9为完成栅极金属层刻蚀与光刻胶剥离之后的阵列基板沿AA剖切线的结构剖视图。
图10为在形成介质层之后的阵列基板沿AA剖切线的结构剖视图。
图11为在对光刻胶进行曝光显影之后的阵列基板沿AA剖切线的结构剖视图。
图12为完成介质层和栅绝缘层刻蚀与光刻胶剥离之后的阵 列基板沿AA剖切线的结构剖视图。
图13为在形成源漏极金属层之后的阵列基板沿AA剖切线的结构剖视图。
图14为在对光刻胶进行曝光显影之后的阵列基板沿AA剖切线的结构剖视图。
图15为完成源漏极金属层刻蚀与光刻胶剥离之后的阵列基板沿AA剖切线的结构剖视图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明所提供的阵列基板及其制备方法和显示装置作进一步详细描述。
如图1和图2所示，本发明的一个实施例提供一种阵列基板，其包括设置在显示区内的多层图案层和设置在非显示区内的测试单元1。测试单元1包括至少一个测试组件10和至少一个测试晶体管13。测试组件10包括测试块图形11和测试线图形12。测试块图形11与多层图案层中的一层同层设置，测试线图形12与多层图案层中的一层同层设置，且测试块图形11和测试线图形12设置在不同层中。测试线图形12在阵列基板上的正投影围绕在测试块图形11在阵列基板上的正投影的外围。测试块图形11连接至测试晶体管13。
本实施例中，测试线图形12在阵列基板上的正投影与测试块图形11在阵列基板上的正投影相互间隔。即，测试线图形12在阵列基板上的正投影与测试块图形11在阵列基板上的正投影完全间隔开，从而能够确保测试线图形12与测试块图形11对相互覆叠情况的检测的精确性。需要说明的是，只要确保测试线图形12上的至少部分图形在阵列基板上的正投影与测试块图形11在阵列基板上的正投影相互间隔设置即可。
测试线图形12在阵列基板上的正投影围绕在测试块图形11在阵列基板上的正投影外围，需要说明的是，测试块图形可以是 矩形块状图形、多边形块状图形、圆形块状图形等，本实施例以矩形块状图形为例进行说明。测试线图形12的正投影能够以任意形状围绕在测试块图形11的正投影外围。例如，测试线图形12可以设置为连续的围绕图形，也可以设置为不连续的围绕图形。
需要说明的是，本实施例中，测试线图形12也可以设置为连接至测试晶体管13。无论是测试块图形11还是测试线图形12连接至测试晶体管13，都是为了给测试晶体管13提供相应的栅、源漏测试信号。由于测试线图形12的面积相对于测试块图形11的面积较小，测试时测试信号较难引入。因此，通常情况下，通过测试块图形11将测试信号引入至测试晶体管13，即，通常将测试块图形11设置为连接至测试晶体管13。
本实施例中，测试组件10中测试线图形12和测试块图形11的设置能够分别测试显示区内多层图案层的图形尺寸是否满足设计和工艺要求。测试线图形12与测试块图形11在阵列基板上的正投影之间的间隔距离能够测试设置在显示区内不同层上的多层图案层之间的相互覆叠程度是否满足设计和工艺要求。多层图案层的图形尺寸以及多层图案层之间的相互覆叠程度通过光学测试设备进行光学测试后获得。测试晶体管13的设置能够测试显示区内用于控制显示的晶体管的特性是否满足设计和工艺要求。显示区内晶体管特性的测试通过电测试设备进行电测试获得。通过测试单元1的设置，能够检测显示区内的各图案层的工艺水平，及时发现制备工艺过程中出现的不良，并对不良进行及时改善，从而大大减少了阵列基板在制备过程中的成本浪费，确保了阵列基板各膜层在制备过程中工艺的稳定性和精确性，进而确保了阵列基板中各膜层的工艺质量。
本实施例中的测试单元1中，通过使测试线图形12在阵列基板上的正投影围绕在测试块图形11在阵列基板上的正投影的外围，并使测试线图形12在阵列基板上的正投影与测试块图形11在阵列基板上的正投影相互间隔，能够实现对显示区内多层 图案层的图形尺寸以及多层图案层之间的相互覆叠程度的整合测试，即，通过对测试块图形11和测试线图形12的上述整合设置，能够实现对显示区内各个图案层的图形尺寸以及各个图案层之间的相互覆叠程度的工艺参数测试。同时，通过使测试晶体管13连接至测试块图形11，能够实现对显示区内晶体管特性的整合测试，即，通过对测试块图形11和测试晶体管13的上述整合设置，能够实现对显示区内晶体管特性的工艺参数测试，从而针对显示区内各图案层的工艺性能的测试无需再独立设置更多的测试元件，进而节约了测试单元1在非显示区内的占用空间，并降低了测试成本。同时，对测试单元1中测试块图形11、测试线图形12和测试晶体管13的整合设置，在针对测试单元1通过测试设备进行测试时，测试设备无需再频繁挪动位置就能对阵列基板的各项性能进行有效测试，从而提高了测试的时效性。
多层图案层包括源漏电极层、透明电极层、栅极层、有源层和介质层中的至少两层图案层，且至少两层图案层设置在不同层中。本实施例中，多层图案层包括源漏电极层(其与稍后描述的源漏金属层500位于同一层中)、栅极层(其与稍后描述的栅极金属层300位于同一层中)和有源层(其与稍后描述的有源层薄膜102位于同一层中)。
本实施例中，测试单元1包括第一测试组件20，第一测试组件20包括第一测试块图形112和第一测试线图形122，第一测试块图形112与栅极层同层设置，第一测试线图形122与源漏电极层同层设置。如此设置，不仅能够测试显示区内栅极层和源漏电极层的图形尺寸，而且能够测试显示区内栅极层和源漏电极层之间的相互覆叠程度，从而实现对显示区内栅极层和源漏电极层的工艺过程的及时有效监测。
本实施例中，测试单元1还包括第二测试组件30，第二测试组件30包括第二测试块图形113和第二测试线图形123，第二测试块图形113与栅极层同层设置，第二测试线图形123与有源层同层设置。如此设置，不仅能够测试显示区内栅极层和有源 层的图形尺寸，而且能够测试显示区内栅极层和有源层之间的相互覆叠程度，从而实现对显示区内栅极层和有源层的工艺过程的及时有效监测。
本实施例中，多层图案层还包括透明电极层。测试单元1还包括第三测试组件40，第三测试组件40包括第三测试块图形111和第三测试线图形121，第三测试块图形111与源漏电极层同层设置，第三测试线图形121与透明电极层同层设置。如此设置，不仅能够测试显示区内源漏电极层和透明电极层的图形尺寸，而且能够测试显示区内源漏电极层与透明电极层之间的相互覆叠程度，从而实现对显示区内源漏电极层和透明电极层的工艺过程的及时有效监测。透明电极层可以为像素电极层。需要说明的是，透明电极层也可以为公共电极层。
本实施例中，多层图案层还包括介质层。测试单元1还包括第四测试组件50，第四测试组件50包括第四测试块图形114和第四测试线图形124，第四测试块图形114与栅极层同层设置，第四测试线图形124与介质层同层设置。如此设置，不仅能够测试显示区内栅极层和介质层的图形尺寸，而且能够测试显示区内栅极层和介质层之间的相互覆叠程度，从而实现对显示区内栅极层和介质层的工艺过程的及时有效监测。
本实施例中，测试单元1中的多个测试组件10在阵列基板上的正投影相互间隔并排成一排。即，第一测试组件20、第二测试组件30、第三测试组件40和第四测试组件50在阵列基板上的正投影相互间隔并排成一排。如此设置，实现了对多个测试组件10的整合设置。在进行测试时，通过光学测试设备将测试光线照射到各个测试块图形11和各个测试线图形12上，从而检测获得显示区内各被测试膜层的图形尺寸和不同层中被测膜层之间的相互覆叠程度，节约了测试成本并提高了测试的效率。
本实施例中，测试晶体管13包括第一测试晶体管131和第二测试晶体管132。第一测试晶体管131和第二测试晶体管132的沟道尺寸不同，沟道尺寸包括长度、宽度、宽长比中任意一种。 测试单元1还包括与第一测试晶体管131的栅极连接的第一栅连接线14和与第二测试晶体管132的栅极连接的第二栅连接线15。第二测试块图形113与第一栅连接线14和第二栅连接线15中的一者连接，第四测试块图形114与第一栅连接线14和第二栅连接线15中的另一者连接。在图1中，第二测试块图形113与第一栅连接线14连接，第四测试块图形114与第二栅连接线15连接。
本实施例中，测试单元1还包括连接至第一测试晶体管131和第二测试晶体管132的源极的源极连接线16和连接至第一测试晶体管131和第二测试晶体管132的漏极的漏极连接线17。第一测试块图形112与源极连接线16和漏极连接线17中的一者连接，第三测试块图形111与源极连接线16和漏极连接线17中的另一者连接。在图1中，第一测试块图形112与源极连接线16连接，第三测试块图形111与漏极连接线17连接。
第一测试晶体管131和第二测试晶体管132能够分别测试显示区内与其沟道尺寸相同的晶体管的特性，从而测试显示区内的晶体管在制备过程中的工艺参数是否满足要求，进而实现对显示区内晶体管的工艺过程的及时有效监测。
需要说明的是，晶体管沟道是指在外加电场的作用下，在源极区以及漏极区之间的有源层区域，沟道尺寸是表征晶体管性能的参数之一，包括沟道的长度、宽度、宽长比等。
测试中，通过电测试设备将电测试信号分别施加到第一测试块图形112、第二测试块图形113和第四测试块图形114上，从而给第一测试晶体管131和第二测试晶体管132提供输入的栅极测试信号和源极测试信号，将从第三测试块图形111上输出的信号输出至电测试设备，从而实现对第一测试晶体管131和第二测试晶体管132的电性能测试。通过对测试块图形11和测试晶体管13的整合设置，在进行测试时电测试设备无需再频繁挪动位置就能对测试晶体管13施加电测试信号以进行测试，从而使该测试单元1实现了对光测试和电测试的整合，进而不仅节约了测 试成本，而且提高了测试效率。
本实施例中，第一测试晶体管131和第二测试晶体管132的有源层与显示区内的有源层同层设置。第一测试晶体管131和第二测试晶体管132的栅极、第一栅连接线14和第二栅连接线15与显示区内的栅极层同层设置。第一测试晶体管131和第二测试晶体管132的源极、漏极、源极连接线16和漏极连接线17与显示区内的源漏电极层同层设置。如此设置，能够在不增加制备工艺步骤的情况下，在显示区内形成晶体管的同时，在非显示区内形成测试晶体管13，从而降低了测试单元1的制备成本。
需要说明的是，本实施例中，源漏电极层位于栅极层的上方，源漏电极层与栅极层之间设置有介质层400。相应地，如图2所示，第一测试线图形122位于第一测试块图形112的上方。源极连接线16与第一测试线图形122同层设置，源极连接线16通过开设在介质层中的过孔(图2中未示出)与第一测试块图形112连接。本实施例中，对于介质层400厚度较厚的情况，当块状测试图形的尺寸较大、线状测试图形的尺寸较小、块状测试图形位于介质层400下方时，在采用光线照射块状测试图形与线状图形之间的对位精度时，位于介质层400下方的块状测试图形更容易被看清楚，从而使对位检测更加准确。
基于本实施例中阵列基板的上述结构，本实施例还提供一种制备该阵列基板的方法，包括在显示区内形成多层图案层，以及在非显示区内形成测试单元。形成测试单元包括形成测试组件和测试晶体管中的至少一个。形成测试组件包括形成测试块图形和测试线图形，测试块图形与多层图案层中的一层通过一次构图工艺形成，测试线图形与多层图案层中的一层通过一次构图工艺形成，且测试块图形和测试线图形形成在不同层中。测试线图形在阵列基板上的正投影围绕在测试块图形在阵列基板上的正投影的外围，且测试线图形在阵列基板上的正投影与测试块图形在阵列基板上的正投影相互间隔。测试块图形连接至测试晶体管。例 如，测试块图形可以与多层图案层中的一层采用相同材料并通过一次构图工艺形成，以简化工艺流程。例如，测试线图形可以与多层图案层中的另一层采用相同材料并通过一次构图工艺形成，以简化工艺流程。
下文中，参照图2至图15，以顶栅型的多晶硅阵列基板为例说明阵列基板非显示区内测试单元的具体制备步骤。
对基板100进行清洗处理，基板100由玻璃等透明材料构成。利用等离子体增强化学气相沉积法在基板100上依次形成缓冲层101和非晶硅有源层薄膜102，如图3所示。缓冲层101由氧化硅、氮化硅形成的单一层或复合层组成，氧化硅的厚度范围为50纳米至100纳米，氮化硅的厚度范围为100纳米至300纳米，非晶硅薄膜的厚度范围为40纳米至50纳米。接着，将基板100送入高温炉中进行处理，以达到脱氢(减少非晶硅薄膜中氢的含量)的目的，一般将氢的含量控制在2％以内。
对完成上述步骤的基板进行准分子激光退火(ELA)处理，使非晶硅有源层薄膜102转变为多晶硅有源层薄膜102，再通过曝光显影形成与第一测试晶体管和第二测试晶体管的有源层对应的光刻胶的图形103和与第二测试线图形123对应的光刻胶的图形，如图2和图4所示。
利用刻蚀的方法来刻蚀有源层，然后将有源层图形上的光刻胶和第二测试线图形123上的光刻胶进行剥离，以形成第一测试晶体管和第二测试晶体管的有源层的图形和第二测试线图形123的图形，如图2和图5所示。
利用等离子体增强化学气相沉积法沉积栅绝缘层200，如图6所示。
利用溅射沉积栅极金属层300，如图7所示。通过曝光显影形成与第一测试晶体管和第二测试晶体管的栅极对应的光刻胶的图形301、与第一测试块图形112对应的光刻胶的图形、与第二测试块图形113对应的光刻胶的图形、与第四测试块图形114对应的光刻胶的图形、与第一栅连接线14对应的光刻胶的图形 (未示出)和与第二栅连接线15对应的光刻胶的图形(未示出)，如图2和图8所示。然后，利用蚀刻的方式对栅极金属层未被光刻胶覆盖区域进行蚀刻，以及将栅极图形上的光刻胶进行剥离，以形成第一测试晶体管和第二测试晶体管的栅极的图形、第一测试块图形112的图形、第二测试块图形113的图形、第四测试块图形114的图形、第一栅连接线14的图形和第二栅连接线15的图形(未示出)，如图2和图9所示。
利用等离子体增强化学气相沉积法沉积介质层400，如图10所示。在形成介质层之后，通过曝光显影形成与介质层中的过孔对应的光刻胶的图形401和与第四测试线图形124对应的光刻胶的图形，如图2和图11所示。然后，利用蚀刻的方式对介质层400未被光刻胶覆盖区域进行蚀刻，以及将与介质层400中的过孔对应的光刻胶和与第四测试线图形124对应的光刻胶进行剥离，以形成过孔的图形和第四测试线图形124，如图2和图12所示。
利用溅射沉积源漏极金属层500，如图13所示。再通过曝光显影形成与第一测试晶体管和第二测试晶体管的源漏极对应的光刻胶的图形501、与第一测试线图形122对应的光刻胶的图形、与源极连接线16对应的光刻胶的图形(未示出)和与漏极连接线17对应的光刻胶的图形(未示出)，如图2和图14所示。
利用刻蚀的方法对源漏极金属层未被光刻胶覆盖区域进行刻蚀，以及将源漏极上的光刻胶、第一测试线图形122上的光刻胶、源极连接线16上的光刻胶和漏极连接线17上的光刻胶进行剥离，以形成第一测试晶体管和第二测试晶体管源极和漏极的图形、第一测试线图形122的图形、源极连接线16的图形和漏极连接线17的图形，如图15所示。
利用等离子体增强化学气相沉积法沉积钝化层。接着，利用溅射沉积透明电极层(即，像素电极层)，通过曝光显影形成与第三测试线图形121对应的光刻胶的图形，利用蚀刻的方式对像素电极层未被光刻胶覆盖区域进行蚀刻，以及将第三测试线图形 121上的光刻胶进行剥离，以在像素电极层中形成第三测试线图形121，如图2所示。
本实施例中，非显示区内的第三测试块图形111、第一测试线图形122、源极连接线16、漏极连接线17以及第一测试晶体管和第二测试晶体管的源极和漏极与显示区内的晶体管的源极和漏极采用相同材料并通过一次构图工艺同时形成。显示区内的晶体管的源极和漏极采用相同材料并同层设置。非显示区内的第一测试块图形112、第二测试块图形113、第四测试块图形114、第一栅连接线14、第二栅连接线15以及第一测试晶体管和第二测试晶体管的栅极与显示区内的栅极层采用相同材料并通过一次构图工艺同时形成。非显示区内的第二测试线图形123以及第一测试晶体管和第二测试晶体管的有源层与显示区内的晶体管的有源层采用相同材料并通过一次构图工艺同时形成。非显示区内的第三测试线图形121与显示区内的像素电极采用相同材料并通过一次构图工艺同时形成。非显示区内的第四测试线图形124与显示区内的介质层采用相同材料并通过一次构图工艺同时形成。通过如此设置，能够在不增加阵列基板制备工艺步骤的情况下，在显示区内制备形成各个膜层的同时，在非显示区内制备形成测试单元，从而节约了阵列基板的制备成本。
本发明的另一实施例提供一种阵列基板，与上述实施例不同的是，本实施例中的测试单元只包括一个测试组件，该测试组件可以是第一测试组件，也可以是第二测试组件、第三测试组件或第四测试组件。可替代地，该测试组件还可以是在设置方式上类似于第一测试组件、第二测试组件、第三测试组件或第四测试组件的其他的测试组件。
本实施例中，测试单元可以包括测试晶体管，也可以不包括测试晶体管。在测试单元包括测试晶体管的情况下，测试晶体管的栅极、源极和漏极可以分别与不同的测试块图形或测试线图形连接，由测试块图形或测试线图形输入测试信号。可替代地，测试晶体管的栅极、源极和漏极也可以不与测试块图形或测试线图 形连接，而直接由外部测试设备输入测试信号。
需要说明的是，在本发明其他实施例中，测试单元也可以包括两个、三个或五个以上的测试组件，每个测试组件在设置方式上均类似于上述实施例中的第一测试组件、第二测试组件、第三测试组件或第四测试组件。
通过不同的测试组件，能够测试设置在显示区内的任意两个不同层中的图案层的图形尺寸以及相互覆叠情况，从而实现对显示区内多个图案层的图形尺寸和相互覆叠情况的整合测试。
在根据本发明实施例的阵列基板中，通过设置测试组件和测试晶体管，并使测试组件中的测试线图形在阵列基板上的正投影围绕在测试块图形在阵列基板上的正投影的外围，能够实现对显示区内多层图案层的图形尺寸以及多层图案层之间的相互覆叠程度的整合测试。同时，通过使测试晶体管连接至测试块图形或者测试线图形，能够实现对显示区内晶体管特性的整合测试，从而针对显示区内各图案层工艺性能的测试无需再独立设置更多的测试元件，进而节约了测试单元在非显示区内的占用空间，并降低了工艺测试成本。同时，对测试单元中测试组件和测试晶体管的整合设置，针对测试单元通过测试设备进行测试时，测试设备无需再频繁挪动位置就能对阵列基板的各项性能进行有效测试，从而提高了工艺测试的时效性。
本发明实施例还提供一种显示装置，包括上述实施例中的阵列基板。
通过采用根据本发明实施例的阵列基板，不仅降低了该显示装置的工艺能力测试成本，而且提高了该显示装置的工艺能力测试时效。
该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况 下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (19)

  1. 一种阵列基板，包括设置在显示区内的多层图案层和设置在非显示区内的测试单元，其中
    所述测试单元包括至少一个测试组件和至少一个测试晶体管，所述测试组件包括测试块图形和测试线图形；
    所述测试块图形与所述多层图案层中的一层同层设置，所述测试线图形与所述多层图案层中的一层同层设置，且所述测试块图形和所述测试线图形设置在不同层中；
    所述测试线图形在所述阵列基板上的正投影围绕在所述测试块图形在所述阵列基板上的正投影的外围；以及
    所述测试块图形或者所述测试线图形连接至所述测试晶体管。
  2. 根据权利要求1所述的阵列基板，其中，所述测试线图形在所述阵列基板上的正投影与所述测试块图形在所述阵列基板上的正投影相互间隔。
  3. 根据权利要求1或2所述的阵列基板，其中，所述多层图案层包括源漏电极层、透明电极层、栅极层、有源层和介质层中的至少两层图案层，且所述至少两层图案层为不同层。
  4. 根据权利要求3所述的阵列基板，其中，所述多层图案层包括所述源漏电极层、所述栅极层和所述有源层。
  5. 根据权利要求4所述的阵列基板，其中，所述测试单元包括第一测试组件，所述第一测试组件包括第一测试块图形和第一测试线图形，
    所述第一测试块图形与所述栅极层同层设置，所述第一测试线图形与所述源漏电极层同层设置。
  6. 根据权利要求4所述的阵列基板，其中，所述测试单元包括第二测试组件，所述第二测试组件包括第二测试块图形和第二测试线图形，
    所述第二测试块图形与所述栅极层同层设置，所述第二测试线图形与所述有源层同层设置。
  7. 根据权利要求4所述的阵列基板，其中，所述多层图案层还包括所述透明电极层，所述测试单元包括第三测试组件，所述第三测试组件包括第三测试块图形和第三测试线图形，
    所述第三测试块图形与所述源漏电极层同层设置，所述第三测试线图形与所述透明电极层同层设置。
  8. 根据权利要求5所述的阵列基板，其中，所述多层图案层还包括所述透明电极层，所述测试单元还包括第三测试组件，所述第三测试组件包括第三测试块图形和第三测试线图形，
    所述第三测试块图形与所述源漏电极层同层设置，所述第三测试线图形与所述透明电极层同层设置。
  9. 根据权利要求4所述的阵列基板，其中，所述多层图案层还包括所述介质层，所述测试单元包括第四测试组件，所述第四测试组件包括第四测试块图形和第四测试线图形，
    所述第四测试块图形与所述栅极层同层设置，所述第四测试线图形与所述介质层同层设置。
  10. 根据权利要求6所述的阵列基板，其中，所述多层图案层还包括所述介质层，所述测试单元还包括第四测试组件，所述第四测试组件包括第四测试块图形和第四测试线图形，
    所述第四测试块图形与所述栅极层同层设置，所述第四测试线图形与所述介质层同层设置。
  11. 根据权利要求1所述的阵列基板，其中，所述测试单元中的所述测试组件在所述阵列基板上的正投影相互间隔并排成一排。
  12. 根据权利要求1或2所述的阵列基板，其中，所述测试单元包括两个所述测试组件，所述测试晶体管包括第一测试晶体管和第二测试晶体管，所述第一测试晶体管和所述第二测试晶体管的沟道尺寸不同，所述沟道尺寸包括长度、宽度、宽长比中任意一种；
    所述测试单元还包括与所述第一测试晶体管的栅极连接的第一栅连接线和与所述第二测试晶体管的栅极连接的第二栅连接线；
    两个所述测试组件中的所述测试块图形或者所述测试线图形分别与所述第一栅连接线以及所述第二栅连接线连接。
  13. 根据权利要求10所述的阵列基板，其中，所述测试晶体管包括第一测试晶体管和第二测试晶体管，所述第一测试晶体管和所述第二测试晶体管的沟道尺寸不同，所述沟道尺寸包括长度、宽度、宽长比中任意一种；
    所述测试单元还包括与所述第一测试晶体管的栅极连接的第一栅连接线和与所述第二测试晶体管的栅极连接的第二栅连接线；
    所述第二测试块图形与所述第一栅连接线和所述第二栅连接线中的一者连接，所述第四测试块图形与所述第一栅连接线和所述第二栅连接线中的另一者连接。
  14. 根据权利要求8所述的阵列基板，其中，所述测试晶体管包括第一测试晶体管和第二测试晶体管，所述第一测试晶体管和所述第二测试晶体管的沟道尺寸不同，所述沟道尺寸包括长 度、宽度、宽长比中任意一种；
    所述测试单元还包括与所述第一测试晶体管和所述第二测试晶体管的源极连接的源极连接线和与所述第一测试晶体管和所述第二测试晶体管的漏极连接的漏极连接线；
    所述第一测试块图形与所述源极连接线和漏极连接线中的一者连接，所述第三测试块图形与所述源极连接线和漏极连接线中的另一者连接。
  15. 根据权利要求13所述的阵列基板，其中，所述第一测试晶体管和所述第二测试晶体管的有源层与所述显示区内的所述有源层同层设置；
    所述第一测试晶体管和所述第二测试晶体管的栅极、所述第一栅连接线和所述第二栅连接线与所述显示区内的所述栅极层同层设置。
  16. 根据权利要求14所述的阵列基板，其中，所述第一测试晶体管和所述第二测试晶体管的有源层与所述显示区内的所述有源层同层设置；
    所述第一测试晶体管和所述第二测试晶体管的源极、漏极、所述源极连接线和所述漏极连接线与所述显示区内的所述源漏电极层同层设置。
  17. 一种显示装置，包括权利要求1至16中任意一项所述的阵列基板。
  18. 一种制备权利要求1至16中任意一项所述的阵列基板的方法，包括在显示区内形成多层图案层，以及在非显示区内形成测试单元，其中
    形成所述测试单元包括形成至少一个测试组件和至少一个测试晶体管，形成所述测试组件包括形成测试块图形和测试线图 形；
    所述测试块图形与所述多层图案层中的一层通过一次构图工艺形成，所述测试线图形与所述多层图案层中的一层通过一次构图工艺形成，且所述测试块图形和所述测试线图形形成在不同层中；
    所述测试线图形在所述阵列基板上的正投影围绕在所述测试块图形在所述阵列基板上的正投影的外围；
    所述测试块图形或者所述测试线图形连接至所述测试晶体管。
  19. 根据权利要求18所述的阵列基板的制备方法，其中，所述测试线图形在所述阵列基板上的正投影与所述测试块图形在所述阵列基板上的正投影相互间隔。
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