WO2016021320A1 - アクティブマトリクス基板およびその製造方法 - Google Patents
アクティブマトリクス基板およびその製造方法 Download PDFInfo
- Publication number
- WO2016021320A1 WO2016021320A1 PCT/JP2015/068178 JP2015068178W WO2016021320A1 WO 2016021320 A1 WO2016021320 A1 WO 2016021320A1 JP 2015068178 W JP2015068178 W JP 2015068178W WO 2016021320 A1 WO2016021320 A1 WO 2016021320A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- film
- insulating film
- semiconductor
- active matrix
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 129
- 239000011159 matrix material Substances 0.000 title claims abstract description 96
- 238000004519 manufacturing process Methods 0.000 title claims description 33
- 239000004020 conductor Substances 0.000 claims abstract description 101
- 230000001681 protective effect Effects 0.000 claims abstract description 64
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 39
- 239000000463 material Substances 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 24
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract description 18
- 239000011733 molybdenum Substances 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims description 139
- 238000000034 method Methods 0.000 claims description 52
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- 238000000059 patterning Methods 0.000 claims description 9
- 229910001182 Mo alloy Inorganic materials 0.000 claims description 8
- 229910001257 Nb alloy Inorganic materials 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 8
- 239000010955 niobium Substances 0.000 claims description 8
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 59
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 39
- 238000009413 insulation Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 282
- 239000010410 layer Substances 0.000 description 228
- 229910004205 SiNX Inorganic materials 0.000 description 57
- 230000005684 electric field Effects 0.000 description 13
- 238000000206 photolithography Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 239000010936 titanium Substances 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- DTSBBUTWIOVIBV-UHFFFAOYSA-N molybdenum niobium Chemical compound [Nb].[Mo] DTSBBUTWIOVIBV-UHFFFAOYSA-N 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133345—Insulating layers
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13454—Drivers integrated on the active matrix substrate
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/13629—Multilayer wirings
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
- G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
- G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/40—Arrangements for improving the aperture ratio
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2202/00—Materials and properties
- G02F2202/10—Materials and properties semiconductor
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2202/00—Materials and properties
- G02F2202/10—Materials and properties semiconductor
- G02F2202/103—Materials and properties semiconductor a-Si
Definitions
- the present invention relates to a display device, and more particularly, to an active matrix substrate having a common electrode and a manufacturing method thereof.
- a liquid crystal panel included in a liquid crystal display device has a structure in which an active matrix substrate and a counter substrate are bonded to each other, and a liquid crystal layer is provided between two substrates.
- a plurality of gate lines, a plurality of data lines, a plurality of pixel circuits including thin film transistors (hereinafter referred to as TFTs) and pixel electrodes are formed.
- a vertical electric field method and a horizontal electric field method are known as methods for applying an electric field to a liquid crystal layer of a liquid crystal panel.
- a substantially vertical electric field is applied to a liquid crystal layer using a pixel electrode and a common electrode formed on a counter substrate.
- a horizontal electric field type liquid crystal panel a common electrode is formed on an active matrix substrate together with a pixel electrode, and a substantially horizontal electric field is applied to the liquid crystal layer using the pixel electrode and the common electrode.
- a horizontal electric field type liquid crystal panel has an advantage that a viewing angle is wider than that of a vertical electric field type liquid crystal panel.
- an IPS (In-Plane Switching) mode and an FFS (Fringe Field Switching) mode are known.
- the pixel electrode and the common electrode are each formed in a comb-like shape and are arranged so as not to overlap in a plan view.
- a slit is formed in one of the common electrode and the pixel electrode, and the pixel electrode and the common electrode are disposed so as to overlap with each other through a protective insulating film in plan view.
- the FFS mode liquid crystal panel has an advantage that the aperture ratio is higher than that of the IPS mode liquid crystal panel.
- Patent Document 1 describes a method for manufacturing an active matrix substrate using five photomasks.
- the semiconductor layer is patterned using the source layer photomask without using the semiconductor layer photomask, and the TFT of the TFT is formed using the pixel electrode layer photomask. A channel region is formed.
- the data lines are stacked wirings formed in the semiconductor layer, the ohmic contact layer, the source layer, and the pixel electrode layer. The portions formed in the semiconductor layer, the ohmic contact layer, and the source layer of the data line have the same shape, and the portion formed in the pixel electrode layer is formed so as to cover the portion formed in the three layers.
- the pixel electrode and the common electrode face each other with a protective insulating film interposed therebetween.
- the capacitance storage capacitance
- the protective insulating film serving as an interlayer film between the pixel electrode and the common electrode is thin.
- particles and generated foreign matter may break through the protective insulating film. For this reason, a point defect caused by a leak between the pixel electrode and the common electrode or a linear defect caused by a leak between the data line and the common electrode occurs, which causes a problem that the yield of the active matrix substrate is lowered.
- an object of the present invention is to provide a high-yield active matrix substrate having a common electrode.
- a first aspect of the present invention is an active matrix substrate, A plurality of gate lines formed in the first wiring layer; A plurality of data lines that are stacked wirings formed in the first semiconductor layer, the second semiconductor layer, the second wiring layer, and the pixel electrode layer; A plurality of pixel circuits arranged corresponding to the intersections of the gate lines and the data lines, each including a switching element and a pixel electrode; A protective insulating film formed in an upper layer than the gate line, the data line, the switching element, and the pixel electrode; A common electrode formed in an upper layer of the protective insulating film,
- the switching element is A gate electrode formed in the first wiring layer; A source electrode and a drain electrode formed on the second wiring layer; A channel region formed in the first semiconductor layer; A semiconductor portion formed under the source electrode and the drain electrode in the second semiconductor layer; A conductor portion formed on the source electrode and the drain electrode in the pixel electrode layer, A portion of the data line formed in the second semiconductor layer is formed larger than a portion formed in the second wiring layer and the pixel
- a portion of the data line formed in the first semiconductor layer is larger than a portion formed in the second semiconductor layer.
- the protective insulating film includes a lower insulating film and an upper insulating film formed using the same material under different conditions.
- One of the lower insulating film and the upper insulating film generates compressive stress, and the other generates tensile stress.
- the lower insulating film has a thickness of 150 to 350 nm, and the upper insulating film has a thickness of 400 to 600 nm.
- the portion of the data line formed in the second wiring layer, the source electrode, and the drain electrode are made of molybdenum or a material containing molybdenum.
- a seventh aspect of the present invention is the sixth aspect of the present invention, A portion of the data line formed in the second wiring layer, the source electrode, and the drain electrode are formed of an alloy of molybdenum and niobium.
- An eighth aspect of the present invention is a method of manufacturing an active matrix substrate, Forming a plurality of gate lines and gate electrodes of a plurality of switching elements in the first wiring layer; Forming a gate insulating film, forming a first semiconductor film on the first semiconductor layer, and forming a second semiconductor film on the second semiconductor layer; In the second wiring layer, a first conductor portion that is a source of a main conductor portion of a plurality of data lines and a second conductor portion that is a source of a source electrode and a drain electrode of the switching element are formed.
- a second semiconductor part that is a source of the first semiconductor part under the main conductor part, a channel region in the first semiconductor layer of the switching element, A source layer forming step of forming a third semiconductor part as a base of the semiconductor part under the source electrode and the drain electrode in the second semiconductor layer;
- a pixel electrode, a third conductor portion overlying the main conductor portion, and a conductor portion overlying the source electrode and the drain electrode are formed, and the first and second conductor portions are formed A portion of the second semiconductor portion formed in the second semiconductor layer, and by patterning the third semiconductor portion, the main conductor portion, the source electrode and the drain electrode, the first semiconductor portion, And a pixel electrode layer forming step for forming the semiconductor portion; Forming a protective insulating film on the pixel electrode; and Forming a common electrode on an upper layer of the protective insulating film, In the pixel electrode layer forming step, a portion formed in the second semiconductor layer of the first semiconductor portion
- a ninth aspect of the present invention is the eighth aspect of the present invention,
- the source layer forming step is characterized in that a portion formed in the first semiconductor layer of the first semiconductor portion is formed larger than a portion formed in the second semiconductor layer.
- a tenth aspect of the present invention is the eighth aspect of the present invention.
- the pixel electrode layer forming step includes a film forming process, a photoresist forming process, an etching process, and a photoresist stripping process,
- the etching process performs wet etching on the film obtained by the film formation process and the first and second conductor portions using the photoresist formed by the photoresist formation process as a mask, and Dry etching is performed on a portion of the second semiconductor portion formed in the second semiconductor layer and the third semiconductor portion.
- An eleventh aspect of the present invention is the ninth aspect of the present invention.
- the pattern for forming the second semiconductor part included in the photomask used in the source layer forming step forms the main conductor part included in the photomask used in the pixel electrode layer forming step. It is larger than the pattern.
- a twelfth aspect of the present invention is the eighth aspect of the present invention.
- the step of forming the protective insulating film includes a process of forming a lower insulating film and an upper insulating film under different conditions using the same material.
- a thirteenth aspect of the present invention is the twelfth aspect of the present invention.
- the process of forming the lower insulating film and the upper insulating film is characterized in that a lower layer insulating film and an upper insulating film that generate a stretching stress on the one hand and a tensile stress on the other hand are formed.
- a fourteenth aspect of the present invention is the twelfth aspect of the present invention.
- the process of forming the lower insulating film and the upper insulating film is characterized by forming a lower insulating film having a thickness of 150 to 350 nm and an upper insulating film having a thickness of 400 to 600 nm.
- a fifteenth aspect of the present invention is the eighth aspect of the present invention,
- the first and second conductor portions are formed of molybdenum or a material containing molybdenum.
- a sixteenth aspect of the present invention is the fifteenth aspect of the present invention.
- the source layer forming step is characterized in that the first and second conductor portions are formed of an alloy of molybdenum and niobium.
- the portion formed in the lower layer is set to be more than the portion formed in the upper layer (second wiring layer and pixel electrode layer).
- the cross-sectional shape of the data line and the source electrode and the drain electrode of the switching element are formed in a staircase shape. Accordingly, the coverage of the protective insulating film formed on the data lines and the switching elements can be increased, and the yield of the active matrix substrate having the common electrode can be increased.
- the data line by forming a portion of the data line formed in the first semiconductor layer larger than a portion formed in the second semiconductor layer, the data line has a larger number. It is formed in a staircase shape having steps. Therefore, the coverage of the protective insulating film formed on the data line can be further increased, and the yield of the active matrix substrate having the common electrode can be further increased.
- the third or twelfth aspect of the present invention by forming a two-layer protective insulating film using the same material, even when conductive foreign matter is present on the substrate before the protective insulating film is formed, A two-layer protective insulating film that can insulate the pixel electrode layer from the common electrode layer can be easily formed.
- the stress generated in the protective insulating film of each layer can be offset by forming the two protective insulating films in which stresses in the opposite directions are generated. Therefore, the coverage of the protective insulating film can be increased and the yield of the active matrix substrate having the common electrode can be increased.
- the stress generated in the protective insulating film of each layer can be offset, and the leak rate of the data line and the common electrode can be suppressed. Therefore, the coverage of the protective insulating film can be increased and the yield of the active matrix substrate having the common electrode can be increased.
- the main conductor portion of the data line is formed by forming molybdenum or a material containing molybdenum (for example, an alloy of molybdenum and niobium). Generation of foreign matters can be prevented and the yield of an active matrix substrate having a common electrode can be increased.
- molybdenum or a material containing molybdenum for example, an alloy of molybdenum and niobium.
- wet etching and dry etching are continuously performed using the same photomask, so that the portion formed in the second semiconductor layer is the second wiring layer. Further, it can be formed larger than the portion formed in the pixel electrode layer.
- the first semiconductor layer of the data line is formed by setting a size difference in the pattern of the photomask used between the source layer forming step and the pixel electrode layer forming step.
- the portion to be formed can be formed larger than the portion formed in the second semiconductor layer.
- FIG. 2 is a plan view of the active matrix substrate shown in FIG. 1. It is a figure which shows patterns other than the common electrode of the active matrix substrate shown in FIG. It is a figure which shows the pattern of the common electrode of the active matrix substrate shown in FIG. It is a figure which shows the manufacturing method of the active matrix substrate shown in FIG. It is a continuation figure of FIG. 5A. It is a continuation figure of FIG. 5B. It is a continuation figure of FIG. 5C. It is a continuation figure of FIG. 5D. It is a continuation figure of FIG. 5E. It is a continuation figure of FIG. 5F. It is a continuation figure of FIG.
- FIG. 5G It is a continuation figure of FIG. 5H. It is a continuation figure of FIG. 5I. It is a continuation figure of FIG. 5J. It is sectional drawing of the data line after completion of the etching of a 4th process. It is sectional drawing of TFT after the completion of the etching of a 4th process.
- 2 is a table showing an example of film formation conditions and characteristics of two layers of SiNx films of the active matrix substrate shown in FIG. 1. It is a figure which shows the relationship between the film thickness of two layers of SiNx films
- FIG. 2 is a diagram showing a relationship between a total film thickness of two SiNx films of the active matrix substrate shown in FIG. 1 and a leak rate of a data line and a common electrode.
- FIG. 1 is a block diagram showing a configuration of a liquid crystal display device including an active matrix substrate according to an embodiment of the present invention.
- a liquid crystal display device 1 shown in FIG. 1 includes a liquid crystal panel 2, a display control circuit 3, a gate line driving circuit 4, a data line driving circuit 5, and a backlight 6.
- m and n are integers of 2 or more, i is an integer of 1 to m, and j is an integer of 1 to n.
- the liquid crystal panel 2 is an FFS mode liquid crystal panel.
- the liquid crystal panel 2 has a structure in which an active matrix substrate 10 and a counter substrate 40 are bonded together and a liquid crystal layer is provided between the two substrates.
- a black matrix (not shown) or the like is formed on the counter substrate 40.
- m gate lines G1 to Gm, n data lines S1 to Sn, (m ⁇ n) pixel circuits 20, a common electrode 30 (dot pattern portion), and the like are formed on the active matrix substrate 10.
- the A semiconductor chip that functions as the gate line drive circuit 4 and a semiconductor chip that functions as the data line drive circuit 5 are mounted on the active matrix substrate 10.
- FIG. 1 schematically shows the configuration of the liquid crystal display device 1, and the shape of the elements described in FIG. 1 is not accurate.
- gate lines G1 to Gm extend in the row direction and are arranged in parallel to each other.
- the data lines S1 to Sn extend in the column direction and are arranged in parallel to each other.
- the gate lines G1 to Gm and the data lines S1 to Sn intersect at (m ⁇ n) locations.
- the (m ⁇ n) pixel circuits 20 are two-dimensionally arranged corresponding to the intersections of the gate lines G1 to Gm and the data lines S1 to Sn.
- the pixel circuit 20 includes an N-channel TFT 21 and a pixel electrode 22.
- the gate electrode of the TFT 21 included in the pixel circuit 20 in the i-th row and j-th column is connected to the gate line Gi
- the source electrode is connected to the data line Sj
- the drain electrode is connected to the pixel electrode 22.
- a protective insulating film (not shown) is formed above the gate lines G 1 to Gm, the data lines S 1 to Sn, the TFT 21, and the pixel electrode 22.
- the common electrode 30 is formed in the upper layer of the protective insulating film.
- the pixel electrode 22 and the common electrode 30 face each other with a protective insulating film interposed therebetween.
- the backlight 6 is disposed on the back side of the liquid crystal panel 2 and irradiates the back surface of the liquid crystal panel 2 with light.
- the display control circuit 3 outputs a control signal C1 to the gate line driving circuit 4, and outputs a control signal C2 and a data signal D1 to the data line driving circuit 5.
- the gate line driving circuit 4 drives the gate lines G1 to Gm based on the control signal C1.
- the data line driving circuit 5 drives the data lines S1 to Sn based on the control signal C2 and the data signal D1. More specifically, the gate line driving circuit 4 selects one gate line from the gate lines G1 to Gm in each horizontal period (line period) and applies a high level voltage to the selected gate line.
- the data line driving circuit 5 applies n data voltages corresponding to the data signal D1 to the data lines S1 to Sn in each horizontal period. As a result, n pixel circuits 20 are selected within one horizontal period, and n data voltages are respectively written to the selected n pixel circuits 20.
- FIG. 2 is a plan view of the active matrix substrate 10.
- FIG. 2 shows some of the elements formed on the active matrix substrate 10.
- the active matrix substrate 10 is divided into a facing region 11 that faces the facing substrate 40 and a non-facing region 12 that does not face the facing substrate 40.
- the non-facing region 12 is located on the right side and the lower side of the facing region 11.
- a display area 13 (area indicated by a broken line) for arranging the pixel circuit 20 is set in the facing area 11.
- a portion obtained by removing the display area 13 from the facing area 11 is referred to as a frame area 14.
- (m ⁇ n) pixel circuits 20, m gate lines 23, and n data lines 24 are formed.
- the (m ⁇ n) pixel circuits 20 are two-dimensionally arranged in the display area 13.
- the non-facing region 12 is provided with an external terminal 15 for inputting a common electrode signal.
- the first common trunk line 16 formed in the same wiring layer as the gate line 23 and the data line 24 are provided in the frame region 14.
- a second common trunk wiring 17 formed in the wiring layer is formed.
- the first common trunk line 16 is formed on the upper side, the left side, and the lower side of the display area 13, and the second common trunk line 17 is formed on the right side of the display area 13.
- a connecting circuit (not shown) for connecting the common electrode 30, the first common trunk line 16 and the second common trunk line 17 is formed in the A1 part and the A2 part of FIG.
- a mounting region 18 for mounting the gate line driving circuit 4 and a mounting region 19 for mounting the data line driving circuit 5 are set.
- a gate layer, a gate insulating film, a first semiconductor layer, a second semiconductor layer, a source layer, a pixel electrode layer, a protective insulating film, and a common electrode layer are formed in this order from the lower layer on a glass substrate. (Details will be described later).
- the gate line 23 and the first common trunk line 16 are formed in the gate layer.
- the data line 24 and the second common trunk wiring 17 are stacked wirings formed in the first semiconductor layer, the second semiconductor layer, the source layer, and the pixel electrode layer.
- FIG. 3 is a diagram showing patterns other than the common electrode 30 of the active matrix substrate 10.
- the gate line 23 (lower left hatched portion) extends in the row direction while being refracted midway.
- the data line 24 (lower right oblique line) extends in the column direction while being refracted near the intersection with the gate line 23.
- the gate line 23 and the data line 24 are formed in different wiring layers.
- a TFT 21 is formed near the intersection of the gate line 23 and the data line 24.
- a pixel electrode 22 is formed in a region partitioned by the gate line 23 and the data line 24.
- the TFT 21 has a gate electrode connected to the gate line 23, a source electrode connected to the data line 24, and a drain electrode connected to the pixel electrode 22.
- the liquid crystal panel 2 includes a plurality of pixel circuits 20 arranged corresponding to the intersections of the gate lines 23 and the data lines 24.
- FIG. 4 is a diagram showing a pattern of the common electrode 30 of the active matrix substrate 10.
- the common electrode 30 is formed in an upper layer of the protective insulating film formed in an upper layer (that is, a side closer to the liquid crystal layer) than the TFT 21, the pixel electrode 22, the gate line 23, and the data line 24. As shown in FIG. 4, the common electrode 30 is formed so as to cover the entire surface of the display region 13 except for the following portions.
- the common electrode 30 has a plurality of slits 31 corresponding to the pixel electrode 22 in order to generate a horizontal electric field applied to the liquid crystal layer together with the pixel electrode 22.
- the common electrode 30 has seven slits 31 corresponding to one pixel electrode 22. The slit 31 is refracted near the middle.
- the common electrode 30 has a notch 32 formed in a region including the source electrode arrangement region and the channel region of the TFT 21. By providing the notch 32 in the common electrode 30, it is possible to prevent the common electrode 30 formed above the TFT 21 from affecting the operation of the TFT 21.
- FIGS. 5A to 5K show a process of forming the gate line 23, the data line 24, the TFT 21, and the switching circuit, respectively.
- gate layer pattern (FIG. 5A) Ti (titanium), Al (aluminum), and Ti are sequentially formed on the glass substrate 101 by sputtering. Subsequently, the gate layer is patterned using photolithography and etching to form the gate line 23, the gate electrode 111 of the TFT 21, the first common trunk line 16, and the like.
- patterning using a photolithography method and etching refers to the following processing. First, a photoresist is applied to the substrate. Next, the substrate is exposed with a photomask having a desired pattern, thereby leaving the photoresist in the same pattern as the photomask on the substrate. Next, the substrate is etched using the remaining photoresist as a mask to form a pattern on the surface of the substrate. Finally, the photoresist is peeled off.
- a MoNb (molybdenum niobium) film 131 is formed on the substrate shown in FIG. 5B by sputtering. Subsequently, the source layer and the semiconductor layer are patterned using photolithography and etching to form the main conductor portion 133 of the data line 24, the conductor portion 134 of the TFT 21, the main conductor portion 135 of the second common trunk line 17, and the like. .
- the conductor portion 134 of the TFT 21 is formed at the position of the source electrode, the drain electrode, and the channel region of the TFT 21.
- a photomask that leaves the photoresist 132 in positions such as the main conductor parts 133 and 135 and the conductor part 134 is used. Therefore, after exposure, the photoresist 132 remains at positions such as the main conductor portions 133 and 135 and the conductor portion 134 (FIG. 5C).
- the MoNb film 131 formed in the third process is first etched, and then the n + amorphous Si film 123 and the amorphous Si film 122 formed in the second process are successively etched (FIG. 5D).
- the amorphous Si film 122 and the n + amorphous Si film 123 are patterned in substantially the same shape as the source layer.
- the photoresist 132 is removed to obtain the substrate shown in FIG. 5E.
- the MoNb film 131 that remains without being etched becomes the main conductor portion 133 of the data line 24, the conductor portion 134 of the TFT 21, the main conductor portion 135 of the second common trunk line 17, and the like.
- the substrate shown in FIG. 5E the MoNb film 131 that remains without being etched becomes the main conductor portion 133 of the data line 24, the conductor portion 134 of the TFT 21, the main conductor portion 135 of the second common trunk line 17, and the like.
- the amorphous Si film 122 and the n + amorphous Si film 123 are disposed below the main conductor portion 133 of the data line 24, the conductor portion 134 of the TFT 21, and the main conductor portion 135 of the second common trunk line 17. Exists.
- FIG. 5F Formation of Pixel Electrode
- An IZO film 141 to be the pixel electrode 22 is formed on the substrate shown in FIG. 5E by sputtering. Subsequently, the pixel electrode layer is patterned using photolithography and etching. In the fourth step, a photomask that leaves the photoresist 142 at the position of the pixel electrode 22 and the position of the source layer pattern (except for the position of the channel region of the TFT 21) is used. For this reason, after exposure, the photoresist 142 remains at the position of the pixel electrode 22 and the position of the source layer pattern excluding the position of the channel region of the TFT 21 (FIG. 5F).
- the IZO film 141 and the conductor part 134 existing at the channel region position of the TFT 21 are first etched by wet etching, and then the n + amorphous Si film existing at the channel region position of the TFT 21 by dry etching. 123 is etched (FIGS. 5G and 5H).
- FIG. 5G shows the substrate when the etching of the conductor portion 134 is completed.
- FIG. 5H shows the substrate when the etching of the n + amorphous Si film 123 is completed.
- the film thickness of the amorphous Si film 122 existing in the channel region of the TFT 21 is reduced by dry etching.
- the photoresist 142 is removed to obtain the substrate shown in FIG. 5I.
- the channel region of the TFT 21 is formed, and the source electrode 143 and the drain electrode 144 of the TFT 21 are separated from each other.
- the IZO film 141 remains on the main conductor portion 133 of the data line 24, the source electrode 143 and the drain electrode 144 of the TFT 21, and the main conductor portion 135 of the second common trunk line 17.
- FIG. 5J Formation of protective insulating film (FIG. 5J)
- Two layers of SiNx films 151 and 152 to be protective insulating films are sequentially formed on the substrate shown in FIG. 5I by CVD.
- the deposition conditions for the lower SiNx film 151 and the deposition conditions for the upper SiNx film 152 are different (details will be described later).
- the two-layer SiNx films 151 and 152 formed in the fifth process and the SiNx film 121 formed in the second process are patterned by using a photolithography method and etching. As shown in FIG.
- a contact hole 153 penetrating the two layers of SiNx films 151 and 152 and the SiNx film 121 and two layers of SiNx films 151 and 152 are formed at the position where the reconnection circuit is formed.
- a penetrating contact hole 154 is formed.
- the photomask used in the sixth step has a pattern corresponding to the slit 31 and the notch 32.
- the common electrode 30 having the slit 31 and the notch 32 can be formed.
- the data line 24 includes a stacked wiring (amorphous Si film 122, n + amorphous Si film 123, main conductor portion 133, and IZO film) formed in the first semiconductor layer, the second semiconductor layer, the source layer, and the pixel electrode layer. 141 (see FIG. 5K (b)).
- the TFT 21 includes a gate electrode 111 formed in the gate layer, a source electrode 143 and a drain electrode 144 formed in the source layer, a channel region (amorphous Si film 122) formed in the first semiconductor layer, The semiconductor portion (n + amorphous Si film 123) formed under the source electrode 143 and the drain electrode 144 in the two semiconductor layers, and the conductor portion (IZO film formed over the source electrode 143 and the drain electrode 144 in the pixel electrode layer) 141) (see FIG. 5K (c)).
- the photolithography method is executed using different photomasks in the first and third to sixth steps, and the photolithography method is not executed in the second step.
- the total number of photomasks used in the manufacturing method according to this embodiment is five.
- Cu copper
- Mo molybdenum
- Al Al
- Ti Ti
- TiN titanium nitride
- alloys thereof or a laminated film of these metals may be used.
- a three-layer film in which an Al alloy is laminated on the upper layer of MoNb and MoNb is further laminated on the upper layer of the Al alloy may be used.
- ITO indium tin oxide
- a laminated film of a SiOx (silicon oxide) film or a SiON (silicon nitride oxide) film may be used instead of the SiNx film.
- the thicknesses of the various films formed on the substrate are suitably determined according to the material and function of the film.
- the thickness of the film is, for example, about 10 nm to 1 ⁇ m.
- an example of the film thickness is shown.
- a Ti film having a thickness of 25 to 35 nm, an Al film having a thickness of 180 to 220 nm, and a Ti film having a thickness of 90 nm to 110 nm are sequentially formed.
- an SiNx film 121 having a thickness of 360 to 450 nm, an amorphous Si film 122 having a thickness of 100 to 200 nm, and an n + amorphous Si film 123 having a thickness of 30 to 80 nm are successively formed.
- the MoNb film 131 having a thickness of 180 to 220 nm is formed, and in the fourth step, the IZO film 141 having a thickness of 50 to 80 nm is formed.
- a lower SiNx film 151 having a thickness of 220 to 280 nm and an upper SiNx film 152 having a thickness of 450 to 550 nm are formed.
- an IZO film having a thickness of 110 to 140 nm is formed.
- the n + amorphous Si film 123 is formed to be larger than the main conductor portion 133 and the IZO film 141 at the position of the data line 24, and the n + amorphous Si film 123 is
- the electrode 143, the drain electrode 144, and the IZO film 141 are formed to be larger (hereinafter referred to as a first feature).
- FIG. 6 is a cross-sectional view of the data line 24 after completion of the etching in the fourth step.
- FIG. 7 is a cross-sectional view of the TFT 21 after completion of the etching in the fourth step.
- FIGS. 6 and 7 describe FIGS. 5H (b) and 5H (c) in more detail, respectively.
- 6 and 7 show the photoresist 142 formed in the fourth step.
- an area covered with the photoresist 142 when the substrate is viewed from directly above is referred to as a covered area.
- the covering region of the photoresist 142 is determined by the pattern of the photomask (hereinafter referred to as a pixel electrode layer photomask) used in the fourth step.
- a pixel electrode layer photomask used in the fourth step.
- the IZO film 141 and the conductor portion 134 existing at the channel region position of the TFT 21 are etched by wet etching, and subsequently, the dry etching is performed to the channel region position of the TFT 21.
- the existing n + amorphous Si film 123 is etched.
- the IZO film 141, the main conductor portion 133, and the n + amorphous Si film 123 at the position of the data line 24 are simultaneously etched.
- the n + amorphous Si film 123 is dry-etched using the photoresist 142 as a mask. Therefore, the n + amorphous Si film 123 is etched almost according to the pattern of the photoresist 142 (that is, the photomask pattern for the pixel electrode layer). . Specifically, the n + amorphous Si film 123 outside the coating region of the photoresist 142 is not etched, and the n + amorphous Si film 123 inside the coating region of the photoresist 142 remains without being etched. Therefore, the position of the end E2 of the n + amorphous Si film 123 is substantially equal to the position of the end of the photoresist 142.
- the main conductor portion 133, the conductor portion 134 of the data line 24, and the IZO film 141 formed in the upper layer of the data line 24 cause an etch shift due to wet etching. Etched small. Specifically, the main conductor portion 133, the conductor portion 134, and the IZO film 141 that are not more than a predetermined distance from the end within the photoresist 142 coverage region are etched in addition to the region outside the photoresist 142 coverage region. Disappear. Therefore, in FIG.
- the position of the end E1 of the main conductor portion 133 and the IZO film 141 is inside the coating region of the photoresist 142 rather than the position of the end E2 of the n + amorphous Si film 123.
- the source electrode 143, the drain electrode 144, and the end E ⁇ b> 1 of the IZO film 141 are inside the coating region of the photoresist 142 rather than the position of the end E ⁇ b> 2 of the n + amorphous Si film 123.
- the n + amorphous Si film 123 is formed larger than the main conductor portion 133 and the IZO film 141 at the position of the data line 24, and the n + amorphous Si film 123 is formed at the position of the TFT 21 as the source.
- the electrode 143, the drain electrode 144, and the IZO film 141 are formed larger. Therefore, the first feature can be realized by performing the etching in the fourth step.
- the portion formed in the lower layer (second semiconductor layer) is formed larger than the portion formed in the upper layer (source layer and pixel electrode layer).
- the cross-sectional shapes of the line 24 and the source electrode 143 and the drain electrode 144 of the TFT 21 are formed stepwise. Therefore, the coverage of the protective insulating film formed on the data line 24 and the TFT 21 can be increased, and the yield of the active matrix substrate 10 having the common electrode 30 can be increased.
- the active matrix substrate 10 has a characteristic that the amorphous Si film 122 is formed larger than the n + amorphous Si film 123 at the position of the data line 24 (hereinafter referred to as a second characteristic).
- the position of the end E3 of the amorphous Si film 122 is determined by the pattern of the photomask (hereinafter referred to as a source layer photomask) used in the third step (FIGS. 5D and 5H). See).
- a source layer photomask used in the third step.
- the pattern of the photomask for the source layer is made larger than the pattern of the photomask for the pixel electrode layer at the position of the data line 24. Is increased by a predetermined amount (for example, 1 ⁇ m or more). For this reason, in FIG.
- the position of the end E3 of the amorphous Si film 122 is outside the region covered with the photoresist 142, rather than the position of the end E2 of the n + amorphous Si film 123. Thereby, the second feature can be realized.
- the data line 24 has more stages by forming the portion formed in the first semiconductor layer of the data line 24 larger than the portion formed in the second semiconductor layer. It is formed in steps. Therefore, the coverage of the protective insulating film formed on the data line 24 can be made higher, and the yield of the active matrix substrate 10 having the common electrode 30 can be made higher.
- the active matrix substrate 10 includes, as a protective insulating film, a lower insulating film and an upper insulating film that generate compressive stress on the one hand and tensile stress on the other hand (hereinafter referred to as a third characteristic).
- a protective insulating film composed of two layers of SiNx films 151 and 152 is formed (FIG. 5J), and the film formation conditions for the lower SiNx film 151 and the film formation conditions for the upper SiNx film 152 are different.
- a thin film having a high film density formed under a high temperature condition is used for the lower SiNx film 151, and a thick film having a low film density formed under a low temperature condition is used for the upper SiNx film 152. Further, the lower layer SiNx film 151 and the upper layer SiNx film 152 are formed so as to generate stress in opposite directions.
- FIG. 8 is a table showing an example of film forming conditions and characteristics of a two-layer SiNx film.
- the deposition temperature of the lower SiNx film 151 is 270 ⁇ 10 ° C.
- the deposition temperature of the upper SiNx film 152 is 210 ⁇ 10 ° C. Therefore, the lower SiNx film 151 has a poor step coverage and a high film density, and the upper SiNx film 152 has a good step coverage and a low film density.
- the film thickness is 500 nm
- a compressive stress of 380 MPa is generated in the lower SiNx film 151
- a tensile stress of 160 MPa is generated in the upper SiNx film 152.
- FIG. 9 is a diagram showing the relationship between the film thickness of the two-layer SiNx film and the film stress.
- FIG. 9 shows the relationship between the film thickness of the lower SiNx film 151 and compressive stress, and the relationship between the film thickness of the upper SiNx film 152 and tensile stress.
- the compressive stress generated in the lower SiNx film 151 and the tensile stress generated in the upper SiNx film 152 are offset, and the smaller the difference between the two, the higher the coverage of the protective insulating film.
- the difference between the compressive stress generated in the lower SiNx film 151 and the tensile stress generated in the upper SiNx film 152 is small.
- the film thicknesses of the two SiNx films 151 and 152 are determined so as to fall within the range R1, for example.
- FIG. 10 is a diagram showing the relationship between the total film thickness of the two layers of SiNx films and the leak rate of the data lines and the common electrode.
- the leak rate decreases as the total film thickness increases.
- the leak occurrence rate is sufficiently small, ie, 0.10 pieces / substrate.
- the thicknesses of the two SiNx films 151 and 152 are determined so that the total film thickness falls within the range R2, for example.
- the film thickness of the lower SiNx film 151 is determined to be 250 ⁇ 100 nm, and the film thickness of the upper SiNx film 152 is 500 ⁇ . Determined to be 100 nm.
- the lower SiNx film 151 has a thickness of 150 to 350 nm, and the upper SiNx film 152 has a thickness of 400 to 600 nm.
- the active matrix substrate 10 a two-layer protective insulating film that generates stress in the opposite direction is formed.
- produces in the protective insulating film of each layer can be canceled. Therefore, the coverage of the protective insulating film can be increased and the yield of the active matrix substrate 10 having the common electrode 30 can be increased.
- the foreign matter is covered with the two layers of the protective insulating film, and the pixel electrode layer and the upper SiNx layer below the lower SiNx film 151 are covered.
- the common electrode layer on the upper layer of the film 152 can be insulated.
- the pixel electrode layer and the common electrode layer can be insulated by the upper SiNx film 152 when the lower SiNx film 151 has pinholes, and the lower SiNx film 151 when the upper SiNx film 152 has pinholes. it can.
- the two-layer protective insulating film can be easily formed.
- the main conductor portion 133 of the data line 24 and the source electrode 143 and the drain electrode 144 of the TFT 21 are molybdenum or a material containing molybdenum (hereinafter, both are collectively referred to as a Mo-based material). It has the characteristic (henceforth a 4th characteristic) that it is formed by.
- a Mo-based material is used instead of the Al-based material.
- the main conductor portion 133 of the data line 24 and the source electrode 143 and the drain electrode 144 of the TFT 21 are formed of a Mo-based material (for example, MoNb that is an alloy of molybdenum and niobium). . Therefore, generation
- Mo-based material for example, MoNb that is an alloy of molybdenum and niobium.
- the upper layer of the main conductor portion 133 formed of the Al-based material and It is preferable to form a conductor film using a Mo-based material (for example, MoNb which is an alloy of molybdenum and niobium) under the IZO film 141. Even with such a configuration, it is possible to suppress a decrease in yield due to hillocks of the Al-based material.
- Mo-based material for example, MoNb which is an alloy of molybdenum and niobium
- the active matrix substrate 10 includes the plurality of gate lines 23 formed in the first wiring layer (gate layer), the first semiconductor layer, the second semiconductor layer, and the second wiring layer.
- (Source layer) and a plurality of data lines 24 which are stacked wirings formed in the pixel electrode layer, and are arranged corresponding to the intersections of the gate lines 23 and the data lines 24, and each of them is a switching element (TFT 21) and a pixel
- TFT 21 switching element
- pixel circuits 20 including electrodes 22, a gate line 23, a data line 24, a switching element, a protective insulating film (SiNx films 151 and 152) formed above the pixel electrode 22, and a protective insulating film And a common electrode 30 formed in an upper layer.
- the switching element includes a gate electrode 111 formed in the first wiring layer, a source electrode 143 and a drain electrode 144 formed in the second wiring layer, and a channel region (amorphous Si film 122) formed in the first semiconductor layer.
- IZO film 141 A portion (n + amorphous Si film 123) formed in the second semiconductor layer of the data line 24 is formed larger than portions (main conductor portion 133 and IZO film 141) formed in the second wiring layer and the pixel electrode layer.
- the semiconductor portion is formed larger than the source electrode 143, the drain electrode 144, and the conductor portion.
- the method for manufacturing the active matrix substrate 10 includes a step (first step) of forming a plurality of gate lines 23 and gate electrodes 111 of a plurality of switching elements in a first wiring layer, and a gate insulating film (SiNx film 121). Forming a first semiconductor film (amorphous Si film 122) on the first semiconductor layer, and forming a second semiconductor film (n + amorphous Si film 123) on the second semiconductor layer (second process) ), A first conductor portion (main conductor portion 133 shown in FIG. 5E (b)) serving as a source of the main conductor portions 133 of the plurality of data lines 24, the source electrode 143 and the drain of the switching element.
- the first semiconductor portion under the main conductor portion 133 is formed.
- a portion (n + amorphous Si film 123 shown in FIG. 5I (c)) formed in the second semiconductor layer of the first semiconductor portion is formed to be larger than the main conductor portion 133 and the third conductor portion.
- the semiconductor portion is formed larger than the source electrode 143, the drain electrode 144, and the conductor portion.
- the data lines 24 and The cross-sectional shapes of the source electrode and the drain electrode of the switching element are formed stepwise. Therefore, the coverage of the protective insulating film formed on the data line 24 and the switching element can be increased, and the yield of the active matrix substrate having the common electrode 30 can be increased.
- the pixel electrode layer forming step includes a film forming process, a photoresist forming process, an etching process, and a photoresist stripping process.
- the etching process is performed using the photoresist 142 formed in the photoresist forming process as a mask.
- Wet etching is performed on the film (IZO film 141) obtained in step 1 and the first and second conductor portions, and a portion formed in the second semiconductor layer of the second semiconductor portion and a third semiconductor portion
- dry etching is performed.
- wet etching and dry etching are continuously performed using the same photomask, so that portions formed in the second semiconductor layer are formed in the second wiring layer and the pixel electrode layer. It can be formed larger than the portion.
- the portion of the data line 24 formed in the first semiconductor layer is formed larger than the portion formed in the second semiconductor layer (n + amorphous Si film 123). ing.
- the source layer forming step forms a portion formed in the first semiconductor layer of the first semiconductor portion larger than a portion formed in the second semiconductor layer. In this manner, by forming a portion of the data line 24 formed in the first semiconductor layer larger than a portion formed in the second semiconductor layer, the data line is formed in a stepped shape having more steps. Therefore, the coverage of the protective insulating film formed on the data line 24 can be made higher, and the yield of the active matrix substrate 10 having the common electrode 30 can be made higher.
- the pattern for forming the second semiconductor part included in the photomask used in the source layer forming step is more than the pattern for forming the main conductor part 133 included in the photomask used in the pixel electrode layer forming step. Is also big. In this way, by setting a size difference in the pattern of the photomask used between the source layer forming step and the pixel electrode layer forming step, the portion formed in the first semiconductor layer of the data line 24 is changed to the second semiconductor. It can be formed larger than the portion formed in the layer.
- the protective insulating film includes a lower insulating film (lower SiNx film 151) and an upper insulating film (upper SiNx film 152) formed using the same material under different conditions.
- the step of forming the protective insulating film includes a process of forming the lower insulating film and the upper insulating film under different conditions using the same material.
- one of the lower insulating film and the upper insulating film generates a compressive stress, and the other generates a tensile stress.
- the process of forming the lower insulating film and the upper insulating film forms the lower insulating film and the upper insulating film that generate the stretching stress on the one hand and the tensile stress on the other hand.
- the stress generated in the protective insulating film in each layer can be offset. Therefore, the coverage of the protective insulating film can be increased and the yield of the active matrix substrate 10 having the common electrode 30 can be increased.
- the thickness of the lower insulating film is 150 to 350 nm, and the thickness of the upper insulating film is 400 to 600 nm.
- the process of forming the lower insulating film and the upper insulating film is to form a lower insulating film having a thickness of 150 to 350 nm and an upper insulating film having a thickness of 400 to 600 nm. Therefore, the stress generated in the protective insulating film of each layer can be offset, and the leak occurrence rate of the data line 24 and the common electrode 30 can be suppressed. Therefore, the coverage of the protective insulating film can be increased and the yield of the active matrix substrate 10 having the common electrode 30 can be increased.
- the portion formed in the second wiring layer of the data line 24, the source electrode 143, and the drain electrode 144 are formed of molybdenum or a material containing molybdenum (for example, an alloy of molybdenum and niobium).
- the first and second conductor portions are formed of molybdenum or a material containing molybdenum.
- the active matrix substrate 10 described above has the first to fourth characteristics, but as a modification of the present embodiment, an active matrix substrate having only the first characteristic among the first to fourth characteristics, An active matrix substrate having the first feature and one or two of the second to fourth features may be configured.
- the active matrix substrate according to these modified examples can be manufactured by a manufacturing method in which the characteristics in the process for realizing the second to fourth characteristics are removed from the manufacturing method of the active matrix substrate 10 described above.
- the present invention is applied to an active matrix substrate of a horizontal electric field type liquid crystal panel has been described so far, but the present invention can also be applied to an active matrix substrate of a vertical electric field type liquid crystal panel.
- the active matrix substrate of the present invention has a common electrode and a high yield, it can be used for a liquid crystal panel or the like.
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
第1配線層に形成された複数のゲート線と、
第1半導体層、第2半導体層、第2配線層、および、画素電極層に形成された積層配線である複数のデータ線と、
前記ゲート線と前記データ線の交点に対応して配置され、それぞれがスイッチング素子および画素電極を含む複数の画素回路と、
前記ゲート線、前記データ線、前記スイッチング素子、および、前記画素電極よりも上層に形成された保護絶縁膜と、
前記保護絶縁膜の上層に形成された共通電極とを備え、
前記スイッチング素子は、
前記第1配線層に形成されたゲート電極と、
前記第2配線層に形成されたソース電極およびドレイン電極と、
前記第1半導体層に形成されたチャネル領域と、
前記第2半導体層において前記ソース電極および前記ドレイン電極の下に形成された半導体部と、
前記画素電極層において前記ソース電極および前記ドレイン電極の上に形成された導体部とを含み、
前記データ線の前記第2半導体層に形成された部分は、前記第2配線層および前記画素電極層に形成された部分よりも大きく形成され、前記半導体部は、前記ソース電極、前記ドレイン電極、および、前記導体部よりも大きく形成されていることを特徴とする。
前記データ線の前記第1半導体層に形成された部分は、前記第2半導体層に形成された部分よりも大きく形成されていることを特徴とする。
前記保護絶縁膜は、同じ材料を用いて異なる条件で成膜された下層絶縁膜と上層絶縁膜を含むことを特徴とする。
前記下層絶縁膜と前記上層絶縁膜の一方では圧縮応力が発生し、他方では引張応力が発生することを特徴とする。
前記下層絶縁膜の膜厚は150~350nmであり、前記上層絶縁膜の膜厚は400~600nmであることを特徴とする。
前記データ線の前記第2配線層に形成された部分、前記ソース電極、および、前記ドレイン電極は、モリブデンまたはモリブデンを含む材料で形成されていることを特徴とする。
前記データ線の前記第2配線層に形成された部分、前記ソース電極、および、前記ドレイン電極は、モリブデンとニオブの合金で形成されていることを特徴とする。
第1配線層に、複数のゲート線と、複数のスイッチング素子のゲート電極とを形成するステップと、
ゲート絶縁膜を成膜し、第1半導体層に第1半導体膜を成膜し、第2半導体層に第2半導体膜を成膜するステップと、
第2配線層に、複数のデータ線の主導体部の元になる第1導体部と、前記スイッチング素子のソース電極およびドレイン電極の元になる第2導体部とを形成すると共に、前記第1および第2半導体膜をパターニングすることにより、前記主導体部の下にある第1半導体部の元になる第2半導体部と、前記スイッチング素子の、前記第1半導体層にあるチャネル領域と、前記第2半導体層において前記ソース電極および前記ドレイン電極の下にある半導体部の元になる第3半導体部とを形成するソース層形成ステップと、
画素電極層に、画素電極と、前記主導体部の上にある第3導体部と、前記ソース電極および前記ドレイン電極の上にある導体部とを形成すると共に、前記第1および第2導体部、前記第2半導体部の前記第2半導体層に形成された部分、並びに、前記第3半導体部をパターニングすることにより、前記主導体部、前記ソース電極および前記ドレイン電極、前記第1半導体部、並びに、前記半導体部を形成する画素電極層形成ステップと、
前記画素電極の上層に保護絶縁膜を形成するステップと、
前記保護絶縁膜の上層に共通電極を形成するステップとを備え、
前記画素電極層形成ステップは、前記第1半導体部の前記第2半導体層に形成される部分を前記主導体部および前記第3導体部よりも大きく形成し、前記半導体部を前記ソース電極、前記ドレイン電極、および、前記導体部よりも大きく形成することを特徴とする。
前記ソース層形成ステップは、前記第1半導体部の前記第1半導体層に形成される部分を前記第2半導体層に形成される部分よりも大きく形成することを特徴とする。
前記画素電極層形成ステップは、成膜処理、フォトレジスト形成処理、エッチング処理、および、フォトレジスト剥離処理を含み、
前記エッチング処理は、前記フォトレジスト形成処理で形成されたフォトレジストをマスクとして、前記成膜処理で得られた膜と、前記第1および第2導体部とに対してウェットエッチングを行い、前記第2半導体部の前記第2半導体層に形成された部分と、前記第3半導体部とに対してドライエッチングを行うことを特徴とする。
前記ソース層形成ステップで使用されるフォトマスクに含まれる前記第2半導体部を形成するためのパターンは、前記画素電極層形成ステップで使用されるフォトマスクに含まれる前記主導体部を形成するためのパターンよりも大きいことを特徴とする。
前記保護絶縁膜を形成するステップは、同じ材料を用いて異なる条件で下層絶縁膜と上層絶縁膜を成膜する処理を含むことを特徴とする。
前記下層絶縁膜と前記上層絶縁膜を成膜する処理は、一方では伸縮応力が発生し、他方では引張応力が発生する下層絶縁膜と上層絶縁膜を成膜することを特徴とする。
前記下層絶縁膜と前記上層絶縁膜を成膜する処理は、膜厚150~350nmの下層絶縁膜と、膜厚400~600nmの上層絶縁膜とを成膜することを特徴とする。
前記ソース層形成ステップは、前記第1および第2導体部をモリブデンまたはモリブデンを含む材料で形成することを特徴とする。
前記ソース層形成ステップは、前記第1および第2導体部をモリブデンとニオブの合金で形成することを特徴とする。
ガラス基板101上にスパッタリング法によって、Ti(チタン)、Al(アルミニウム)、および、Tiを順次成膜する。続いて、フォトリソグラフィ法とエッチングを用いてゲート層をパターニングし、ゲート線23、TFT21のゲート電極111、第1共通幹配線16などを形成する。ここで、フォトリソグラフィ法とエッチングを用いたパターニングとは、以下の処理をいう。まず、基板にフォトレジストを塗布する。次に、所望のパターンを有するフォトマスクを被せて基板を露光することにより、基板上にフォトマスクと同じパターンにフォトレジストを残す。次に、残したフォトレジストをマスクとして基板をエッチングすることにより、基板の表面にパターンを形成する。最後に、フォトレジストを剥離する。
図5Aに示す基板にCVD(Chemical Vapor Deposition )法によって、ゲート絶縁膜となるSiNx膜121と、アモルファスSi膜122と、n+アモルファスSi膜123とを連続して成膜する。第2工程では、半導体層のパターニングを行わない。半導体層のパターニングは、ソース層のパターニングと共に第3工程で行われる。
図5Bに示す基板にスパッタリング法によって、MoNb(モリブデンニオブ)膜131を成膜する。続いて、フォトリソグラフィ法とエッチングを用いてソース層と半導体層をパターニングし、データ線24の主導体部133、TFT21の導体部134、第2共通幹配線17の主導体部135などを形成する。TFT21の導体部134は、TFT21のソース電極、ドレイン電極、および、チャネル領域の位置に形成される。第3工程では、主導体部133、135、および、導体部134などの位置にフォトレジスト132を残すフォトマスクが使用される。このため露光後には、主導体部133、135、および、導体部134などの位置にフォトレジスト132が残る(図5C)。フォトレジスト132をマスクとして、まず第3工程で成膜したMoNb膜131をエッチングし、次に第2工程で成膜したn+アモルファスSi膜123とアモルファスSi膜122とを連続してエッチングする(図5D)。これにより、アモルファスSi膜122とn+アモルファスSi膜123は、ソース層とほぼ同じ形状にパターニングされる。最後にフォトレジスト132を剥離することにより、図5Eに示す基板が得られる。図5Eに示す基板では、エッチングされずに残ったMoNb膜131が、データ線24の主導体部133、TFT21の導体部134、および、第2共通幹配線17の主導体部135などになる。図5Eに示す基板では、データ線24の主導体部133、TFT21の導体部134、および、第2共通幹配線17の主導体部135の下層には、アモルファスSi膜122とn+アモルファスSi膜123が存在する。
図5Eに示す基板にスパッタリング法によって、画素電極22となるIZO膜141を成膜する。続いて、フォトリソグラフィ法とエッチングを用いて画素電極層をパターニングする。第4工程では、画素電極22の位置とソース層パターンの位置(ただし、TFT21のチャネル領域の位置を除く)にフォトレジスト142を残すフォトマスクが使用される。このため露光後には、画素電極22の位置、および、ソース層パターンの位置からTFT21のチャネル領域の位置を除いた位置にフォトレジスト142が残る(図5F)。フォトレジスト142をマスクとして、まずウェットエッチングによってIZO膜141とTFT21のチャネル領域の位置に存在する導体部134とをエッチングし、続いてドライエッチングによってTFT21のチャネル領域の位置に存在するn+アモルファスSi膜123をエッチングする(図5G、図5H)。図5Gには、導体部134のエッチングが完了した時点の基板が記載されている。図5Hには、n+アモルファスSi膜123のエッチングが完了した時点の基板が記載されている。図5Hに示すように、ドライエッチングによって、TFT21のチャネル領域に存在するアモルファスSi膜122の膜厚は薄くなる。最後にフォトレジスト142を剥離することにより、図5Iに示す基板が得られる。図5Iに示す基板では、TFT21のチャネル領域が形成され、TFT21のソース電極143とドレイン電極144は分離された状態になる。データ線24の主導体部133、TFT21のソース電極143とドレイン電極144、および、第2共通幹配線17の主導体部135の上層には、IZO膜141が残る。
図5Iに示す基板にCVD法によって、保護絶縁膜となる2層のSiNx膜151、152を順次成膜する。下層SiNx膜151の成膜条件と上層SiNx膜152の成膜条件は異なる(詳細は後述)。続いて、フォトリソグラフィ法とエッチングを用いて、第5工程で形成された2層のSiNx膜151、152、および、第2工程で形成されたSiNx膜121をパターニングする。繋ぎ換え回路を形成する位置には、図5J(d)に示すように、2層のSiNx膜151、152とSiNx膜121を貫通するコンタクトホール153、および、2層のSiNx膜151、152を貫通するコンタクトホール154が形成される。
図5Jに示す基板にスパッタリング法によって、共通電極30となるIZO膜を成膜する。続いて、フォトリソグラフィ法とエッチングを用いて共通電極層をパターニングし、共通電極30と繋ぎ換え電極161を形成する。図5K(d)に示すように、繋ぎ換え電極161は、コンタクトホール153の位置で第1共通幹配線16に直接接触し、コンタクトホール154の位置でIZO膜141を介して第2共通幹配線17の主導体部135に電気的に接続される。また、繋ぎ換え電極161は、共通電極30と一体に形成される。したがって、繋ぎ換え電極161を用いて、共通電極30と第1共通幹配線16と第2共通幹配線17とを電気的に接続することができる。
2…液晶パネル
3…表示制御回路
4…ゲート線駆動回路
5…データ線駆動回路
6…バックライト
10…アクティブマトリクス基板
20…画素回路
21…TFT
22…画素電極
23…ゲート線
24…データ線
30…共通電極
40…対向基板
111…ゲート電極
121、151、152…SiNx膜
122…アモルファスSi膜
123…n+アモルファスSi膜
133、135…主導体部
134…導体部
141…IZO膜
143…ソース電極
144…ドレイン電極
Claims (16)
- 第1配線層に形成された複数のゲート線と、
第1半導体層、第2半導体層、第2配線層、および、画素電極層に形成された積層配線である複数のデータ線と、
前記ゲート線と前記データ線の交点に対応して配置され、それぞれがスイッチング素子および画素電極を含む複数の画素回路と、
前記ゲート線、前記データ線、前記スイッチング素子、および、前記画素電極よりも上層に形成された保護絶縁膜と、
前記保護絶縁膜の上層に形成された共通電極とを備え、
前記スイッチング素子は、
前記第1配線層に形成されたゲート電極と、
前記第2配線層に形成されたソース電極およびドレイン電極と、
前記第1半導体層に形成されたチャネル領域と、
前記第2半導体層において前記ソース電極および前記ドレイン電極の下に形成された半導体部と、
前記画素電極層において前記ソース電極および前記ドレイン電極の上に形成された導体部とを含み、
前記データ線の前記第2半導体層に形成された部分は、前記第2配線層および前記画素電極層に形成された部分よりも大きく形成され、前記半導体部は、前記ソース電極、前記ドレイン電極、および、前記導体部よりも大きく形成されていることを特徴とする、アクティブマトリクス基板。 - 前記データ線の前記第1半導体層に形成された部分は、前記第2半導体層に形成された部分よりも大きく形成されていることを特徴とする、請求項1に記載のアクティブマトリクス基板。
- 前記保護絶縁膜は、同じ材料を用いて異なる条件で成膜された下層絶縁膜と上層絶縁膜を含むことを特徴とする、請求項1に記載のアクティブマトリクス基板。
- 前記下層絶縁膜と前記上層絶縁膜の一方では圧縮応力が発生し、他方では引張応力が発生することを特徴とする、請求項3に記載のアクティブマトリクス基板。
- 前記下層絶縁膜の膜厚は150~350nmであり、前記上層絶縁膜の膜厚は400~600nmであることを特徴とする、請求項3に記載のアクティブマトリクス基板。
- 前記データ線の前記第2配線層に形成された部分、前記ソース電極、および、前記ドレイン電極は、モリブデンまたはモリブデンを含む材料で形成されていることを特徴とする、請求項1に記載のアクティブマトリクス基板。
- 前記データ線の前記第2配線層に形成された部分、前記ソース電極、および、前記ドレイン電極は、モリブデンとニオブの合金で形成されていることを特徴とする、請求項6に記載のアクティブマトリクス基板。
- 第1配線層に、複数のゲート線と、複数のスイッチング素子のゲート電極とを形成するステップと、
ゲート絶縁膜を成膜し、第1半導体層に第1半導体膜を成膜し、第2半導体層に第2半導体膜を成膜するステップと、
第2配線層に、複数のデータ線の主導体部の元になる第1導体部と、前記スイッチング素子のソース電極およびドレイン電極の元になる第2導体部とを形成すると共に、前記第1および第2半導体膜をパターニングすることにより、前記主導体部の下にある第1半導体部の元になる第2半導体部と、前記スイッチング素子の、前記第1半導体層にあるチャネル領域と、前記第2半導体層において前記ソース電極および前記ドレイン電極の下にある半導体部の元になる第3半導体部とを形成するソース層形成ステップと、
画素電極層に、画素電極と、前記主導体部の上にある第3導体部と、前記ソース電極および前記ドレイン電極の上にある導体部とを形成すると共に、前記第1および第2導体部、前記第2半導体部の前記第2半導体層に形成された部分、並びに、前記第3半導体部をパターニングすることにより、前記主導体部、前記ソース電極および前記ドレイン電極、前記第1半導体部、並びに、前記半導体部を形成する画素電極層形成ステップと、
前記画素電極の上層に保護絶縁膜を形成するステップと、
前記保護絶縁膜の上層に共通電極を形成するステップとを備え、
前記画素電極層形成ステップは、前記第1半導体部の前記第2半導体層に形成される部分を前記主導体部および前記第3導体部よりも大きく形成し、前記半導体部を前記ソース電極、前記ドレイン電極、および、前記導体部よりも大きく形成することを特徴とする、アクティブマトリクス基板の製造方法。 - 前記ソース層形成ステップは、前記第1半導体部の前記第1半導体層に形成される部分を前記第2半導体層に形成される部分よりも大きく形成することを特徴とする、請求項8に記載のアクティブマトリクス基板の製造方法。
- 前記画素電極層形成ステップは、成膜処理、フォトレジスト形成処理、エッチング処理、および、フォトレジスト剥離処理を含み、
前記エッチング処理は、前記フォトレジスト形成処理で形成されたフォトレジストをマスクとして、前記成膜処理で得られた膜と、前記第1および第2導体部とに対してウェットエッチングを行い、前記第2半導体部の前記第2半導体層に形成された部分と、前記第3半導体部とに対してドライエッチングを行うことを特徴とする、請求項8に記載のアクティブマトリクス基板の製造方法。 - 前記ソース層形成ステップで使用されるフォトマスクに含まれる前記第2半導体部を形成するためのパターンは、前記画素電極層形成ステップで使用されるフォトマスクに含まれる前記主導体部を形成するためのパターンよりも大きいことを特徴とする、請求項9に記載のアクティブマトリクス基板の製造方法。
- 前記保護絶縁膜を形成するステップは、同じ材料を用いて異なる条件で下層絶縁膜と上層絶縁膜を成膜する処理を含むことを特徴とする、請求項8に記載のアクティブマトリクス基板の製造方法。
- 前記下層絶縁膜と前記上層絶縁膜を成膜する処理は、一方では伸縮応力が発生し、他方では引張応力が発生する下層絶縁膜と上層絶縁膜を成膜することを特徴とする、請求項12に記載のアクティブマトリクス基板の製造方法。
- 前記下層絶縁膜と前記上層絶縁膜を成膜する処理は、膜厚150~350nmの下層絶縁膜と、膜厚400~600nmの上層絶縁膜とを成膜することを特徴とする、請求項12に記載のアクティブマトリクス基板の製造方法。
- 前記ソース層形成ステップは、前記第1および第2導体部をモリブデンまたはモリブデンを含む材料で形成することを特徴とする、請求項8に記載のアクティブマトリクス基板の製造方法。
- 前記ソース層形成ステップは、前記第1および第2導体部をモリブデンとニオブの合金で形成することを特徴とする、請求項15に記載のアクティブマトリクス基板の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016540106A JP6196387B2 (ja) | 2014-08-07 | 2015-06-24 | アクティブマトリクス基板 |
US15/323,440 US9869917B2 (en) | 2014-08-07 | 2015-06-24 | Active matrix substrate and method for manufacturing the same |
CN201580036053.1A CN106575062B (zh) | 2014-08-07 | 2015-06-24 | 有源矩阵基板及其制造方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014-161943 | 2014-08-07 | ||
JP2014161943 | 2014-08-07 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2016021320A1 true WO2016021320A1 (ja) | 2016-02-11 |
Family
ID=55263598
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2015/068178 WO2016021320A1 (ja) | 2014-08-07 | 2015-06-24 | アクティブマトリクス基板およびその製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9869917B2 (ja) |
JP (1) | JP6196387B2 (ja) |
CN (1) | CN106575062B (ja) |
WO (1) | WO2016021320A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10879273B2 (en) | 2018-07-02 | 2020-12-29 | Sharp Kabushiki Kaisha | Active matrix substrate |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019090939A (ja) * | 2017-11-15 | 2019-06-13 | シャープ株式会社 | アクティブマトリックス基板、表示装置、および制御方法 |
KR102406807B1 (ko) * | 2018-01-04 | 2022-06-13 | 삼성디스플레이 주식회사 | 윈도우 부재 |
CN110596975A (zh) * | 2018-06-12 | 2019-12-20 | 夏普株式会社 | 有源矩阵基板及其制造方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6194346A (ja) * | 1984-10-15 | 1986-05-13 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JPH0843853A (ja) * | 1994-07-27 | 1996-02-16 | Hitachi Ltd | 液晶表示装置およびその製造方法 |
JP2003297850A (ja) * | 2002-04-02 | 2003-10-17 | Advanced Display Inc | 薄膜トランジスタアレイ及びその製造方法並びにこれを用いた液晶表示装置 |
JP2012169610A (ja) * | 2011-01-28 | 2012-09-06 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法及び半導体装置 |
JP2013097349A (ja) * | 2011-11-07 | 2013-05-20 | Mitsubishi Electric Corp | 配線構造及びそれを備える薄膜トランジスタアレイ基板並びに表示装置 |
JP2013101232A (ja) * | 2011-11-09 | 2013-05-23 | Mitsubishi Electric Corp | 配線構造及びそれを備える薄膜トランジスタアレイ基板並びに表示装置 |
Family Cites Families (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100482468B1 (ko) * | 2000-10-10 | 2005-04-14 | 비오이 하이디스 테크놀로지 주식회사 | 프린지 필드 구동 액정 표시 장치 |
KR100707016B1 (ko) * | 2001-05-31 | 2007-04-11 | 비오이 하이디스 테크놀로지 주식회사 | 박막 트랜지스터 액정표시장치의 제조방법 |
JP4067090B2 (ja) * | 2002-10-03 | 2008-03-26 | シャープ株式会社 | Tft基板およびその製造方法 |
JP2005234091A (ja) * | 2004-02-18 | 2005-09-02 | Hitachi Displays Ltd | 表示装置 |
KR101221261B1 (ko) * | 2006-02-15 | 2013-01-11 | 엘지디스플레이 주식회사 | 액정 표시 장치용 어레이 기판 및 그 제조 방법 |
KR101182322B1 (ko) * | 2006-06-30 | 2012-09-20 | 엘지디스플레이 주식회사 | 수평 전계 인가형 박막 트랜지스터 기판 및 그 제조 방법 |
CN101421663B (zh) * | 2006-07-19 | 2012-06-13 | 夏普株式会社 | 有源矩阵基板、液晶面板、显示装置、电视接收机 |
KR100978266B1 (ko) * | 2006-12-29 | 2010-08-26 | 엘지디스플레이 주식회사 | 액정표시장치 및 그 제조방법 |
KR101076446B1 (ko) * | 2007-04-13 | 2011-10-25 | 엘지디스플레이 주식회사 | 박막 트랜지스터 기판 및 그를 구비하는 평판 표시장치 |
BRPI0915210A2 (pt) * | 2008-07-15 | 2016-02-16 | Sharp Kk | dispositivo de exibição |
JP5646162B2 (ja) | 2009-01-23 | 2014-12-24 | 三菱電機株式会社 | 薄膜トランジスタアレイ基板、その製造方法、及び液晶表示装置 |
JP5500712B2 (ja) * | 2009-09-02 | 2014-05-21 | 株式会社ジャパンディスプレイ | 液晶表示パネル |
KR101746198B1 (ko) * | 2009-09-04 | 2017-06-12 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 표시장치 및 전자기기 |
KR101286497B1 (ko) * | 2009-09-23 | 2013-07-16 | 엘지디스플레이 주식회사 | 시야각 조절 액정표시장치 |
US8804081B2 (en) * | 2009-12-18 | 2014-08-12 | Samsung Display Co., Ltd. | Liquid crystal display device with electrode having opening over thin film transistor |
US9599871B2 (en) * | 2011-11-18 | 2017-03-21 | Sharp Kabushiki Kaisha | Semiconductor device, display device, and method for producing semiconductor device |
WO2013099697A1 (ja) * | 2011-12-28 | 2013-07-04 | シャープ株式会社 | アクティブマトリクス基板 |
WO2014017406A1 (ja) * | 2012-07-27 | 2014-01-30 | シャープ株式会社 | 半導体装置およびその製造方法 |
US20150287799A1 (en) * | 2012-09-26 | 2015-10-08 | Sharp Kabushiki Kaisha | Semiconductor device, display panel, and semiconductor device manufacturing method |
US20150295092A1 (en) * | 2012-10-01 | 2015-10-15 | Sharp Kabushiki Kaisha | Semiconductor device |
CN107492357B (zh) * | 2012-10-30 | 2020-11-03 | 夏普株式会社 | 有源矩阵基板、显示面板以及具备该显示面板的显示装置 |
US9448454B2 (en) * | 2012-11-08 | 2016-09-20 | Sharp Kabushiki Kaisha | Active matrix substrate and display device |
CN104956475B (zh) * | 2013-01-25 | 2017-08-29 | 夏普株式会社 | 半导体装置 |
US9001297B2 (en) * | 2013-01-29 | 2015-04-07 | Apple Inc. | Third metal layer for thin film transistor with reduced defects in liquid crystal display |
WO2015045581A1 (ja) * | 2013-09-26 | 2015-04-02 | シャープ株式会社 | 表示部品及び表示装置 |
KR102021106B1 (ko) * | 2013-11-12 | 2019-09-11 | 엘지디스플레이 주식회사 | 액정표시장치용 어레이 기판 및 그 제조방법 |
US9971215B2 (en) * | 2013-11-21 | 2018-05-15 | Sharp Kabushiki Kaisha | Display device |
KR102204674B1 (ko) * | 2014-04-03 | 2021-01-20 | 삼성디스플레이 주식회사 | 표시 장치 |
US20170139296A1 (en) * | 2014-07-30 | 2017-05-18 | Sharp Kabushiki Kaisha | Display device and method for manufacturing same |
US10175518B2 (en) * | 2014-07-30 | 2019-01-08 | Sharp Kabushiki Kaisha | Method for manufacturing display device including a wiring layer of a molybdenum-based material |
WO2016021318A1 (ja) * | 2014-08-07 | 2016-02-11 | シャープ株式会社 | アクティブマトリクス基板、液晶パネル、および、アクティブマトリクス基板の製造方法 |
WO2016021319A1 (ja) * | 2014-08-07 | 2016-02-11 | シャープ株式会社 | アクティブマトリクス基板、液晶パネル、および、アクティブマトリクス基板の製造方法 |
CN104317089B (zh) * | 2014-10-27 | 2017-02-01 | 合肥鑫晟光电科技有限公司 | 一种阵列基板及其制备方法、显示面板、显示装置 |
JP6518576B2 (ja) * | 2015-11-27 | 2019-05-22 | 株式会社ジャパンディスプレイ | 表示装置及び表示装置のタッチ検出方法 |
-
2015
- 2015-06-24 WO PCT/JP2015/068178 patent/WO2016021320A1/ja active Application Filing
- 2015-06-24 JP JP2016540106A patent/JP6196387B2/ja active Active
- 2015-06-24 US US15/323,440 patent/US9869917B2/en active Active
- 2015-06-24 CN CN201580036053.1A patent/CN106575062B/zh active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6194346A (ja) * | 1984-10-15 | 1986-05-13 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JPH0843853A (ja) * | 1994-07-27 | 1996-02-16 | Hitachi Ltd | 液晶表示装置およびその製造方法 |
JP2003297850A (ja) * | 2002-04-02 | 2003-10-17 | Advanced Display Inc | 薄膜トランジスタアレイ及びその製造方法並びにこれを用いた液晶表示装置 |
JP2012169610A (ja) * | 2011-01-28 | 2012-09-06 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法及び半導体装置 |
JP2013097349A (ja) * | 2011-11-07 | 2013-05-20 | Mitsubishi Electric Corp | 配線構造及びそれを備える薄膜トランジスタアレイ基板並びに表示装置 |
JP2013101232A (ja) * | 2011-11-09 | 2013-05-23 | Mitsubishi Electric Corp | 配線構造及びそれを備える薄膜トランジスタアレイ基板並びに表示装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10879273B2 (en) | 2018-07-02 | 2020-12-29 | Sharp Kabushiki Kaisha | Active matrix substrate |
Also Published As
Publication number | Publication date |
---|---|
JPWO2016021320A1 (ja) | 2017-04-27 |
CN106575062B (zh) | 2019-11-08 |
JP6196387B2 (ja) | 2017-09-13 |
US9869917B2 (en) | 2018-01-16 |
US20170139298A1 (en) | 2017-05-18 |
CN106575062A (zh) | 2017-04-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10504800B2 (en) | Array substrate for display device and manufacturing method thereof | |
US8609477B2 (en) | Manufacturing method for array substrate with fringe field switching type thin film transistor liquid crystal display | |
US8497966B2 (en) | FFS type TFT-LCD array substrate and manufacturing method thereof | |
WO2017166341A1 (zh) | Tft基板的制作方法及制得的tft基板 | |
JP5315468B2 (ja) | アクティブマトリクス基板の製造方法、表示パネル、及び表示装置 | |
US20120161140A1 (en) | Tft array substrate and manufacturing method thereof | |
WO2016061940A1 (zh) | 薄膜晶体管阵列基板及其制作方法、显示装置 | |
US9299763B2 (en) | Thin film transistor array substrate and method of manufacturing the same | |
JP6497876B2 (ja) | 液晶表示パネル、及びその製造方法 | |
US20180190679A1 (en) | Thin film transistor substrate and method for manufacturing same | |
US9159867B2 (en) | Array substrate, manufacturing method thereof, and display device | |
KR102221845B1 (ko) | 표시 기판 및 그의 제조방법 | |
JP2013507771A (ja) | マスク・レベルを削減した金属酸化物fetの製造法 | |
KR20100005457A (ko) | 박막 트랜지스터 표시판 및 이의 제조 방법 | |
JP6218949B2 (ja) | アクティブマトリクス基板および液晶パネル | |
JP6501514B2 (ja) | 薄膜トランジスタ基板およびその製造方法 | |
JP6196387B2 (ja) | アクティブマトリクス基板 | |
WO2016021319A1 (ja) | アクティブマトリクス基板、液晶パネル、および、アクティブマトリクス基板の製造方法 | |
US8877570B2 (en) | Array substrate with improved pad region and method for manufacturing the same | |
WO2016201778A1 (zh) | 阵列基板及其制造方法 | |
JPWO2013011601A1 (ja) | 液晶表示装置およびその製造方法 | |
US20150187825A1 (en) | Method of Manufacturing Array Substrate of LCD | |
JP5560227B2 (ja) | 液晶表示装置の製造方法及び液晶表示装置 | |
US20190377232A1 (en) | Active matrix substrate and method for manufacturing the same | |
JPWO2016194804A1 (ja) | アクティブマトリクス基板、液晶パネル、および、アクティブマトリクス基板の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 15829729 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2016540106 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 15323440 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 15829729 Country of ref document: EP Kind code of ref document: A1 |