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WO2016090621A1 - 数据存储的方法和装置 - Google Patents

数据存储的方法和装置 Download PDF

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Publication number
WO2016090621A1
WO2016090621A1 PCT/CN2014/093653 CN2014093653W WO2016090621A1 WO 2016090621 A1 WO2016090621 A1 WO 2016090621A1 CN 2014093653 W CN2014093653 W CN 2014093653W WO 2016090621 A1 WO2016090621 A1 WO 2016090621A1
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WIPO (PCT)
Prior art keywords
data
target
ber
written
page
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PCT/CN2014/093653
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English (en)
French (fr)
Inventor
徐君
杨伟
刘海燕
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201480036916.0A priority Critical patent/CN106415502B/zh
Priority to PCT/CN2014/093653 priority patent/WO2016090621A1/zh
Publication of WO2016090621A1 publication Critical patent/WO2016090621A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes

Definitions

  • the present invention relates to the field of data storage and, more particularly, to a method and apparatus for data storage.
  • SSDs solid state drives
  • SLC single-level storage unit
  • MLC multi-state storage unit
  • MSB Most Significant Bit
  • LSB Least Significant Bit
  • Flash memory represents stored data based on how much electrons are stored in its floating gate electrode.
  • the data states exhibited by the memory cells are "00", “01", “10” and “11", respectively.
  • the error rate of the flash memory is related to the data state represented in the memory unit of the flash memory, that is, the different data states exhibited by the memory cells have different bit error rates (BER), and the main causes of the bit error rate are also Not the same.
  • the flash page in flash memory is a read-write unit, and the types of flash pages include MSB pages and LSB pages.
  • the existing data storage method writes data written to a flash page based on an Error Correction Code (ECC) algorithm, and corrects errors in the data according to the ECC algorithm.
  • ECC Error Correction Code
  • the method uses a fixed ECC algorithm and error correction bits to correct the errored data and uses fixed ECC error correction capability. This method cannot match the appropriate error correction capability, which causes the error correction capability of the ECC algorithm to be wasted, thus resulting in a large amount of calculation of the error correction.
  • Embodiments of the present invention provide a data storage method and apparatus, which can reduce the calculation amount of data error correction on the basis of ensuring data correctness.
  • a method of data storage is provided, the method being applied to a non-volatile memory
  • the method includes: receiving a write request, the write request including data to be written and an address; determining a type of the target flash page according to the address, wherein the target flash page stores the to-be-written in the non-volatile memory a flash page of data; calculating a predicted bit error rate BER of the target flash page according to the determined type of the target flash page and the data to be written; determining a target of the data to be written according to the predicted BER of the target flash page
  • the error correction code ECC algorithm and the target error correction bit number; the data to be written is written to the target flash page according to the determined target ECC algorithm and the target error correction bit number.
  • the target error correction code ECC algorithm and the target error correction bit number of the data to be written are determined according to the predicted BER of the target flash page, including Determining the target ECC algorithm of the data to be written and the target error correction bit according to the predicted BER of the target flash page and the preset correspondence between the predicted BER of the target flash page and the error correction capability information,
  • the error correction capability information includes an ECC algorithm and an error correction bit number.
  • the predicted bit error rate BER of the target flash page includes: calculating a predicted BER of the target flash page according to a type of the target flash page and the to-be-written data by using a BER calculation method corresponding to the type of the target flash page.
  • the BER is calculated as: The B MSB is the predicted BER of the MSB page; the P 00 is the proportion of the 00 in the data to be written; the P 10 is the proportion of 10 in the data to be written; The BER of the left-biased error for the preset write 00; A BER with a right-biased error occurs for a preset write of 10.
  • the BER is calculated as: The B LSB is the predicted BER of the LSB page; the P 11 is the proportion of the 11 to be written data; the P 10 is the proportion of the 10 to be written data; the P 00 is the waiting The proportion of 00 in the written data; the P 01 is the proportion of 01 in the data to be written; The BER of the right-biased error occurs for the preset write 11; a BER that causes a left-biased error for a preset write of 10; The BER of the right-biased error occurs for the preset write 00; The BER of the left-biased error occurs for the preset write 01.
  • the data to be written is written to the target flash page according to the determined target ECC algorithm and the target error correction bit number
  • the method includes: recording the target ECC algorithm and the target error correction bit number.
  • a device configured to apply to a non-volatile memory, comprising: a receiving module, configured to receive a write request, the write request includes data and an address to be written; and a type determining module, configured to The address determines a type of the target flash page, wherein the target flash page is a flash page in the non-volatile memory that stores the data to be written; and a calculation module, configured to determine, according to the type, the target flash page determined by the module Type and the data to be written, calculating a predicted bit error rate BER of the target flash page; an algorithm determining module, configured to determine a target error correction code ECC algorithm and target of the to-be-written data according to the predicted BER of the target flash page An error correction bit; a writing module, configured to write the data to be written to the target flash page according to the target ECC algorithm determined by the algorithm determining module and the target error correction bit number.
  • a receiving module configured to receive a write request, the write request includes data and an address to be written
  • the algorithm determining module is specifically configured to: predict a BER according to the target flash page, and predict BER and error correction according to the preset target flash page Corresponding relationship of the capability information, the target ECC algorithm of the data to be written and the target error correction bit number are determined, and the error correction capability information includes an ECC algorithm and an error correction bit number.
  • the calculating module is specifically configured to: according to the type of the target flash page and the to-be-written The incoming data is calculated by the BER calculation method corresponding to the type of the target flash page, and the predicted BER of the target flash page is calculated.
  • the calculating module is specifically configured to: calculate according to the BER the way: Calculating a predicted BER of the target flash page, wherein the B MSB is a predicted BER of the MSB page; the P 00 is a proportion of 00 in the to-be-written data; the P 10 is 10 of the to-be-written data Ratio The BER of the left-biased error for the preset write 00; A BER with a right-biased error occurs for a preset write of 10.
  • the calculating module is specifically configured to: calculate according to the BER the way: Calculating a predicted BER of the target flash page, wherein the B LSB is a predicted BER of the LSB page; the P 11 is a proportion of the 11 to be written data; the P 10 is 10 of the to-be-written data ratio; P 00 the proportion of the write data to be for 00; P 01 for the data to be written to the proportion of 01; the The BER of the right-biased error occurs for the preset write 11; a BER that causes a left-biased error for a preset write of 10; The BER of the right-biased error occurs for the preset write 00; The BER of the left-biased error occurs for the preset write 01.
  • the fifth possible implementation manner of the second aspect further includes: a recording module, Used to record the target ECC algorithm and the target number of error correction bits.
  • the bit error rate is predicted for the data to be written to the flash page, the appropriate ECC algorithm and the number of error correction bits are selected according to the predicted bit error rate, and the selected ECC algorithm and the number of error correction bits are to be written.
  • the data entered into the flash page is written to the flash page to facilitate error correction of the data in which the error occurred.
  • the method can select an appropriate ECC algorithm and the number of error correction bits, thereby saving the error correction capability of the ECC algorithm and reducing the calculation amount of error correction on the basis of ensuring the correctness of the data.
  • FIG. 1 is a schematic diagram of an error model of a data state of a flash memory cell of the present invention.
  • FIG. 2 is a schematic flow chart of a method of data storage according to an embodiment of the present invention.
  • FIG. 3 is a schematic flowchart of a method for data storage according to another embodiment of the present invention.
  • FIG. 4 is a schematic flow chart of a method of data storage according to an embodiment of the present invention.
  • FIG. 5 is a schematic block diagram of an apparatus in accordance with one embodiment of the present invention.
  • Figure 6 is a schematic block diagram of an apparatus in accordance with another embodiment of the present invention.
  • FIG. 1 is a schematic diagram of an error model of a data state of a flash memory cell of the present invention.
  • the flash memory represents the stored data according to the amount of electrons stored in its floating gate electrode. of.
  • the data states exhibited by the memory cells are "00", “01", “10” and “11", respectively.
  • the error rate of the flash memory is related to the data state represented in the memory unit of the flash memory, that is, the different data states exhibited by the memory cells have different bit error rates (BER), and the main causes of the bit error rate are also Not the same.
  • the flash page in flash memory is a read-write unit, and the types of flash pages include MSB pages and LSB pages.
  • the two main errors are errors and programming errors caused by leakage.
  • the abscissa V is a voltage value expressed by a memory cell
  • the ordinate P is a distribution of cells.
  • the leakage error will cause the electrons in the memory cell to leak, causing the voltage to drop, causing the data state to shift to the left.
  • This error is a left-biased error. Due to the repeated program erase of the flash chip and the programming operation of the nearby chip, the electrons in the flash memory chip rise, and the data state is right-biased. This error is a right-bias error.
  • FIG. 2 is a schematic flow chart of a method of data storage according to an embodiment of the present invention.
  • the method of Figure 2 can be performed by the apparatus shown in Figure 5, which can be a non-volatile memory.
  • the method includes:
  • 201 Receive a write request, where the write request includes data to be written and an address.
  • Flash memory pages are used to read data or write data.
  • a write request can be received, which can include data to be written and an address.
  • the target flash page is a flash page in the non-volatile memory that stores the data to be written.
  • the data to be written can be written to different types of flash pages according to the address in the write request.
  • the types of flash pages include MSB pages and LSB pages.
  • An error may occur during the writing process, which may be a left-biased error or a right-biased error.
  • the written data should be "10".
  • a right-biased error occurs, the written data becomes "00", that is, the data "1" written to the MSB page is changed to a right-off error to become "0".
  • the type of target flash page may be a flash page for storing different bit data.
  • the type of the target flash page is related to the number of bit data storable by each storage unit in the target flash page. If the bit data storable by each storage unit in the target flash page is 2-bit data, the data to be written is
  • the bit data respectively written in each storage unit of the target flash page may include high-order bit data, that is, Most Significant Bit (MSB) data and low-order bit data, that is, Least Significant Bit (referred to as Least Significant Bit). LSB).
  • the type of the target flash page may include an MSB page for storing MSB data and an LSB page for storing LSB data.
  • bit data that can be stored in each storage unit of the target flash page is data of 4 or more bits
  • the bit data of each storage unit in the target flash page respectively written in the data to be written may further include other Bit data of the bit, correspondingly, the type of the target flash page may further include a flash page for storing the other bit data.
  • the type of flash page can be determined based on the address in the write request.
  • the bit error rate (BER) of this type of flash page can be predicted based on the type of flash page determined by the data and address to be written.
  • the predicted bit error rate of the flash page can be the predicted bit error rate of the MSB page or the predicted bit error rate of the LSB page.
  • the different types of flash pages may correspond to different computing methods.
  • the different calculation methods are divided into a calculation method of the prediction bit error rate corresponding to the MSB page and a calculation method of the prediction bit error rate corresponding to the LSB page.
  • the BER of the target flash page is calculated according to the type of the target flash page and the data to be written. For example, according to the type of the target flash page, combined with the specific content of the data to be written, the calculation is performed.
  • the BER of the target flash page may be a distribution of different data types in the data to be written, and the different data types may be different bit data, such as a specific distribution of 0 and 1.
  • the BER of the target flash page may also be a Content Dependent Bit Error Rate (CDBER).
  • CDBER Content Dependent Bit Error Rate
  • the BER of the target flash page may be calculated, for example, according to the type of the target flash page and the distribution of different types of data in the data to be written, such as the distribution of 11, 10, 01, and 00. .
  • the target flash page is an MSB page, it can be based on The predicted bit error rate of the MSB page selects the target ECC algorithm corresponding to the MSB page and the target error correction bit number; if the target flash page is an LSB page, the target ECC algorithm corresponding to the LSB page may be selected based on the predicted bit error rate of the LSB page and The number of target error corrections.
  • the ECC algorithm may be a BCH (Bose Ray-Chaudhuri Hocquenghem) algorithm, and the error correction bit number may be N bits, and N is a positive integer greater than or equal to 1.
  • BCH Bit-Chaudhuri Hocquenghem
  • the data to be written to the MSB page can be written to the MSB page according to the target ECC algorithm corresponding to the MSB page and the target number of error correction bits. And correcting the error data; if the target flash page is an LSB page, the data to be written to the LSB page can be written into the LSB page according to the target ECC algorithm corresponding to the LSB page and the target error correction bit number, and Error data occurred for error correction. That is to say, the operation of the flash page in the embodiment of the present invention may operate on the MSB page, and may also operate on the LSB page, and the present invention is not limited thereto.
  • the ECC algorithm and the number of error correction bits are selected for error correction.
  • the write error can be a Content Dependent Bit Error Rate (CDBER).
  • the embodiments of the present invention may be applied to a non-volatile memory, and may also be applied to a memory using a flash memory granule as a storage medium, such as a solid-state hard disk SSD, a flash memory card capable memory.
  • a flash memory granule as a storage medium, such as a solid-state hard disk SSD, a flash memory card capable memory.
  • the bit error rate is predicted for the data to be written to the flash page, the appropriate ECC algorithm and the number of error correction bits are selected according to the predicted bit error rate, and the selected ECC algorithm and the number of error correction bits are to be written.
  • the data of the flash page is written to the flash page to facilitate error correction of the data in which the error occurred.
  • the method can select an appropriate ECC algorithm and the number of error correction bits, and save the error correction capability of the ECC algorithm, thereby reducing the amount of error correction calculation.
  • the predicted BER of the target flash page may be calculated according to the type of the target flash page and the data to be written, using a BER calculation manner corresponding to the type of the target flash page.
  • the type of the target flash page is divided into an MSB page and an LBS page, and the MSB page and the LSB page respectively correspond to different BER calculation modes.
  • the ratio of the four data states to the write data can be obtained.
  • the proportion of different data states in the write data and the BER of the preset write data Ability to calculate the predicted bit error rate of a flash page.
  • the BER of the preset write data can be obtained based on experimental data and empirical values.
  • the flash page includes the MSB page and the LSB page
  • the method of calculating the predicted bit error rate of the flash page is also applicable to the MSB page and the LSB page. That is, the flash page in the embodiment of the present invention can be replaced with an MSB page or an LSB page. In this way, the predicted bit error rate of the MSB page and the LSB page can be separately calculated, and the ECC algorithm and the error correction bit number can be respectively selected, thereby respectively correcting the write data of the MSB page and the LSB page.
  • the BER calculation manner may be:
  • B MSB is the predicted BER of the MSB page
  • P 00 is the proportion of 00 in the data to be written
  • P 10 is the proportion of 10 in the data to be written
  • the BER of the left-biased error occurs for the preset write 00
  • a BER with a right-biased error occurs for a preset write of 10.
  • the BER is calculated as:
  • B LSB is the predicted BER of the LSB page;
  • P 11 is the proportion of 11 in the data to be written;
  • P 10 is the proportion of 10 in the data to be written;
  • P 00 is the proportion of 00 in the data to be written.
  • P 01 is the proportion of 01 in the data to be written;
  • the BER of the right-biased error occurs for the preset write 11;
  • the BER of the left-biased error occurs for the preset write 10;
  • the BER of the right-biased error occurs for the preset write 00;
  • the BER of the left-biased error occurs for the preset write 01.
  • the proportion of the data state to which the data belongs can be obtained.
  • the proportions of the four data states be P 11 , P 10 , P 00 , P 01 , respectively .
  • P 11 represents the proportion of “11” in the data to be written
  • P 10 represents the proportion of “10” in the data to be written
  • P 00 represents the proportion of “00” in the data to be written
  • P 01 represents the proportion of "01" in the data to be written.
  • the BER of the preset data written to the flash page may include a left-biased error and a right-biased error.
  • Left-handed errors can include: among them, The BER of the left-biased error occurs for the preset write 11 For the default write of 10, the BER of the left-biased error occurs. The BER of the left-biased error occurs for the preset write 00, The BER of the left-biased error occurs for the preset write 01.
  • Right deviation errors can include: among them, The BER of the right-biased error occurs for the preset write 11 The BER of the right-biased error occurs for the default write of 10, The BER of the right-biased error occurs for the preset write 00, The BER of the right-biased error occurs for the preset write 01. Can be drawn from Figure 1
  • the formula for calculating the predicted bit error rate of the MSB page and the LSB page can be as follows:
  • the embodiment of the present invention may determine, according to the predicted BER of the target flash page and the correspondence between the predicted BER and the error correction capability information of the preset target flash page, to be written.
  • the target ECC algorithm of the data and the target error correction bit number, and the error correction capability information includes the ECC algorithm and the number of error correction bits.
  • the error correction capability information of the ECC algorithm has a correspondence relationship with the predicted BER of the flash page.
  • the error correction capability of the ECC algorithm indicates that the ECC algorithm and the number of error correction bits can correct a range of bit error rates. Different ECC algorithms and error correction bits can correct a range of bit error rates. That is, there is a correspondence between different ECC algorithms and the number of error correction bits and the bit error rate.
  • the correspondence between the predicted BER of the preset target flash page and the error correction capability information may be set according to empirical data.
  • the preset ECC algorithm and the correspondence between the number of error correction bits and the predicted BER of the target flash page can achieve the purpose of ensuring data reliability and minimizing the computational overhead of the ECC.
  • the page theoretical minimum error rate and the page theoretical maximum error rate of the flash page may be set first, and the range of the set page theoretical minimum BER to the page theoretical maximum BER bit error rate is divided into multiple bit error rates. of range.
  • the range of different bit error rates may correspond to different error correction capability information. That is to say, the range of the bit error rate that can be corrected by the ECC algorithm and the number of error correction bits is the range of the bit error rate corresponding to the ECC algorithm and the number of error correction bits.
  • the embodiment of the present invention may determine N error rate ranges corresponding to N error correction capability information, where N is greater than or equal to 1; and determine, from the N bit error rate ranges, a predicted bit error rate of the flash page.
  • the target bit error rate range; the ECC algorithm and the number of error correction bits corresponding to the target bit error rate range are determined as the target ECC algorithm and the target error correction bit number.
  • the correctable bit error rate of the ECC algorithm and the error correction bit number selected by the embodiment of the present invention is greater than the predicted bit error rate of the flash page, and the ECC error correction capability can be saved on the basis of ensuring data reliability, thereby reducing calculation. Volume, improve system performance and space utilization.
  • the correspondence between the error correction capability information of the ECC algorithm and the bit error rate of the flash page may be expressed as the error correction capability information of the ECC algorithm corresponding to a certain bit error rate range.
  • the N error correction capability information may correspond to an N bit error rate range. If the predicted bit error rate of the target flash page belongs to the target bit error rate range in the N bit error rate range, the ECC algorithm corresponding to the target bit error rate range and the error correction bit number may be used to write the data information of the flash page. Make corrections.
  • the flash page in embodiments of the present invention may be replaced with an MSB page or an LSB page.
  • the minimum and maximum values of the bit error rate in the N bit error rate ranges are determined based on the predicted bit error rate of the target flash page.
  • the minimum value of the bit error rate is the page theoretical minimum BER
  • the maximum value of the bit error rate is the page theoretical maximum BER.
  • the correspondence between the N error correction capability information and the N bit error rate ranges can be established as follows according to the above description.
  • the bit error rate range of the moderately divided table 1 corresponds to the corresponding ECC algorithm and the number of error correction bits, and the ECC algorithm and the number of error correction bits are set to an error correction level.
  • the correspondence between the error correction capability information of the ECC algorithm and the bit error rate will be described in detail in conjunction with Table 1 below.
  • CDBER min is the page theory minimum bit error rate
  • CDBER max is the page theoretical maximum bit error rate.
  • the embodiment of the present invention may use the CDBER min corresponding to the MSB page and the smaller CDBER min corresponding to the LSB page as the CDBER in the correspondence table of Table 1.
  • min i.e. the theoretical minimum bit error rate p
  • the MSB page and the LSB page use the same correspondence table in common.
  • the ECC algorithm in the embodiment of the present invention selects the BCH algorithm, and other ECC algorithms may also be used, and the embodiment of the present invention is not limited thereto.
  • the bit error rate range is the same. That is, the range of CDBER min -CDBER 1 can be the same as the range of CDBER 1-CDBER 2. If the number of N error correction bits is non-equal, the range of bit error rates is also different. For example, when the error correction level is 0, the bit error rate range corresponding to 1 bit of the error correction bit number is CDBER min -CDBER 1, and when the error correction level is 1, the bit error rate range corresponding to 3 bits of the error correction bit number is 2 Double CDBER min -CDBER 1.
  • the embodiment of the present invention may look up Table 1 and determine the bit error rate range in which the calculated predicted BER of the target flash page falls, and select the bit error rate.
  • the range corresponding ECC algorithm and the number of error correction bits write the data to be written to the flash memory, and correct the errored data according to the selected ECC algorithm and the number of error correction bits. For example, if the predicted bit error rate of the MSB page is within the bit error rate range corresponding to the error correction level of 1, the BCH algorithm and the 2 bit error correction bit number are selected to write the data to the MSB page.
  • FIG. 3 is a schematic flowchart of a method for data storage according to another embodiment of the present invention.
  • the same steps in Fig. 3 as those in Fig. 2 are given the same reference numerals.
  • the method can be performed by the apparatus shown in FIG. 5, and the method can further include:
  • a data prediction bit error rate is written for a flash memory page, an appropriate ECC algorithm and an error correction bit number are selected according to the predicted bit error rate, and the selected ECC algorithm and the number of error correction bits are to be written.
  • the data of the flash page is written to the flash memory to facilitate correction of the data in which the error occurred.
  • the method can select an appropriate ECC algorithm and the number of error correction bits, and save the error correction capability of the ECC algorithm, thereby reducing the calculation amount of the error correction process.
  • the target ECC algorithm and the target error correction bit number may be recorded, and the corresponding error correction level may also be recorded.
  • the embodiment of the present invention may call the error correction level, and perform error correction using the ECC algorithm corresponding to the error correction level and the number of error correction bits.
  • FIG. 4 is a schematic flow chart of a method of data storage according to an embodiment of the present invention. The process can be performed by the apparatus shown in FIG. 5, which can be a solid state drive SSD, the method comprising:
  • the type of the flash page is determined based on the address in the write request.
  • the types of flash pages are divided into MSB pages and LSB pages.
  • the flash page is an MSB page
  • the data to be written may be data of one flash page in the flash memory.
  • a flash page can be 4KB or 8KB in size.
  • the embodiment of the present invention does not limit the size of the flash page.
  • the proportion of the data state to which the data belongs can be obtained.
  • the proportions of the four data states be P 11 , P 10 , P 00 , P 01 , respectively .
  • P 11 represents the proportion of “11” in the data to be written
  • P 10 represents the proportion of “10” in the data to be written
  • P 00 represents the proportion of “00” in the data to be written
  • P 01 represents the proportion of "01" in the data to be written.
  • the BER of the preset data written to the flash page may include a left-biased error and a right-biased error.
  • the left bias error to include: among them, The BER of the left-biased error occurs for the preset write 11 For the default write of 10, the BER of the left-biased error occurs. The BER of the left-biased error occurs for the preset write 00, The BER of the left-biased error occurs for the preset write 01. Can be drawn from Figure 1
  • the BER of the right-biased error occurs for the preset write 11
  • the BER of the right-biased error occurs for the default write of 10
  • the BER of the right-biased error occurs for the preset write 00
  • the BER of the right-biased error occurs for the preset write 01.
  • the predicted BER of the LSB page is calculated according to the proportion of the four data states in the data to be written and the BER of the preset write data.
  • the error correction capability information includes an ECC algorithm and an error correction bit number.
  • the correspondence between the error correction capability information of the ECC algorithm and the bit error rate of the flash page may be expressed as the error correction capability information of the ECC algorithm corresponding to a certain bit error rate range.
  • the N error correction capability information may correspond to an N bit error rate range. If the predicted bit error rate of the target flash page belongs to the target bit error rate range in the N bit error rate range, the ECC algorithm corresponding to the target bit error rate range and the error correction bit number may be used to write the data information of the flash page. Make corrections.
  • the minimum and maximum values of the bit error rate in the N bit error rate ranges are determined based on the predicted bit error rate of the target flash page.
  • the minimum value of the BER corresponding to the MSB page and the minimum value of the BER corresponding to the LSB page may be used as the page theoretical minimum bit error rate; and the maximum value of the BER corresponding to the MSB page corresponds to the LSB page.
  • the larger of the maximum values of BER is used as the page theoretical maximum bit error rate.
  • the MSB page and the LSB page use the same correspondence table in common.
  • the ECC algorithm and the number of error correction bits may correspond to an error correction level.
  • the error correction level can also be recorded in the embodiment of the present invention.
  • the embodiment of the present invention may call the error correction level of the record, and use the ECC algorithm corresponding to the error correction level and the number of error correction bits to correct the error data in the data written in the flash page. wrong.
  • the embodiment of the present invention may perform error correction on data that is erroneous in the data written in the MSB page according to the ECC algorithm and the number of error correction bits selected by the predicted bit error rate of the MSB page, or may be based on the predicted bit of the LSB page.
  • the error rate selected ECC algorithm and the number of error correction bits correct the error data in the data written to the LSB page.
  • the bit error rate is predicted for the data to be written to the flash page, the appropriate ECC algorithm and the number of error correction bits are selected according to the predicted bit error rate, and the selected ECC algorithm and the number of error correction bits are to be written.
  • the data of the flash page is written to the flash page to facilitate error correction of the data in which the error occurred.
  • the method can select an appropriate ECC algorithm and the number of error correction bits, and save the error correction capability of the ECC algorithm, thereby reducing the amount of error correction calculation.
  • FIG. 5 is a schematic block diagram of an apparatus in accordance with one embodiment of the present invention.
  • the apparatus shown in FIG. 5 can implement the methods of FIGS. 2 and 3 described above and the process of FIG.
  • the device can be a non-volatile memory, and the device 50 includes:
  • the receiving module 51 is configured to receive a write request, where the write request includes data to be written and an address;
  • the type determining module 52 is configured to determine a type of the target flash page according to the address, wherein the target flash page is a flash page in the non-volatile memory that stores the data to be written;
  • the calculating module 53 is configured to calculate a predicted bit error rate BER of the target flash page according to the type of the target flash page determined by the type determining unit and the data to be written;
  • the algorithm determining module 54 is configured to determine a target error correction code ECC algorithm and a target error correction bit number of the data to be written according to the predicted BER of the target flash page;
  • a writing module 55 configured to determine, according to an algorithm, a target ECC algorithm and target error correction determined by the module The number of bits writes the data to be written to the target flash page.
  • the bit error rate is predicted for the data to be written to the flash page, the appropriate ECC algorithm and the number of error correction bits are selected according to the predicted bit error rate, and the selected ECC algorithm and the number of error correction bits are to be written.
  • the data of the flash page is written to the flash page to facilitate error correction of the data in which the error occurred.
  • the method can select an appropriate ECC algorithm and the number of error correction bits, and save the error correction capability of the ECC algorithm, thereby reducing the amount of error correction calculation.
  • the algorithm determining module 54 may determine the target ECC of the data to be written according to the predicted BER of the target flash page and the corresponding relationship between the predicted BER and the error correction capability information of the preset target flash page.
  • the algorithm and the target error correction bit number, the error correction capability information includes the ECC algorithm and the number of error correction bits.
  • the calculating module 53 may calculate the predicted BER of the target flash page according to the type of the target flash page and the data to be written, using a BER calculation manner corresponding to the type of the target flash page.
  • the calculation module 53 may calculate according to the BER:
  • B MSB is the predicted BER of the MSB page
  • P 00 is the proportion of 00 in the data to be written
  • P 10 is the proportion of 10 in the data to be written
  • the BER of the left-biased error occurs for the preset write 00
  • a BER with a right-biased error occurs for a preset write of 10.
  • the calculation module 53 may calculate according to the BER:
  • B LSB is the predicted BER of the LSB page
  • P 11 is the proportion of 11 in the data to be written
  • P 10 is the proportion of 10 in the data to be written
  • P 00 is The proportion of 00 to be written in the data
  • P 01 is the proportion of 01 in the data to be written
  • the BER of the right-biased error occurs for the preset write 11
  • the BER of the left-biased error occurs for the preset write 10
  • the BER of the right-biased error occurs for the preset write 00
  • the BER of the left-biased error occurs for the preset write 01.
  • the apparatus 50 may further include a recording module 56 for recording the target ECC algorithm and the target error correction bit number.
  • FIG. 6 is a schematic block diagram of an apparatus in accordance with another embodiment of the present invention.
  • the apparatus 60 of FIG. 6 can be used to implement the steps and methods of the above method embodiments.
  • the apparatus of FIG. 6 includes a processor 61 and a memory 62.
  • the processor 61 and the memory 62 are connected by a bus system 69.
  • the processor 61 controls the operation of the device 60.
  • Memory 62 can include read only memory and random access memory and provides instructions and data to processor 61.
  • a portion of memory 62 may also include non-volatile line random access memory (NVRAM).
  • NVRAM non-volatile line random access memory
  • the various components of device 60 are coupled together by a bus system 69, which in addition to the data bus includes a power bus, a control bus, and a status signal bus. However, for clarity of description, various buses are labeled as bus system 69 in the figure.
  • Processor 61 may be an integrated circuit chip with signal processing capabilities.
  • the processor 61 described above may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or discrete hardware. Component.
  • the methods, steps, and logical block diagrams disclosed in the embodiments of the present invention may be implemented or carried out.
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the processor 61 reads the information in the memory 62 in conjunction with the various components of its hardware control device 60.
  • device 60 performs the following operations:
  • the target flash page is a flash page in the non-volatile memory that stores the data to be written
  • the data to be written is written to the target flash page according to the determined target ECC algorithm and the target number of error correction bits.
  • the bit error rate is predicted for the data to be written to the flash page
  • the appropriate ECC algorithm and the number of error correction bits are selected according to the predicted bit error rate, and the selected ECC algorithm and the number of error correction bits are to be written.
  • the data of the flash page is written to the flash page to correct the data with errors. wrong.
  • the method can select an appropriate ECC algorithm and the number of error correction bits, and save the error correction capability of the ECC algorithm, thereby reducing the amount of error correction calculation.
  • the processor 61 may determine a target ECC algorithm to be written according to a predicted BER of the target flash page and a corresponding relationship between the predicted BER of the target flash page and the error correction capability information. And the target error correction bit number, the error correction capability information includes the ECC algorithm and the number of error correction bits.
  • the processor 61 may calculate the predicted BER of the target flash page according to the type of the target flash page and the data to be written, using a BER calculation manner corresponding to the type of the target flash page.
  • the BER is calculated as: Wherein, B MSB is the predicted BER of the MSB page; P 00 is the proportion of 00 in the data to be written; P 10 is the proportion of 10 in the data to be written; The BER of the left-biased error occurs for the preset write 00; A BER with a right-biased error occurs for a preset write of 10.
  • the BER is calculated as: Among them, B LSB is the predicted BER of the LSB page; P 11 is the proportion of 11 in the data to be written; P 10 is the proportion of 10 in the data to be written; P 00 is the proportion of 00 in the data to be written. Ratio; P 01 is the proportion of 01 in the data to be written; The BER of the right-biased error occurs for the preset write 11; The BER of the left-biased error occurs for the preset write 10; The BER of the right-biased error occurs for the preset write 00; The BER of the left-biased error occurs for the preset write 01.
  • the processor 61 may also record the target ECC algorithm and the target number of error correction bits.
  • system and “network” are used interchangeably herein.
  • the word “and/or” is merely an association relationship describing the associated object, indicating that there may be three relationships, for example, A and/or B, which may indicate that A exists separately, A and B exist simultaneously, and B exists separately. three situations.
  • the character “/” in this article generally indicates that the contextual object is an "or" relationship.
  • B corresponding to A means that B is associated with A, and B can be determined according to A.
  • determining B from A does not mean that B is only determined based on A, and that B can also be determined based on A and/or other information.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, or an electrical, mechanical or other form of connection.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present invention.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or software. The form of the functional unit is implemented.
  • Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a computer.
  • computer readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage media or other magnetic storage device, or can be used for carrying or storing in the form of an instruction or data structure.
  • connection may suitably be a computer readable medium.
  • the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave
  • coaxial cable , fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, wireless, and microwave are included in the fixing of the associated media.
  • a disk and a disc include a compact disc (CD), a laser disc, a compact disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data. Combinations of the above should also be included within the scope of the computer readable media.
  • CD compact disc
  • DVD digital versatile disc
  • floppy disk a compact disc
  • Blu-ray disc wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data.

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Abstract

本发明实施例提供了一种数据存储的方法和装置，该方法包括：接收写请求，写请求包括待写入数据和地址；根据地址确定目标闪存页的类型；根据目标闪存页的类型及待写入数据，计算目标闪存页的预测BER；根据目标闪存页的预测BER，确定待写入数据的目标ECC算法和目标纠错位数；根据目标ECC算法和目标纠错位数将待写入数据写入目标闪存页。本发明实施例中针对待写入闪存页的数据预测比特错误率，根据预测的比特错误率选择合适的ECC算法和纠错位数，并使用该ECC算法和纠错位数将待写入闪存页的数据写入闪存页，以便于对出现错误的数据进行纠错。该方法能够选择适当的ECC算法和纠错位数，节约ECC算法的纠错能力，因而能够降低纠错的计算量。

Description

数据存储的方法和装置 技术领域
本发明涉及数据存储领域，并且更具体地，涉及数据存储的方法和装置。
背景技术
数据存储领域常用的数据载体是机械硬盘和固态硬盘(Solid State Drive，SSD)。SSD具有高性能、低延迟、低功耗、环境适应性强等优点，同时成本也在不断降低，因此，SSD的应用越来越普遍。
随着闪存存储技术的发展，由原先一个存储单元存储一个比特的单状态存储单元(Single Level Cell，SLC)到现在一个存储单元存储两个比特的多状态存储单元(Multiple Level Cell，MLC)。MLC中的两个比特位分别称为最高有效比特位(Most Significant Bit，MSB)和最低有效比特位(Least Significant Bit，LSB)。
闪存是根据存储到其浮栅电极中的电子多少来表示存储的数据的。当闪存的存储单元中存储的电子所表示出来的电压值在不同的区域，则该存储单元表现出的数据状态分别为“00”，“01”，“10”和“11”。闪存的错误率与闪存的存储单元中所表示的数据状态相关，即存储单元表现出的不同数据状态具有不同的比特错误率(Bit Error Rate，BER)，并且比特错误率产生的主要原因也各不相同。闪存中的闪存页为读写单元，闪存页的类型包括MSB页和LSB页。
现有的数据存储方法对写入闪存页的数据基于错误纠正码(Error Correction Code，ECC)算法进行写入，并根据ECC算法对出现错误的数据进行纠错。该方法采用固定的ECC算法和纠错位数对出现错误的数据进行纠错，并采用固定的ECC纠错能力。该方法不能够匹配适当的纠错能力，造成ECC算法的纠错能力浪费，因而导致该纠错的计算量较大。
发明内容
本发明实施例提供了一种数据存储的方法和装置，能够在保证数据正确性的基础上减少数据纠错的计算量。
第一方面，提供了一种数据存储的方法，该方法应用于非易失性存储器 中，该方法包括：接收写请求，该写请求包括待写入数据和地址；根据该地址确定目标闪存页的类型，其中，该目标闪存页为该非易失性存储器中存储该待写入数据的闪存页；根据确定的该目标闪存页的类型及该待写入数据，计算该目标闪存页的预测比特错误率BER；根据该目标闪存页的预测BER，确定该待写入数据的目标错误纠正码ECC算法和目标纠错位数；根据确定的该目标ECC算法和该目标纠错位数将该待写入数据写入该目标闪存页。
结合第一方面，在第一方面的第一种可能的实现方式中，该根据该目标闪存页的预测BER，确定该待写入数据的目标错误纠正码ECC算法和目标纠错位数，包括：根据该目标闪存页的预测BER以及根据预设的该目标闪存页的预测BER与纠错能力信息的对应关系，确定该待写入数据的该目标ECC算法和该目标纠错位数，该纠错能力信息包括ECC算法和纠错位数。
结合第一方面或第一方面的第一种可能的实现方式，在第一方面的第二种可能的实现方式中，该根据确定的该目标闪存页的类型及该待写入数据，计算该目标闪存页的预测比特错误率BER，包括：根据该目标闪存页的类型和该待写入数据，采用与该目标闪存页的类型对应的BER计算方式，计算该目标闪存页的预测BER。
结合第一方面的第二种可能的实现方式，在第一方面的第三种可能的实现方式中，若该目标闪存页为最高有效比特位MSB页，该BER计算方式为：
Figure PCTCN2014093653-appb-000001
其中，该BMSB为MSB页的预测BER；该P00为该待写入数据中00所占的比例；该P10为该待写入数据中10所占的比例；该
Figure PCTCN2014093653-appb-000002
为预设的写入00发生左偏错误的BER；该
Figure PCTCN2014093653-appb-000003
为预设的写入10发生右偏错误的BER。
结合第一方面的第二种可能的实现方式，在第一方面的第四种可能的实现方式中，若该目标闪存页为最低有效比特位LSB页，该BER计算方式为：
Figure PCTCN2014093653-appb-000004
其中，该BLSB为LSB页的预测BER；该P11为该待写入数据中11所占的比例；该P10为该待写入数据中10所占的比例；该P00为该待写入数据中00所占的比例；该P01为该待写入数据中01所占的比例；该
Figure PCTCN2014093653-appb-000005
为预设的写入11发生右偏错误的BER；该
Figure PCTCN2014093653-appb-000006
为预设的写入10发生左偏错误的BER；该
Figure PCTCN2014093653-appb-000007
为预设的写入00发生右偏错误的BER；该
Figure PCTCN2014093653-appb-000008
为预设的写入01发生左偏错误的BER。
结合第一方面或第一方面的第一种至第四种可能的实现方式中的任一 种可能的实现方式，在第一方面的第五种可能的实现方式中，该根据确定的该目标ECC算法和该目标纠错位数将该待写入数据写入该目标闪存页之后，还包括：记录该目标ECC算法和该目标纠错位数。
第二方面，提供了一种装置，该装置应用于非易失性存储器中，包括：接收模块，用于接收写请求，该写请求包括待写入数据和地址；类型确定模块，用于根据该地址确定目标闪存页的类型，其中，该目标闪存页为该非易失性存储器中存储该待写入数据的闪存页；计算模块，用于根据该类型确定模块确定的该目标闪存页的类型及该待写入数据，计算该目标闪存页的预测比特错误率BER；算法确定模块，用于根据该目标闪存页的预测BER，确定该待写入数据的目标错误纠正码ECC算法和目标纠错位数；写入模块，用于根据该算法确定模块确定的该目标ECC算法和该目标纠错位数将该待写入数据写入该目标闪存页。
结合第二方面，在第二方面的第一种可能的实现方式中，该算法确定模块具体用于：根据该目标闪存页的预测BER以及根据预设的该目标闪存页的预测BER与纠错能力信息的对应关系，确定该待写入数据的该目标ECC算法和该目标纠错位数，该纠错能力信息包括ECC算法和纠错位数。
结合第二方面或第二方面的第一种可能的实现方式，在第二方面的第二种可能的实现方式中，该计算模块，具体用于：根据该目标闪存页的类型和该待写入数据，采用与该目标闪存页的类型对应的BER计算方式，计算该目标闪存页的预测BER。
结合第二方面的第二种可能的实现方式，在第二方面的第三种可能的实现方式中，若该目标闪存页为最高有效比特位MSB页，该计算模块具体用于：根据BER计算方式：
Figure PCTCN2014093653-appb-000009
计算该目标闪存页的预测BER，其中，该BMSB为MSB页的预测BER；该P00为该待写入数据中00所占的比例；该P10为该待写入数据中10所占的比例；该
Figure PCTCN2014093653-appb-000010
为预设的写入00发生左偏错误的BER；该
Figure PCTCN2014093653-appb-000011
为预设的写入10发生右偏错误的BER。
结合第二方面的第二种可能的实现方式，在第二方面的第四种可能的实现方式中，若该目标闪存页为最低有效比特位LSB页，该计算模块具体用于：根据BER计算方式：
Figure PCTCN2014093653-appb-000012
计算该目标闪存页的预测BER，其中，该BLSB为LSB页的预测BER；该P11为该待写入数据中11所占的比例；该P10为该待写入数据中10所占的比例；该P00为该待写 入数据中00所占的比例；该P01为该待写入数据中01所占的比例；该
Figure PCTCN2014093653-appb-000013
为预设的写入11发生右偏错误的BER；该
Figure PCTCN2014093653-appb-000014
为预设的写入10发生左偏错误的BER；该
Figure PCTCN2014093653-appb-000015
为预设的写入00发生右偏错误的BER；该
Figure PCTCN2014093653-appb-000016
为预设的写入01发生左偏错误的BER。
结合第二方面或第二方面的第一种至第四种可能的实现方式中的任一种可能的实现方式，在第二方面的第五种可能的实现方式中，还包括：记录模块，用于记录该目标ECC算法和该目标纠错位数。
本发明实施例中针对待写入闪存页的数据预测比特错误率，根据该预测的比特错误率选择合适的ECC算法和纠错位数，并使用选择的ECC算法和纠错位数将待写入闪存页的数据写入闪存页，以便于对出现错误的数据进行纠错。该方法能够选择适当的ECC算法和纠错位数，从而能够在保证数据正确性的基础上节约ECC算法的纠错能力，降低纠错的计算量。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对本发明实施例中所需要使用的附图作简单地介绍，显而易见地，下面所描述的附图仅仅是本发明的一些实施例的附图。
图1是本发明闪存存储单元的数据状态的错误模型示意图。
图2是本发明一个实施例的数据存储的方法的示意性流程图。
图3是本发明另一实施例的数据存储的方法的示意性流程图。
图4是本发明一个实施例的数据存储的方法的示意性流程图。
图5是本发明一个实施例的装置的示意框图。
图6是本发明另一实施例的装置的示意框图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明的一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都应属于本发明保护的范围。
图1是本发明闪存存储单元的数据状态的错误模型示意图。
应理解，闪存是根据存储到其浮栅电极中的电子多少来表示存储的数据 的。当闪存的存储单元中存储的电子所表示出来的电压值在不同的区域，则该存储单元表现出的数据状态分别为“00”，“01”，“10”和“11”。闪存的错误率与闪存的存储单元中所表示的数据状态相关，即存储单元表现出的不同数据状态具有不同的比特错误率(Bit Error Rate，BER)，并且比特错误率产生的主要原因也各不相同。闪存中的闪存页为读写单元，闪存页的类型包括MSB页和LSB页。
闪存中写入闪存页的数据可能出现错误。最主要的两种错误为漏电导致的错误和编程错误。如图1所示，横坐标V为存储单元表现出的电压值，纵坐标P为存储单元分布(distribution of cells)。其中，漏电错误会导致存储单元中的电子泄露，使得电压下降，则导致数据状态向左偏移，这种错误为左偏错误。由于闪存芯片反复的编程擦除以及附近芯片的编程操作的影响，会导致该闪存存储芯片中的电子上升，从而使得数据状态右偏，这种错误为右偏错误。
在图1中，根据MSB页和LSB页的比特“0”和“1”的数据状态可知，对于MSB页，只在“10”状态发生右偏和“00”状态左偏时会导致MSB页的数据发生错误，如图1中的标号1所示区域；对于LSB页的数据，只在“11”状态和“00”状态发生右偏错误，“10”状态和“01”状态发生左偏时发生左偏错误，如图1中的标号2所示区域。
图2是本发明一个实施例的数据存储的方法的示意性流程图。图2的方法可以由图5所示的装置执行，该装置可以为非易失性存储器。
该方法包括：
201，接收写请求，写请求包括待写入数据和地址。
闪存的闪存页用于读数据或写数据。当在该闪存中写入数据时，可以接收写请求，该写请求可以包括待写入数据和地址。
202，根据地址确定目标闪存页的类型，其中，目标闪存页为非易失性存储器中存储待写入数据的闪存页。
实际应用中，可以将待写入数据根据写请求中的地址写入不同类型的闪存页。闪存页的类型包括MSB页和LSB页。在写入过程可能会发生错误，该写入错误可以为左偏错误，也可以为右偏错误。例如，该写入的数据应该为“10”，发生右偏错误时，该写入的数据变为“00”，也就是写入MSB页的数据“1”发生右偏错误变为“0”。
203，根据确定的目标闪存页的类型及待写入数据计算目标闪存页的预测比特错误率BER。
目标闪存页的类型可以是用于存储不同比特位数据的闪存页。目标闪存页的类型与该目标闪存页中各存储单元可存储的比特数据位数有关，若该目标闪存页中各存储单元可存储的比特数据为2位比特数据，则该待写入数据中分别写入该目标闪存页中各存储单元的比特数据可包括高位比特数据，即最高有效比特位(Most Significant Bit，简称MSB)数据及低位比特数据，即最低有效比特位(Least Significant Bit，简称LSB)。那么，该目标闪存页的类型可包括用于存储MSB数据的MSB页和用于存储LSB数据的LSB页。若该目标闪存页中各存储单元可存储的比特数据为4位或更多位比特的数据，则该待写入数据中分别写入该目标闪存页中各存储单元的比特数据还可包括其他位的比特数据，对应的，该目标闪存页的类型还可包括用于存储该其他比特数据的闪存页。
在本发明实施例中，根据写请求中的地址，可以确定闪存页的类型。根据待写入数据和地址确定的闪存页的类型，可以预测该类型的闪存页的比特错误率(Bit Error Rate,BER)。闪存页的预测比特错误率可以为MSB页的预测比特错误率，也可以为LSB页的预测比特错误率。
应理解，不同类型的闪存页可以对应不同的计算方法。该不同的计算方法分为MSB页对应的预测比特错误率的计算方法和LSB页对应的预测比特错误率的计算方法。本实施例方案中，根据该目标闪存页的类型及该待写入数据计算该目标闪存页的BER，例如可以是根据目标闪存页的类型，结合该待写入数据的具体内容，计算获得该目标闪存页的BER。其中，该待写入数据的具体内容可以是不同数据类型在该待写入数据中的分布，该不同数据类型可以是不同的比特位数据，如0和1的具体分布。因而，该目标闪存页的BER也可以为基于内容的比特错误率(Content Dependent Bit Error Rate，简称CDBER)。在本实施例中，该目标闪存页的BER，例如可以是根据该目标闪存页的类型及该待写入数据中不同类型的数据的分布，如11、10、01和00的分布而计算获得。
204，根据目标闪存页的预测BER，确定待写入数据的目标错误纠正码ECC算法和目标纠错位数。
在选择ECC算法和纠错位数时，若目标闪存页为MSB页，可以基于 MSB页的预测比特错误率选择该MSB页对应的目标ECC算法和目标纠错位数；若目标闪存页为LSB页，可以基于LSB页的预测比特错误率选择该LSB页对应的目标ECC算法和目标纠错位数。
还应理解，该ECC算法可以为BCH(Bose Ray-Chaudhuri Hocquenghem)算法，该纠错位数可以为N个比特，N为大于或等于1的正整数。
205，根据确定的目标ECC算法和目标纠错位数将待写入数据写入目标闪存页。
在确定出目标ECC算法和目标纠错位数之后，若目标闪存页为MSB页，可以根据MSB页对应的目标ECC算法和目标纠错位数将待写入该MSB页的数据写入MSB页，并对出现错误的数据进行纠错；若目标闪存页为LSB页，可以根据LSB页对应的目标ECC算法和目标纠错位数将待写入该LSB页的数据写入LSB页，并对出现错误的数据进行纠错。也就是说，本发明实施例中针对闪存页的操作可以对MSB页进行操作，也可以对LSB页进行操作，本发明并不限于此。
在本发明实施例中，在获知待写入闪存页的数据信息的基础上，选择ECC算法和纠错位数进行纠错。该写入错误可以为基于内容的比特错误率(Content Dependent Bit Error Rate，CDBER)。
需要说明的是，本发明实施例可以应用在非易失性存储器中，也可以应用在以闪存颗粒为存储介质的存储器，例如固态硬盘SSD，闪存卡能存储器。
本发明实施例中针对待写入闪存页的数据预测比特错误率，根据预测的比特错误率选择合适的ECC算法和纠错位数，并使用选择的ECC算法和纠错位数将待写入闪存页的数据写入闪存页，以便于对出现错误的数据进行纠错。该方法能够选择适当的ECC算法和纠错位数，节约ECC算法的纠错能力，因而能够降低纠错的计算量。
可选地，作为另一实施例，在203中，可以根据目标闪存页的类型和待写入数据，采用与目标闪存页的类型对应的BER计算方式，计算目标闪存页的预测BER。
具体地，目标闪存页的类型分为MSB页和LBS页，MSB页和LSB页分别对应不同的BER计算方式。
根据待写入闪存页的数据，可以得到四种数据状态在写入数据中所占的比例。根据写入数据中不同数据状态所占的比例和预设的写入数据的BER， 能够计算闪存页的预测比特错误率。该预设的写入数据的BER可以根据实验数据和经验值获得。
应理解，闪存页包括MSB页和LSB页，该计算闪存页的预测比特错误率的方法也适用于MSB页和LSB页。也就是说，本发明实施例中的闪存页可以用MSB页或LSB页替换。这样，能够分别计算MSB页和LSB页的预测比特错误率，并分别选择ECC算法和纠错位数，从而对MSB页和LSB页的写入数据分别进行纠错。
可选地，作为另一实施例，在203中，若目标闪存页为MSB页，该BER计算方式可以为：
Figure PCTCN2014093653-appb-000017
其中，BMSB为MSB页的预测BER；P00为待写入数据中00所占的比例；P10为待写入数据中10所占的比例；
Figure PCTCN2014093653-appb-000018
为预设的写入00发生左偏错误的BER；
Figure PCTCN2014093653-appb-000019
为预设的写入10发生右偏错误的BER。
可选地，作为另一实施例，在203中，若目标闪存页为最低有效比特位LSB页，BER计算方式为：
Figure PCTCN2014093653-appb-000020
其中，BLSB为LSB页的预测BER；P11为待写入数据中11所占的比例；P10为待写入数据中10所占的比例；P00为待写入数据中00所占的比例；P01为待写入数据中01所占的比例；
Figure PCTCN2014093653-appb-000021
为预设的写入11发生右偏错误的BER；
Figure PCTCN2014093653-appb-000022
为预设的写入10发生左偏错误的BER；
Figure PCTCN2014093653-appb-000023
为预设的写入00发生右偏错误的BER；
Figure PCTCN2014093653-appb-000024
为预设的写入01发生左偏错误的BER。
下面将结合图1，对如何计算MSB页的预测BER和LSB页的预测BER进行详细描述。
根据待写入数据可以得到该数据所属的数据状态所占的比例。设该四种数据状态所占的比例分别为P11，P10，P00，P01。其中，P11表示待写入数据中“11”所占的比例，P10表示待写入数据中“10”所占的比例，P00表示待写入数据中“00”所占的比例，P01表示待写入数据中“01”所占的比例。
预设的写入闪存页的数据的BER可以包括左偏错误和右偏错误。左偏错误可以包括：
Figure PCTCN2014093653-appb-000025
其中，
Figure PCTCN2014093653-appb-000026
为预设的写入11发生左偏错误的BER，
Figure PCTCN2014093653-appb-000027
为预设的写入10发生左偏错误的BER，
Figure PCTCN2014093653-appb-000028
为预设的写入00发生左偏错误的BER，
Figure PCTCN2014093653-appb-000029
为预设的写入01发生左偏错误的BER。从图1可以 得出
Figure PCTCN2014093653-appb-000030
右偏错误可以包括：
Figure PCTCN2014093653-appb-000031
其中，
Figure PCTCN2014093653-appb-000032
为预设的写入11发生右偏错误的BER，
Figure PCTCN2014093653-appb-000033
为预设的写入10发生右偏错误的BER，
Figure PCTCN2014093653-appb-000034
为预设的写入00发生右偏错误的BER，
Figure PCTCN2014093653-appb-000035
为预设的写入01发生右偏错误的BER。从图1可以得出
Figure PCTCN2014093653-appb-000036
在图1中，根据MSB页和LSB页的比特“0”和“1”的数据状态可知，对于MSB页，只在“10”状态发生右偏和“00”状态左偏时会导致MSB页的数据发生错误，如图1中的标号1所示区域；对于LSB页的数据，只在“11”状态和“00”状态发生右偏错误，“10”状态和“01”状态发生左偏时发生左偏错误，如图1中的标号2所示区域。
因此，根据待写入数据中不同数据状态所占的比例和预设的写入闪存页的数据的BER，计算MSB页和LSB页的预测比特错误率的公式可以如下：
Figure PCTCN2014093653-appb-000037
Figure PCTCN2014093653-appb-000038
可选地，作为另一实施例，在204中，本发明实施例可以根据目标闪存页的预测BER以及根据预设的目标闪存页的预测BER与纠错能力信息的对应关系，确定待写入数据的目标ECC算法和目标纠错位数，纠错能力信息包括ECC算法和纠错位数。
下面详细介绍预设的目标闪存页的预测BER与纠错能力信息的对应关系的设定方法。
具体地，ECC算法的纠错能力信息与闪存页的预测BER存在对应关系。ECC算法的纠错能力表示该ECC算法及纠错位数能够纠正一定范围的比特错误率。不同的ECC算法和纠错位数能够纠正的比特错误率的范围不同。即不同的ECC算法和纠错位数与比特错误率之间存在对应关系。
可选地，作为一个实施例，预设的目标闪存页的预测BER与纠错能力信息的对应关系可以根据经验数据来设定。具体的，预设的ECC算法和纠错位数和目标闪存页的预测BER的对应关系可以达到保证数据的可靠性并最大限度的减少ECC的计算开销的目的。例如，目标闪存页的预测BER值越小，预设的ECC算法的可纠错位数越少，目标闪存页的预测BER值越大，预设的ECC算法的可纠错位数越多(即可纠错能力越强)。具体的，可以先设定闪存页的页理论最小错误率和页理论最大错误率，并将设定的页理论最小BER到页理论最大BER这一比特错误率的范围划分成多个比特错误率的 范围。不同的比特错误率的范围可以对应不同的纠错能力信息。也就是说，ECC算法和纠错位数能够纠正的比特错误率的范围即为该ECC算法和纠错位数对应的比特错误率的范围。
具体地，本发明实施例可以确定N个纠错能力信息对应的N个比特错误率范围，其中，N大于或等于1；从N个比特错误率范围中确定闪存页的预测比特错误率所属的目标比特错误率范围；确定目标比特错误率范围对应的ECC算法和纠错位数为目标ECC算法和目标纠错位数。
本发明实施例选择的ECC算法和纠错位数的可纠正的比特错误率大于该闪存页的预测比特错误率，可以在保障数据可靠性的基础上，节省ECC的纠错能力，从而减少计算量，提升系统性能和空间利用率。
具体地，ECC算法的纠错能力信息与闪存页的比特错误率存在对应关系可以表示为ECC算法的纠错能力信息对应一定的比特错误率范围。N个纠错能力信息可以对应N个比特错误率范围。若目标闪存页的预测比特错误率属于该N个比特错误率范围中的目标比特错误率范围，则可以使用目标比特错误率范围对应的ECC算法和纠错位数对写入闪存页的数据信息进行纠错。
还应理解，本发明实施例中的闪存页可以替换为MSB页或LSB页。可选地，作为另一实施例，N个比特错误率范围中的比特错误率的最小值和最大值基于目标闪存页的预测比特错误率确定。比特错误率的最小值即为页理论最小BER，比特错误率的最大值即为页理论最大BER。
具体地，N个纠错能力信息与N个比特错误率范围的对应关系可以根据上述描述建立如下表1。该表1中等分的比特错误率范围对应相应地ECC算法和纠错位数，并将该ECC算法和纠错位数设定纠错等级。本文将结合如下表1详细描述ECC算法的纠错能力信息与比特错误率的对应关系。
表1纠错能力信息与比特错误率对应关系表
纠错等级 ECC算法和纠错位数 比特错误率范围
0 BCH(1bit) CDBERmin-CDBER 1
1 BCH(2bit) CDBER 1-CDBER 2
… … …
N-1 BCH(Nbit) CDBER N-1-CDBERmax
CDBERmin为页理论最小比特错误率，CDBERmax为页理论最大比特错误率。将公式
Figure PCTCN2014093653-appb-000039
中的P10,P00取合适值，使得MSB页的预测比 特错误率取得最小值时，可以得到MSB页对应的CDBERmin；将公式
Figure PCTCN2014093653-appb-000040
中的P10,P00取合适值，使得MSB页的预测比特错误率取得最大值时，可以得到MSB页对应的CDBERmax。
同理，将公式
Figure PCTCN2014093653-appb-000041
中的P11，P10，P00，P01取合适值，使得LSB页的预测比特错误率取得最小值时，可以得到LSB页对应的CDBERmin；将上述公式中的P11，P10，P00，P01取合适值，使得LSB页的预测比特错误率取得最大值时，可以得到LSB页对应的CDBERmax。
如表1所示，可选地，作为另一实施例，本发明实施例可以将MSB页对应的CDBERmin和LSB页对应的CDBERmin中的较小值作为表1的对应关系表中的CDBERmin，即页理论最小比特错误率；将MSB页对应的CDBERmax和LSB页对应的CDBERmax中的较大值作为表1的对应关系表中的CDBERmax，即页理论最大比特错误率。这样，本发明实施例中MSB页和LSB页共同使用同一个对应关系表。
应理解，表1中仅仅示出了三个错误等级，在本发明实施例中可以包括N个纠错等级。可选地，作为另一个实施例，本发明实施例中的ECC算法选用BCH算法，也可以选用其他ECC算法，本发明实施例并不限于此。
N个纠错位数为等分变化时，其比特错误率范围相同。即CDBERmin-CDBER 1的范围可以与CDBER 1-CDBER 2的范围相同。若N个纠错位数为非等分变化时，其比特错误率范围也不同。例如，纠错等级为0时，纠错位数为1bit对应的比特错误率范围为CDBERmin-CDBER 1，则纠错等级为1时，纠错位数为3bit对应的比特错误率范围为2倍的CDBERmin-CDBER 1。
在确定MSB页或LSB页的预测比特错误率后，本发明实施例可以查找表1，并判定该计算得出的目标闪存页的预测BER落入的比特错误率范围，并选择该比特错误率范围对应的ECC算法和纠错位数将待写入的数据写入闪存，并根据选择的ECC算法和纠错位数对出现错误的数据进行纠错。例如，若MSB页的预测比特错误率在纠错等级为1对应的比特错误率范围内，则选择BCH算法和2bit的纠错位数将数据写入MSB页。
图3是本发明另一实施例的数据存储的方法的示意性流程图。图3中与图2中相同的步骤采用相同的标号。该方法可以由图5所示的装置执行，该方法还可以包括：
206，记录目标ECC算法和目标纠错位数。
本发明实施例中针对写入闪存页的数据预测比特错误率，根据该预测的比特错误率选择合适的ECC算法和纠错位数，并使用选择的ECC算法和纠错位数将待写入闪存页的数据写入闪存，以便于对出现错误的数据进行纠正。该方法能够选择适当的ECC算法和纠错位数，节约ECC算法的纠错能力，因而能够降低该纠错过程的计算量。
在获得目标ECC算法和目标纠错位数后，可以记录该目标ECC算法和目标纠错位数，也可以记录其对应的纠错等级。在写入的数据出现错误时，本发明实施例可以调用该纠错等级，使用该纠错等级对应的ECC算法和纠错位数进行纠错。
图4是本发明一个实施例的数据存储的方法的示意性流程图。该过程可以由图5所示的装置执行，该装置可以为固态硬盘SSD，该方法包括：
401，接收包括待写入数据和地址的写请求。
402，根据写请求中的地址确定闪存页的类型。
具体地，根据写请求中的地址确定闪存页的类型。闪存页的类型分为MSB页和LSB页。
403，若闪存页为MSB页，根据待写入数据中00、10所占的比例和预设的写入数据的BER，计算MSB页的预测BER。
应理解，待写入数据可以为闪存中一个闪存页的数据。其中，一个闪存页的大小可以为4KB或8KB等。可选地，本发明实施例对于闪存页的大小并不做限定。
根据待写入数据可以得到该数据所属的数据状态所占的比例。设该四种数据状态所占的比例分别为P11，P10，P00，P01。其中，P11表示待写入数据中“11”所占的比例，P10表示待写入数据中“10”所占的比例，P00表示待写入数据中“00”所占的比例，P01表示待写入数据中“01”所占的比例。
预设的写入闪存页的数据的BER可以包括左偏错误和右偏错误。
设左偏错误包括：
Figure PCTCN2014093653-appb-000042
其中，
Figure PCTCN2014093653-appb-000043
为预设的写入11发生左偏错误的BER，
Figure PCTCN2014093653-appb-000044
为预设的写入10发生左偏错误的BER，
Figure PCTCN2014093653-appb-000045
为预设的写入00发生左偏错误的BER，
Figure PCTCN2014093653-appb-000046
为预设的写入01发生左偏错误的BER。从图1可以得出
Figure PCTCN2014093653-appb-000047
设右偏错误包括：
Figure PCTCN2014093653-appb-000048
其中，
Figure PCTCN2014093653-appb-000049
为预设的写入11发生右 偏错误的BER，
Figure PCTCN2014093653-appb-000050
为预设的写入10发生右偏错误的BER，
Figure PCTCN2014093653-appb-000051
为预设的写入00发生右偏错误的BER，
Figure PCTCN2014093653-appb-000052
为预设的写入01发生右偏错误的BER。从图1可以得出
Figure PCTCN2014093653-appb-000053
在图1中，对于MSB页，只在“10”状态发生右偏和“00”状态左偏时会导致MSB页的数据发生错误，如图1中的标号1所示区域。因此，可以得出计算MSB页的预测BER的公式可以如下：
Figure PCTCN2014093653-appb-000054
404，若闪存页为LSB页，根据待写入数据中四种数据状态分别所占的比例和预设的写入数据的BER，计算LSB页的预测BER。
在图1中，对于LSB页的数据，只在“11”状态和“00”状态发生右偏错误，“10”状态和“01”状态发生左偏时发生左偏错误，如图1中的标号2所示区域。因此，可以得出计算LSB页的预测BER的公式可以如下：
Figure PCTCN2014093653-appb-000055
405，根据MSB页或LSB页的预测比特错误率以及根据预设的目标闪存页的预测BER与纠错能力信息的对应关系，选择ECC算法和纠错位数。
具体地，纠错能力信息包括ECC算法和纠错位数。ECC算法的纠错能力信息与闪存页的比特错误率存在对应关系可以表示为ECC算法的纠错能力信息对应一定的比特错误率范围。N个纠错能力信息可以对应N个比特错误率范围。若目标闪存页的预测比特错误率属于该N个比特错误率范围中的目标比特错误率范围，则可以使用目标比特错误率范围对应的ECC算法和纠错位数对写入闪存页的数据信息进行纠错。
可选地，作为另一实施例，N个比特错误率范围中的比特错误率的最小值和最大值基于目标闪存页的预测比特错误率确定。
将公式
Figure PCTCN2014093653-appb-000056
中的P10,P00取合适值，使得MSB页的预测比特错误率取得最小值时，可以得到MSB页对应的BER的最小值；将公式
Figure PCTCN2014093653-appb-000057
中的P10,P00取合适值，使得MSB页的预测比特错误率取得最大值时，可以得到MSB页对应的BER的最大值。
同理，将公式
Figure PCTCN2014093653-appb-000058
中的P11，P10，P00，P01取合适值，使得LSB页的预测比特错误率取得最小值时，可以得到LSB页对应的BER的最小值；将上述公式中的P11，P10，P00，P01取合适值，使得LSB页的预测比特错误率取得最大值时，可以得到LSB页对应的BER的最大值。
本发明实施例可以将MSB页对应的BER的最小值和LSB页对应的BER的最小值中的较小值作为页理论最小比特错误率；将MSB页对应的BER的最大值和LSB页对应的BER的最大值中的较大值作为页理论最大比特错误率。这样，本发明实施例中MSB页和LSB页共同使用同一个对应关系表。
406，记录选择的ECC算法和纠错位数。
可选地，作为另一实施例，ECC算法和纠错位数可以对应纠错等级。本发明实施例还可以记录该纠错等级。
407，利用选择的ECC算法和纠错位数对出现错误的数据进行纠错。
可选地，作为另一实施例，本发明实施例可以调用记录的纠错等级，采用该纠错等级对应的ECC算法和纠错位数对写入闪存页的数据中出现错误的数据进行纠错。
具体地，本发明实施例可以根据MSB页的预测比特错误率选择的ECC算法和纠错位数，对写入MSB页的数据中出现错误的数据进行纠错，也可以根据LSB页的预测比特错误率选择的ECC算法和纠错位数，对写入LSB页的数据中出现错误的数据进行纠错。
本发明实施例中针对待写入闪存页的数据预测比特错误率，根据预测的比特错误率选择合适的ECC算法和纠错位数，并使用选择的ECC算法和纠错位数将待写入闪存页的数据写入闪存页，以便于对出现错误的数据进行纠错。该方法能够选择适当的ECC算法和纠错位数，节约ECC算法的纠错能力，因而能够降低纠错的计算量。
图5是本发明一个实施例的装置的示意框图。图5所示的装置可以实现上述图2和图3的方法和图4的过程。该装置可以为非易失性存储器，该装置50包括：
接收模块51，用于接收写请求，写请求包括待写入数据和地址；
类型确定模块52，用于根据地址确定目标闪存页的类型，其中，目标闪存页为非易失性存储器中存储待写入数据的闪存页；
计算模块53，用于根据类型确定模块确定的目标闪存页的类型及待写入数据，计算目标闪存页的预测比特错误率BER；
算法确定模块54，用于根据目标闪存页的预测BER，确定待写入数据的目标错误纠正码ECC算法和目标纠错位数；
写入模块55，用于根据算法确定模块确定的目标ECC算法和目标纠错 位数将待写入数据写入目标闪存页。
本发明实施例中针对待写入闪存页的数据预测比特错误率，根据预测的比特错误率选择合适的ECC算法和纠错位数，并使用选择的ECC算法和纠错位数将待写入闪存页的数据写入闪存页，以便于对出现错误的数据进行纠错。该方法能够选择适当的ECC算法和纠错位数，节约ECC算法的纠错能力，因而能够降低纠错的计算量。
可选地，作为另一实施例，算法确定模块54可以根据目标闪存页的预测BER以及根据预设的目标闪存页的预测BER与纠错能力信息的对应关系，确定待写入数据的目标ECC算法和目标纠错位数，纠错能力信息包括ECC算法和纠错位数。
可选地，作为另一实施例，计算模块53可以根据目标闪存页的类型和待写入数据，采用与目标闪存页的类型对应的BER计算方式，计算目标闪存页的预测BER。
可选地，作为另一实施例，若目标闪存页为最高有效比特位MSB页，计算模块53可以根据BER计算方式：
Figure PCTCN2014093653-appb-000059
计算目标闪存页的预测BER，其中，BMSB为MSB页的预测BER；P00为待写入数据中00所占的比例；P10为待写入数据中10所占的比例；
Figure PCTCN2014093653-appb-000060
为预设的写入00发生左偏错误的BER；
Figure PCTCN2014093653-appb-000061
为预设的写入10发生右偏错误的BER。
可选地，作为另一实施例，若目标闪存页为最低有效比特位LSB页，计算模块53可以根据BER计算方式：
Figure PCTCN2014093653-appb-000062
计算目标闪存页的预测BER，其中，BLSB为LSB页的预测BER；P11为待写入数据中11所占的比例；P10为待写入数据中10所占的比例；P00为待写入数据中00所占的比例；P01为待写入数据中01所占的比例；
Figure PCTCN2014093653-appb-000063
为预设的写入11发生右偏错误的BER；
Figure PCTCN2014093653-appb-000064
为预设的写入10发生左偏错误的BER；
Figure PCTCN2014093653-appb-000065
为预设的写入00发生右偏错误的BER；
Figure PCTCN2014093653-appb-000066
为预设的写入01发生左偏错误的BER。
可选地，作为另一实施例，该装置50还可以包括记录模块56，用于记录目标ECC算法和目标纠错位数。
图6是本发明另一实施例的装置的示意框图。图6的装置60可用于实现上述方法实施例中各步骤及方法。图6的装置包括处理器61和存储器62。处理器61和存储器62通过总线系统69连接。
处理器61控制装置60的操作。存储器62可以包括只读存储器和随机存取存储器，并向处理器61提供指令和数据。存储器62的一部分还可以包括非易失行随机存取存储器(NVRAM)。装置60的各个组件通过总线系统69耦合在一起，其中总线系统69除包括数据总线之外，还包括电源总线、控制总线和状态信号总线。但是为了清楚说明起见，在图中将各种总线都标为总线系统69。
处理器61可能是一种集成电路芯片，具有信号的处理能力。上述的处理器61可以是通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现成可编程门阵列(FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本发明实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。处理器61读取存储器62中的信息，结合其硬件控制装置60的各个部件。
图2和图3的方法可以在图6的装置60中实现，为避免重复，不再详细描述。
具体地，在处理器61的控制之下，装置60完成以下操作：
接收写请求，写请求包括待写入数据和地址；
根据地址确定目标闪存页的类型，其中，目标闪存页为非易失性存储器中存储待写入数据的闪存页；
根据确定的目标闪存页的类型及待写入数据，计算目标闪存页的预测比特错误率BER；
根据目标闪存页的预测BER，确定待写入数据的目标错误纠正码ECC算法和目标纠错位数；
根据确定的目标ECC算法和目标纠错位数将待写入数据写入目标闪存页。
本发明实施例中针对待写入闪存页的数据预测比特错误率，根据预测的比特错误率选择合适的ECC算法和纠错位数，并使用选择的ECC算法和纠错位数将待写入闪存页的数据写入闪存页，以便于对出现错误的数据进行纠 错。该方法能够选择适当的ECC算法和纠错位数，节约ECC算法的纠错能力，因而能够降低纠错的计算量。
可选地，作为另一实施例，处理器61可以根据目标闪存页的预测BER以及根据预设的目标闪存页的预测BER与纠错能力信息的对应关系，确定待写入数据的目标ECC算法和目标纠错位数，纠错能力信息包括ECC算法和纠错位数。
可选地，作为另一实施例，处理器61可以根据目标闪存页的类型和待写入数据，采用与目标闪存页的类型对应的BER计算方式，计算目标闪存页的预测BER。
可选地，作为另一实施例，若目标闪存页为最高有效比特位MSB页，BER计算方式为：
Figure PCTCN2014093653-appb-000067
其中，BMSB为MSB页的预测BER；P00为待写入数据中00所占的比例；P10为待写入数据中10所占的比例；
Figure PCTCN2014093653-appb-000068
为预设的写入00发生左偏错误的BER；
Figure PCTCN2014093653-appb-000069
为预设的写入10发生右偏错误的BER。
可选地，作为另一实施例，若目标闪存页为最低有效比特位LSB页，BER计算方式为：
Figure PCTCN2014093653-appb-000070
其中，BLSB为LSB页的预测BER；P11为待写入数据中11所占的比例；P10为待写入数据中10所占的比例；P00为待写入数据中00所占的比例；P01为待写入数据中01所占的比例；
Figure PCTCN2014093653-appb-000071
为预设的写入11发生右偏错误的BER；
Figure PCTCN2014093653-appb-000072
为预设的写入10发生左偏错误的BER；
Figure PCTCN2014093653-appb-000073
为预设的写入00发生右偏错误的BER；
Figure PCTCN2014093653-appb-000074
为预设的写入01发生左偏错误的BER。
可选地，作为另一实施例，处理器61还可以记录目标ECC算法和目标纠错位数。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本发明的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。在本发明的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本发明实施例的实施过程构成任何限定。
另外，本文中术语“系统”和“网络”在本文中常被可互换使用。本文中术 语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
应理解，在本发明实施例中，“与A相应的B”表示B与A相关联，根据A可以确定B。但还应理解，根据A确定B并不意味着仅仅根据A确定B，还可以根据A和/或其它信息确定B。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、装置或单元的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本发明实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以是两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件 功能单元的形式实现。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到本发明可以用硬件实现，或固件实现，或它们的组合方式来实现。当使用软件实现时，可以将上述功能存储在计算机可读介质中或作为计算机可读介质上的一个或多个指令或代码进行传输。计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是计算机能够存取的任何可用介质。以此为例但不限于：计算机可读介质可以包括RAM、ROM、EEPROM、CD-ROM或其他光盘存储、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质。此外。任何连接可以适当的成为计算机可读介质。例如，如果软件是使用同轴电缆、光纤光缆、双绞线、数字用户线(DSL)或者诸如红外线、无线电和微波之类的无线技术从网站、服务器或者其他远程源传输的，那么同轴电缆、光纤光缆、双绞线、DSL或者诸如红外线、无线和微波之类的无线技术包括在所属介质的定影中。如本发明所使用的，盘(Disk)和碟(disc)包括压缩光碟(CD)、激光碟、光碟、数字通用光碟(DVD)、软盘和蓝光光碟，其中盘通常磁性的复制数据，而碟则用激光来光学的复制数据。上面的组合也应当包括在计算机可读介质的保护范围之内。总之，以上所述仅为本发明技术方案的较佳实施例而已，并非用于限定本发明的保护范围。

Claims (12)

  1. 一种数据存储的方法，所述方法应用于非易失性存储器中，其特征在于，包括：
    接收写请求，所述写请求包括待写入数据和地址；
    根据所述地址确定目标闪存页的类型，其中，所述目标闪存页为所述非易失性存储器中存储所述待写入数据的闪存页；
    根据确定的所述目标闪存页的类型及所述待写入数据，计算所述目标闪存页的预测比特错误率BER；
    根据所述目标闪存页的预测BER，确定所述待写入数据的目标错误纠正码ECC算法和目标纠错位数；
    根据确定的所述目标ECC算法和所述目标纠错位数将所述待写入数据写入所述目标闪存页。
  2. 根据权利要求1所述的方法，其特征在于，所述根据所述目标闪存页的预测BER，确定所述待写入数据的目标错误纠正码ECC算法和目标纠错位数，包括：
    根据所述目标闪存页的预测BER以及根据预设的所述目标闪存页的预测BER与纠错能力信息的对应关系，确定所述待写入数据的所述目标ECC算法和所述目标纠错位数，所述纠错能力信息包括ECC算法和纠错位数。
  3. 根据权利要求1或2所述的方法，其特征在于，所述根据确定的所述目标闪存页的类型及所述待写入数据，计算所述目标闪存页的预测比特错误率BER，包括：
    根据所述目标闪存页的类型和所述待写入数据，采用与所述目标闪存页的类型对应的BER计算方式，计算所述目标闪存页的预测BER。
  4. 根据权利要求3所述的方法，其特征在于，若所述目标闪存页为最高有效比特位MSB页，所述BER计算方式为：
    Figure PCTCN2014093653-appb-100001
    其中，所述BMSB为MSB页的预测BER；所述P00为所述待写入数据中00所占的比例；所述P10为所述待写入数据中10所占的比例；所述
    Figure PCTCN2014093653-appb-100002
    为预设的写入00发生左偏错误的BER；所述
    Figure PCTCN2014093653-appb-100003
    为预设的写入10发生右偏错误的BER。
  5. 根据权利要求3所述的方法，其特征在于，若所述目标闪存页为最 低有效比特位LSB页，所述BER计算方式为：
    Figure PCTCN2014093653-appb-100004
    其中，所述BLSB为LSB页的预测BER；所述P11为所述待写入数据中11所占的比例；所述P10为所述待写入数据中10所占的比例；所述P00为所述待写入数据中00所占的比例；所述P01为所述待写入数据中01所占的比例；所述
    Figure PCTCN2014093653-appb-100005
    为预设的写入11发生右偏错误的BER；所述
    Figure PCTCN2014093653-appb-100006
    为预设的写入10发生左偏错误的BER；所述
    Figure PCTCN2014093653-appb-100007
    为预设的写入00发生右偏错误的BER；所述
    Figure PCTCN2014093653-appb-100008
    为预设的写入01发生左偏错误的BER。
  6. 根据权利要求1-5任意一项所述的方法，所述根据确定的所述目标ECC算法和所述目标纠错位数将所述待写入数据写入所述目标闪存页之后，还包括：
    记录所述目标ECC算法和所述目标纠错位数。
  7. 一种装置，所述装置应用于非易失性存储器中，其特征在于，包括：
    接收模块，用于接收写请求，所述写请求包括待写入数据和地址；
    类型确定模块，用于根据所述地址确定目标闪存页的类型，其中，所述目标闪存页为所述非易失性存储器中存储所述待写入数据的闪存页；
    计算模块，用于根据所述类型确定模块确定的所述目标闪存页的类型及所述待写入数据，计算所述目标闪存页的预测比特错误率BER；
    算法确定模块，用于根据所述目标闪存页的预测BER，确定所述待写入数据的目标错误纠正码ECC算法和目标纠错位数；
    写入模块，用于根据所述算法确定模块确定的所述目标ECC算法和所述目标纠错位数将所述待写入数据写入所述目标闪存页。
  8. 根据权利要求1所述的装置，其特征在于，所述算法确定模块具体用于：
    根据所述目标闪存页的预测BER以及根据预设的所述目标闪存页的预测BER与纠错能力信息的对应关系，确定所述待写入数据的所述目标ECC算法和所述目标纠错位数，所述纠错能力信息包括ECC算法和纠错位数。
  9. 根据权利要求7或8所述的装置，其特征在于，所述计算模块，具体用于：
    根据所述目标闪存页的类型和所述待写入数据，采用与所述目标闪存页的类型对应的BER计算方式，计算所述目标闪存页的预测BER。
  10. 根据权利要求9所述的装置，其特征在于，若所述目标闪存页为最高有效比特位MSB页，所述计算模块具体用于：
    根据BER计算方式：
    Figure PCTCN2014093653-appb-100009
    计算所述目标闪存页的预测BER，
    其中，所述BMSB为MSB页的预测BER；所述P00为所述待写入数据中00所占的比例；所述P10为所述待写入数据中10所占的比例；所述
    Figure PCTCN2014093653-appb-100010
    为预设的写入00发生左偏错误的BER；所述
    Figure PCTCN2014093653-appb-100011
    为预设的写入10发生右偏错误的BER。
  11. 根据权利要求9所述的装置，其特征在于，若所述目标闪存页为最低有效比特位LSB页，所述计算模块具体用于：
    根据BER计算方式：
    Figure PCTCN2014093653-appb-100012
    计算所述目标闪存页的预测BER，
    其中，所述BLSB为LSB页的预测BER；所述P11为所述待写入数据中11所占的比例；所述P10为所述待写入数据中10所占的比例；所述P00为所述待写入数据中00所占的比例；所述P01为所述待写入数据中01所占的比例；所述
    Figure PCTCN2014093653-appb-100013
    为预设的写入11发生右偏错误的BER；所述
    Figure PCTCN2014093653-appb-100014
    为预设的写入10发生左偏错误的BER；所述
    Figure PCTCN2014093653-appb-100015
    为预设的写入00发生右偏错误的BER；所述
    Figure PCTCN2014093653-appb-100016
    为预设的写入01发生左偏错误的BER。
  12. 根据权利要求7-11任意一项所述的装置，还包括：
    记录模块，用于记录所述目标ECC算法和所述目标纠错位数。
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