WO2014079099A1 - Esd保护芯片数码显示检测系统 - Google Patents
Esd保护芯片数码显示检测系统 Download PDFInfo
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- WO2014079099A1 WO2014079099A1 PCT/CN2012/085706 CN2012085706W WO2014079099A1 WO 2014079099 A1 WO2014079099 A1 WO 2014079099A1 CN 2012085706 W CN2012085706 W CN 2012085706W WO 2014079099 A1 WO2014079099 A1 WO 2014079099A1
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- WIPO (PCT)
- Prior art keywords
- digital
- data line
- electrically connected
- logic operation
- display
- Prior art date
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/001—Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing
- G01R31/002—Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing where the device under test is an electronic circuit
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
- G01R31/2827—Testing of electronic protection circuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/04—Display protection
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2370/00—Aspects of data communication
- G09G2370/14—Use of low voltage differential signaling [LVDS] for display data communication
Definitions
- the invention relates to an ESD protection circuit of a liquid crystal LVDS driving circuit, in particular to an ESD protection chip digital display detecting system of a liquid crystal LVDS driving circuit.
- TFT-LCD Thin Film Transistor Liquid Crystal Display
- LCD Thin Film Transistor Liquid Crystal Display
- FIG. 1 is a schematic diagram of the main driving principle of the TFT-LCD.
- the principle is that the system PCB main board converts the R/G/B compression signal, the control signal and the driving signal through the wire and the LVDS interface on the PCB.
- Connection, PCB board by directly connecting the LVDS data processing chip IC to the source terminal and gate terminal of the flexible printed circuit board (S-COF (Source-Chip on Film) and G-COF (Gate-Chip) On Film)) is connected to the display area, and the gate terminal and the source terminal are used to obtain the required power and signal of the LCD.
- S-COF Source-Chip on Film
- G-COF Gate-Chip
- the signal transmitted by the liquid crystal display system driving the display area to the PCB main board by using the method is mainly a low voltage differential signal (LVDS) format, and the signal voltage of the LVDS format is low, the precision is high, and the voltage is changed. More sensitive, any static electricity will damage the LVDS data processing chip IC, but it will be inevitable when static electricity is generated during plugging and unplugging. Therefore, in order to avoid damage to the LVDS data processing chip IC caused by the static electricity generated in the LVDS interface, it is generally necessary to set the ESD protection circuit for the important signal at the connection between the LVDS interface and the LVDS data processing chip IC.
- LVDS low voltage differential signal
- the ESD protection circuit uses an ESD protection chip 60, which uses a Zener diode and two parallel diodes with four diodes in parallel.
- the LV1P0 signal is transmitted from the LVDS interface 20 to the LVDS data processing chip IC40 as an example.
- the LV1P0 pin, the LV1N0 pin, the LV1P1 pin, and the LV1N1 pin of the LVDS interface 20 are respectively pin-connected to the LVDS data processing chip IC40, wherein the first pin LV1P0 and the ESD protection chip 60 are simultaneously One of the series-parallel branches is connected, and the first opposing pin LV1N0 is also simultaneously connected to the other series-parallel branch of the ESD protection chip 60.
- the ESD protection chip 60 has the same diode characteristics, and the voltage drop is U D+ during forward conduction, and the reverse cutoff voltage is U D.
- the signal is transmitted. For the value U, then U D+ ⁇ U ⁇ U D- (the normal LVDS signal is about 1.2v; 11 0- is 3v; U D+ is 0.7v).
- the voltage applied to the LVDS interface 20LV1P0 pin can not form a loop through the diode D 0 and the GND pin of the LVDS interface 20, so the LVDS interface 20LV1P0 pin
- the applied voltage is the same as the voltage on the LV1P0 pin of the LVDS data processing chip IC40.
- the signal transmission path is as shown in the figure, and the signal can be normally transmitted to the LV1P0 pin of the LVDS data processing chip IC40.
- the ESD protection chip 60 when the ESD protection chip 60 is soldered over on the PCB, the normal LVDS signal input from the LV1P0 pin of the LVDS interface 20 flows through the diode to the ground GND of the LVDS interface 20, at which time LVDS data processing
- the tube voltage distortion of the LV1P0 pin in the chip IC40 is the turn-on voltage U D+ of the diode, which causes the signal output to the display area of the display screen to be abnormal, causing abnormality of the picture.
- the forward and reverse signs of the ESD protection chip are difficult to distinguish, it is difficult to separate the welding abnormal products from the normal products by the human eye alone, which may cause the defective products to be sent to the client, causing losses to the customer, and selecting welding. Abnormal products require a lot of manpower and material resources, resulting in an increase in production costs. Summary of the invention
- the object of the present invention is to provide an ESD protection chip digital display detection system, which uses the system to detect three signals on the LVDS interface, thereby quickly distinguishing the ESD protection chip welding normal product from the welding abnormal product, and accurately positioning the abnormal position. It saves manpower and material resources, reduces production costs, and prevents welding abnormal products from flowing out to the client, causing losses to customers.
- an ESD protection chip digital display detection system including: an LVDS interface, a display system, first, second, and third data lines, a power supply, and a resistor, the first, second, and One end of the three data lines is electrically connected to the LVDS interface, and the other end is electrically connected to the display system.
- One end of the resistor is electrically connected to the display system, and the other end is electrically connected to one end of the power supply, and the other end of the power supply is electrically connected to the LVDS interface.
- the display system includes: a logic operation module and a digital display module electrically connected to the logic operation module, wherein the logic operation module is electrically connected to the first, second, and third data lines, and the ESD protection chip is electrically connected During the LVDS interface, the logic operation module collects signals on the first, second, and third data lines, and drives the digital display module to display characters after logical operations.
- the display system includes first to fourth pins, one end of the first data line is electrically connected to the first pin of the display system, and one end of the second data line is electrically connected to the second pin of the display system.
- One end of the third data line is electrically connected to a third pin of the display system, and the One end of the resistor is electrically connected to the fourth pin of the display system.
- the LVDS interface includes: a fifth pin, a fifth opposite pin, a sixth pin, and a ground pin, and the other end of the first data line is electrically connected to the fifth pin, the second data line The other end is electrically connected to the fifth opposite pin, and the other end of the third data line is electrically connected to the sixth pin.
- the power source includes a positive pole and a negative pole, and the other end of the resistor is electrically connected to the positive pole of the power source, and the negative pole of the power source is connected to the grounding pin of the LVDS interface, thereby enabling the power source, the resistor, the display system, the ESD protection chip and The LVDS interface forms a loop.
- the digital display module is a seven-segment common anode digital display tube, and the digital display module includes: seventh to thirteenth pins, and the logic operation module applies signals on the seventh to thirteenth pins They are A to G digital signals, respectively, and the digital display module displays different characters according to the A to G digital signals.
- the seven-segment common anode digital display tube includes seven display fields a to g, and the A to G digital signal corresponds to seven display field settings of a to g.
- the characters displayed by the digital display module include: 1, 2, 3 and 5, when the first data line is turned on separately, the digital display module displays the character 1, and when the second data line is turned on separately, the digital display module Displaying character 2, when the third data line is turned on separately, the digital display module displays the character 3, and when the plurality of data lines are simultaneously turned on, the digital display module displays the character, the logical operation module has a plurality of digital NOT gates, or And a gate logic operation unit, wherein the logic operation module generates the A to G digital signals by using signals on the first, second, and third data lines.
- the digital signal obtained by the logic operation module collecting the signal on the first data line is recorded as: the digital signal obtained by the logic operation module collecting the signal on the second data line is recorded as Y, and the logic operation module collects the third data.
- the digital signal obtained by the signal on the line is recorded as Z, and the A to G digital signals generated by the logic operation module satisfy the following relationship:
- the digital signal is generated by a digital signal operation by a NOT gate in the logic operation module, and the digital signal is generated by a digital signal operation by a NOT gate in the logic operation module, and the digital signal is generated by a logic operation module.
- the non-gate is generated using a digital signal Z operation.
- the invention also provides an ESD protection chip digital display detection system, comprising: an LVDS interface, a display system, first, second and third data lines, a power supply and a resistor, and one end of the first, second and third data lines The other end is electrically connected to the display system, the other end is electrically connected to one end of the power supply, and the other end of the power supply is electrically connected to the LVDS interface, and the display is electrically connected to the LVDS interface.
- the system includes: a logic operation module and a digital display module electrically connected to the logic operation module, wherein the logic operation module is electrically connected to the first, second, and third data lines, and the ESD protection chip is electrically connected to the LVDS interface
- the logic operation module collects signals on the first, second, and third data lines, and drives the digital display module to display characters after logical operations;
- the display system includes first to fourth pins, one end of the first data line is electrically connected to the first pin of the display system, and one end of the second data line is electrically connected to the second end of the display system. a pin, the third data line is electrically connected to the third pin of the display system, and one end of the resistor is electrically connected to the fourth pin of the display system;
- the LVDS interface includes: a fifth pin, a fifth opposite pin, a sixth pin, and a ground pin, and the other end of the first data line is electrically connected to the fifth pin, the second The other end of the data line is electrically connected to the fifth opposite pin, and the other end of the third data line is electrically connected to the sixth pin;
- the power source includes a positive pole and a negative pole, and the other end of the resistor is electrically connected to the positive pole of the power source, and the negative pole of the power source is connected to the grounding pin of the LVDS interface, thereby enabling the power supply, the resistor, the display system, and the ESD protection.
- the chip and the LVDS interface form a loop;
- the digital display module is a seven-segment common anode digital display tube, and the digital display module includes: seventh to thirteenth pins, and the logic operation module is applied to the seventh to thirteenth
- the signals on the pins are respectively A to G digital signals, and the digital display module displays different characters according to the A to G digital signals;
- the seven-segment common anode digital display tube comprises seven display fields a to g, and the A to G digital signals correspond to seven display field settings of a to g;
- the characters displayed by the digital display module include: 1, 2, 3, and 5.
- the digital display module displays the character 1, and when the second data line is turned on separately, the digital The display module displays the character 2, when the third data line is turned on separately, the digital display module displays the character 3, and when the plurality of data lines are simultaneously turned on, the digital display module displays the character 5;
- the logic operation module has a plurality of digital NOT gates, OR gates, and AND gate logic operation units, and the logic operation module generates signals by using signals on the first, second, and third data lines.
- the digital signal obtained by the logic operation module collecting the signal on the first data line is recorded as: the digital signal obtained by the logic operation module collecting the signal on the second data line is recorded as, and the logic operation module collects the third
- the digital signal obtained by the signal on the data line is denoted as Z, and the A to G digital signals generated by the logic operation module satisfy the following relationship:
- the digital display detection system of the ESD protection chip of the present invention detects three signals on the LVDS interface pin, and transmits the collected signal to the logic operation module for logic operation, thereby making the corresponding corresponding in the digital display tube
- the diode emits light, and then displays different characters.
- the system can be expanded into a multi-channel detection system as needed.
- FIG. 1 is a schematic structural view of a conventional TFT-LCD driving principle
- FIG. 2 is a schematic diagram of a normal access circuit of an existing LVDS line ESD protection chip
- FIG. 3 is a schematic diagram of a reverse abnormal access circuit of an existing LVDS line ESD protection chip
- FIG. 4 is a circuit diagram of a digital display detection system of an ESD protection chip according to the present invention
- 5 is a schematic diagram of a connection structure between an ESD protection chip digital display detection system and an ESD protection chip according to the present invention
- FIG. 6 is a schematic diagram showing the circuit structure of a logic operation module in the digital display detection system of the ESD protection chip of the present invention. Detailed ways
- the present invention provides an ESD protection chip digital display detection system, including: an LVDS interface 20, a display system 30, one end electrically connected to the LVDS interface 20, and the other end electrically connected to the display system 30.
- a data line L1, a second data line L2 and a third data line L3, a power source 50 and one end are electrically connected to the display system 30, and the other end is connected to the power source.
- the electrical connection 50 is electrically connected to the LVDS interface 20, and the display system 30 includes: a logic operation module 301 and a digital display module 302 electrically connected to the logic operation module 301, the logic operation The module 301 is electrically connected to the first data line L1, the second data line L2, and the third data line L3.
- the logic operation module 301 collects the first data.
- the signals on the line L1, the second data line L2 and the third data line L3 are driven to drive the digital display module 302 to display characters, and the user can quickly determine the ESD protection chip 60 according to the characters displayed by the digital display module 302. Whether the welding is correct, saving manpower and material resources, improving work efficiency and reducing production costs.
- the display system 30 includes first to fourth pins P1-P4, and the LVDS interface 20 includes a fifth pin P51, a fifth opposite pin P52, a sixth pin P6, and a ground pin GND.
- 50 includes a positive electrode and a negative electrode.
- the first data line L1 is electrically connected to the first pin P1 of the display system 30, and the other end is electrically connected to the fifth pin P51.
- the second data line L2 is electrically connected to the display system 30.
- the second pin P2 is electrically connected to the fifth opposite pin P52;
- the third data line L3 is electrically connected to the third pin P3 of the display system 30, and the other end is electrically connected to the a six-pin P6;
- the resistor R-terminal is electrically connected to the fourth pin P4 of the display system 30, and the other end is electrically connected to the positive pole of the power supply 50;
- the negative terminal of the power supply 50 is connected to the grounding lead of the LVDS interface 20.
- the foot GND causes the power supply 50, the resistor R, the display system 30, the ESD protection chip 60, and the LVDS interface 20 to form a loop that drives the digital display module 302 in the display system 30 to display characters.
- the logic operation module 301 has a plurality of digital NOT gates 304, OR gates 305 and AND gates 306 logic operation units, and the logic operation modules 301 generate A to G digital signals by using signals on the first to third data lines L1-L3. .
- the preferred standard voltage is 0.95V. The following description is based on 0.95V:
- the line works normally in LVDS.
- the connection of the ESD protection chip 60 on the line is abnormal.
- the digital signal on the first data line L1 is recorded as a digital signal generated by the non-operation of the digital signal by the NOT gate 304 in the logic operation module 301.
- the second data line L2 When >0.95V, it indicates that the fifth relative pin P52 of the LVDS interface 20 connected to the second data line L2 is normal, the second data line L2 is disconnected, and the logic operation module 301 collects the simulation on the second data line L2. The signal gets a digital signal of zero. The digital signal on the second data line L2 is recorded as a digital signal generated by the logic operation module 301 via the NOT gate 304 to the digital signal.
- the logic operation module 301 satisfies the following relationship according to the input signal and the A to G digital signals generated by the above definition:
- G ⁇ Y + Z takes the generation of digital signals B and C as an example to illustrate the logical connection relationship between the input digital signal and Z of its logic operation input module.
- the first and the Z signals are respectively connected in parallel with a non-gate 304 logic operation unit to generate ⁇ , ⁇ 7 and signals.
- Generation of digital signal The OR signal is operated by an OR gate logic operation unit 305, and then subjected to a non-operation by a NOT gate logic operation unit 304, thereby obtaining a digital signal A;
- the generation of the digital signal B an aND gate logic operation unit, ⁇ 7 and Z signals and the operation produces the digital signal H, generates a digital signal i by one aND gate logic operation unit 306, Gamma] and a signal with the operation of an aND gate logic unit 306
- the AND signal is ANDed to generate a digital signal j, and then the h, i and j signals are connected to an OR gate logic operation unit 305, and then subjected to a non-operation by a NOT gate logic operation unit 304, thereby obtaining a digital signal B. ;
- the generation of the digital signal C is performed by an OR gate logic operation unit 305 and then the Z signal is ORed, and then subjected to a non-operation by a NOT gate logic operation unit 304, thereby obtaining a digital signal C;
- the generation of the digital signal F an AND signal is operated by an AND logic operation unit to generate a digital signal k, and an AND logic operation unit 306 and the Z signal are combined to generate a digital signal 1, which is operated by an AND gate.
- the unit 306 performs an AND operation on the Z signal to generate a digital signal m, and then connects the k, 1 and m signals to an OR gate logic operation unit 305, and then performs a non-operation through a NOT gate logic operation unit 304 to obtain a number.
- Signal F an AND signal is operated by an AND logic operation unit to generate a digital signal k, and an AND logic operation unit 306 and the Z signal are combined to generate a digital signal 1, which is operated by an AND gate.
- the unit 306 performs an AND operation on the Z signal to generate a digital signal m, and then connects the k, 1 and m signals to an OR gate logic operation unit 305, and then performs a non-operation through a NOT gate logic operation unit 304 to obtain a number.
- the generation of the digital signal G The OR signal is ORed by an OR gate logic operation unit, and the non-gate logic operation unit 304 performs a non-operation, thereby obtaining a digital signal G.
- the digital display module 302 is a seven-segment common anode digital display tube 303, and the digital display module 302 includes: seventh to thirteenth pins, and the logic operation module 301 is applied to the seventh to thirteenth leads.
- the signals on the feet are respectively A to G digital signals, and the digital display module 302 displays different characters according to the A to G digital signals.
- the characters displayed by the digital display module 302 include: 1, 2, 3, and 5.
- the digital display module 302 displays the character 1 when the second data line L2 is turned on separately.
- the digital display module 302 displays the character 2
- the digital display module 302 displays the character 3 when multiple data lines are simultaneously turned on (two or three of the three data lines) At the same time, the digital display module 302 displays the character 5.
- the detection system of the present invention is not limited to three-way detection, and can be expanded to a multi-channel detection system as needed.
- the present invention provides an ESD protection chip digital display detection system, which detects three signals on an LVDS interface pin, and transmits the acquired signal to a logic operation module for logic operation, thereby correspondingly corresponding to the digital display tube.
- the diode emits light, and then displays different characters.
- the characters displayed on the digital display tube are used to judge whether the welding of the ESD protection chip on the LVDS interface is normal, and the welding normal product and the welding abnormal product can be quickly distinguished, and the abnormal position can be accurately located. It saves manpower and material resources, reduces production costs, prevents welding abnormal products from flowing out to the client, and causes losses to customers.
- the system can be expanded into a multi-channel detection system as needed.
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- Crystallography & Structural Chemistry (AREA)
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US13/807,066 US8836353B2 (en) | 2012-11-23 | 2012-12-01 | Digitally displaying inspection system for ESD protection chip |
DE112012007175.1T DE112012007175B4 (de) | 2012-11-23 | 2012-12-01 | Prüfsystem mit digitaler Anzeige für ESD-Schutzbaustein |
Applications Claiming Priority (2)
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CN201210483171.5 | 2012-11-23 | ||
CN201210483171.5A CN102937689B (zh) | 2012-11-23 | 2012-11-23 | Esd保护芯片数码显示检测系统 |
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WO2014079099A1 true WO2014079099A1 (zh) | 2014-05-30 |
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PCT/CN2012/085706 WO2014079099A1 (zh) | 2012-11-23 | 2012-12-01 | Esd保护芯片数码显示检测系统 |
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CN (1) | CN102937689B (zh) |
DE (1) | DE112012007175B4 (zh) |
WO (1) | WO2014079099A1 (zh) |
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CN104749437B (zh) * | 2013-12-25 | 2018-02-06 | 上海华虹宏力半导体制造有限公司 | 版图上io间esd电阻的检查方法 |
CN104008743B (zh) * | 2014-05-28 | 2017-01-11 | 深圳市华星光电技术有限公司 | 一种静电放电保护芯片及驱动电路 |
CN105118412A (zh) * | 2015-09-29 | 2015-12-02 | 京东方科技集团股份有限公司 | Dvi信号转换装置和dvi信号输入测试板卡 |
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2012
- 2012-11-23 CN CN201210483171.5A patent/CN102937689B/zh active Active
- 2012-12-01 WO PCT/CN2012/085706 patent/WO2014079099A1/zh active Application Filing
- 2012-12-01 DE DE112012007175.1T patent/DE112012007175B4/de not_active Expired - Fee Related
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Publication number | Publication date |
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CN102937689B (zh) | 2015-04-01 |
DE112012007175T5 (de) | 2015-08-13 |
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