WO2013135181A1

WO2013135181A1 - Inverter topology in high-frequency application and control method therefor

Info

Publication number: WO2013135181A1
Application number: PCT/CN2013/072582
Authority: WO
Inventors: 谢胜仁; 冯卓民; 顾亦磊
Original assignee: 伊顿制造（格拉斯哥）有限合伙莫尔日分支机构
Priority date: 2012-03-14
Filing date: 2013-03-14
Publication date: 2013-09-19
Also published as: CN103312202B; CN103312202A

Abstract

Provided is an inverter topology in high-frequency application, comprising: a first and second capacitor, a first, second, third and fourth power switch transistor, and a second and third diode. Each power switch transistor comprises anti-parallel parasitic diodes; the first capacitor and the second capacitor are connected in series, both ends thereof being connected to a positive DC bus and a negative DC bus respectively, so as to provide a DC input and output; the contact point of the second and third power switch transistor is connected with an inductor to provide an AC output; one reverse fifth power switch transistor and one reverse sixth power switch transistor are connected in series to the first and fourth power switch transistor respectively, each of the fifth and sixth power switch transistors comprises anti-parallel parasitic diodes, and the freewheeling current flowing through the parasitic diodes of the first and fourth power switch transistor is cut off by controlling the ON and OFF state the fifth and sixth power switch transistor; also, a discrete first diode and a discrete fourth diode are connected in parallel to the positive DC bus and the negative DC bus respectively, so as to provide a freewheeling circuit.

Description

Inverter topology in high frequency application and its control method

The present invention relates to the field of inverters, and more particularly to an inverter topology and a control method thereof for high frequency applications. Background technique

In today's inverter sector, designing inverters with smaller volumes and higher power densities is one of the trends. The Super Junction Field Effect Transistor (Cool MOSFET, abbreviated as Cool MOS) is a new generation of semiconductor switching devices with very small on-resistance equivalents and no current tailing of insulated gate bipolar transistors (IGBTs). It has been widely used in the field of high frequency communication power supplies. However, Cool MOS applications have certain limitations on high frequency inverters. Because: (1) its parasitic body diode reverse recovery is poor, causing the freewheeling current (ie, passive current) to generate a large reverse recovery current on the diode, resulting in high switching loss and even the risk of instantaneous short circuit; (2) Poor reverse recovery of the parasitic body diode also causes high voltage spikes, thereby burning the MOSFET.

For example, FIG. 1 is a topological structure of a high efficiency inverter in the prior art, including two capacitors, two diodes Dx and Dx, and four power switches Ql, Q2, Q3, and Q4. Among them, Ql and Q4 are Cool MOS, and Q2 and Q3 are IGBTs. The control method is traditional SPWM (sinusoidal pulse width modulation), but its switching frequency is generally not high, mostly 19.2K. When the power is increased, the switching frequency may be lowered.

With continued reference to Figure 1, when the load on the inverter is a non-linear load, there is a reverse current on the output filter inductor 102 when the positive half-bridge upper arm 101 is operating. When Q1 is Cool MOS, the reverse freewheeling current will continue to flow through the parasitic body diode 103 of Q1. If the reverse recovery of the parasitic body diode 103 of Q1 is poor, when Q3 is turned on, Q1, Q2, and Q3 will be turned on at the same time, and a short circuit will be formed to the ground (that is, the neutral point shown in the circuit) through Dx. Even if the body diode of Q1 can be turned off in time (the tube is not damaged), a large current spike will cause a voltage spike on the tube.

In order to achieve an efficient high frequency inverter, the switching frequency is increased and the magnetic component volume is reduced. As shown in the inverter structure shown in Figure 2, all the switching tubes are Cool MOS, so that even with higher frequency switching, the loss on the switching tube will not be large, because Cool MOS has better switching characteristics. . Among them, Q1 and Q4 need to have ultra-fast recovery parasitic diodes, but The cost of class Cool MOS is very high. Summary of the invention

The technical problem to be solved by the present invention is to provide an inverter topology and a control method thereof in a high frequency application, which have lower cost and obtain higher efficiency.

According to an embodiment of the present invention, an inverter topology in a high frequency application is provided, including: first and second capacitors, first, second, third, and fourth power switches, second and a three diode; wherein each power switch tube comprises a parasitic body diode connected in anti-parallel;

The first capacitor and the second capacitor are connected in series, and the two ends thereof are respectively connected to the positive DC bus and the negative DC bus to provide DC input and output;

The second diode is connected in series with the third diode, and the four power switching tubes are sequentially connected in series with the source and the drain connected;

The two capacitors connected in series are connected in parallel with the four power switch tubes connected in series, and the junction of the first capacitor and the second capacitor is connected to the junction of the second diode and the third diode and connected Sexual point or reference ground;

The cathode of the second diode is connected to the junction of the first power switch tube and the second power switch tube, and the anode of the third diode is connected to the contact point of the third power switch tube and the fourth power switch tube;

The second and third power switch tubes are connected to the inductor to provide an AC output; wherein, the first and fourth power switch tubes are respectively connected in series with a reverse fifth and sixth power switch tubes, and each Each of the power switch tubes includes an antiparallel parasitic body diode and a parasitic capacitance connected in parallel to block flow through the first and fourth power switch tubes by controlling turn-on and turn-off of the fifth and sixth power switch tubes The freewheeling current of the parasitic diode; at the same time, a separate first and fourth diodes are connected in parallel to the upper and lower arms to provide a freewheeling circuit.

Optionally, the serial connection manner of the first to sixth power switch tubes is:

The source of the first power switch is connected to the source of the fifth power switch,

a drain of the fifth power switch is connected to a drain of the second power switch,

a source of the second power switch is connected to a drain of the third power switch,

The source of the third power switch is connected to the drain of the fourth power switch,

The source of the fourth power switch tube is connected to the source of the sixth power switch tube;

The cathode of the second diode is connected to the junction of the fifth and second power switch tubes, the third two The anode of the pole tube is connected to the junction of the third and fourth power switch tubes;

The cathode of the first diode is connected to the drain of the first power switch tube, the anode of the fourth diode is connected to the drain of the sixth power switch tube, and the junction of the first and fourth diodes is connected to the second Connected to the junction of the third power switch.

a drain of the fifth power switch is connected to a drain of the first power switch,

a source of the first power switch is connected to a drain of the second power switch,

The source of the third power switch tube is connected to the source of the sixth power switch tube,

a drain of the sixth power switch is connected to a drain of the fourth power switch;

a cathode of the second diode is connected to a junction of the first and second power switch tubes, and an anode of the third diode is connected to a junction of the third and sixth power switch tubes;

The cathode of the first diode is connected to the source of the fifth power switch tube, the anode of the fourth diode is connected to the source of the fourth power switch tube, and the junction of the first and fourth diodes is connected to the second Connected to the junction of the third power switch.

a cathode of the second diode is connected to a junction of the fifth and second power switch tubes, and an anode of the third diode is connected to a junction of the third and fourth power switch tubes;

a cathode of the first diode is connected to a drain of the first power switch tube, and an anode of the first diode is connected to a contact point of the fifth and second power switch tubes;

The anode of the fourth diode is coupled to the drain of the sixth power switch transistor, and the cathode of the fourth diode is coupled to the junction of the third and fourth power switch transistors.

Optionally, the parasitic body diodes of the fifth and sixth power switch tubes are diodes having avalanche breakdown characteristics.

Optionally, the fifth and sixth power switch tubes have R _ds _ as small as possible. _n . According to another aspect of the present invention, a method for driving a control signal of an inverter topology is provided, including:

When working in the middle of a week:

Steps A, first, second, and fifth power switch tubes are turned on, so that current in the topology passes through the three power switch tubes;

Step A2, the first and fifth power switch tubes are turned off, so that the current in the topology first charges the parasitic capacitances of the first and fifth power switch tubes, and then flows through the first diode;

Step A3, the third and fifth power switch tubes are turned on, so that the current in the topology is freewheeled through the third power switch tube and the third diode; and the parasitic capacitance of the first power tube passes through the fifth power tube and the second Power tube charging;

Step A4: The third power switch is turned off, so that the reverse passive current reversely charges the parasitic capacitance of the first power switch tube until the V _{ds of the} first power switch tube is lower than the fifth power switch tube. V _ds ;

Step A5, the fifth power switch tube is turned off to block the reverse current, so that the current in the topology is freewheeled through the first diode;

When working in the negative half cycle:

Steps Bl, third, fourth, the sixth power switch tube is turned on, so that the current in the topology passes through the three power switch tubes;

Step B2, the fourth and sixth power switch tubes are turned off, so that the current first charges the parasitic capacitances of the fourth and sixth power switch tubes, and then flows through the fourth diode;

Step B3, the second and sixth power tubes are turned on, and the inductor current can be freewheeled by the second diode and the second power tube; meanwhile, the parasitic capacitance of the fourth power tube is charged by the sixth power tube and the third power tube;

Step B4: The second power tube is turned off, so that the reverse passive current is reversely charged to the parasitic capacitance of the fourth power tube through the sixth power tube and the third power tube until the V _d on the fourth power tube is in the The maximum power of the six power tubes can withstand V _ds ;

Step B5, the sixth power tube is turned off, and the reverse current is blocked to make it flow through the fourth diode.

Optionally, the step A3 of the positive half-cycle operation further comprises: simultaneously opening the third and fifth power switch tubes; and the step B3 of the negative half-cycle operation further comprises: simultaneously opening the second and sixth power switch tubes. Optionally, the first and fourth diodes are fast recovery or ultra fast recovery rectifier diodes. According to still another aspect of the present invention, a method for driving a control signal of an inverter topology is provided, including:

When working in the middle of a week:

Step Cl, the first, second, and fifth power switch tubes are turned on, so that the current in the topology passes through the three power switch tubes;

Step C2, the first and fifth power switch tubes are turned off, and when the inductor current and the voltage are in the same direction, the current in the topology flows through the second diode and the second power switch tube, and when the inductor current and the voltage are reversed, The current in the topology flows through the first diode to the positive DC bus;

Step C3, the first and fifth power switch tubes are kept off, and the third power switch tube is turned on. When the inductor current and the voltage are in the same direction, the current in the topology flows through the second diode and the second power switch tube. When the inductor current is reversed from the voltage, the current in the topology flows through the third diode and the third power switch tube;

Step C4, the first and fifth power switch tubes are kept off, the third power switch tube is turned off, and when the inductor current and the voltage are in the same direction, the current in the topology flows through the second diode and the second power switch tube. When the inductor current is reversed from the voltage, the current in the topology continues to flow through the first diode.

When working in the negative half cycle:

Steps D1, third, fourth, the sixth power switch tube is turned on, so that the current in the topology passes through the three power switch tubes;

Step D2, the fourth and sixth power switch tubes are turned off, and when the inductor current and the voltage are in the same direction, the current in the topology is freewheeled through the third power switch tube and the third diode, and when the inductor current and the voltage are reversed, The current in the topology flows from the negative DC bus to the output through the fourth diode;

Step D3, the fourth and sixth power switch tubes are kept off, the second power switch tube is turned on, and when the inductor current and the voltage are in the same direction, the current in the topology flows through the third power switch tube and the third diode. When the inductor current is reversed from the voltage, the current in the topology flows through the second diode and the second power switch tube;

Step D4, the fourth and sixth power switch tubes are kept off, the second power switch tube is turned off, and when the inductor current and the voltage are in the same direction, the current in the topology passes through the third power switch tube and the third diode freewheeling When the inductor current is reversed from the voltage, the current in the topology continues to flow through the fourth diode. Compared with the prior art, the invention has the advantages that: the added fifth and sixth power switch tubes and diodes are of a low voltage type, and the cost is low; the first and fourth power switch tubes in the inverter topology are not A special Cool MOS with a fast recovery body diode is required, and a cheaper common Cool MOS can be selected, and such a Cool MOS has a lower on-resistance, a lower price, and a higher efficiency. Moreover, the second and third power switch tubes only need to select a normal Cool MOS. DRAWINGS

1 is a schematic diagram of a topology structure of a commonly used high efficiency inverter in the prior art;

2 is a schematic diagram of a topology of an inverter suitable for a high frequency switch in the prior art; FIG. 3 is a schematic diagram of a topology of a high frequency inverter proposed in an embodiment of the present invention; FIG. 4a-4d are diagrams A schematic diagram of driving mode and working mode of the high frequency inverter proposed in one embodiment;

5 is a schematic diagram of a driving mode of a high frequency inverter according to another embodiment of the present invention; FIGS. 6a-6f are schematic diagrams showing an operation mode of the driving mode of FIG. 5;

7 is a schematic diagram of a topology structure of a high frequency inverter according to another embodiment of the present invention; and FIG. 8 is a schematic diagram of a topology structure of a high frequency inverter proposed in still another embodiment of the present invention. detailed description

In order to make the objects, technical solutions, and advantages of the present invention more comprehensible, the present invention will be further described in detail below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

According to the analysis of the background art, in order to achieve high frequency of the inverter, it is necessary to reduce the switching loss of the power switch tube at a high frequency, and at the same time, have a low conduction loss. Using Cool MOS as a power switch is a good choice, but in a three-level inverter, due to the nonlinearity of the load, it is necessary to consider the reverse freewheeling current to the high frequency switch in the case of a non-linear load. The influence of the parasitic body diode of the tube. Cool MOS with good body diode reverse recovery is a solution, but these diodes are more expensive.

The inventors found through research that: in the high-frequency switch tube (Ql, Q4 of Figure 2), a reverse low-voltage switch tube is connected in series, and by controlling the turn-on and turn-off of the low-voltage switch tube, the high-frequency switch can be blocked. The freewheeling current of the parasitic body diode, and a separate diode (Dl, D4) in parallel with the upper and lower arms to provide a freewheeling circuit, which can avoid ordinary Cool in high frequency applications. Problems caused by poor reverse recovery of MOS parasitic diodes. Based on the above findings, in accordance with an embodiment of the present invention, a three-level inverter suitable for high frequency applications is provided. As shown in FIG. 3, the topology (ie, circuit structure) includes capacitors Cl, C2, power switch tubes Q1, Q2, Q3, Q4, power switch tubes Q5 and Q6, diodes D1, D2, D3, D4; each power The switching transistors all have parasitic body diodes and parasitic capacitances (not shown in Figure 3).

Wherein, one end of the capacitor C1 and one end of the capacitor C2 are connected in series; the anode of the diode D2 is connected in series with the cathode of D3; the anode of the diode D1 is connected in series with the cathode of D4; the power switch tube Ql, Q2, Q3, Q4, Q5 and Q6 are connected in series; the series connection mode of the power switch is that the source of Q1 is connected to the source of Q5, the drain of Q5 is connected to the drain of Q2, the source of Q2 and the drain of Q3. Connected, the source of Q3 is connected to the drain of Q4, and the source of Q4 is connected to the source of Q6;

The other end of the capacitor C1 is connected to the drain of the power switch tube Q1, the other end of the capacitor C2 is connected to the drain of the power switch tube Q6, and the junction of the capacitors C1 and C2 is connected to the junction of the diodes D2 and D3 and connected to the Neutral ( Neutral point, refers to the N line in the input L, N line, that is, the zero line; is the reference ground of the inverter system); the cathode of the diode D2 is connected to the junction of the power switch tube Q5 and Q2, and the anode connection power of the diode D3 The junction of the switch tube Q3 and Q4; the cathode of the diode D1 is connected to the drain of the power switch tube Q1, the anode of the diode D4 is connected to the drain of the power switch tube Q6, the junction of the diodes D1 and D4 is connected with the power switch tube Q2 and The junction of Q3 is connected.

When Q5, Q6 are turned on, the current will not pass through its parasitic body diodes D5 and D6 (bypassing diodes D5 and D6), the conduction loss is low; when Q5, Q6 are turned off, the passive current will flow through D1 and D4. , avoiding the problem of poor reverse recovery of the parasitic body diodes of Q1 and Q4 (using Cool MOS). That is, the power switch tubes Q5, Q6 and D1, D4 can prevent passive current from passing through the parasitic body diodes of Q1 and Q4, so that Q1 and Q4 can be used with lower source-drain equivalent resistance (Low R _ds _ _on ) It does not require the ultra-fast recovery of the body MOS of the body MOS, which reduces the cost of the inverter circuit structure.

In this embodiment, the upper bridge arm includes power switch tubes Q1, Q2, and Q5; and the lower bridge arm includes Q3, Q4, and Q6.

Preferably, in order to achieve higher efficiency, Q5, Q6 should have as small as possible R _ds _. _n (for example, 1.8m ohm). The control method of the inverter topology shown in Fig. 3 will be described below.

Since the current and voltage phases are inconsistent when the load is a non-resistive load (PF is not a power factor of 1), there will be instantaneous high voltage on the low voltage pipes Q5 and Q6, so if the low voltage pipes Q5 and Q6 are connected to the diode (ie, the parasitic diodes of the low-voltage tubes Q5 and Q6) With the avalanche breakdown function, the MOS tubes of the low-voltage tubes Q5 and Q6 can be protected.

According to an embodiment of the present invention, the power switching tubes Q5 and Q6 are low voltage switching tubes including a diode having an avalanche breakdown characteristic. The timing chart of the driving signals of the inverter topology shown in FIG. 3 may be as shown in FIG. 4a. Among them, Ql, Q2, Q3, Q4 drive the traditional SPWM control of the switch. Q1 and Q3, Q2 and Q4 are high frequency complementary, while Q1 and Q3 work in the first half of the power frequency cycle, and Q2 and Q4 work in the second half of the power frequency cycle. The Q5 driver follows Ql and the Q6 driver follows Q4. The working mode of the corresponding circuit is shown in Figures 4b~4c.

Due to the symmetrical relationship of the circuit, it can be explained by the working process of the positive half cycle, where: (1) Ql, Q2, Q5 are turned on, when the voltage and current are in the same direction, the circuit works as shown in Fig. 4b, and the voltage is modulated according to the sine law. Change; current from the positive DC bus end, that is, the positive end of C1, through Ql, Q5, Q2 through the output inductor and capacitor, to the load end, and finally through the load, into the ground of the system is the neutral point. When the load current is reversed, the current flows through the inductor, Q2, Q5, and Q1 to the positive DC bus.

(2) In the dead time (Ql, Q5 is off and Q3 is not open), when the inductor current and voltage are in the same direction, the circuit works as shown in Figure 4c, and the inductor current will immediately flow through D2 and Q2. The current flows to D2, Q2 to the output inductor, and returns to the ground of the system through the load. If the current is reversed at this time, the inductor current can flow through D1 to the positive DC bus terminal.

(3) After the dead time, Ql, Q5 are closed and Q3 is turned on. When the inductor current is positive, the inductor current loop remains unchanged, as shown in Figure 4c. However, if the inductor current is reversed, the inductor current will continue to flow through Q3 and D3. At this time, the parasitic capacitance on Q1 will be charged, and the capacitance between the DS drain and source will reach the positive bus voltage, as shown in 4d.

(4) When Q3 is turned off and Q1 and Q5 are not turned on, if the inductor current is positive, the operating state of the circuit remains unchanged in Figure 4c. However, if the inductor current is reversed, the inductor current will continue to flow through D1, but the voltage across D1 will be the positive bus voltage. On the Q1, the source remains at zero voltage, and the drain-source voltage difference is the positive bus voltage. Due to Q2 It is always on, at this time Q5 is subject to the back pressure of the positive bus voltage value. If a low pressure pipe is used, there will be an overpressure phenomenon. If a high pressure pipe is used, the efficiency will be affected.

Therefore, when Q5 has an avalanche breakdown parasitic diode, that is, D5 is an avalanche diode: When Q5 is subjected to back pressure, D5 reversely conducts, charging Q1 parasitic capacitance, forming protection for Q5 body; When the voltage value is less than the avalanche breakdown voltage value of D5, D5 is turned off, and the freewheeling current only flows through D1.

(5) When Q1 and Q5 are turned on, the current operation state returns to (1). If the power switch tubes Q5 and Q6 are low voltage switch tubes including a general (no avalanche breakdown characteristic) parasitic body diode, according to another embodiment of the present invention, another embodiment is provided for the inverter topology shown in FIG. A control method, as shown in Figure 5.

When the current and voltage have the same phase, the circuit operates in the same way as the traditional ideal mode (as shown in Figure 4a for Ql, Q2, Q3, Q4). However, the voltage and current on the inductor are always in phase difference. The design of the drive signal shown in Figure 5 is designed to properly handle the charge and discharge of the parasitic capacitance of the switch tube by controlling the switching of the device to avoid voltage spikes in the low-voltage tube. produce.

In Figure 5, the drive signal contains four period-period periodic drive signals:

Before tl time, Q5 can also be turned on one's in advance, and the time is turned on to avoid switching loss on Q5 when Q1 is turned on.

In the tl-t2 interval, Q5 remains open and conducts current;

In the t2-t3 interval, Q5 is turned off;

In the t3-t4 interval, Q5 can be turned on, which is beneficial to reduce the loss caused by the Q1 parasitic capacitance charging current. In the t4-t5 interval, Q5 is first turned on to reversely charge Q1, avoiding Q5 has a higher back pressure, and then turning off Q5 to block Q1. Reverse current

When it is close to t5, the inverter repeats the above cycle work.

In the control method of the driving signal of Fig. 5, the operation mode of the corresponding circuit is as shown in Figs. 6a to 6f. Due to the symmetrical relationship of the circuit, the working process in the positive half cycle can be used here, where:

In the first time phase, when the time t in the interval t1 and t2 in FIG. 5 (ie, when tl<t<t2), the power switch tubes Ql, Q5, and Q2 are turned on, and in FIG. 6a, the current is filtered from the output inductor, through Q2. Q5 then flows through Q1 to the positive DC bus. In the second time phase, when the time t in Figure 5 is in the interval t2 and t3 (ie, when t2 < t < t3), the power switch tube Q1 is turned off, and the inverter operates in the dead time area; The working phase is shown in Figure 6b and Figure 6c. In Figure 6b, when the power switching transistors Ql, Q5 are turned off, the current does not immediately pass through the diode D1, but the parasitic capacitance of the power switching transistors Ql, Q5 is first charged. At this point, the inductor current flows from the output filter inductor, through the parasitic capacitances on Q2, Q5, and Q1, to the positive DC bus terminal. Because of these parasitic capacitances, and the forward voltage of D1 is low, this phase is shorter. Until the voltage of the parasitic capacitor on Q5 and Q1 exceeds the forward voltage of D1, D1 will be turned on; in Figure 6c, the current flows through diode D1 to the positive DC bus, and D1 is the fast recovery or ultrafast recovery rectifier diode;

In the third time phase, when the time t in FIG. 5 is in the interval t3 and t4 (ie, t3<t<t4), in FIG. 6d, the power switch tube Q3 is turned on, and the current on the inductor passes through the power switch tube Q3 and the diode D3. After the freewheeling current, the current on the inductor flows through Q3 and D3 to the ground. At the same time, the positive DC bus charges the parasitic capacitance of Q1. At this stage, the power switch Q5 can be turned on at any time, and Q5 is turned on to provide impedance to the parasitic capacitance of Q1. Small charging circuit. Preferably, in order to realize an efficient inverter, the power switch tubes Q5 and Q3 are simultaneously turned on;

The fourth time phase, when the time t in FIG. 5 is located in the interval t4 and t5 (ie, when t4<t<t5), includes two working phases as shown in FIG. 6e and FIG. 6f; in FIG. 6e, when the power switch tube When Q3 is turned off and Q5 is still on, the reverse passive current (indicated by the arrow in the figure) reversely charges the parasitic capacitance of Q1 until the V _d of the power switch Q1 is at the maximum V _{ds of the} power switch Q5; In Figure 6f, turn off the low-voltage power switch Q5 to block the reverse current; the inductor current continues to flow through D1. In this way, the Q5 tube is briefly turned on after the Q3 tube is turned off, and the parasitic capacitance of the Q1 tube can be charged in advance, so that the voltage spike caused by the hard switch does not appear on the Q5.

The above control can solve the transient high pressure of the low pressure pipe during the switching process. If the low-voltage power switch Q5 is not turned on to reverse the capacitance of the power switch Q1 in the corresponding working phase of Figure 6e, Q5 needs to withstand the instantaneous high voltage when the diode D1 is turned on, because the midpoint of the bridge arm on the left side of the inductor It is the positive bus voltage, and Q1 and Q5 still maintain the low voltage state before D1 is turned on. In accordance with another embodiment of the present invention, an inverter topology suitable for high frequency applications is also provided. As shown in FIG. 7, the topology (ie, circuit structure) includes capacitors Cl, C2, power switch tubes Q1, Q2, Q3, Q4, power switch tubes Q5 and Q6, diodes D1, D2, D3, D4; The rate switch tubes have parasitic body diodes and parasitic capacitances (not shown).

The difference from the topology shown in FIG. 3 is: The positions of the power switch tubes Q5 and Q1 in FIG. 7 are opposite to those of the power switch tubes Q5 and Q1 in FIG. 3; the positions and diagrams of the power switch tubes Q6 and Q4 in FIG. 3 The position of the middle power switch tubes Q6 and Q4 is opposite. In this embodiment, the upper arm includes power switch tubes Q5, Q1, and Q2; and the lower arm includes Q3, Q6, and Q4.

The control scheme of the inverter topology suitable for high frequency applications shown in Fig. 7 is the same as that of the topology shown in Fig. 3, as shown in Fig. 4a and Fig. 5, respectively. In accordance with yet another embodiment of the present invention, an inverter topology suitable for high frequency applications is also provided. As shown in FIG. 8, the topology (ie, circuit structure) includes capacitors Cl, C2, power switch tubes Q1, Q2, Q3, Q4, power switch tubes Q5 and Q6, diodes D1, D2, D3, D4; each power The switching transistors each have a parasitic body diode and a parasitic capacitance (not shown).

The difference from the topology shown in Figure 3 is that the diode D1 in Figure 8 is connected in parallel with the circuit in series with the power switch tubes Q5 and Q1; in Figure 8, the diode D4 is connected in parallel with the circuit in series with the power switch tubes Q6 and Q4. In this embodiment, the upper arm includes power switches Q1 and Q5; and the lower arm includes Q4 and Q6.

The control scheme of the inverter topology suitable for high frequency applications shown in Fig. 8 is the same as that of the topology shown in Fig. 3, as shown in Fig. 4a and Fig. 5, respectively. The power switch tubes Q5, Q6 and diodes added in the above inverter topology are of low voltage type, and the cost is low; the power switch tubes Q1 and Q4 in the inverter topology do not require special quick recovery body diodes. Cool MOS, which can choose the cheaper common Cool MOS, has lower on-resistance, lower price and higher efficiency. Moreover, Q2 and Q3 only need to select ordinary Cool MOS.

It will be appreciated and appreciated that various modifications and improvements can be made to the present invention described above without departing from the spirit and scope of the invention. Therefore, the scope of the claimed technical solutions is not limited by any particular exemplary teachings presented.

Claims

Rights request:

1. An inverter topology in high frequency applications, including:

First and second capacitors, first, second, third and fourth power switching tubes, second and third diodes;

The junctions of the second and third power switches are connected to the inductor to provide an AC output; the features are:

An inverse fifth and sixth power switching tubes are respectively connected in series on the first and fourth power switching tubes, and each of the power switching tubes includes an antiparallel parasitic body diode and a parallel parasitic capacitance, and is controlled by Turning on and off the fifth and sixth power switch tubes to block the freewheeling current flowing through the parasitic body diodes of the first and fourth power switch tubes; and simultaneously connecting a separate first sum in the upper and lower arms The fourth diode provides a freewheeling circuit.

2. The inverter topology in a high frequency application according to claim 1, wherein the series connection manner of the first to sixth power switching tubes is:

a cathode of the second diode is connected to a junction of the fifth and second power switch tubes, and an anode of the third diode is connected to a junction of the third and fourth power switch tubes; The cathode of the first diode is connected to the drain of the first power switch tube, the anode of the fourth diode is connected to the drain of the sixth power switch tube, and the junction of the first and fourth diodes is connected to the second Connected to the junction of the third power switch.

3. The inverter topology in high frequency application according to claim 1, wherein

The serial connection manner of the first to sixth power switch tubes is:

4. The inverter topology in high frequency application according to claim 1, wherein

The serial connection manner of the first to sixth power switch tubes is:

The inverter topology in high frequency application according to any one of claims 1 to 4, wherein the parasitic body diodes of the fifth and sixth power switching tubes are diodes having avalanche breakdown characteristics .

1 to 4 according to the topology of the inverter according to any one of claims frequency application, wherein said fifth and sixth power switch as small an R _ds _. _n .

7. A method of driving a control signal of an inverter topology according to claim 1, comprising:

When working in the middle of a week:

When working in the negative half cycle:

Step B4: The second power tube is turned off, so that the reverse passive current is reversely charged to the parasitic capacitance of the fourth power tube through the sixth power tube and the third power tube until the V _ds on the fourth power tube is lower than The sixth power tube can withstand the maximum V _ds ;

8. The method of driving a control signal according to claim 7, wherein the positive half cycle is operated The step A3 further includes: the third and fifth power switch tubes are simultaneously turned on; and the step B3 during the negative half-cycle operation further comprises: simultaneously opening the second and sixth power switch tubes.

9. The method of driving a control signal according to claim 7, wherein the first and fourth diodes are fast recovery or ultrafast recovery rectifier diodes.

10. A method of driving a control signal of an inverter topology according to claim 5, comprising:

When working in the middle of a week:

Step C4, the first and fifth power switch tubes are kept off, the third power switch tube is turned off, and when the inductor current and the voltage are in the same direction, the current in the topology flows through the second diode and the second power switch tube. When the inductor current and the voltage are reversed, the current in the topology flows through the first diode;

When working in the negative half cycle:

Step D4, the fourth and sixth power switch tubes are kept off, the second power switch tube is turned off, and when the inductor current and the voltage are in the same direction, the current in the topology passes through the third power switch tube and the third diode Freewheeling, when the inductor current is reversed from the voltage, the current in the topology is freewheeled through the fourth diode ₍