WO2013102968A1 - 貼り合わせsoiウェーハの製造方法 - Google Patents
貼り合わせsoiウェーハの製造方法 Download PDFInfo
- Publication number
- WO2013102968A1 WO2013102968A1 PCT/JP2012/007690 JP2012007690W WO2013102968A1 WO 2013102968 A1 WO2013102968 A1 WO 2013102968A1 JP 2012007690 W JP2012007690 W JP 2012007690W WO 2013102968 A1 WO2013102968 A1 WO 2013102968A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- wafer
- rta
- soi
- treatment
- ion
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000012212 insulator Substances 0.000 title abstract 2
- 230000003647 oxidation Effects 0.000 claims abstract description 81
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 81
- 238000010438 heat treatment Methods 0.000 claims abstract description 45
- 238000011282 treatment Methods 0.000 claims abstract description 45
- 238000005468 ion implantation Methods 0.000 claims abstract description 19
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000013078 crystal Substances 0.000 claims description 9
- 239000007789 gas Substances 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 claims description 4
- 238000009832 plasma treatment Methods 0.000 claims description 4
- 238000004151 rapid thermal annealing Methods 0.000 abstract description 41
- 230000007547 defect Effects 0.000 abstract description 16
- 230000003746 surface roughness Effects 0.000 abstract description 15
- 230000032798 delamination Effects 0.000 abstract description 6
- 238000009826 distribution Methods 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 76
- 239000010408 film Substances 0.000 description 46
- 238000000137 annealing Methods 0.000 description 19
- 230000000052 comparative effect Effects 0.000 description 14
- 150000002500 ions Chemical class 0.000 description 8
- 239000001257 hydrogen Substances 0.000 description 7
- 229910052739 hydrogen Inorganic materials 0.000 description 7
- 238000000926 separation method Methods 0.000 description 6
- 238000005498 polishing Methods 0.000 description 5
- -1 hydrogen ions Chemical class 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 230000001590 oxidative effect Effects 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 238000001816 cooling Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000003776 cleavage reaction Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 230000007017 scission Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
Definitions
- the present invention relates to a method for manufacturing a bonded SOI wafer using an ion implantation delamination method, and in particular, a silicon single crystal wafer implanted with hydrogen ions or the like is bonded to a base wafer serving as a support substrate, and then peeled and bonded.
- the present invention relates to a method for manufacturing an SOI wafer.
- ion implantation separation method a technique also called Smart Cut Method (registered trademark)
- an oxide film is formed on at least one of two wafers, and gas ions such as hydrogen ions and rare gas ions are implanted from the upper surface of one wafer (bond wafer).
- the surface into which the ions are implanted is brought into close contact with the other wafer (base wafer) through an oxide film (insulating film), and then heat treatment (peeling) Heat treatment) or mechanical external force is applied to peel off one wafer (bond wafer) into a thin film with the ion-implanted layer as a cleavage plane, and further heat treatment (bond heat treatment) to form a thin film on the base wafer.
- heat treatment peel off one wafer (bond wafer) into a thin film with the ion-implanted layer as a cleavage plane, and further heat treatment (bond heat treatment) to form a thin film on the base wafer.
- This is a technique for manufacturing a bonded SOI wafer having (SOI layer) (see Patent Document 1).
- a bonded SOI wafer having a high uniformity in the thickness of a thin film, particularly an SOI layer can be easily obtained.
- polishing polish in order to remove the damaged layer and the like, mirror polishing (removal allowance: about 100 nm) called “polishing polish” has been performed in the final step after the bonding heat treatment.
- polishing including a machining element since the polishing allowance is not uniform, the film thickness uniformity of the SOI layer achieved to some extent by implantation and peeling of hydrogen ions and the like deteriorates. Problem arises.
- Patent Document 2 a heat treatment in a reducing atmosphere containing hydrogen without polishing the surface of the SOI layer (or rapid thermal annealing (RTA)) after peeling heat treatment (or after bonding heat treatment). ).
- RTA rapid thermal annealing
- Patent Document 3 after the peeling heat treatment (or after the bonding heat treatment), after forming an oxide film on the SOI layer by heat treatment in an oxidizing atmosphere, the oxide film is removed (so-called sacrificial oxidation treatment), and then reduced. It is proposed to add a heat treatment (rapid heating / rapid cooling heat treatment (RTA treatment)) in a neutral atmosphere.
- RTA treatment rapid thermal annealing
- the SOI wafer after peeling is subjected to sacrificial oxidation treatment after planarization heat treatment in an inert gas, hydrogen gas, or mixed gas atmosphere thereof, thereby planarizing the peeled surface and OSF.
- a flattening process for improving the surface roughness by performing a high-temperature heat treatment instead of the touch polish is performed, and at present, the film thickness range of the SOI layer with a diameter of 300 mm (maximum in the plane).
- An SOI wafer having a film thickness uniformity of 3 nm or less (a value obtained by subtracting the minimum film thickness value from the film thickness value) is obtained at the mass production level by the ion implantation delamination method.
- Patent Document 5 in order to reduce the surface roughness of the peeling surface, co-injection of ion species of at least two different atoms is performed, and “RTA + StabOx (stabilized oxidation)” is performed once or as a finishing step. Multiple times are described (see paragraph [0046]). [0078] In the paragraph, this StabOx (stabilized oxidation (sacrificial oxidation)) is described as 900 ° C. oxidation + 1100 ° C. Ar annealing (2 hours). Similarly, in paragraph [0087] of Patent Document 6, it is described that RTA + StabOx + RTA + thinning is performed to improve the surface roughness of the peeled surface by co-implantation of ion species.
- Patent Document 8 describes a process of delamination ⁇ ozone cleaning ⁇ hydrogen RTA (1100 to 1250 ° C.) ⁇ sacrificial oxidation ⁇ Ar annealing in order to reduce concave defects in the SOI layer (in the embodiment, RTA). (1150 ° C./30 sec) + Ar annealing (1200 ° C./1 hr)).
- Patent Documents 5 to 8 there are several methods for performing a process combining RTA and sacrificial oxidation for the purpose of improving the surface roughness of the peeling surface or reducing defects in the SOI layer. Or has been proposed.
- sacrificial oxidation is performed at a high temperature continuously after oxidation using a resistance heating type heat treatment furnace (batch furnace) as described in 900 ° C. oxidation + 1100 ° C. Ar annealing (2 hours). Since this process includes annealing for a period of time (post-annealing), there is a problem that the frequency of occurrence of slip dislocation increases.
- Patent Document 7 1100 ° C. is disclosed as the temperature of StabOx.
- OSF oxidation induction
- the method of Patent Document 8 is effective in reducing the concave defects in the SOI layer, but since Ar annealing after sacrificial oxidation is performed at a high temperature for a long time, slip dislocations are performed as in Patent Documents 5 and 6. There was a problem that the frequency of occurrence increased.
- the present invention has been made in view of the above problems, and in the production of a bonded SOI wafer by an ion implantation separation method, the occurrence of slip dislocations and defects while improving the surface roughness of the SOI layer after separation.
- An object of the present invention is to provide a method capable of manufacturing a bonded SOI wafer having an SOI layer having a desired film thickness and an excellent film thickness distribution.
- the present invention forms an ion-implanted layer inside a bond wafer by ion-implanting at least one kind of hydrogen ion or rare gas ion from the surface of a bond wafer made of a silicon single crystal. And bonding the ion-implanted surface of the bond wafer and the surface of the base wafer through an insulating film, and then peeling off a part of the bond wafer with the ion-implanted layer.
- a thermal oxide film is formed on the surface of the SOI layer by performing only thermal oxidation in a batch heat treatment furnace at a temperature of 900 ° C. or higher and 1000 ° C. or lower in the first and second sacrificial oxidation processes.
- the temperature of thermal oxidation in the first and second sacrificial oxidation treatments be 950 ° C. or higher.
- the temperature of thermal oxidation in the first and second sacrificial oxidation treatments be 950 ° C. or higher.
- a mechanical external force is applied to a part of the bond wafer by the ion implantation layer. It is preferable to use and peel. By performing bonding and mechanical peeling in this manner, the surface roughness of the peeled surface can be reduced, and the SOI layer can be planarized more efficiently.
- the first and second RTA processes are performed at a temperature of 1230 ° C. or lower. By performing the first and second RTA processes at such a temperature, occurrence of slip dislocation can be reliably suppressed.
- a high-quality bonded SOI wafer having an SOI layer that is flat and has high film thickness uniformity can be manufactured while suppressing the occurrence of slip dislocation and defects.
- FIG. 1 is a flowchart of a method for manufacturing a bonded SOI wafer according to the present invention.
- a mirror-polished silicon single crystal wafer is prepared as a bond wafer 10 and a base wafer 11 serving as a support substrate.
- an oxide film 12 is formed on the bond wafer 10 by, for example, thermal oxidation or CVD oxidation.
- the oxide film 12 may be formed only on the base wafer 11 or may be formed on both wafers.
- step (c) of FIG. 1 at least one kind of gas ion is implanted among hydrogen ions and rare gas ions to form an ion implantation layer 13 inside the bond wafer 10.
- the surface of the bond wafer 10 on the ion-implanted side and the surface of the base wafer 11 are bonded together with the oxide film 12 interposed therebetween.
- both wafers may be cleaned before bonding.
- the bond wafer 10 is peeled off with the ion implantation layer 13 as a boundary, the buried oxide film 14 and the SOI layer 16 are formed on the base wafer 11, and the bonded SOI wafer 15 is obtained. .
- a method of performing peeling using a mechanical external force without performing heat treatment or after applying a low-temperature heat treatment not to peel is preferable.
- heat treatment can be performed at a temperature of 500 ° C. or higher in an inert gas atmosphere, and peeling can be performed by crystal rearrangement and bubble aggregation.
- the first RTA process is performed on the bonded SOI wafer 15 after peeling, then the first sacrificial oxidation process is performed, and then the second RTA process is performed. Then, a second sacrificial oxidation process is performed. At this time, the first and second RTA processes are performed at a temperature of 1100 ° C. or higher in an atmosphere containing hydrogen gas. Further, in the first and second sacrificial oxidation treatments, a thermal oxide film is formed on the surface of the SOI layer 16 by performing only thermal oxidation in a batch heat treatment furnace at a temperature of 900 ° C. or higher and 1000 ° C. or lower, and then the thermal oxidation film is formed. A process for removing the oxide film is performed.
- post-annealing after thermal oxidation of sacrificial oxidation treatment (for example, heat treatment in a non-oxidizing atmosphere at a temperature exceeding 1000 ° C.) is performed by performing RTA treatment at a temperature of 1100 ° C. or higher in an atmosphere containing hydrogen gas.
- thermal oxidation of sacrificial oxidation treatment for example, heat treatment in a non-oxidizing atmosphere at a temperature exceeding 1000 ° C.
- RTA treatment at a temperature of 1100 ° C. or higher in an atmosphere containing hydrogen gas.
- the sacrificial oxidation treatment can be performed after the damaged layer on the peeled surface is recovered and flattened by the RTA treatment, the occurrence of defects during thermal oxidation can be suppressed. Further, by performing the planarization and the thinning process to a desired film thickness by the sacrificial oxidation process, a flat SOI layer having a desired film thickness can be obtained while maintaining the film thickness uniformity. Thermal oxidation of such sacrificial oxidation treatment can be efficiently formed at a temperature of 900 ° C. or higher because the damaged layer is recovered by RTA treatment in advance, and is also performed at a temperature of 1000 ° C. or lower. By doing so, generation of defects in the SOI layer can be reliably suppressed. By performing the RTA process and the sacrificial oxidation process twice, the SOI layer can be sufficiently flattened and the damage can be removed, and the desired film thickness can be reliably obtained.
- the temperature of thermal oxidation in the first and second sacrificial oxidation treatments of the present invention is 950 ° C. or higher.
- a defect occurs on the surface of the SOI layer. Since high-temperature hydrogen RTA treatment is performed before sacrificial oxidation to flatten the surface and recover the damaged layer by ion implantation, the OSF can be achieved even if the thermal oxidation temperature is 950 ° C. or higher (1000 ° C. or lower). The inventors have found that this does not occur. Therefore, by performing thermal oxidation at 950 ° C. or higher, the oxidation time can be shortened even when a relatively thick oxide film is formed, and the production efficiency can be improved.
- the frequency of occurrence of slip dislocation is lower than that of heat treatment in a high-temperature and long-time batch-type heat treatment furnace.
- the flattening effect is enhanced, since the frequency of occurrence of slip dislocation increases when the treatment is performed at a temperature exceeding 1230 ° C., the treatment is preferably performed at a temperature of 1230 ° C. or less.
- the first and second sacrificial oxidation treatments of the present invention can be performed, for example, by forming a thermal oxide film on the surface of the SOI layer by the thermal oxidation described above and removing the thermal oxide film with an aqueous solution containing HF or the like. Further, if the heat treatment time of the first and second RTA processes of the present invention is performed for 1 to 300 seconds, for example, the SOI layer can be planarized and damage can be removed.
- the rapid heating / rapid cooling device used in the first and second RTA processes of the present invention is not particularly limited as long as it is an apparatus capable of performing the RTA process.
- a single-wafer type lamp heating apparatus is used. Can do.
- the batch heat treatment furnace used in the present invention can perform heat treatment by placing a plurality of wafers in a vertical or horizontal heat treatment furnace.
- a resistance heating type batch heat treatment furnace is used. be able to.
- Example 1 to 6 Comparative Examples 1 to 4
- a bond wafer and a base wafer a mirror-polished silicon single crystal wafer having a diameter of 300 mm and a crystal orientation ⁇ 100> was prepared, a thermal oxide film having a thickness of 150 nm was formed on the surface of the bond wafer, and through the thermal oxide film, Hydrogen ion implantation (dose amount: 6 ⁇ 10 16 / cm 2 , implantation energy: 50 keV) is performed, and the bonding surface is bonded at room temperature via a base wafer and an oxide film activated by plasma treatment, at 350 ° C., After heat treatment for 1 hour (no peeling occurred by this heat treatment), the ion-implanted layer was pe
- Examples 5 and 6 and Comparative Example 4 As a bond wafer and a base wafer, a mirror-polished silicon single crystal wafer having a diameter of 300 mm and a crystal orientation ⁇ 100> was prepared, and a thermal oxide film having a thickness of 150 nm was formed on the surface of the bond wafer. Hydrogen ion implantation (dose amount: 5 ⁇ 10 16 / cm 2 , implantation energy: 50 keV) is performed, and the base wafer and the oxide film are bonded together at room temperature, followed by heat treatment at 500 ° C. for 0.5 hours, and peeling. did.
- Hydrogen ion implantation dose amount: 5 ⁇ 10 16 / cm 2 , implantation energy: 50 keV
- Example 1-6 and Comparative Examples 1 and 2 the fabricated SOI wafer was subjected to RTA treatment and sacrificial oxidation treatment (thermal oxidation + thermal oxide film removal using HF solution). The conditions are shown in Table 1.
- FIG. 2 shows a temperature profile of thermal oxidation in the sacrificial oxidation process of the first embodiment.
- Comparative Example 3 the manufactured SOI wafer was subjected to RTA treatment and sacrificial oxidation treatment (thermal oxidation + thermal oxide film removal by HF solution).
- Continuous post-annealing (100% Ar, 1100 ° C., 2 hours) was performed.
- Comparative Example 3 shows temperature profiles of thermal oxidation and post-annealing in the sacrificial oxidation treatment of Comparative Example 3.
- Ar annealing (100% Ar, 1200 ° C., 1 hour) using a batch heat treatment furnace was performed instead of the second RTA treatment.
- Example 1 to 6 good results were obtained in all of etch pits, slip generation rate, and surface roughness. Moreover, the film thickness distribution of the SOI layer measured separately showed that the film thickness range (a value obtained by subtracting the minimum film thickness value from the in-plane maximum film thickness value) was within 3 nm and good film thickness uniformity was obtained. In Examples 5 and 6, since peeling was performed by heat treatment, the surface roughness was slightly larger than in Examples 1 to 4, but it was sufficiently reduced compared to the surface roughness immediately after peeling. The etch pit and slip occurrence rates were at the same level as in Examples 1 to 4.
- Comparative Example 1 since the temperature of the thermal oxidation in the sacrificial oxidation process exceeds 1000 ° C., OSF due to damage that cannot be completely removed by the RTA process before oxidation occurs, and the SOI layer has defects ( Etch pits) occurred frequently.
- Comparative Example 2 since the temperature of the RTA treatment was less than 1100 ° C., damage removal was insufficient, OSF was generated even in thermal oxidation at 950 ° C., and defects (etch pits) occurred frequently in the SOI layer.
- Comparative Example 3 the post-annealing was continued for a long time at a high temperature after completion of the thermal oxidation, so that the slip generation rate deteriorated and was about twice that of Examples 1-6.
- Comparative Example 4 since high-temperature Ar annealing was performed in a batch heat treatment furnace instead of the second RTA treatment, the slip generation rate deteriorated, and was about twice that of Examples 1-6.
- the present invention is not limited to the above embodiment.
- the above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Element Separation (AREA)
Abstract
Description
このイオン注入剥離法は、二枚のウェーハの内、少なくとも一方に酸化膜を形成すると共に、一方のウェーハ(ボンドウェーハ)の上面から水素イオンや希ガスイオン等のガスイオンを注入し、該ウェーハ内部にイオン注入層(微小気泡層)を形成させた後、該イオンを注入した方の面を酸化膜(絶縁膜)を介して他方のウェーハ(ベースウェーハ)と密着させ、その後、熱処理(剥離熱処理)又は機械的な外力を加えてイオン注入層を劈開面として一方のウェーハ(ボンドウェーハ)を薄膜状に剥離し、さらに熱処理(結合熱処理)を加えて強固に結合してベースウェーハ上に薄膜(SOI層)を有する貼り合わせSOIウェーハを作製する技術(特許文献1参照)である。この方法では、薄膜、特にはSOI層の膜厚の均一性が高い貼り合わせSOIウェーハが容易に得られている。
ところが、SOI層に機械加工的要素を含む研磨をしてしまうと、研磨の取り代が均一でないために、水素イオンなどの注入、剥離によってある程度達成されたSOI層の膜厚均一性が悪化してしまうという問題が生じる。
例えば、特許文献2では、剥離熱処理後(または結合熱処理後)に、SOI層の表面を研磨することなく水素を含む還元性雰囲気下の熱処理(急速加熱・急速冷却熱処理(RTA:Rapid Thermal Annealing))を加えることを提案している。さらに、特許文献3では、剥離熱処理後(又は結合熱処理後)に、酸化性雰囲気下の熱処理によりSOI層に酸化膜を形成した後に該酸化膜を除去し(いわゆる犠牲酸化処理)、次に還元性雰囲気の熱処理(急速加熱・急速冷却熱処理(RTA処理))を加えることを提案している。
このように、タッチポリッシュの代わりに高温熱処理を行って表面粗さを改善する平坦化処理が行われるようになったことによって、現在では、直径300mmでSOI層の膜厚レンジ(面内の最大膜厚値から最小膜厚値を引いた値)が3nm以内の膜厚均一性を有するSOIウェーハが、イオン注入剥離法によって量産レベルで得られている。
特許文献6の[0087]段落でも同様に、イオン種の共注入による剥離面の表面粗さ改善として、RTA+StabOx+RTA+薄膜化を行うことが記載されている。
しかしながら、特許文献5、6における犠牲酸化は、900℃酸化+1100℃Arアニール(2時間)と記載されている通り、抵抗加熱式の熱処理炉(バッチ炉)を用いて酸化後に連続的に高温長時間のアニール(ポストアニール)を含む工程であるため、スリップ転位の発生頻度が高まるという問題があった。
このような温度で熱酸化することで、比較的厚い酸化膜をより短時間で形成することができ、生産性を向上させることができる。また、950℃以上でも、先にRTA処理を行って平坦化、イオン注入ダメージ層の回復が行われているためOSF等の欠陥は発生しない。
このように貼り合わせ、機械的剥離を行うことで、剥離面の面粗さを低減でき、より効率的にSOI層を平坦化することができる。
このような温度で第1及び第2のRTA処理することで、スリップ転位の発生を確実に抑制することができる。
図1は本発明の貼り合わせSOIウェーハの製造方法のフロー図である。
次に、図1の工程(c)では、水素イオン、希ガスイオンのうち少なくとも一種類のガスイオンを注入して、ボンドウェーハ10の内部にイオン注入層13を形成する。
なお、貼り合わせる前に、ウェーハの表面に付着しているパーティクルおよび有機物を除去するため、両ウェーハに貼り合わせ前洗浄を行ってもよい。
このように機械的な外力で剥離させることで、剥離面の面粗さを低減できるため、本発明のRTA処理で、十分に平坦化できるだけでなく、RTA処理の条件を緩和することも可能となる。
また、機械的な外力による剥離方法以外にも、例えば、不活性ガス雰囲気下、500℃以上の温度で熱処理を行い、結晶の再配列と気泡の凝集とによって剥離させることもできる。
このとき、第1及び第2のRTA処理を、水素ガス含有雰囲気下、1100℃以上の温度で行う。また、第1及び第2の犠牲酸化処理において、900℃以上1000℃以下の温度でバッチ式熱処理炉による熱酸化のみを行うことによってSOI層16の表面に熱酸化膜を形成した後、該熱酸化膜を除去する処理を行う。
従来は、剥離直後の貼り合わせSOIウェーハに対して950℃以上の温度で熱酸化を行うと、SOI層表面に欠陥(OSF)が発生してしまうという問題があったが、本発明の場合、犠牲酸化の前に高温の水素RTA処理を行って表面の平坦化とイオン注入のダメージ層の回復が行われているため、熱酸化の温度を950℃以上(1000℃以下)にしてもOSFは発生しないことを本発明者らは見出した。従って、950℃以上で熱酸化を行うことで、比較的厚い酸化膜を形成する場合であっても酸化時間の短縮を図ることができ、生産効率を向上させることができる。
また、本発明の第1及び第2のRTA処理の熱処理時間としては、例えば1~300秒間行えば、SOI層の平坦化及びダメージ除去が可能である。
(実施例1~6、比較例1~4)
[SOIウェーハの製法(剥離工程まで):機械的剥離]実施例1~4、比較例1~3
ボンドウェーハ及びベースウェーハとして、直径300mm、結晶方位<100>の鏡面研磨されたシリコン単結晶ウェーハを準備し、ボンドウェーハの表面に厚さ150nmの熱酸化膜を形成し、該熱酸化膜を通して、水素イオン注入(ドーズ量:6×1016/cm2、注入エネルギー:50keV)を行い、貼り合わせ面をプラズマ処理によって活性化したベースウェーハと酸化膜を介して室温にて貼り合わせ、350℃、1時間の熱処理(この熱処理で剥離は発生しない)を行った後、イオン注入層に機械的な外力を加えて剥離した。
ボンドウェーハ及びベースウェーハとして、直径300mm、結晶方位<100>の鏡面研磨されたシリコン単結晶ウェーハを準備し、ボンドウェーハの表面に厚さ150nmの熱酸化膜を形成し、該熱酸化膜を通して、水素イオン注入(ドーズ量:5×1016/cm2、注入エネルギー:50keV)を行い、ベースウェーハと酸化膜を介して室温にて貼り合わせ、500℃、0.5時間の熱処理を加えて剥離した。
また、比較例3において、作製したSOIウェーハにRTA処理と犠牲酸化処理(熱酸化+HF溶液による熱酸化膜除去)を行ったが、第1及び第2の犠牲酸化処理では、熱酸化の終了後に連続的にポストアニール(100%Ar、1100℃、2時間)を実施した。図3に、比較例3の犠牲酸化処理における熱酸化及びポストアニールの温度プロファイルを示す。
比較例4では、第2のRTA処理の代わりにバッチ式熱処理炉によるArアニール(100%Ar、1200℃、1時間)を実施した。
製造したSOIウェーハについて、クロムレスの選択エッチング液でSOI層表面を30nmエッチングし、光学顕微鏡でエッチピット密度を測定した。
[スリップ発生率]
各実施例、比較例の熱処理条件でSOIウェーハを100枚処理し、スリップ不良の限度見本と比較してスリップ不良と判断されたものの比率を調べた。
[表面粗さ]
第2の犠牲酸化処理後のSOI層表面をAFMにより測定した(測定領域30μm角)。
以上の評価結果を表1に示す。
なお、実施例5,6は、熱処理による剥離を行っているため、表面粗さが実施例1~4に比べてやや大きな値となったが、剥離直後の表面粗さと比較すると十分に低減されており、エッチピット、スリップ発生率は、実施例1~4と同等レベルであった。
比較例2では、RTA処理の温度が1100℃未満であるため、ダメージの除去が不十分となり、950℃の熱酸化でもOSFが発生し、SOI層に欠陥(エッチピット)が多発した。
比較例4では、第2のRTA処理の代わりにバッチ式熱処理炉による高温Arアニールを実施したため、スリップの発生率が悪化し、実施例1~6に比べて2倍程度となった。
Claims (4)
- シリコン単結晶からなるボンドウェーハの表面から水素イオン、希ガスイオンの少なくとも一種類のガスイオンをイオン注入して該ボンドウェーハ内部にイオン注入層を形成し、前記ボンドウェーハのイオン注入された側の表面とベースウェーハの表面とを絶縁膜を介して貼り合わせた後、前記ボンドウェーハの一部を前記イオン注入層で剥離して、前記ベースウェーハ上にSOI層を有する貼り合わせSOIウェーハを製造する方法であって、
前記剥離後の貼り合わせSOIウェーハに対して、第1のRTA処理を行った後、第1の犠牲酸化処理を行い、その後、第2のRTA処理を行った後、第2の犠牲酸化処理を行う工程を有し、
前記第1及び第2のRTA処理を、水素ガス含有雰囲気下、1100℃以上の温度で行い、前記第1及び第2の犠牲酸化処理において、900℃以上1000℃以下の温度でバッチ式熱処理炉による熱酸化のみを行うことによって前記SOI層表面に熱酸化膜を形成した後、該熱酸化膜を除去する処理を行うことを特徴とする貼り合わせSOIウェーハの製造方法。 - 前記第1及び第2の犠牲酸化処理における熱酸化の温度を、950℃以上とすることを特徴とする請求項1に記載の貼り合わせSOIウェーハの製造方法。
- 前記ボンドウェーハと前記ベースウェーハの少なくとも一方の表面にプラズマ処理を施した後に前記絶縁膜を介して貼り合わせた後、前記ボンドウェーハの一部を前記イオン注入層で機械的な外力を用いて剥離することを特徴とする請求項1又は請求項2に記載の貼り合わせSOIウェーハの製造方法。
- 前記第1及び第2のRTA処理を、1230℃以下の温度で行うことを特徴とする請求項1乃至請求項3のいずれか一項に記載の貼り合わせSOIウェーハの製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/364,162 US9076840B2 (en) | 2012-01-06 | 2012-11-30 | Method for manufacturing a bonded SOI wafer |
CN201280065462.0A CN104025254A (zh) | 2012-01-06 | 2012-11-30 | 贴合soi晶片的制造方法 |
EP12864102.4A EP2802001A4 (en) | 2012-01-06 | 2012-11-30 | METHOD FOR PRODUCING A BONDED SILICON ON ISOLATOR (SOI) WAFERS |
KR1020147018404A KR20140121392A (ko) | 2012-01-06 | 2012-11-30 | 접합 soi 웨이퍼의 제조방법 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012001611A JP2013143407A (ja) | 2012-01-06 | 2012-01-06 | 貼り合わせsoiウェーハの製造方法 |
JP2012-001611 | 2012-01-06 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2013102968A1 true WO2013102968A1 (ja) | 2013-07-11 |
Family
ID=48745045
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2012/007690 WO2013102968A1 (ja) | 2012-01-06 | 2012-11-30 | 貼り合わせsoiウェーハの製造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US9076840B2 (ja) |
EP (1) | EP2802001A4 (ja) |
JP (1) | JP2013143407A (ja) |
KR (1) | KR20140121392A (ja) |
CN (1) | CN104025254A (ja) |
WO (1) | WO2013102968A1 (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6086031B2 (ja) * | 2013-05-29 | 2017-03-01 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
JP6200273B2 (ja) * | 2013-10-17 | 2017-09-20 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
JP6036732B2 (ja) | 2014-03-18 | 2016-11-30 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
JP2016082093A (ja) * | 2014-10-17 | 2016-05-16 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
JP6380245B2 (ja) * | 2015-06-15 | 2018-08-29 | 信越半導体株式会社 | Soiウェーハの製造方法 |
JP6531743B2 (ja) * | 2016-09-27 | 2019-06-19 | 信越半導体株式会社 | 貼り合わせsoiウェーハの製造方法 |
CN106601615B (zh) * | 2016-12-27 | 2020-05-15 | 上海新傲科技股份有限公司 | 提高键合强度的退火方法 |
FR3093860B1 (fr) * | 2019-03-15 | 2021-03-05 | Soitec Silicon On Insulator | Procédé de transfert d’une couche utile sur un substrat support |
FR3093858B1 (fr) * | 2019-03-15 | 2021-03-05 | Soitec Silicon On Insulator | Procédé de transfert d’une couche utile sur un substrat support |
CN114664657A (zh) * | 2021-10-29 | 2022-06-24 | 中国科学院上海微系统与信息技术研究所 | 一种晶圆表面处理方法 |
CN116387241A (zh) * | 2023-04-21 | 2023-07-04 | 中芯先锋集成电路制造(绍兴)有限公司 | 绝缘体上半导体衬底的制造方法及半导体器件的制造方法 |
CN117096012B (zh) * | 2023-08-22 | 2024-03-26 | 中环领先半导体科技股份有限公司 | 一种氧化膜、硅片及其制备方法 |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05211128A (ja) | 1991-09-18 | 1993-08-20 | Commiss Energ Atom | 薄い半導体材料フィルムの製造方法 |
JPH11307472A (ja) | 1998-04-23 | 1999-11-05 | Shin Etsu Handotai Co Ltd | 水素イオン剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ |
JP2000124092A (ja) | 1998-10-16 | 2000-04-28 | Shin Etsu Handotai Co Ltd | 水素イオン注入剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ |
WO2003009386A1 (fr) | 2001-07-17 | 2003-01-30 | Shin-Etsu Handotai Co.,Ltd. | Procede de production de plaquettes de liaison |
JP2003510799A (ja) * | 1999-08-20 | 2003-03-18 | エス オー イ テク シリコン オン インシュレータ テクノロジース | マイクロエレクトロニクス用基板の処理方法及び該方法により得られた基板 |
JP2007500435A (ja) | 2003-07-29 | 2007-01-11 | エス.オー.アイ.テック、シリコン、オン、インシュレター、テクノロジーズ | 共注入と熱アニールによって特性の改善された薄層を得るための方法 |
WO2007074550A1 (ja) * | 2005-12-27 | 2007-07-05 | Shin-Etsu Chemical Co., Ltd. | Soiウェーハの製造方法及びsoiウェーハ |
JP2008513989A (ja) | 2004-09-21 | 2008-05-01 | エス.オー.アイ.テック シリコン オン インシュレータ テクノロジーズ | 気泡の形成を回避し、かつ、粗さを制限する条件により共注入工程を行う薄層転写方法 |
JP2008526010A (ja) | 2004-12-28 | 2008-07-17 | エス. オー. アイ. テック シリコン オン インシュレーター テクノロジーズ | 低いホール密度を有する薄層を得るための方法 |
JP2009032972A (ja) | 2007-07-27 | 2009-02-12 | Shin Etsu Handotai Co Ltd | 貼り合わせウエーハの製造方法 |
WO2010106101A1 (en) * | 2009-03-18 | 2010-09-23 | S.O.I.Tec Silicon On Insulator Technologies | Finishing method for a substrate of "silicon-on-insulator" soi type |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100730806B1 (ko) * | 1999-10-14 | 2007-06-20 | 신에쯔 한도타이 가부시키가이샤 | Soi웨이퍼의 제조방법 및 soi 웨이퍼 |
FR2895563B1 (fr) * | 2005-12-22 | 2008-04-04 | Soitec Silicon On Insulator | Procede de simplification d'une sequence de finition et structure obtenue par le procede |
JP5263509B2 (ja) * | 2008-09-19 | 2013-08-14 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
-
2012
- 2012-01-06 JP JP2012001611A patent/JP2013143407A/ja active Pending
- 2012-11-30 EP EP12864102.4A patent/EP2802001A4/en not_active Withdrawn
- 2012-11-30 WO PCT/JP2012/007690 patent/WO2013102968A1/ja active Application Filing
- 2012-11-30 US US14/364,162 patent/US9076840B2/en active Active
- 2012-11-30 CN CN201280065462.0A patent/CN104025254A/zh active Pending
- 2012-11-30 KR KR1020147018404A patent/KR20140121392A/ko not_active Application Discontinuation
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05211128A (ja) | 1991-09-18 | 1993-08-20 | Commiss Energ Atom | 薄い半導体材料フィルムの製造方法 |
JPH11307472A (ja) | 1998-04-23 | 1999-11-05 | Shin Etsu Handotai Co Ltd | 水素イオン剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ |
JP2000124092A (ja) | 1998-10-16 | 2000-04-28 | Shin Etsu Handotai Co Ltd | 水素イオン注入剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ |
JP2003510799A (ja) * | 1999-08-20 | 2003-03-18 | エス オー イ テク シリコン オン インシュレータ テクノロジース | マイクロエレクトロニクス用基板の処理方法及び該方法により得られた基板 |
WO2003009386A1 (fr) | 2001-07-17 | 2003-01-30 | Shin-Etsu Handotai Co.,Ltd. | Procede de production de plaquettes de liaison |
JP2007500435A (ja) | 2003-07-29 | 2007-01-11 | エス.オー.アイ.テック、シリコン、オン、インシュレター、テクノロジーズ | 共注入と熱アニールによって特性の改善された薄層を得るための方法 |
JP2008513989A (ja) | 2004-09-21 | 2008-05-01 | エス.オー.アイ.テック シリコン オン インシュレータ テクノロジーズ | 気泡の形成を回避し、かつ、粗さを制限する条件により共注入工程を行う薄層転写方法 |
JP2008526010A (ja) | 2004-12-28 | 2008-07-17 | エス. オー. アイ. テック シリコン オン インシュレーター テクノロジーズ | 低いホール密度を有する薄層を得るための方法 |
WO2007074550A1 (ja) * | 2005-12-27 | 2007-07-05 | Shin-Etsu Chemical Co., Ltd. | Soiウェーハの製造方法及びsoiウェーハ |
JP2009032972A (ja) | 2007-07-27 | 2009-02-12 | Shin Etsu Handotai Co Ltd | 貼り合わせウエーハの製造方法 |
WO2010106101A1 (en) * | 2009-03-18 | 2010-09-23 | S.O.I.Tec Silicon On Insulator Technologies | Finishing method for a substrate of "silicon-on-insulator" soi type |
Non-Patent Citations (1)
Title |
---|
See also references of EP2802001A4 * |
Also Published As
Publication number | Publication date |
---|---|
CN104025254A (zh) | 2014-09-03 |
US20140322895A1 (en) | 2014-10-30 |
KR20140121392A (ko) | 2014-10-15 |
JP2013143407A (ja) | 2013-07-22 |
EP2802001A4 (en) | 2015-09-16 |
US9076840B2 (en) | 2015-07-07 |
EP2802001A1 (en) | 2014-11-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2013102968A1 (ja) | 貼り合わせsoiウェーハの製造方法 | |
JP5673572B2 (ja) | 貼り合わせsoiウェーハの製造方法 | |
JP4421652B2 (ja) | Soiウェーハの製造方法 | |
JP2009032972A (ja) | 貼り合わせウエーハの製造方法 | |
WO2015141121A1 (ja) | 貼り合わせウェーハの製造方法 | |
WO2015136834A1 (ja) | 貼り合わせsoiウェーハの製造方法 | |
TWI685019B (zh) | 絕緣體上矽晶圓的製造方法 | |
TWI716627B (zh) | 貼合式soi晶圓的製造方法 | |
KR20150112968A (ko) | Soi 웨이퍼의 제조방법 및 soi 웨이퍼 | |
JP2006210899A (ja) | Soiウエーハの製造方法及びsoiウェーハ | |
JP2003347176A (ja) | 貼り合わせウェーハの製造方法 | |
KR102095383B1 (ko) | 접합 웨이퍼의 제조방법 | |
WO2016059748A1 (ja) | 貼り合わせウェーハの製造方法 | |
JP2009283582A (ja) | 貼り合わせウェーハの製造方法及び貼り合わせウェーハ | |
JP6500845B2 (ja) | 貼り合わせウェーハの製造方法 | |
CN105264641A (zh) | 贴合晶圆的制造方法 | |
JP5673180B2 (ja) | 貼り合わせウェーハの製造方法 | |
JP2006202989A (ja) | Soiウエーハの製造方法及びsoiウェーハ | |
JP5368000B2 (ja) | Soi基板の製造方法 | |
KR20160052551A (ko) | 접합 웨이퍼의 제조방법 | |
JP2014212172A (ja) | 貼り合わせウェーハの製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 12864102 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 14364162 Country of ref document: US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2012864102 Country of ref document: EP |
|
ENP | Entry into the national phase |
Ref document number: 20147018404 Country of ref document: KR Kind code of ref document: A |
|
NENP | Non-entry into the national phase |
Ref country code: DE |